diff options
Diffstat (limited to 'fpga/gpmc/xilinx/numato')
3 files changed, 84 insertions, 3 deletions
diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_clock_generator.v b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_clock_generator.v new file mode 100644 index 0000000..f13b1e3 --- /dev/null +++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_clock_generator.v @@ -0,0 +1,76 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// (c) 2014 Timothy Pearson, Raptor Engineering +// Released into the Public Domain +// +////////////////////////////////////////////////////////////////////////////////// + +module logic_analyzer_clock_generator( + input clkin, + output clkout); + + wire clk0; + wire clk2x; + reg reset; + + assign clkout = clk0; +// assign clkout = clk2x; + + // DCM_SP: Digital Clock Manager + // Spartan-6 + // Xilinx HDL Language Template, version 14.7 + + DCM_SP #( + .CLKDV_DIVIDE(2.0), // CLKDV divide value + // (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16). + .CLKFX_DIVIDE(1), // Divide value on CLKFX outputs - D - (1-32) + .CLKFX_MULTIPLY(4), // Multiply value on CLKFX outputs - M - (2-32) + .CLKIN_DIVIDE_BY_2("FALSE"), // CLKIN divide by two (TRUE/FALSE) + .CLKIN_PERIOD(10.0), // Input clock period specified in nS + .CLKOUT_PHASE_SHIFT("NONE"), // Output phase shift (NONE, FIXED, VARIABLE) + .CLK_FEEDBACK("1X"), // Feedback source (NONE, 1X, 2X) + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS + .DFS_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value + .DLL_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value + .DSS_MODE("NONE"), // Unsupported - Do not change value + .DUTY_CYCLE_CORRECTION("TRUE"), // Unsupported - Do not change value + .FACTORY_JF(16'hc080), // Unsupported - Do not change value + .PHASE_SHIFT(0), // Amount of fixed phase shift (-255 to 255) + .STARTUP_WAIT("FALSE") // Delay config DONE until DCM_SP LOCKED (TRUE/FALSE) + ) + DCM_SP_inst ( + .CLK0(clk0), // 1-bit output: 0 degree clock output + .CLK180(), // 1-bit output: 180 degree clock output + .CLK270(), // 1-bit output: 270 degree clock output + .CLK2X(clk2x), // 1-bit output: 2X clock frequency clock output + .CLK2X180(), // 1-bit output: 2X clock frequency, 180 degree clock output + .CLK90(), // 1-bit output: 90 degree clock output + .CLKDV(), // 1-bit output: Divided clock output + .CLKFX(), // 1-bit output: Digital Frequency Synthesizer output (DFS) + .CLKFX180(), // 1-bit output: 180 degree CLKFX output + .LOCKED(), // 1-bit output: DCM_SP Lock Output + .PSDONE(), // 1-bit output: Phase shift done output + .STATUS(), // 8-bit output: DCM_SP status output + .CLKFB(clk0), // 1-bit input: Clock feedback input + .CLKIN(clkin), // 1-bit input: Clock input + .DSSEN(1'b0), // 1-bit input: Unsupported, specify to GND. + .PSCLK(), // 1-bit input: Phase shift clock input + .PSEN(1'b0), // 1-bit input: Phase shift enable + .PSINCDEC(), // 1-bit input: Phase shift increment/decrement input + .RST(reset) // 1-bit input: Active high reset input + ); + + // End of DCM_SP_inst instantiation + + reg [7:0] reset_counter = 8'b00000001; + always @(posedge clkin) begin + if (reset_counter[7] != 1'b1) begin + reset_counter = reset_counter << 1; + reset = 1'b1; + end else begin + reset = 1'b0; + end + end + +endmodule diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf index 2c6b6b9..8e070de 100644 --- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf +++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf @@ -41,6 +41,7 @@ NET "usermem_wait" LOC = "T18" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; NET "userproc_start" LOC = "K16" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; NET "userproc_done" LOC = "L13" | IOSTANDARD = "LVCMOS33"; NET "userlogic_reset" LOC = "E13" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; +NET "userlogic_clock" LOC = "F13" | IOSTANDARD = "LVCMOS33"; NET "usermem_data<0>" LOC = "V14" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; NET "usermem_data<1>" LOC = "T11" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise index ac7f1e3..774cabd 100644 --- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise +++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise @@ -17,23 +17,27 @@ <files> <file xil_pn:name="data_storage.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> - <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="4"/> </file> <file xil_pn:name="lcd_data_storage.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> - <association xil_pn:name="Implementation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> </file> <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> - <association xil_pn:name="Implementation" xil_pn:seqID="4"/> + <association xil_pn:name="Implementation" xil_pn:seqID="5"/> </file> <file xil_pn:name="logic_analyzer_data_storage.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/> </file> + <file xil_pn:name="logic_analyzer_clock_generator.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> + </file> </files> <properties> |