From a4eb2fb6bfae4f5f71d7a0b3b1b384c19d94ecc6 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 9 Jan 2014 21:20:11 -0600 Subject: Move hardware design files to their correct locations --- fpga/gpmc/xilinx/common/data_storage.v | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 fpga/gpmc/xilinx/common/data_storage.v (limited to 'fpga/gpmc/xilinx/common/data_storage.v') diff --git a/fpga/gpmc/xilinx/common/data_storage.v b/fpga/gpmc/xilinx/common/data_storage.v new file mode 100644 index 0000000..b98fb25 --- /dev/null +++ b/fpga/gpmc/xilinx/common/data_storage.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// (c) 2014 Timothy Pearson, Raptor Engineering +// Released into the Public Domain +// +////////////////////////////////////////////////////////////////////////////////// + +module data_storage( + input clka, + input [7:0] dina, + input [(RAM_ADDR_BITS-1):0] addra, + input wea, + output reg [7:0] douta); + + parameter RAM_ADDR_BITS = 14; + parameter RAM_WIDTH = 8; + + // Xilinx specific directive + (* RAM_STYLE="BLOCK" *) + + reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0]; + + always @(posedge clka) begin + if (wea) begin + data_storage_ram[addra] <= dina; + douta <= dina; + end else begin + douta <= data_storage_ram[addra]; + end + end + +endmodule -- cgit v1.2.3