From 400d0abcff5986c764f4a25bec29c2af57286ee1 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Wed, 13 Mar 2013 23:11:33 -0500 Subject: Avoid usage of TQTimer::singleShot in the FPGA viewer part Repair "think-o" in the Spartan 6 block RAM HDL --- fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'fpga/xilinx/digilent') diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v index c3e612c..f1d10be 100644 --- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v +++ b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v @@ -14,7 +14,7 @@ module data_storage( output reg [7:0] douta); parameter RAM_WIDTH = 8; - parameter RAM_ADDR_BITS = 16384; + parameter RAM_ADDR_BITS = 14; // Xilinx specific directive (* RAM_STYLE="BLOCK" *) -- cgit v1.2.3