From f27e0f01840bcc42e521beb29b4f5964b1649bda Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Wed, 30 Oct 2013 13:12:43 -0500 Subject: Allow data processing RAM size to be configured by changing a Verilog parameter on the FPGA side --- .../spartan_6/s6_remotefpga_test/data_storage.v | 2 +- .../digilent/spartan_6/s6_remotefpga_test/main.v | 20 +++++++++++--------- 2 files changed, 12 insertions(+), 10 deletions(-) (limited to 'fpga/xilinx/digilent') diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v index 60c1dff..7c9fcb0 100644 --- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v +++ b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v @@ -9,7 +9,7 @@ module data_storage( input clka, input [7:0] dina, - input [13:0] addra, + input [(RAM_ADDR_BITS-1):0] addra, input wea, output reg [7:0] douta); diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v index 6162ec1..85c08be 100644 --- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v +++ b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v @@ -22,6 +22,8 @@ module main( input serial_input, output serial_output); + parameter RAM_ADDR_BITS = 14; + wire [7:0] four_bit_output; // Output from the user program to the remote access module wire [7:0] four_bit_input; // Input to the user program from the remote access module wire [7:0] eight_bit_output; // Output from the user program to the remote access module @@ -72,12 +74,12 @@ module main( // // Inputs: // .clk: 50MHz clock - // .four_bit_input 4-bit input to the user program from the remote access module - // .eight_bit_input 8-bit input to the user program from the remote access module + // .four_bit_input 4-bit input to the user program from the remote access module + // .eight_bit_input 8-bit input to the user program from the remote access module // .sixteen_bit_input 16-bit input to the user program from the remote access module // .serial_port_receiver Input from the serial port's RxD (receive data) pin // .remote_access_input_enable Toggle remote access input vs. local input mode - // .local_input Local input to the remote program + // .local_input Local input to the remote program // .seize_serial_tx Sieze control of the serial transmitter from the remote control system // .serial_tx_data Byte to be transmitted on transmit strobe if control has been siezed // .serial_tx_strobe Transmit serial data on posedge if transmit control has been siezed @@ -87,7 +89,7 @@ module main( // .sram_wren_in Synchronous SRAM write enable (1=write, 0=read) // .sram_clock_in Synchronous SRAM clock input // .sram_data_in Synchronous SRAM data input (8-bit) - // .sram_address_in Synchronous SRAM address input (14-bit) + // .sram_address_in Synchronous SRAM address input (14-bit by default) // .sram_processing_done When 1, signal release of user control of synchronous SRAM // .led_segment_bus Connect directly to the 8 bits controlling the LED display segments // .led_digit_select Connect directly to the 4 bits enabling the LED display digits @@ -111,7 +113,7 @@ module main( wire sram_wren_in; wire sram_clock_in; wire [7:0] sram_data_in; - wire [13:0] sram_address_in; + wire [(RAM_ADDR_BITS-1):0] sram_address_in; wire [7:0] sram_data_out; wire sram_available; wire sram_processing_done; @@ -124,7 +126,7 @@ module main( assign sram_clock_in = main_fifty_clock; - remote_access remote_access(.main_fifty_clock(main_fifty_clock), .remote_access_4_bit_output(four_bit_output), + remote_access #(RAM_ADDR_BITS) remote_access(.main_fifty_clock(main_fifty_clock), .remote_access_4_bit_output(four_bit_output), .remote_access_4_bit_input(four_bit_input), .remote_access_8_bit_output(eight_bit_output), .remote_access_8_bit_input(eight_bit_input), .remote_access_16_bit_output(sixteen_bit_output), .remote_access_16_bit_input(sixteen_bit_input), @@ -286,13 +288,13 @@ module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done); output reg wren; output reg [7:0] dout; - output reg [13:0] addr; + output reg [(RAM_ADDR_BITS-1):0] addr; input [7:0] din; input enable; output reg done; reg prev_enable; - reg [13:0] counter; + reg [(RAM_ADDR_BITS-1):0] counter; reg toggler; always @(posedge clk) begin @@ -310,7 +312,7 @@ module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done); wren = 1; addr = counter; counter = counter + 1; - if (counter >= 16383) begin + if (counter > (2**RAM_ADDR_BITS)) begin done = 1; end toggler = 0; -- cgit v1.2.3