diff options
| author | tpearson <tpearson@283d02a7-25f6-0310-bc7c-ecb5cbfe19da> | 2010-02-24 18:42:24 +0000 |
|---|---|---|
| committer | tpearson <tpearson@283d02a7-25f6-0310-bc7c-ecb5cbfe19da> | 2010-02-24 18:42:24 +0000 |
| commit | f508189682b6fba62e08feeb1596f682bad5fff9 (patch) | |
| tree | 28aeb0e6c19386c385c1ce5edf8a92c1bca15281 /test | |
| download | piklab-f508189682b6fba62e08feeb1596f682bad5fff9.tar.gz piklab-f508189682b6fba62e08feeb1596f682bad5fff9.zip | |
Added KDE3 version of PikLab
git-svn-id: svn://anonsvn.kde.org/home/kde/branches/trinity/applications/piklab@1095639 283d02a7-25f6-0310-bc7c-ecb5cbfe19da
Diffstat (limited to 'test')
86 files changed, 21674 insertions, 0 deletions
diff --git a/test/boost/interrupt.cpp b/test/boost/interrupt.cpp new file mode 100644 index 0000000..a5c8963 --- /dev/null +++ b/test/boost/interrupt.cpp @@ -0,0 +1,80 @@ +/* + Basic sample for BoostC++ compiler. + Use the 'Led Block' plugin to see + changing value on port B. +*/ +#include <system.h> + +// Set configuration word (sample only, ajust for your particular case) +#ifdef _PIC16 + #pragma DATA 0x2007, _HS_OSC & _WDT_OFF +#endif //_PIC16 + +class CPort +{ +public: + CPort(); + + void Toggle( void ) + { +#ifdef _PIC16 + portb++; +#else + latb++; +#endif + + } +}; + +CPort::CPort() +{ + trisb = 0; //configure port B + +#ifdef _PIC16 + portb = 0; //clear port B +#else + latb = 0; //clear port B +#endif +} + +class CTimer +{ +public: + CTimer(); +}; + +CTimer::CTimer() +{ +#ifdef _PIC16 + option_reg = 7; //set prescaler +#else + // configure Timer0 + set_bit( t0con, TMR0ON ); //enable timer + clear_bit( t0con, T08BIT ); //set 16-bit mode + clear_bit( t0con, T0CS ); // select internal clock + clear_bit( t0con, PSA ); // select prescaler + set_bit( t0con, T0PS0 ); // set 1:64 prescale ratio + clear_bit( t0con, T0PS1 ); + set_bit( t0con, T0PS2 ); +#endif + // enable interrupts + set_bit( intcon, T0IE ); //enable TMR0 overflow bit +} + +class CPort port; //configure port +class CTimer timer; //configure prescaler + +void interrupt( void ) +{ + port.Toggle(); + + clear_bit( intcon, T0IF ); //clear TMR0 overflow flag +} + +void main() +{ + // enable interrupts + set_bit( intcon, GIE ); + + while( 1 ); //endless loop +} diff --git a/test/boost/interrupt.pic16.bas b/test/boost/interrupt.pic16.bas new file mode 100644 index 0000000..370e582 --- /dev/null +++ b/test/boost/interrupt.pic16.bas @@ -0,0 +1,34 @@ +#include <basic\PIC16F877.bas> +' +' Basic sample for BoostBasic compiler. +' Use the "Led Block" plugin to see +' changing value on port B. +' + +' Set configuration word (sample only, ajust for your particular case) +#pragma DATA _CONFIG, _HS_OSC & _WDT_OFF + +Sub interrupt() + + portb = portb + 1 + + intcon = intcon & ~(1 << T0IF) 'clear TMR0 overflow flag + +End Sub + +Sub main() + + trisb = 0 'configure port B + portb = 0 'clear port B + + option_reg = 7 'set prescaler + + ' enable interrupts + intcon = intcon | (1 << T0IE) 'enable TMR0 overflow bit + intcon = intcon | (1 << GIE) 'set global interrupt bit + + ' endless loop + Do while 1 + Loop + +End Sub diff --git a/test/boost/rand.piklab b/test/boost/rand.piklab new file mode 100644 index 0000000..e1127c6 --- /dev/null +++ b/test/boost/rand.piklab @@ -0,0 +1,41 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>16F873</device> + <files> + <item>randtest.c</item> + </files> + <description/> + <version>0.1</version> + <tool>boostc16</tool> + <opened_files> + <item>randtest.c</item> + </opened_files> + </general> + <compiler> + <has_custom_arguments>false</has_custom_arguments> + <custom_options/> + <custom_arguments> + <item>-t %DEVICE</item> + <item>-i</item> + <item>-I$(SRCPATH)</item> + <item>%I</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </compiler> + <linker> + <has_custom_arguments>false</has_custom_arguments> + <custom_options>rand.pic16.lib</custom_options> + <custom_arguments> + <item>-t %DEVICE</item> + <item>-p</item> + <item>rand</item> + <item>-ld</item> + <item>/home/nicolas/wine/Program Files/SourceBoost/Lib</item> + <item>rand.pic16.lib</item> + <item>%OBJS</item> + </custom_arguments> + </linker> +</piklab> diff --git a/test/boost/randtest.c b/test/boost/randtest.c new file mode 100644 index 0000000..812dfd6 --- /dev/null +++ b/test/boost/randtest.c @@ -0,0 +1,48 @@ +/* + Random number generator sample for BoostC compiler. + Use the 'Led Block' plugin to see + changing random value on port B. +*/ + +#include <system.h> +#include <rand.h> + +#pragma CLOCK_FREQ 20000000 + +// Set configuration word +#ifdef _PIC16 + #pragma DATA 0x2007, _HS_OSC & _WDT_OFF +#endif //_PIC16 + + +void main() +{ + trisb = 0; //configure port B + portb = 0; + +#ifdef _PIC16 + option_reg = 7; //set prescaler + + set_bit( intcon, GIE ); + set_bit( intcon, T0IE ); //enable TMR0 overflow bit +#else + clear_bit( t0con, T0CS ); // select internal clock + clear_bit( t0con, PSA ); // select pres-scaler + set_bit( t0con, T0PS0 ); // set pres-scaler to 1:256 + set_bit( t0con, T0PS1 ); + set_bit( t0con, T0PS2 ); + + // enable interrupts + set_bit( intcon, GIE ); + set_bit( intcon, TMR0IE ); //enable TMR0 overflow bit +#endif + + //Set ramdom number generator seed + srand( 0x1234 ); + + while( 1 ) //endless loop + { + portb = rand(); + delay_ms( 100 ); + } +} diff --git a/test/c18/main.c b/test/c18/main.c new file mode 100644 index 0000000..2bab570 --- /dev/null +++ b/test/c18/main.c @@ -0,0 +1,13 @@ +/* Compile options: -ml (Large code model) */ + +#include <stdio.h> + +#pragma config WDT = OFF + +void main (void) +{ + printf ("Hello, world!\n"); + + while (1) + ; +} diff --git a/test/c18/test.piklab b/test/c18/test.piklab new file mode 100644 index 0000000..be034ac --- /dev/null +++ b/test/c18/test.piklab @@ -0,0 +1,13 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>18F452</device> + <tool>c18</tool> + <files> + <item>main.c</item> + </files> + <opened_files> + <item>main.c</item> + </opened_files> + </general> +</piklab> diff --git a/test/cc5x/SAMPLE1.C b/test/cc5x/SAMPLE1.C new file mode 100644 index 0000000..021b5cb --- /dev/null +++ b/test/cc5x/SAMPLE1.C @@ -0,0 +1,61 @@ + +/* global variables */ +char a; +bit b1, b2; + +/* assign names to port pins */ +bit in @ PORTB.0; +bit out @ PORTB.1; + +void sub( void) +{ + char i; /* a local variable */ + + /* generate 20 pulses */ + for ( i = 0; i < 20; i++) { + out = 1; + nop(); + out = 0; + } +} + + + +void main( void) +{ + // if (TO == 1 && PD == 1 /* power up */) { + // WARM_RESET: + // clearRAM(); // clear all RAM + // } + + /* NOTE 1: some devices have a comparator module + that have to be switched off to use certain + pins as digital IO */ + //CMCON = 0x07; // switch comparators off + + /* NOTE 2: devices having AD converter may need to + configure the pins assigned to 'in' and 'out' as + digital IO */ + //ADCON1 = .. + + /* First decide the initial output level on the + output port pins, and then define the input/ + output configuration. This avoids spikes at the + output pins. */ + + PORTB = 0b.0000.0010; /* out = 1 */ + TRISB = 0b.1111.0001; /* xxxx 0001 */ + + a = 9; /* value assigned to global variable */ + + do { + if (in == 0) /* stop if 'in' is low */ + break; + sub(); + } while ( -- a > 0); /* 9 iterations */ + + // if (some condition) + // goto WARM_RESET; + + /* main is terminated by a SLEEP instruction */ +} diff --git a/test/cc5x/sample1.piklab b/test/cc5x/sample1.piklab new file mode 100644 index 0000000..f89a9dc --- /dev/null +++ b/test/cc5x/sample1.piklab @@ -0,0 +1,10 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>16F690</device> + <tool>cc5x</tool> + <files> + <item>SAMPLE1.C</item> + </files> + </general> +</piklab> diff --git a/test/ccsc/blinker.piklab b/test/ccsc/blinker.piklab new file mode 100644 index 0000000..a0810cd --- /dev/null +++ b/test/ccsc/blinker.piklab @@ -0,0 +1,33 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>16F877</device> + <files> + <item>test.c</item> + </files> + <tool>ccsc</tool> + <description/> + <version>0.1</version> + <opened_files> + <item>test.c</item> + </opened_files> + </general> + <compiler> + <has_custom_arguments>false</has_custom_arguments> + <custom_options/> + <custom_arguments> + <item>+STDERR</item> + <item>-P</item> + <item>+LSlst</item> + <item>+OWhex</item> + <item>-J</item> + <item>-A</item> + <item>+F%FAMILY</item> + <item>-ICD</item> + <item>%I</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </compiler> +</piklab> diff --git a/test/ccsc/standalone_blinker.c b/test/ccsc/standalone_blinker.c new file mode 100644 index 0000000..e1d3384 --- /dev/null +++ b/test/ccsc/standalone_blinker.c @@ -0,0 +1,18 @@ +// This file is used to test the CCS compiler from within Piklab +// The resulting HEX file has not been verified in hardware + +#include <16F877.h> +#fuses HS,NOWDT,PUT,NOPROTECT +#use delay(clock=4000000) + +#define LED_PIN PIN_B0 + +void main(void) +{ + while(1){ + output_low(LED_PIN); + delay_ms(500); + output_high(LED_PIN); + delay_ms(500); + } +}
\ No newline at end of file diff --git a/test/ccsc/test.c b/test/ccsc/test.c new file mode 100644 index 0000000..e4a5c5a --- /dev/null +++ b/test/ccsc/test.c @@ -0,0 +1,18 @@ +// This file is used to test the CCS compiler from within Piklab +// The resulting HEX file has not been verified in hardware + +#include </home/azhyd/prog/ccs/devices/16f877.h> +#fuses HS,NOWDT,PUT,NOPROTECT +#use delay(clock=4000000) + +#define LED_PIN PIN_B0 + +void main(void) +{ + while(1){ + output_low(LED_PIN); + delay_ms(500); + output_high(LED_PIN); + delay_ms(500); + } +}
\ No newline at end of file diff --git a/test/commands/icd2_18F452_connect.dat b/test/commands/icd2_18F452_connect.dat new file mode 100644 index 0000000..04e4213 --- /dev/null +++ b/test/commands/icd2_18F452_connect.dat @@ -0,0 +1,43 @@ +<0801C9> + [0E0102060806] +<0807CF> + [0A07043C] +<0A2A824E> + [082ADB] +<0E06007FFF44> + [0806CE] +<0A05FF62> + [0805CD] +<0837D2> + [0A37A450] +<0834CF> + [0A347746] +<0835D0> + [0A35A34D] +<0837D2> + [0A37A450] +<0834CF> + [0A347746] +<0835D0> + [0A35A44E] +<082CDD> + [0A2C0248] +<184A003FFFFE000000014F> + [084ADD] + {2604CC} + [084ADD] +<0A330037> + [0833CE] +02 +<0808D0> + [0A080039] +<0801C9> + [0E0102060806] +<082CDD> + [0A2C0248] +<0807CF> + [0A07043C] +<0802CA> + [12020000000000A5] +<0A330037> + [0833CE] diff --git a/test/commands/icd2_18F452_program_debug.dat b/test/commands/icd2_18F452_program_debug.dat new file mode 100644 index 0000000..806c556 --- /dev/null +++ b/test/commands/icd2_18F452_program_debug.dat @@ -0,0 +1,283 @@ +<0A330037> + [0833CE] +<0834CF> + [0A34503D] +<082CDD> + [0A2C0248] +<184A003FFFFE000000014F> + [084ADD] + {2604CC} + [084ADD] +<0A330037> + [0833CE] +<0A330037> + [0833CE] +<0829D3> + [0829D3] +<082CDD> + [0A2C0248] +<18450030000000000007DC> + [0845D1] +{00270F0F000185000FC00FE00F40F1} + [0845D1] +<082CDD> + [0A2C0248] +<18430000000000000020D2> + [0843CF] +{00000000E06A936A816A81800DEC00F081900DEC00F005EF00F0100E3D6E100E3E6EFF0E3F6E3F2E13EF00F03E2E11EF00F03D2E0FEF00F01200FFFFFFFFFFFFF9} + [0843CF] +<082CDD> + [0A2C0248] +<184300007DC00000012001> + [0843CF] +{23D0EAD8F950FA45F926000036D03AD044D045D062D063D080D081D07ED07FD0ACD00ED0B3D00CD00BD00AD009D008D007D006D005D004D003D002D0B2D0B3D0FA6BE2D8E1D8DDD7E0CFFDF50501D8CFFEF5FF6FE9CFFCF5EACFFBF5FACFF5F5FBCFF4F5D450C80B5209D46EFC66C9D7FC2AFD6AFE6AFF6AC4D7C6D8000EFA6FC3D8BFD7C1D8010EFA6FBED8000EFA6FBBD8030EFA6FB8D8B4D7F69101D0F681B3D89AD8FAC5E9FF97D8FAC5EAFF94D8FAC5F9F591D8FAC5F8F5F967F82BF6B104D0EECFFAF5A0D803D086D8FAC5EEFFF92FF5D7F82FF3D794D7F69102D0F68100D092D879D8A96E77D876D8FAC5F9F573D8A69EF6B105D0A680A8CFFAF584D807D0A68469D8FAC5A8FF60D8A6B2FED7A92AF92FEFD7A69474D7F69101D0F68173D85AD8FAC5F6FF57D8FAC5F7FF54D8FAC5F8FF51D850D8FAC5F9F54DD8FAC5F8F5F82BF6A104D0940EA66E3FD80000F6A105D041D8FAC5F5FF0D0004D00900F5CFFAF551D8F92FF3D7F82FF1D7F6A148D7F6062BD8000044D746D82DD8FA53D8A402D0D49801D0D4883BD73DD8FDCFFAF53AD8FECFFAF537D8FFCFFAF534D830D732D803D030D8D48A00D0FCC5E9FFFBC5EAFFFF51FEC5D8FFFDC5E0FFF4C5FBFFF5C5FAFFD480D498E100550EA76EAA0EA76EA6821200D484D450E8B6FDD7D450E8A6FDD7D494200EE82CFED7080EF76FD484D494FA47FA91D450E8B6FA81F72FF7D7D4941200D484D450E8B6FDD7D450E8A6FDD7D494D492200EE82CFED7080ED484FABFD486FAAFD496D494FA47E82CF7D7D494D4821200FFFFFFFFFFFF5B} + [0843CF] +<082CDD> + [0A2C0248] +<18410020002800000008E2> + [0841CD] +{E0EF3EF000FFFFFFFFFFFFFFFFFFFFFF52} + [0841CD] +<0A0C0044> + [080CDB] +<082CDD> + [0A2C0248] +<184200000FB500000001FD> + [0842CE] +<0A0C0145> + [080CDB] +<0A330037> + [0833CE] +<0834CF> + [0A344F52] +<082CDD> + [0A2C0248] +<184A003FFFFE000000014F> + [084ADD] + {2604CC} + [084ADD] +<0A330037> + [0833CE] +<082CDD> + [0A2C0248] +<18470000000000000020D6> + [0847D3] + {00000000E06A936A816A81800DEC00F081900DEC00F005EF00F0100E3D6E100E3E6EFF0E3F6E3F2E13EF00F03E2E11EF00F03D2E0FEF00F01200FFFFFFFFFFFFF9} + [0847D3] +<082CDD> + [0A2C0248] +<184700007DC00000012005> + [0847D3] + {23D0EAD8F950FA45F926000036D03AD044D045D062D063D080D081D07ED07FD0ACD00ED0B3D00CD00BD00AD009D008D007D006D005D004D003D002D0B2D0B3D0FA6BE2D8E1D8DDD7E0CFFDF50501D8CFFEF5FF6FE9CFFCF5EACFFBF5FACFF5F5FBCFF4F5D450C80B5209D46EFC66C9D7FC2AFD6AFE6AFF6AC4D7C6D8000EFA6FC3D8BFD7C1D8010EFA6FBED8000EFA6FBBD8030EFA6FB8D8B4D7F69101D0F681B3D89AD8FAC5E9FF97D8FAC5EAFF94D8FAC5F9F591D8FAC5F8F5F967F82BF6B104D0EECFFAF5A0D803D086D8FAC5EEFFF92FF5D7F82FF3D794D7F69102D0F68100D092D879D8A96E77D876D8FAC5F9F573D8A69EF6B105D0A680A8CFFAF584D807D0A68469D8FAC5A8FF60D8A6B2FED7A92AF92FEFD7A69474D7F69101D0F68173D85AD8FAC5F6FF57D8FAC5F7FF54D8FAC5F8FF51D850D8FAC5F9F54DD8FAC5F8F5F82BF6A104D0940EA66E3FD80000F6A105D041D8FAC5F5FF0D0004D00900F5CFFAF551D8F92FF3D7F82FF1D7F6A148D7F6062BD8000044D746D82DD8FA53D8A402D0D49801D0D4883BD73DD8FDCFFAF53AD8FECFFAF537D8FFCFFAF534D830D732D803D030D8D48A00D0FCC5E9FFFBC5EAFFFF51FEC5D8FFFDC5E0FFF4C5FBFFF5C5FAFFD480D498E100550EA76EAA0EA76EA6821200D484D450E8B6FDD7D450E8A6FDD7D494200EE82CFED7080EF76FD484D494FA47FA91D450E8B6FA81F72FF7D7D4941200D484D450E8B6FDD7D450E8A6FDD7D494D492200EE82CFED7080ED484FABFD486FAAFD496D494FA47E82CF7D7D494D4821200FFFFFFFFFFFF5B} + [0847D3] +<082CDD> + [0A2C0248] +<18400020002800000008E1> + [0840CC] + {E0EF3EF000FFFFFFFFFFFFFFFFFFFFFF52} + [0840CC] +<0A330037> + [0833CE] +<0834CF> + [0A34503D] +<082CDD> + [0A2C0248] +<184A003FFFFE000000014F> + [084ADD] + {2604CC} + [084ADD] +<082CDD> + [0A2C0248] +<18450030000000000005DA> + [0845D1] +{FFF9FEF0FFFE7BFFFFFF40} + [0845D1] +<082CDD> + [0A2C0248] +<18450030000C00000001E9> + [0845D1] +{0F40DA} + [0845D1] +<082CDD> + [0A2C0248] +<18450030000A00000001E7> + [0845D1] +{FFFF18} + [0845D1] +<082CDD> + [0A2C0248] +<18490030000000000007E0> + [0849D5] + {00210E00000001000FC00FE00F40C7} + [0849D5] +<082CDD> + [0A2C0248] +<0A330138> + [0833CE] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<181B00000FB5000000010A> + [081BDB] +{0060} + [081BDB] +02 +<0808D0> + [0A080039] +<0801C9> + [0E0102060806] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<0804CC> + [0E04010003FD] +<0807CF> + [0A07043C] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<181B00000FB5000000010A> + [081BDB] +{0161} + [081BDB] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082DDE> + [082DDE] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<181B00000FB5000000010A> + [081BDB] +{0060} + [081BDB] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<181B00000FB5000000010A> + [081BDB] +{0060} + [081BDB] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<181E000000000000002CF4> + [081EDE] + {3000AA09400800B00721002A906000090280188070102480014440014008200200A01008000380800C528020A1} + [081EDE] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<181E000005FE0000000110> + [081EDE] + {1061} + [081EDE] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<181E000005FD000000010F> + [081EDE] + {0060} + [081EDE] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<181E000005FF0000000111> + [081EDE] + {D67A} + [081EDE] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<181B00000FB5000000010A> + [081BDB] +{0060} + [081BDB] +<083DDF> + [103D0000000058] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<082CDD> + [0A2C0046] +<0804CC> + [0E04010003FD] +<181B00000FB5000000010A> + [081BDB] +{0060} + [081BDB] +<083DDF> + [103D0000000058] diff --git a/test/dummy_hex.txt b/test/dummy_hex.txt new file mode 100644 index 0000000..4dfa09f --- /dev/null +++ b/test/dummy_hex.txt @@ -0,0 +1,32 @@ +* 10F200: + code: [000-0FE] 123 456 789 FFF...FFF 012 + cal: [0FF-0FF] 345 + user id: [100-103] 1 2 3 4 + config: [1FF] FE3 (invalid config !!) + +* 12C508A: + code: [000-1FE] 123 456 FFF...FFF 123 + cal: [1FF-1FF] 345 + user id: [200-203] 1 2 3 4 + config: [0FFF] FE9 + +* 16F877: + code: [0000-1FFF] 1234 3456 3FFF...3FFF 3456 0123 + user id: [2000-2003] 12 34 56 78 + config: [2007] 0E02 + eeprom: [0000-00FF] FF FF...FF (0x0080) 12 34 FF..FF 56 78 + +* 17C42A: + code: [000000-0007FF] 1234 5678 FFFF...FFFF 1234 5678 + config: [00FE00] FFE2 + +* 18F452: + code: [000000-007FFF] 1234 5678 90FF FF...FF 1234 + user id: [200000-200007] 1 2 3 4 5 6 7 8 + config: [300000-30000D] 22 08 0F 01 85 0F C0 0F E0 0F 40 + eeprom: [000000-0000FF] 12 34 FF...FF 56 78 + +* 30F2010: + code: [000000-001FFF] 123456 789012 FF...FF 987654 321098 + config: [F80000-F8000D] C10F 003F 83A3 0005 C003 (0005 is invalid !!) + eeprom: [7FFC00-7FFFFF] 1234 5678 FFF...FFF 0987 6543 diff --git a/test/dummy_hex_32/dummy_10F200_inhx32.hex b/test/dummy_hex_32/dummy_10F200_inhx32.hex new file mode 100644 index 0000000..37c4cd9 --- /dev/null +++ b/test/dummy_hex_32/dummy_10F200_inhx32.hex @@ -0,0 +1,37 @@ +:020000040000FA +:10000000230156048907FF0FFF0FFF0FFF0FFF0F9C +:10001000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F70 +:10002000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F60 +:10003000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F50 +:10004000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F40 +:10005000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F30 +:10006000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F20 +:10007000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F10 +:10008000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F00 +:10009000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FF0 +:1000A000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FE0 +:1000B000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FD0 +:1000C000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FC0 +:1000D000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FB0 +:1000E000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FA0 +:1000F000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F90 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+:087FB800FF00FF00FF00FF00C5 +:087FC000FF00FF00FF00FF00BD +:087FC800FF00FF00FF00FF00B5 +:087FD000FF00FF00FF00FF00AD +:087FD800FF00FF00FF00FF00A5 +:087FE000FF00FF00FF00FF009D +:087FE800FF00FF00FF00FF0095 +:087FF000FF00FF00FF00FF008D +:087FF800FF00FF0087004300B9 +:080000000F003F00A3000F00F8 +:060008000F0005000300DB +:00000001FF diff --git a/test/empty.piklab b/test/empty.piklab new file mode 100644 index 0000000..55b4945 --- /dev/null +++ b/test/empty.piklab @@ -0,0 +1,7 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>16F871</device> + <tool>gputils</tool> + </general> +</piklab> diff --git a/test/gputils/blinker/blinker.asm b/test/gputils/blinker/blinker.asm new file mode 100644 index 0000000..42f946b --- /dev/null +++ b/test/gputils/blinker/blinker.asm @@ -0,0 +1,148 @@ + + #include <p16f877.inc> ; processor specific variable definitions + + __CONFIG _CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC & _WRT_ENABLE_ON & _LVP_OFF & _CPD_OFF + ;__CONFIG _CP_OFF & _WDT_OFF & _PWRTE_ON & _EXTRC_CLKOUT + +;********************************************************************** +M_SAVE_STATE macro + movwf w_saved + movfw STATUS + movwf status_saved + endm + +M_RESTORE_STATE macro + movfw status_saved + movwf STATUS + swapf w_saved,f + swapf w_saved,w + endm + +BANK0 = 0x0 +BANK1 = 0x80 +BANK2 = 0x100 +BANK3 = 0x180 + +;********************************************************************** +INT_VAR UDATA_SHR 0x20 +w_saved RES 1 +status_saved RES 1 +pclath_saved RES 1 +INT1_VAR UDATA_SHR 0xA0 +w_saved1 RES 1 + +TEMP_VAR UDATA_SHR +count RES 1 +count2 RES 1 +ledA RES 1 +ledC RES 1 +ledB RES 1 + +;********************************************************************** +STARTUP CODE 0x000 ; processor reset vector + nop ; for debugger + movlw high start ; load upper byte of 'start' label + movwf PCLATH ; initialize PCLATH + goto start ; go to beginning of program + +;********************************************************************** +INT_VECTOR CODE 0x004 ; interrupt vector location + goto interrupt + +;********************************************************************** +PROG1 CODE +interrupt + M_SAVE_STATE + M_SAVE_STATE ; try using twice a macro + +; increment duty cycle +; btfss CCP1CON ^ BANK0,4 +; goto duty_cycle_inc_bit0 +; bcf CCP1CON ^ BANK0,4 +; btfss CCP1CON ^ BANK0,5 +; goto duty_cycle_inc_bit1 +; bcf CCP1CON ^ BANK0,5 +; incfsz CCPR1L ^ BANK0,f +; goto update_duty_cycle_done +;duty_cycle_inc_bit0 +; bsf CCP1CON ^ BANK0,4 +; goto update_duty_cycle_done +;duty_cycle_inc_bit1 +; bsf CCP1CON ^ BANK0,5 +;update_duty_cycle_done + +; increment count + decfsz count,1 + goto done + movlw .10 + movwf count + +; blink and output + movfw ledB + xorlw B'00001111' + movwf ledB + movwf PORTB + +done + bcf INTCON,2 ; reset TMR0 interrupt flag + M_RESTORE_STATE + retfie ; return from interrupt + +;********************************************************************** +start +; initialize microchip + clrf TMR0 ^ BANK0 + clrf INTCON ^ BANK0 +; clrf PORTA ^ BANK0 + clrf PORTB ^ BANK0 +; clrf PORTC ^ BANK0 +; clrf PORTD ^ BANK0 +; clrf PORTE ^ BANK0 + banksel TRISA ; bank 1 +; clrf TRISA ^ BANK1 ; all outputs + clrf TRISB ^ BANK1 ; all outputs +; clrf TRISC ^ BANK1 ; all outputs +; clrf TRISD ^ BANK1 ; all outputs +; clrf TRISE ^ BANK1 ; all outputs + movlw B'11010101' ; set prescaler to 64 + movwf OPTION_REG ^ BANK1 ; and start TMR0 (internal source clock) +; movlw B'00000110' ; set PORTA and PORTE to be all digital +; movwf ADCON1 ^ BANK1 + banksel INTCON ; back to bank 0 + bsf INTCON,T0IE ; enable TMR0 interrupt + bsf INTCON,GIE ; enable all interrupts + +; initialize PWM +; CLRF CCP1CON ^ BANK0 ; disable CCP module +; CLRF TMR2 ^ BANK0 ; clear Timer2 (also set the pre-scaler to 1) +; MOVLW .1 +; MOVWF CCPR1L ^ BANK0 ; set duty cycle = (CCPR1L+1)/(PR2+1) [25% for (31+1)/(127+1)] +; banksel PR2 ; select bank 1 +; MOVLW .255 +; MOVWF PR2 ^ BANK1 ; set period = Fosc/4/pre-scaler/(PR2+1) +; BCF TRISC ^ BANK1,2 ; set CCP1 pin as output +; banksel PIR1 ; back to bank 0 +; MOVLW B'001100' +; MOVWF CCP1CON ^ BANK0 ; set PWM mode (the 2 LSBs of the duty cycle are set to '00') +; BSF T2CON ^ BANK0,TMR2ON ; Timer2 starts to increment + + ; The CCP1 interrupt is disabled, + ; do polling on the TMR2 Interrupt flag bit +;PWM_Period_Match +; BTFSS PIR1, TMR2IF +; GOTO PWM_Period_Match + + ; Update this PWM period and the following PWM Duty cycle +; BCF PIR1, TMR2IF + +; initialize variables + movlw B'00000101' + movwf ledB + movlw .10 + movwf count + +; loop forever + goto $ + +;********************************************************************** + END diff --git a/test/gputils/blinker/blinker.piklab b/test/gputils/blinker/blinker.piklab new file mode 100644 index 0000000..4ac7729 --- /dev/null +++ b/test/gputils/blinker/blinker.piklab @@ -0,0 +1,89 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <files> + <item>blinker.asm</item> + </files> + <version>0.1</version> + <description/> + <device>16F877</device> + <tool>gputils</tool> + <custom_linker_script/> + <is_library>true</is_library> + <output_type>executable</output_type> + <opened_files> + <item>blinker.asm</item> + </opened_files> + </general> + <assembler> + <warning_level>0</warning_level> + <include_dir/> + <custom_options/> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>-c</item> + <item>-I$(SRCPATH)</item> + <item>-p%DEVICE</item> + <item>-w1</item> + <item>%I</item> + <item>-g</item> + <item>-I/usr/share/gputils/header</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </assembler> + <linker> + <debug>0</debug> + <hex_format>inhx32</hex_format> + <object_dir/> + <custom_options/> + <format>inhx32</format> + <custom_linker_script>/home/nicolas/prog/piklab/piklab/test/sdcc/16f873.lkr</custom_linker_script> + <has_custom_arguments>false</has_custom_arguments> + <custom_libraries/> + <custom_arguments> + <item>-o%O</item> + <item>-c</item> + <item>-ainhx32</item> + <item>-m</item> + <item>-I$(SRCPATH)</item> + <item>$LKR(-s%LKR)</item> + <item>%OBJS</item> + <item>%LIBS</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </linker> + <sdcc> + <custom_options/> + <include_dir/> + </sdcc> + <compiler> + <has_custom_arguments>false</has_custom_arguments> + <custom_options/> + <warning_level>0</warning_level> + <custom_arguments> + <item>-I$(SRCPATH)</item> + <item>-I</item> + <item>-p</item> + <item>%DEVICE</item> + <item>%I</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </compiler> + <librarian> + <has_custom_arguments>false</has_custom_arguments> + <custom_options/> + <custom_arguments> + <item>-c</item> + <item>%O</item> + <item>%OBJS</item> + <item>%LIBS</item> + </custom_arguments> + </librarian> + <editors/> +</piklab> diff --git a/test/gputils/blinker18/blinker_18.asm b/test/gputils/blinker18/blinker_18.asm new file mode 100644 index 0000000..4a00daf --- /dev/null +++ b/test/gputils/blinker18/blinker_18.asm @@ -0,0 +1,59 @@ +; LIST p=18F452 ;PIC18F452 is the target processor + INCLUDE "p18f452.inc" ;Include file with register defines + + ;Programming Configuration Information + __CONFIG _CONFIG1H, _XT_OSC_1H ;XT HS PLL (10MHz XTAL) + __CONFIG _CONFIG2L, _BOR_ON_2L & _PWRT_ON_2L ;Power-Up timer ON, Brown-out at 2.7V + + __CONFIG _CONFIG2H, _WDT_OFF_2H & _WDTPS_1_2H ;WDT OFF for debug + __CONFIG _CONFIG3H, _CCP2MX_OFF_3H ;CCP Module Off + __CONFIG _CONFIG4L, _LVP_OFF_4L & _DEBUG_OFF_4L + + ;UnProtect entire device program space for DEBUG + __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L + __CONFIG _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H + __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L + __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H + +;Assorted miscellaneous general-purpose registers +DlyRegA equ 0x3D ;Temp register for delay +DlyRegB equ 0x3E ;Temp register for delay +DlyRegC equ 0x3F ;Temp register for delay + +STARTUP CODE 0x000 + nop ;Required for ICD Debugging + nop + goto Main + +Main + clrf BSR,A ;Ensure BSR register points to first block + clrf TRISB,A + movlw 0x7 + movwf PORTB,A + +Loop + bsf PORTB,0 ;Turn the LED on + call LongDelay + bcf PORTB,0 ;Turn the LED off + call LongDelay + goto Loop + +;A long delay +LongDelay + movlw H'10' ;Adjust to produce a suitable time delay + movwf DlyRegA +ldelayc movlw H'10' + movwf DlyRegB +ldelayb movlw H'FF' + movwf DlyRegC +ldelaya decfsz DlyRegC,f ;Inner Loop + goto ldelaya + decfsz DlyRegB,f ;Middle Loop + goto ldelayb + decfsz DlyRegA,f ;Outer Loop + goto ldelayc + return + + END + + diff --git a/test/gputils/blinker18/blinker_18.piklab b/test/gputils/blinker18/blinker_18.piklab new file mode 100644 index 0000000..c1582de --- /dev/null +++ b/test/gputils/blinker18/blinker_18.piklab @@ -0,0 +1,52 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>18F452</device> + <files> + <item>blinker_18.asm</item> + </files> + <watched_ios> + <item>3969</item> + </watched_ios> + <description/> + <version>0.1</version> + <tool>gputils</tool> + <opened_files> + <item>blinker_18.asm</item> + </opened_files> + </general> + <assembler> + <custom_options/> + <warning_level>0</warning_level> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>-c</item> + <item>-I$(SRCPATH)</item> + <item>-w0</item> + <item>%I</item> + <item>-g</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </assembler> + <linker> + <custom_options/> + <format>inhx32</format> + <custom_libraries/> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>-o%O</item> + <item>-c</item> + <item>-ainhx8m</item> + <item>-m</item> + <item>-I$(SRCPATH)</item> + <item>$LKR(-s%LKR)</item> + <item>%OBJS</item> + <item>%LIBS</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </linker> +</piklab> diff --git a/test/gputils/compile_error/blinker.asm b/test/gputils/compile_error/blinker.asm new file mode 100644 index 0000000..cd9f495 --- /dev/null +++ b/test/gputils/compile_error/blinker.asm @@ -0,0 +1,145 @@ +; list p=16f871 ; list directive to define processor + #include <p16f871.inc> ; processor specific variable definitions + + __CONFIG _CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC & _WRT_ENABLE_ON & _LVP_OFF & _CPD_OFF + ;__CONFIG _CP_OFF & _WDT_OFF & _PWRTE_ON & _EXTRC_CLKOUT + +;********************************************************************** +M_SAVE_STATE macro + mov wf w_saved + movfw STATUS + movwf status_saved + endm + +M_RESTORE_STATE macro + movfw status_saved + movwf STATUS + swapf w_saved,f + swapf w_saved,w + endm + +BANK0 = 0x0 +BANK1 = 0x80 +BANK2 = 0x100 +BANK3 = 0x180 + +;********************************************************************** +INT_VAR UDATA_SHR +w_saved RES 1 ; variable used for context saving +status_saved RES 1 ; variable used for context saving + +TEMP_VAR UDATA_SHR +count RES 1 +count2 RES 1 +ledA RES 1 +ledC RES 1 +ledB RES 1 + +;********************************************************************** +STARTUP CODE 0x000 ; processor reset vector + nop ; for debugger + movlw high start ; load upper byte of 'start' label + movwf PCLATH ; initialize PCLATH + goto start ; go to beginning of program + +;********************************************************************** +INT_VECTOR CODE 0x004 ; interrupt vector location + goto interrupt + +;********************************************************************** +PROG1 CODE +interrupt + M_SAVE_STATE + M_SAVE_STATE ; try using twice a macro + +; increment duty cycle +; btfss CCP1CON ^ BANK0,4 +; goto duty_cycle_inc_bit0 +; bcf CCP1CON ^ BANK0,4 +; btfss CCP1CON ^ BANK0,5 +; goto duty_cycle_inc_bit1 +; bcf CCP1CON ^ BANK0,5 +; incfsz CCPR1L ^ BANK0,f +; goto update_duty_cycle_done +;duty_cycle_inc_bit0 +; bsf CCP1CON ^ BANK0,4 +; goto update_duty_cycle_done +;duty_cycle_inc_bit1 +; bsf CCP1CON ^ BANK0,5 +;update_duty_cycle_done + +; increment count + decfsz count,1 + goto done + movlw .10 + movwf count + +; blink and output + movfw ledB + xorlw B'00001111' + movwf ledB + movwf PORTB + +done + bcf INTCON,2 ; reset TMR0 interrupt flag + M_RESTORE_STATE + retfie ; return from interrupt + +;********************************************************************** +start +; initialize microchip + clrf TMR0 ^ BANK0 + clrf INTCON ^ BANK0 +; clrf PORTA ^ BANK0 + clrf PORTB ^ BANK0 +; clrf PORTC ^ BANK0 +; clrf PORTD ^ BANK0 +; clrf PORTE ^ BANK0 + banksel TRISA ; bank 1 +; clrf TRISA ^ BANK1 ; all outputs + clrf TRISB ^ BANK1 ; all outputs +; clrf TRISC ^ BANK1 ; all outputs +; clrf TRISD ^ BANK1 ; all outputs +; clrf TRISE ^ BANK1 ; all outputs + movlw B'11010101' ; set prescaler to 64 + movwf OPTION_REG ^ BANK1 ; and start TMR0 (internal source clock) +; movlw B'00000110' ; set PORTA and PORTE to be all digital +; movwf ADCON1 ^ BANK1 + banksel INTCON ; back to bank 0 + bsf INTCON,T0IE ; enable TMR0 interrupt + bsf INTCON,GIE ; enable all interrupts + +; initialize PWM +; CLRF CCP1CON ^ BANK0 ; disable CCP module +; CLRF TMR2 ^ BANK0 ; clear Timer2 (also set the pre-scaler to 1) +; MOVLW .1 +; MOVWF CCPR1L ^ BANK0 ; set duty cycle = (CCPR1L+1)/(PR2+1) [25% for (31+1)/(127+1)] +; banksel PR2 ; select bank 1 +; MOVLW .255 +; MOVWF PR2 ^ BANK1 ; set period = Fosc/4/pre-scaler/(PR2+1) +; BCF TRISC ^ BANK1,2 ; set CCP1 pin as output +; banksel PIR1 ; back to bank 0 +; MOVLW B'001100' +; MOVWF CCP1CON ^ BANK0 ; set PWM mode (the 2 LSBs of the duty cycle are set to '00') +; BSF T2CON ^ BANK0,TMR2ON ; Timer2 starts to increment + + ; The CCP1 interrupt is disabled, + ; do polling on the TMR2 Interrupt flag bit +;PWM_Period_Match +; BTFSS PIR1, TMR2IF +; GOTO PWM_Period_Match + + ; Update this PWM period and the following PWM Duty cycle +; BCF PIR1, TMR2IF + +; initialize variables + movlw B00000101' + movwf ledB + movlw .10 + movwf count + +; loop forever + goto $ + +;********************************************************************** + END
\ No newline at end of file diff --git a/test/gputils/compile_error/compile_error.piklab b/test/gputils/compile_error/compile_error.piklab new file mode 100644 index 0000000..a5d6ad4 --- /dev/null +++ b/test/gputils/compile_error/compile_error.piklab @@ -0,0 +1,74 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <files> + <item>blinker.asm</item> + </files> + <version>0.1</version> + <description/> + <device>16F877</device> + <tool>gputils</tool> + <custom_linker_script/> + <opened_files> + <item>blinker.asm</item> + </opened_files> + </general> + <assembler> + <warning_level>0</warning_level> + <include_dir/> + <custom_options/> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>-c</item> + <item>-I$(SRCPATH)</item> + <item>-p%DEVICE</item> + <item>-w1</item> + <item>%I</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </assembler> + <linker> + <debug>0</debug> + <hex_format>inhx32</hex_format> + <object_dir/> + <custom_options/> + <format>inhx32</format> + <custom_linker_script>/home/nicolas/prog/piklab/piklab/test/sdcc/16f873.lkr</custom_linker_script> + <has_custom_arguments>false</has_custom_arguments> + <custom_libraries/> + <includes> + <item>$(SRCPATH)</item> + </includes> + <custom_arguments> + <item>-o%O</item> + <item>-c</item> + <item>-ainhx32</item> + <item>-m</item> + <item>-I$(SRCPATH)</item> + <item>$LKR(-s%LKR)</item> + <item>%OBJS</item> + <item>%LIBS</item> + </custom_arguments> + </linker> + <sdcc> + <custom_options/> + <include_dir/> + </sdcc> + <compiler> + <has_custom_arguments>false</has_custom_arguments> + <custom_options/> + <warning_level>0</warning_level> + <custom_arguments> + <item>-I$(SRCPATH)</item> + <item>-I</item> + <item>-p</item> + <item>%DEVICE</item> + <item>%I</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </compiler> +</piklab> diff --git a/test/gputils/project/test.asm b/test/gputils/project/test.asm new file mode 100644 index 0000000..e4fcbe8 --- /dev/null +++ b/test/gputils/project/test.asm @@ -0,0 +1,60 @@ +; list p=16f877 + #include <p16f871.inc> + #include <test.inc> + + __CONFIG _CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _RC_OSC & _WRT_ENABLE_ON & _LVP_ON & _CPD_OFF + +;********************************************************************** +BANK0 = 0x0 +BANK1 = 0x80 +BANK2 = 0x100 +BANK3 = 0x180 + +;********************************************************************** +INT_VAR UDATA_SHR +w_saved RES 1 ; variable used for context saving +status_saved RES 1 ; variable used for context saving + +TEMP_VAR UDATA_SHR 0x20 +index RES 1 + +;********************************************************************** +STARTUP CODE ; processor reset vector + nop ; for debugger + movlw high start ; load upper byte of 'start' label + movwf PCLATH ; initialize PCLATH + goto start ; go to beginning of program + +;********************************************************************** +INT_VECTOR CODE 0x0004 ; interrupt vector location + movwf w_saved + movfw STATUS + movwf status_saved + + bcf INTCON,2 ; reset TMR0 interrupt flag + bsf PORTB,0 + + movfw status_saved + movwf STATUS + swapf w_saved,f + swapf w_saved,w + retfie ; return from interrupt + +;********************************************************************** +MAIN CODE +start +; initialize microchip + clrf TMR0 ^ BANK0 + clrf INTCON ^ BANK0 + banksel TRISA ; bank 1 + movlw B'11010100' ; set prescaler at 32 (32768 Hz / 4 / 256 / 32 = 1 Hz) + movwf OPTION_REG ^ BANK1 ; and start TMR0 (internal source clock) + movlw B'00000110' ; set PORTA and PORTE to be all digital + movwf ADCON1 ^ BANK1 + banksel INTCON ; back to bank 0 + bsf INTCON,T0IE ; enable TMR0 interrupt + bsf INTCON,GIE ; enable all interrupts + + nop + + END ; directive 'end of program' diff --git a/test/gputils/project/test.inc b/test/gputils/project/test.inc new file mode 100644 index 0000000..e956bd9 --- /dev/null +++ b/test/gputils/project/test.inc @@ -0,0 +1 @@ +; empty diff --git a/test/gputils/project/test.lib b/test/gputils/project/test.lib Binary files differnew file mode 100644 index 0000000..d0050e3 --- /dev/null +++ b/test/gputils/project/test.lib diff --git a/test/gputils/project/test2.asm b/test/gputils/project/test2.asm new file mode 100644 index 0000000..6a9ed66 --- /dev/null +++ b/test/gputils/project/test2.asm @@ -0,0 +1,6 @@ +MAIN CODE + +; loop forever + goto $ + END ; directive 'end of program' + diff --git a/test/gputils/project/test_project.piklab b/test/gputils/project/test_project.piklab new file mode 100644 index 0000000..2a26260 --- /dev/null +++ b/test/gputils/project/test_project.piklab @@ -0,0 +1,52 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <files> + <item>test.asm</item> + <item>test.lib</item> + <item>test2.asm</item> + </files> + <version>0.2</version> + <description/> + <device>16F871</device> + <tool>gputils</tool> + <opened_files> + <item>test.asm</item> + <item>test2.asm</item> + </opened_files> + </general> + <assembler> + <warning_level>0</warning_level> + <custom_options/> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>-c</item> + <item>-I$(SRCPATH)</item> + <item>-p%DEVICE</item> + <item>-w0</item> + <item>%I</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </assembler> + <linker> + <format>inhx32</format> + <custom_options/> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>-o%O</item> + <item>-c</item> + <item>-ainhx32</item> + <item>-m</item> + <item>-I$(SRCPATH)</item> + <item>$LKR(-s%LKR)</item> + <item>%OBJS</item> + <item>%LIBS</item> + </custom_arguments> + </linker> + <compiler> + <includes>$(SRCPATH)</includes> + <custom_options/> + </compiler> +</piklab> diff --git a/test/gputils/project/test_project.pikprj b/test/gputils/project/test_project.pikprj new file mode 100644 index 0000000..341ea8d --- /dev/null +++ b/test/gputils/project/test_project.pikprj @@ -0,0 +1,20 @@ +[Assembler] +include-dir= +other-options= +radix=dec +target-device=16F871 +warn-level=0 + +[Files] +inputFiles=test.asm,test2.asm,test.lib + +[General] +description= +output=test_project.hex +version=0.1 + +[Linker] +debug=false +hex-format=inhx32 +objs-libs-dir= +other-options= diff --git a/test/gputils/standalone/test_stand_alone.asm b/test/gputils/standalone/test_stand_alone.asm new file mode 100644 index 0000000..27e607a --- /dev/null +++ b/test/gputils/standalone/test_stand_alone.asm @@ -0,0 +1,53 @@ + list p=16f877 + #include <p16f877.inc> + + __CONFIG _CP_ALL & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _RC_OSC & _WRT_ENABLE_ON & _LVP_ON & _CPD_OFF + +;********************************************************************** +BANK0 = 0x0 +BANK1 = 0x80 +BANK2 = 0x100 +BANK3 = 0x180 + +;********************************************************************** +w_saved EQU 0x70 ; variable used for context saving +status_saved EQU 0x71 ; variable used for context saving +index EQU 0x20 + +;********************************************************************** + ORG 0x000 ; processor reset vector + movlw high start ; load upper byte of 'start' label + movwf PCLATH ; initialize PCLATH + goto start ; go to beginning of program + +;********************************************************************** + ORG 0x004 ; interrupt vector location + movwf w_saved + movfw STATUS + movwf status_saved + + bcf INTCON,2 ; reset TMR0 interrupt flag + + movfw status_saved + movwf STATUS + swapf w_saved,f + swapf w_saved,w + retfie ; return from interrupt + +;********************************************************************** +start +; initialize microchip + clrf TMR0 ^ BANK0 + clrf INTCON ^ BANK0 + banksel TRISA ; bank 1 + movlw B'11010100' ; set prescaler at 32 (32768 Hz / 4 / 256 / 32 = 1 Hz) + movwf OPTION_REG ^ BANK1 ; and start TMR0 (internal source clock) + movlw B'00000110' ; set PORTA and PORTE to be all digital + movwf ADCON1 ^ BANK1 + banksel INTCON ; back to bank 0 + bsf INTCON,T0IE ; enable TMR0 interrupt + bsf INTCON,GIE ; enable all interrupts + +; loop forever + goto $ + END ; directive 'end of program' diff --git a/test/hex_test/broken_format.hex b/test/hex_test/broken_format.hex new file mode 100644 index 0000000..9998fa9 --- /dev/null +++ b/test/hex_test/broken_format.hex @@ -0,0 +1,37 @@ +:020000040000FA +:11000000230156048907FF0FFF0FFF0FFF0FFF0F9C +:10001000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F70 +:10002000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F60 +:10003000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F50 +:10004000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F40 +:10005000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F30 +:10006000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F20 +:10007000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F10 +:10008000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F00 +:10009000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FF0 +:1000A000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FE0 +:1000B000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FD0 +:1000C000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FC0 +:1000D000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FB0 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+:10013000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F4F +:10014000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F3F +:10015000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F2F +:10016000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F1F +:10017000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F0F +:10018000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FFF +:10019000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FEF +:1001A000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FDF +:1001B000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FCF +:1001C000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FBF +:1001D000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FAF +:1001E000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F9F +:0E01F000FF0FFF0FFF0FFF0FFF0FFF0F12009B +:021FFE00E30FEF +:080200000100020003000400EC +:0201FE004503B7 + diff --git a/test/hex_test/good.hex b/test/hex_test/good.hex new file mode 100644 index 0000000..37c4cd9 --- /dev/null +++ b/test/hex_test/good.hex @@ -0,0 +1,37 @@ +:020000040000FA +:10000000230156048907FF0FFF0FFF0FFF0FFF0F9C +:10001000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F70 +:10002000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F60 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+:10019000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FEF +:1001A000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FDF +:1001B000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FCF +:1001C000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FBF +:1001D000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0FAF +:1001E000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F9F +:0E01F000FF0FFF0FFF0FFF0FFF0FFF0F12009B +:021FFE00E30FEF +:080200000100020003000400EC +:0201FE004503B7 +:00000001FF diff --git a/test/hex_test/good_equal.hex b/test/hex_test/good_equal.hex new file mode 100644 index 0000000..bd18067 --- /dev/null +++ b/test/hex_test/good_equal.hex @@ -0,0 +1,37 @@ +:020000040000FA +:10000000230156048907FF0FFF0FFF0FFF0FFF0F9C +:10001000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F70 +:10002000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F60 +:10003000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F50 +:10004000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F40 +:10005000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F30 +:10006000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F20 +:10007000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F10 +:10008000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F00 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+:1001F000FF0FFF0FFF0FFF0FFF0FFF0F1200FFFF9B +:021FFE00E30FEF +:100200000100020003000400FFFFFFFFFFFFFFFFEC +:0201FE004503B7 +:00000001FF diff --git a/test/hex_test/good_subset.hex b/test/hex_test/good_subset.hex new file mode 100644 index 0000000..bba3548 --- /dev/null +++ b/test/hex_test/good_subset.hex @@ -0,0 +1,6 @@ +:020000040000FA +:10000000230156048907FF0FFF0FFF0FFF0FFF0F9C +:021FFE00E30FEF +:080200000100020003000400EC +:0201FE004503B7 +:00000001FF diff --git a/test/hex_test/line_truncated.hex b/test/hex_test/line_truncated.hex new file mode 100644 index 0000000..d61742b --- /dev/null +++ b/test/hex_test/line_truncated.hex @@ -0,0 +1,37 @@ +:020000040000 +:10000000230156048907FF0FFF0FFF0FFF0FFF0F9C +:10001000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F70 +:10002000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F60 +:10003000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F50 +:10004000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F40 +:10005000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F30 +:10006000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F20 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+:1001E000FF0FFF0FFF0FFF0FFF0FFF0FFF0FFF0F9F +:0E01F000FF0FFF0FFF0FFF0FFF0FFF0F12009B +:021FFE00E30FEF +:080200000100020003000400EC +:0201FE004503B7 +:00000001FF diff --git a/test/jal/test.jal b/test/jal/test.jal new file mode 100644 index 0000000..c19fbc7 --- /dev/null +++ b/test/jal/test.jal @@ -0,0 +1,13 @@ +include 16c84_10 + +include jdelay +include hd447804 + + +HD44780_clear + +HD44780_write( 72 ) -- H +HD44780_write( 97 ) -- a +HD44780_write( 108 ) -- l +HD44780_write( 108 ) -- l +HD44780_write( 111 ) -- o diff --git a/test/jal/test.piklab b/test/jal/test.piklab new file mode 100644 index 0000000..6a6a4ff --- /dev/null +++ b/test/jal/test.piklab @@ -0,0 +1,15 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>16C84</device> + <tool>jal</tool> + <files> + <item>test.jal</item> + <item>test2.jal</item> + </files> + <opened_files> + <item>test.jal</item> + <item>test2.jal</item> + </opened_files> + </general> +</piklab> diff --git a/test/jal/test2.jal b/test/jal/test2.jal new file mode 100644 index 0000000..e26aa9c --- /dev/null +++ b/test/jal/test2.jal @@ -0,0 +1,2 @@ + +HD44780_write( 111 ) -- o
\ No newline at end of file diff --git a/test/jal/test_standalone.jal b/test/jal/test_standalone.jal new file mode 100644 index 0000000..c19fbc7 --- /dev/null +++ b/test/jal/test_standalone.jal @@ -0,0 +1,13 @@ +include 16c84_10 + +include jdelay +include hd447804 + + +HD44780_clear + +HD44780_write( 72 ) -- H +HD44780_write( 97 ) -- a +HD44780_write( 108 ) -- l +HD44780_write( 108 ) -- l +HD44780_write( 111 ) -- o diff --git a/test/pic30/standalone_test.s b/test/pic30/standalone_test.s new file mode 100644 index 0000000..98a8d5c --- /dev/null +++ b/test/pic30/standalone_test.s @@ -0,0 +1,19 @@ + .title " Sample dsPIC Assembler Source Code" + .sbttl " For illustration only." + ; dsPIC registers + .equ CORCONL, CORCON + .equ PSV,2 + .section .const,psv +hello: + .ascii "Hello world!\n\0" + .text + .global __reset +__reset: + ; set PSVPAG to page that contains 'hello' + mov #psvpage(hello),w0 + mov w0,PSVPAG + ; enable Program Space Visibility + bset.b CORCONL,#PSV + ; make a pointer to 'hello' + mov #psvoffset(hello),w0 + .end diff --git a/test/pic30/standalone_test_c.c b/test/pic30/standalone_test_c.c new file mode 100644 index 0000000..9e9be37 --- /dev/null +++ b/test/pic30/standalone_test_c.c @@ -0,0 +1,18 @@ +//#include <p30f2010.h> + +int main(void); +unsigned int Add(unsigned int a, unsigned int b); +unsigned int x, y, z; + +int main(void) +{ + x = 2; + y = 5; + z = Add(x,y); + return 0; +} + +unsigned int Add(unsigned int a, unsigned int b) +{ + return(a+b); +} diff --git a/test/pic30/test.piklab b/test/pic30/test.piklab new file mode 100644 index 0000000..9ec721d --- /dev/null +++ b/test/pic30/test.piklab @@ -0,0 +1,27 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>30F6015</device> + <files> + <item>test.s</item> + </files> + <description/> + <version>0.1</version> + <tool>pic30</tool> + <opened_files> + <item>test.s</item> + </opened_files> + </general> + <compiler> + <includes>$(SRCPATH)</includes> + <custom_options/> + </compiler> + <assembler> + <includes>$(SRCPATH)</includes> + <custom_options/> + </assembler> + <linker> + <custom_options/> + <format>inhx32</format> + </linker> +</piklab> diff --git a/test/pic30/test.s b/test/pic30/test.s new file mode 100644 index 0000000..98a8d5c --- /dev/null +++ b/test/pic30/test.s @@ -0,0 +1,19 @@ + .title " Sample dsPIC Assembler Source Code" + .sbttl " For illustration only." + ; dsPIC registers + .equ CORCONL, CORCON + .equ PSV,2 + .section .const,psv +hello: + .ascii "Hello world!\n\0" + .text + .global __reset +__reset: + ; set PSVPAG to page that contains 'hello' + mov #psvpage(hello),w0 + mov w0,PSVPAG + ; enable Program Space Visibility + bset.b CORCONL,#PSV + ; make a pointer to 'hello' + mov #psvoffset(hello),w0 + .end diff --git a/test/pic30/test_c.c b/test/pic30/test_c.c new file mode 100644 index 0000000..5205e53 --- /dev/null +++ b/test/pic30/test_c.c @@ -0,0 +1,22 @@ +#include <p30f3010.h> +_FOSC(XT_PLL16 & FRC & CSW_FSCM_OFF); +_FWDT(WDTPSB_16 & WDTPSA_512 & WDT_OFF); +_FBORPOR(PWRT_64 & BORV_20 & PBOR_ON & MCLR_EN); +//_FGS(CODE_PROT_ON); + +void delay(void); + +int main (void) +{ +int i = 0xFFFF; + +for (;;) { + delay(); +} +} + +void delay() +{ +int i; +for (i = 0; i < 0xFFFF; i++) {;} +} diff --git a/test/pic30/test_c.piklab b/test/pic30/test_c.piklab new file mode 100644 index 0000000..0985934 --- /dev/null +++ b/test/pic30/test_c.piklab @@ -0,0 +1,103 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>30F3010</device> + <files> + <item>test_c.c</item> + <item>test.s</item> + <item>libp30F3010-coff.a</item> + </files> + <description/> + <version>0.1</version> + <tool>pic30</tool> + <custom_linker_script/> + <is_library>false</is_library> + <opened_files> + <item>test_c.c</item> + </opened_files> + </general> + <sdcc> + <custom_options/> + <include_dir/> + </sdcc> + <assembler> + <warning_level>0</warning_level> + <custom_options/> + <include_dir/> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>--ERRFORMAT</item> + <item>--WARNFORMAT</item> + <item>--MSGFORMAT</item> + <item>--CHIP=%DEVICE</item> + <item>--IDE=mplab</item> + <item>-Q</item> + <item>-C</item> + <item>--ASMLIST</item> + <item>-I$(SRCPATH)</item> + <item>%I</item> + <item>-D</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </assembler> + <linker> + <hex_format>inhx32</hex_format> + <object_dir/> + <custom_options/> + <format>inhx32</format> + <custom_libraries/> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>/k%LKR_PATH</item> + <item>%LKR_NAME</item> + <item>/l</item> + <item>/o%COFF</item> + <item>/m%MAP</item> + <item>%OBJS</item> + <item>%LIBS</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </linker> + <compiler> + <custom_options/> + <has_custom_arguments>false</has_custom_arguments> + <warning_level>0</warning_level> + <custom_arguments> + <item>-S</item> + <item>$NO_AUTO_DEVICE(-mcpu=%DEVICE)</item> + <item>-I/home/nicolas/wine/Program Files/Microchip/MPLAB C30/support/h/</item> + <item>-g</item> + <item>%I</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </compiler> + <bin_to_hex> + <has_custom_arguments>false</has_custom_arguments> + <custom_options/> + <custom_arguments> + <item>%I</item> + </custom_arguments> + </bin_to_hex> + <librarian> + <has_custom_arguments>false</has_custom_arguments> + <custom_options/> + <custom_arguments> + <item>-rc</item> + <item>%O</item> + <item>%LIBS</item> + <item>%OBJS</item> + </custom_arguments> + </librarian> + <editors> + <bookmarks> + <item>file:///home/nicolas/prog/trunk/piklab/test/pic30/test.s,9</item> + <item>file:///home/nicolas/prog/trunk/piklab/test/pic30/test_c.c,1</item> + </bookmarks> + </editors> +</piklab> diff --git a/test/picc/standalone_test.c b/test/picc/standalone_test.c new file mode 100644 index 0000000..4173cf8 --- /dev/null +++ b/test/picc/standalone_test.c @@ -0,0 +1,350 @@ +/* + * level - electronic level using the ADXL202 + * + * $Id: standalone_test.c 713 2006-03-15 00:01:20Z azhyd $ + * $Source$ + * + * This program consists of an interrupt routine that measures the pulse + * width from the ADXL202 and a main routine that updates the dot matrix + * display on the DISPLAY board. + * + * Timer1 and the two Capture/Compare registers are used to measure the + * pulse width. + * + * Use PICCLITE to compile this program for the PIC16F877. + * + * Status: Sept 25, 2003 + * Working. The code is pretty brute force and the resolution isn't + * what I expected. Need to review calculations for angle vs. accel + * (gravity). I determined the zero offsets empirically and hard coded + * them. For coding simplicity I am discarding any measurements where + * the counter overflows during the measurement. + * + * Improvements should include: a method to zero the offsets at + * runtime and increased gain (which probably means going to 16 bit + * values). Also consider filtering the measured values to gain stability. + * Add code to handle counter overflow. + */ + +#include <pic.h> + +/* + * bit macros suggested by the PICCLITE manual + */ +#define BITSET(var, bitno) ((var) |= 1 << (bitno)) +#define BITCLR(var, bitno) ((var) &= ~(1 << (bitno))) + + +/* + * pulse with variables + * + * These are set up the measurePW() ISR and read by the main loop + */ +unsigned char PeriodStartX; +unsigned char PeriodEndX; +unsigned char PulseEndX; +unsigned char PulseEndTempX; +unsigned char PWSyncX; + +unsigned char PeriodStartY; +unsigned char PeriodEndY; +unsigned char PulseEndY; +unsigned char PulseEndTempY; +unsigned char PWSyncY; + +/* + * interrupt service routine to measure pulse width + * + * This routine uses the capture facility of the 16F877 to measure the + * period and the pulse width of a signal. This routine has two states + * the first looks for the rising edge of the signal which indicates the + * end of one period and the beginning of the next. The second state + * looks for the falling edge of the signal to determine the pulse + * width. + * + * Only the high 8 bits of the captured time are record. At 20MHz this + * yields a time resolution of approximately 51us. + * + * RC0 and RC1 indicate ISR over-run (in other words the main loop did + * not handle the measured values quickly enough). + */ +void interrupt +measurePW(void) +{ + /* determined which capture register requires service */ + if (CCP1IF == 1) + { + /* CCP1 */ + if ((CCP1CON & 0b00000111) == 0b00000101) + { + /* rising edge- + * record last rise time (period_end -> period_start) + * record last falling time (pulse_end_temp -> pulse_end) + * record this rise time (capture -> period_end) + * set synchronization flag + * change mode to look for falling edge + */ + PeriodStartX = PeriodEndX; + PulseEndX = PulseEndTempX; + PeriodEndX = CCPR1H; + PWSyncX++; + CCP1CON = 0b00000100; + + /* Indicated an ISR over-run if the sync flag was + * not cleared by the main loop + */ + if (PWSyncX > 1) + { + RC0 = 0; + } + } + else /* assume falling edge */ + { + /* falling- + * save this falling time for later + * change mode to look for rising edge + */ + PulseEndTempX = CCPR1H; + CCP1CON = 0b00000101; + } + /* + * clear interrupt flags and return + */ + CCP1IF = 0; + } + else + { + /* CCP2 */ + if ((CCP2CON & 0b00000111) == 0b00000101) + { + /* rising edge- + * record last rise time (period_end -> period_start) + * record last falling time (pulse_end_temp -> pulse_end) + * record this rise time (capture -> period_end) + * set synchronization flag + * change mode to look for falling edge + */ + PeriodStartY = PeriodEndY; + PulseEndY = PulseEndTempY; + PeriodEndY = CCPR2H; + PWSyncY++; + CCP2CON = 0b00000100; + + /* Indicated an ISR over-run if the sync flag was + * not cleared by the main loop + */ + if (PWSyncY > 1) + { + RC3 = 0; + } + } + else /* assume falling edge */ + { + /* falling- + * save this falling time for later + * change mode to look for rising edge + */ + PulseEndTempY = CCPR2H; + CCP2CON = 0b00000101; + } + /* + * clear interrupt flags and return + */ + CCP2IF = 0; + } +} + + +/* + * measure tilt and update dot matrix display + * + * This program uses the times recorded by the measurePW() ISR to + * calculate pulse width. The pulse width is then translated into a tilt + * measurement and finally displayed on the dot matrix display. + */ +void +main(void) +{ + unsigned char periodX = 0; + unsigned char pulseX = 0; + unsigned char periodY = 0; + unsigned char pulseY = 0; + int tiltX; + int tiltY; + + /* + * Setup I/O ports + * RC0 and RC3 outputs, the rest are inputs. + * RA5 output (power to ADXL202) + * Set port C outputs high to turn off the LEDs + */ + TRISC = 0b11110110; + RA5 = 1; + PORTC = 0xff; + + /* + * Setup the I/O ports that control the dot matrix display + */ + TRISA = 0b11000000; + TRISB = 0b11100000; + TRISD = 0b10000000; + ADCON1 = 0x06; /* disable ADC so that port A is digital I/O */ + PORTD = 0; /* turn off all rows */ + PORTB = 0xff; /* turn off all columns */ + PORTA = 0xff; /* turn off all columns */ + + /* configure timer1 + * 1:1 prescale + * Internal clock (Fosc/4) + * Enabled + */ + T1CON = 0b00000001; + + /* + * configure capture registers + * capture on rising edge + */ + CCP1CON = 0b00000101; + CCP2CON = 0b00000101; + + /* + * clear sync flag + */ + PWSyncX = 0; + PWSyncY = 0; + + /* + * enable interrupts + */ + PEIE = 1; + CCP1IE = 1; + CCP2IE = 1; + ei(); + + /* + * main loop + */ + for (;;) + { + /* + * kick watchdog + */ + CLRWDT(); + + if (PWSyncX > 0) + { + /* + * Test for easy calculations + * i.e., no counter roll over during the measurment + */ + if (PeriodEndX > PeriodStartX) + { + if (PulseEndX > PeriodStartX) + { + /* + * no roll over, so proceed + */ + periodX = PeriodEndX - PeriodStartX; + pulseX = PulseEndX - PeriodStartX; + + periodX = (periodX / 2) + 9; /* offset = 9 */ + tiltX = (periodX) - pulseX; + + /* + * turn off all rows and then figure out which row to turn + * on based on the tilt + */ + PORTD = 0; + if (tiltX < -5) + { + RD6 = 1; + } + else if (tiltX < -4) + { + RD5 = 1; + } + else if (tiltX < -2) + { + RD4 = 1; + } + else if (tiltX > 5) + { + RD0 = 1; + } + else if (tiltX > 4) + { + RD1 = 1; + } + else if (tiltX > 2) + { + RD2 = 1; + } + else + { + RD3 = 1; + } + } + } + PWSyncX = 0; + } + + if (PWSyncY > 0) + { + /* + * Test for easy calculations + * i.e., no counter roll over during the measurment + */ + if (PeriodEndY > PeriodStartY) + { + if (PulseEndY > PeriodStartY) + { + /* + * no roll over, so proceed + */ + periodY = PeriodEndY - PeriodStartY; + pulseY = PulseEndY - PeriodStartY; + + periodY = (periodY / 2) - 1; /* offset = -1 */ + tiltY = (periodY) - pulseY; + + /* + * turn off all columns then figure out which column + * to turn on based on the tilt + */ + PORTA = PORTA | 0b00111111; + PORTB = PORTB | 0b00011111; + if (tiltY < -5) + { + RB1 = 0; + } + else if (tiltY < -4) + { + RB0 = 0; + } + else if (tiltY < -2) + { + RA4 = 0; + } + else if (tiltY > 5) + { + RA0 = 0; + } + else if (tiltY > 4) + { + RA1 = 0; + } + else if (tiltY > 2) + { + RA2 = 0; + } + else + { + RA3 = 0; + } + } + } + PWSyncY = 0; + } + } +} + diff --git a/test/picc/test.c b/test/picc/test.c new file mode 100644 index 0000000..5fc2e81 --- /dev/null +++ b/test/picc/test.c @@ -0,0 +1,348 @@ +/* + * level - electronic level using the ADXL202 + * + * This program consists of an interrupt routine that measures the pulse + * width from the ADXL202 and a main routine that updates the dot matrix + * display on the DISPLAY board. + * + * Timer1 and the two Capture/Compare registers are used to measure the + * pulse width. + * + * Use PICCLITE to compile this program for the PIC16F877. + * + * Status: Sept 25, 2003 + * Working. The code is pretty brute force and the resolution isn't + * what I expected. Need to review calculations for angle vs. accel + * (gravity). I determined the zero offsets empirically and hard coded + * them. For coding simplicity I am discarding any measurements where + * the counter overflows during the measurement. + * + * Improvements should include: a method to zero the offsets at + * runtime and increased gain (which probably means going to 16 bit + * values). Also consider filtering the measured values to gain stability. + * Add code to handle counter overflow. + */ + +#include <pic.h> +#include "test.h" + +/* + * bit macros suggested by the PICCLITE manual + */ +#define BITSET(var, bitno) ((var) |= 1 << (bitno)) +#define BITCLR(var, bitno) ((var) &= ~(1 << (bitno))) + + +/* + * pulse with variables + * + * These are set up the measurePW() ISR and read by the main loop + */ +unsigned char PeriodStartX; +unsigned char PeriodEndX; +unsigned char PulseEndX; +unsigned char PulseEndTempX; +unsigned char PWSyncX; + +unsigned char PeriodStartY; +unsigned char PeriodEndY; +unsigned char PulseEndY; +unsigned char PulseEndTempY; +unsigned char PWSyncY; + +/* + * interrupt service routine to measure pulse width + * + * This routine uses the capture facility of the 16F877 to measure the + * period and the pulse width of a signal. This routine has two states + * the first looks for the rising edge of the signal which indicates the + * end of one period and the beginning of the next. The second state + * looks for the falling edge of the signal to determine the pulse + * width. + * + * Only the high 8 bits of the captured time are record. At 20MHz this + * yields a time resolution of approximately 51us. + * + * RC0 and RC1 indicate ISR over-run (in other words the main loop did + * not handle the measured values quickly enough). + */ +void interrupt +measurePW(void) +{ + /* determined which capture register requires service */ + if (CCP1IF == 1) + { + /* CCP1 */ + if ((CCP1CON & 0b00000111) == 0b00000101) + { + /* rising edge- + * record last rise time (period_end -> period_start) + * record last falling time (pulse_end_temp -> pulse_end) + * record this rise time (capture -> period_end) + * set synchronization flag + * change mode to look for falling edge + */ + PeriodStartX = PeriodEndX; + PulseEndX = PulseEndTempX; + PeriodEndX = CCPR1H; + PWSyncX++; + CCP1CON = 0b00000100; + + /* Indicated an ISR over-run if the sync flag was + * not cleared by the main loop + */ + if (PWSyncX > 1) + { + RC0 = 0; + } + } + else /* assume falling edge */ + { + /* falling- + * save this falling time for later + * change mode to look for rising edge + */ + PulseEndTempX = CCPR1H; + CCP1CON = 0b00000101; + } + /* + * clear interrupt flags and return + */ + CCP1IF = 0; + } + else + { + /* CCP2 */ + if ((CCP2CON & 0b00000111) == 0b00000101) + { + /* rising edge- + * record last rise time (period_end -> period_start) + * record last falling time (pulse_end_temp -> pulse_end) + * record this rise time (capture -> period_end) + * set synchronization flag + * change mode to look for falling edge + */ + PeriodStartY = PeriodEndY; + PulseEndY = PulseEndTempY; + PeriodEndY = CCPR2H; + PWSyncY++; + CCP2CON = 0b00000100; + + /* Indicated an ISR over-run if the sync flag was + * not cleared by the main loop + */ + if (PWSyncY > 1) + { + RC3 = 0; + } + } + else /* assume falling edge */ + { + /* falling- + * save this falling time for later + * change mode to look for rising edge + */ + PulseEndTempY = CCPR2H; + CCP2CON = 0b00000101; + } + /* + * clear interrupt flags and return + */ + CCP2IF = 0; + } +} + + +/* + * measure tilt and update dot matrix display + * + * This program uses the times recorded by the measurePW() ISR to + * calculate pulse width. The pulse width is then translated into a tilt + * measurement and finally displayed on the dot matrix display. + */ +void +main(void) +{ + unsigned char periodX = 0; + unsigned char pulseX = 0; + unsigned char periodY = 0; + unsigned char pulseY = 0; + int tiltX; + int tiltY; + + /* + * Setup I/O ports + * RC0 and RC3 outputs, the rest are inputs. + * RA5 output (power to ADXL202) + * Set port C outputs high to turn off the LEDs + */ + TRISC = 0b11110110; + RA5 = 1; + PORTC = 0xff; + + /* + * Setup the I/O ports that control the dot matrix display + */ + TRISA = 0b11000000; + TRISB = 0b11100000; + TRISD = 0b10000000; + ADCON1 = 0x06; /* disable ADC so that port A is digital I/O */ + PORTD = 0; /* turn off all rows */ + PORTB = 0xff; /* turn off all columns */ + PORTA = 0xff; /* turn off all columns */ + + /* configure timer1 + * 1:1 prescale + * Internal clock (Fosc/4) + * Enabled + */ + T1CON = 0b00000001; + + /* + * configure capture registers + * capture on rising edge + */ + CCP1CON = 0b00000101; + CCP2CON = 0b00000101; + + /* + * clear sync flag + */ + PWSyncX = 0; + PWSyncY = 0; + + /* + * enable interrupts + */ + PEIE = 1; + CCP1IE = 1; + CCP2IE = 1; + ei(); + + /* + * main loop + */ + for (;;) + { + /* + * kick watchdog + */ + CLRWDT(); + + if (PWSyncX > 0) + { + /* + * Test for easy calculations + * i.e., no counter roll over during the measurment + */ + if (PeriodEndX > PeriodStartX) + { + if (PulseEndX > PeriodStartX) + { + /* + * no roll over, so proceed + */ + periodX = PeriodEndX - PeriodStartX; + pulseX = PulseEndX - PeriodStartX; + + periodX = (periodX / 2) + 9; /* offset = 9 */ + tiltX = (periodX) - pulseX; + + /* + * turn off all rows and then figure out which row to turn + * on based on the tilt + */ + PORTD = 0; + if (tiltX < -5) + { + RD6 = 1; + } + else if (tiltX < -4) + { + RD5 = 1; + } + else if (tiltX < -2) + { + RD4 = 1; + } + else if (tiltX > 5) + { + RD0 = 1; + } + else if (tiltX > 4) + { + RD1 = 1; + } + else if (tiltX > 2) + { + RD2 = 1; + } + else + { + RD3 = 1; + } + } + } + PWSyncX = 0; + } + + if (PWSyncY > 0) + { + /* + * Test for easy calculations + * i.e., no counter roll over during the measurment + */ + if (PeriodEndY > PeriodStartY) + { + if (PulseEndY > PeriodStartY) + { + /* + * no roll over, so proceed + */ + periodY = PeriodEndY - PeriodStartY; + pulseY = PulseEndY - PeriodStartY; + + periodY = (periodY / 2) - 1; /* offset = -1 */ + tiltY = (periodY) - pulseY; + + /* + * turn off all columns then figure out which column + * to turn on based on the tilt + */ + PORTA = PORTA | 0b00111111; + PORTB = PORTB | 0b00011111; + if (tiltY < -5) + { + RB1 = 0; + } + else if (tiltY < -4) + { + RB0 = 0; + } + else if (tiltY < -2) + { + RA4 = 0; + } + else if (tiltY > 5) + { + RA0 = 0; + } + else if (tiltY > 4) + { + RA1 = 0; + } + else if (tiltY > 2) + { + RA2 = 0; + } + else + { + RA3 = 0; + } + } + } + PWSyncY = 0; + } + } +} + diff --git a/test/picc/test.h b/test/picc/test.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/test/picc/test.h diff --git a/test/picc/test.piklab b/test/picc/test.piklab new file mode 100644 index 0000000..c3424f7 --- /dev/null +++ b/test/picc/test.piklab @@ -0,0 +1,85 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>16F877</device> + <files> + <item>test.c</item> + </files> + <description/> + <version>0.1</version> + <tool>picclite</tool> + <is_library>true</is_library> + <opened_files> + <item>test.c</item> + </opened_files> + </general> + <compiler> + <custom_options/> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>--ERRFORMAT</item> + <item>--WARNFORMAT</item> + <item>--MSGFORMAT</item> + <item>--CHIP=%DEVICE</item> + <item>--IDE=mplab</item> + <item>-Q</item> + <item>-S</item> + <item>-I$(SRCPATH)</item> + <item>%I</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </compiler> + <assembler> + <custom_options/> + <warning_level>0</warning_level> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>--ERRFORMAT</item> + <item>--WARNFORMAT</item> + <item>--MSGFORMAT</item> + <item>--CHIP=%DEVICE</item> + <item>--IDE=mplab</item> + <item>-Q</item> + <item>-C</item> + <item>--ASMLIST</item> + <item>-I$(SRCPATH)</item> + <item>%I</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </assembler> + <linker> + <custom_options/> + <format>inhx32</format> + <has_custom_arguments>false</has_custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + <custom_arguments> + <item>--ERRFORMAT</item> + <item>--WARNFORMAT</item> + <item>--MSGFORMAT</item> + <item>--CHIP=%DEVICE</item> + <item>--IDE=mplab</item> + <item>-Q</item> + <item>-O%O</item> + <item>-M%MAP</item> + <item>-G%SYM</item> + <item>%OBJS</item> + <item>%LIBS</item> + </custom_arguments> + </linker> + <librarian> + <has_custom_arguments>false</has_custom_arguments> + <custom_options/> + <custom_arguments> + <item>r</item> + <item>%O</item> + <item>%OBJS</item> + <item>%LIBS</item> + </custom_arguments> + </librarian> +</piklab> diff --git a/test/sdcc/add.c b/test/sdcc/add.c new file mode 100644 index 0000000..3cc7636 --- /dev/null +++ b/test/sdcc/add.c @@ -0,0 +1,9 @@ +#include <pic16f873.h> + +extern unsigned char ms_delay; + +void test() { + ms_delay++; + PIR1 = 0; + PEIE = 1; +} diff --git a/test/sdcc/add_sdcc250.c b/test/sdcc/add_sdcc250.c new file mode 100644 index 0000000..9b4d2a3 --- /dev/null +++ b/test/sdcc/add_sdcc250.c @@ -0,0 +1,9 @@ +#include "sdcc250_pic16f873.h" + +extern unsigned char ms_delay; + +void test() { + ms_delay++; + PIR1 = 0; + PEIE = 1; +} diff --git a/test/sdcc/blink.piklab b/test/sdcc/blink.piklab new file mode 100644 index 0000000..5fa967a --- /dev/null +++ b/test/sdcc/blink.piklab @@ -0,0 +1,101 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>16F873</device> + <description/> + <version>0.1</version> + <tool>sdcc</tool> + <custom_linker_script/> + <files> + <item>add.c</item> + <item>blinker.c</item> + </files> + <is_library>true</is_library> + <opened_files> + <item>add.c</item> + <item>blinker.c</item> + </opened_files> + </general> + <sdcc> + <custom_options/> + <include_dir>/home/nicolas/prog/piklab/test/sdcc/</include_dir> + </sdcc> + <assembler> + <warning_level>0</warning_level> + <custom_options/> + <include_dir>/home/nicolas/prog/piklab/test/sdcc/</include_dir> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>-c</item> + <item>-I$(SRCPATH)</item> + <item>-p%DEVICE</item> + <item>-w0</item> + <item>%I</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </assembler> + <linker> + <hex_format>inhx32</hex_format> + <object_dir>/home/nicolas/prog/piklab/test/sdcc/</object_dir> + <custom_options>-Wl-r</custom_options> + <format>inhx32</format> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>-m%FAMILY</item> + <item>-%DEVICE</item> + <item>-V</item> + <item>--debug</item> + <item>-Wl-c</item> + <item>$LKR(-Wl-s%LKR)</item> + <item>-I$(SRCPATH)</item> + <item>-Wl-r</item> + <item>-o%O</item> + <item>%OBJS</item> + <item>%LIBS</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </linker> + <compiler> + <custom_options/> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>-m%FAMILY</item> + <item>-%DEVICE</item> + <item>-V</item> + <item>--debug</item> + <item>-I$(SRCPATH)</item> + <item>-c</item> + <item>%I</item> + <item>-Wa-g</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </compiler> + <bin_to_hex> + <includes>$(SRCPATH)</includes> + <custom_options/> + </bin_to_hex> + <object_viewer> + <includes>$(SRCPATH)</includes> + <custom_options/> + </object_viewer> + <disassembler> + <includes>$(SRCPATH)</includes> + <custom_options/> + </disassembler> + <librarian> + <has_custom_arguments>false</has_custom_arguments> + <custom_options/> + <custom_arguments> + <item>-c</item> + <item>%O</item> + <item>%OBJS</item> + <item>%LIBS</item> + </custom_arguments> + </librarian> +</piklab> diff --git a/test/sdcc/blinker.c b/test/sdcc/blinker.c new file mode 100644 index 0000000..f6a7355 --- /dev/null +++ b/test/sdcc/blinker.c @@ -0,0 +1,35 @@ +#define __16F873 +#include <pic16f873.h> + +typedef unsigned int word; +word at 0x2007 CONFIG = _CP_OFF & _WDT_OFF & _BODEN_ON & \ + _PWRTE_ON & _HS_OSC & _WRT_ENABLE_ON & \ + _LVP_OFF & _DEBUG_OFF & _CPD_OFF; + +unsigned char count, x = 2; +unsigned char ms_delay = 0; + +void Intr() interrupt 0 { + ms_delay++; + PIR1 = 0; + PEIE = 1; +} + +void main() { + NOT_RBPU = 0; + T2CON = 0x7f; + GIE = 1; + PEIE = 1; + //INTCON=0xc0; + PIR1 = 0; + PIE1 = 2; + PR2 = 200; + + TRISB = 0; + ms_delay = 0; + while(1) { + count = ms_delay; + x = PIE1; + PORTB = (count & 0xf0) | (x & 0xf); + } +} diff --git a/test/sdcc/blinker.h b/test/sdcc/blinker.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/test/sdcc/blinker.h diff --git a/test/sdcc/blinker.piklab b/test/sdcc/blinker.piklab new file mode 100644 index 0000000..bd2c19e --- /dev/null +++ b/test/sdcc/blinker.piklab @@ -0,0 +1,78 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>16F873</device> + <description/> + <version>0.1</version> + <tool>sdcc</tool> + <custom_linker_script/> + <files> + <item>add.c</item> + <item>blinker.c</item> + </files> + <opened_files> + <item>add.c</item> + <item>blinker.c</item> + </opened_files> + </general> + <sdcc> + <custom_options/> + <include_dir>/home/nicolas/prog/piklab/test/sdcc/</include_dir> + </sdcc> + <assembler> + <warning_level>0</warning_level> + <custom_options/> + <include_dir>/home/nicolas/prog/piklab/test/sdcc/</include_dir> + <includes>$(SRCPATH)</includes> + </assembler> + <linker> + <hex_format>inhx32</hex_format> + <object_dir>/home/nicolas/prog/piklab/test/sdcc/</object_dir> + <custom_options>-Wl-r</custom_options> + <format>inhx32</format> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>-m%FAMILY</item> + <item>-%DEVICE</item> + <item>-V</item> + <item>--debug</item> + <item>-Wl-c</item> + <item>$LKR(-Wl-s%LKR)</item> + <item>-I$(SRCPATH)</item> + <item>-Wl-r</item> + <item>-o%O</item> + <item>%OBJS</item> + <item>%LIBS</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </linker> + <compiler> + <custom_options/> + <has_custom_arguments>false</has_custom_arguments> + <custom_arguments> + <item>-m%FAMILY</item> + <item>-%DEVICE</item> + <item>-V</item> + <item>-I$(SRCPATH)</item> + <item>-c</item> + <item>%I</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </compiler> + <bin_to_hex> + <includes>$(SRCPATH)</includes> + <custom_options/> + </bin_to_hex> + <object_viewer> + <includes>$(SRCPATH)</includes> + <custom_options/> + </object_viewer> + <disassembler> + <includes>$(SRCPATH)</includes> + <custom_options/> + </disassembler> +</piklab> diff --git a/test/sdcc/blinker_sdcc250.c b/test/sdcc/blinker_sdcc250.c new file mode 100644 index 0000000..ffe2dc8 --- /dev/null +++ b/test/sdcc/blinker_sdcc250.c @@ -0,0 +1,35 @@ +#define __16F873 +#include "sdcc250_pic16f873.h" + +typedef unsigned int word; +word at 0x2007 CONFIG = _CP_OFF & _WDT_OFF & _BODEN_ON & \ + _PWRTE_ON & _HS_OSC & _WRT_ENABLE_ON & \ + _LVP_OFF & _DEBUG_OFF & _CPD_OFF; + +unsigned char count, x = 2; +unsigned char ms_delay; + +void Intr() interrupt 0 { + ms_delay++; + PIR1 = 0; + PEIE = 1; +} + +void main() { + NOT_RBPU = 0; + T2CON = 0x7f; + GIE = 1; + PEIE = 1; + //INTCON=0xc0; + PIR1 = 0; + PIE1 = 2; + PR2 = 200; + + TRISB = 0; + ms_delay = 0; + while(1) { + count = ms_delay; + x = PIE1; + PORTB = (count & 0xf0) | (x & 0xf); + } +} diff --git a/test/sdcc/blinker_sdcc250.piklab b/test/sdcc/blinker_sdcc250.piklab new file mode 100644 index 0000000..abd565c --- /dev/null +++ b/test/sdcc/blinker_sdcc250.piklab @@ -0,0 +1,50 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>16F873</device> + <files> + <item>blinker.c</item> + <item>add.c</item> + </files> + <description/> + <version>0.1</version> + <tool>sdcc</tool> + <custom_linker_script/> + <opened_files> + <item>blinker.c</item> + </opened_files> + </general> + <sdcc> + <custom_options/> + <include_dir>/home/nicolas/prog/piklab/test/sdcc/</include_dir> + </sdcc> + <assembler> + <warning_level>0</warning_level> + <custom_options/> + <include_dir>/home/nicolas/prog/piklab/test/sdcc/</include_dir> + <includes>$(SRCPATH)</includes> + </assembler> + <linker> + <hex_format>inhx32</hex_format> + <object_dir>/home/nicolas/prog/piklab/test/sdcc/</object_dir> + <custom_options>-r</custom_options> + <format>inhx32</format> + <includes>$(SRCPATH)</includes> + </linker> + <compiler> + <includes>$(SRCPATH)</includes> + <custom_options>-Wl-r</custom_options> + </compiler> + <bin_to_hex> + <includes>$(SRCPATH)</includes> + <custom_options/> + </bin_to_hex> + <object_viewer> + <includes>$(SRCPATH)</includes> + <custom_options/> + </object_viewer> + <disassembler> + <includes>$(SRCPATH)</includes> + <custom_options/> + </disassembler> +</piklab> diff --git a/test/sdcc/sdcc250_16f783.lkr b/test/sdcc/sdcc250_16f783.lkr new file mode 100644 index 0000000..755ee4f --- /dev/null +++ b/test/sdcc/sdcc250_16f783.lkr @@ -0,0 +1,29 @@ +// Sample linker command file for 16F873 +// $Id: sdcc250_16f783.lkr 1399 2006-10-01 14:01:23Z azhyd $ + +LIBPATH . + +CODEPAGE NAME=vectors START=0x0 END=0x4 PROTECTED +CODEPAGE NAME=page0 START=0x5 END=0x7FF +CODEPAGE NAME=page1 START=0x800 END=0xFFF +CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED +CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED +CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED + +DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED +DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED +DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED +DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED + +DATABANK NAME=gpr0 START=0x20 END=0x7F +SHAREBANK NAME=gpr0 START=0x120 END=0x17F + +SHAREBANK NAME=gpr1 START=0xA0 END=0xFF +SHAREBANK NAME=gpr1 START=0x1A0 END=0x1FF + +SECTION NAME=STARTUP ROM=vectors // Reset and interrupt vectors +SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 +SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 +SECTION NAME=IDLOCS ROM=.idlocs // ID locations +SECTION NAME=CONFIG ROM=.config // Configuration bits location +SECTION NAME=DEEPROM ROM=eedata // Data EEPROM diff --git a/test/sdcc/sdcc250_pic16f873.h b/test/sdcc/sdcc250_pic16f873.h new file mode 100644 index 0000000..c4957b8 --- /dev/null +++ b/test/sdcc/sdcc250_pic16f873.h @@ -0,0 +1,505 @@ +// +// Register Declarations for Microchip 16F873 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.5 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F873_H +#define P16F873_H + +#define udata udata_shr + +#ifndef BIT_AT +#define BIT_AT(base,bitno) sbit at ((base<<3)+bitno) +#endif + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// +#pragma maxram 0x1FF + +#pragma memmap 0x0020 0x007f RAM 0x100 +#pragma memmap 0x00a0 0x00ff RAM 0x100 + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F873.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F873 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F873 +// 2. LIST directive in the source file +// LIST P=PIC16F873 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.12 01/12/00 Changed some bit names, a register name, configuration bits +// to match datasheet (DS30292B) +//1.11 10/18/98 Changes to file registers to match updated DOS +//1.10 08/17/98 Fixed typo in processor name, RCSTA and ADCON1 +//1.00 08/07/98 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F873 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +data at INDF_ADDR volatile char INDF; +sfr at TMR0_ADDR TMR0; +data at PCL_ADDR volatile char PCL; +sfr at STATUS_ADDR STATUS; +sfr at FSR_ADDR FSR; +sfr at PORTA_ADDR PORTA; +sfr at PORTB_ADDR PORTB; +sfr at PORTC_ADDR PORTC; +sfr at PCLATH_ADDR PCLATH; +sfr at INTCON_ADDR INTCON; +sfr at PIR1_ADDR PIR1; +sfr at PIR2_ADDR PIR2; +sfr at TMR1L_ADDR TMR1L; +sfr at TMR1H_ADDR TMR1H; +sfr at T1CON_ADDR T1CON; +sfr at TMR2_ADDR TMR2; +sfr at T2CON_ADDR T2CON; +sfr at SSPBUF_ADDR SSPBUF; +sfr at SSPCON_ADDR SSPCON; +sfr at CCPR1L_ADDR CCPR1L; +sfr at CCPR1H_ADDR CCPR1H; +sfr at CCP1CON_ADDR CCP1CON; +sfr at RCSTA_ADDR RCSTA; +sfr at TXREG_ADDR TXREG; +sfr at RCREG_ADDR RCREG; +sfr at CCPR2L_ADDR CCPR2L; +sfr at CCPR2H_ADDR CCPR2H; +sfr at CCP2CON_ADDR CCP2CON; +sfr at ADRESH_ADDR ADRESH; +sfr at ADCON0_ADDR ADCON0; + +sfr at OPTION_REG_ADDR OPTION_REG; +sfr at TRISA_ADDR TRISA; +sfr at TRISB_ADDR TRISB; +sfr at TRISC_ADDR TRISC; +sfr at PIE1_ADDR PIE1; +sfr at PIE2_ADDR PIE2; +sfr at PCON_ADDR PCON; +sfr at SSPCON2_ADDR SSPCON2; +sfr at PR2_ADDR PR2; +sfr at SSPADD_ADDR SSPADD; +sfr at SSPSTAT_ADDR SSPSTAT; +sfr at TXSTA_ADDR TXSTA; +sfr at SPBRG_ADDR SPBRG; +sfr at ADRESL_ADDR ADRESL; +sfr at ADCON1_ADDR ADCON1; + +sfr at EEDATA_ADDR EEDATA; +sfr at EEADR_ADDR EEADR; +sfr at EEDATH_ADDR EEDATH; +sfr at EEADRH_ADDR EEADRH; + +sfr at EECON1_ADDR EECON1; +sfr at EECON2_ADDR EECON2; +//----- STATUS Bits -------------------------------------------------------- + +BIT_AT(STATUS_ADDR,7) IRP; +BIT_AT(STATUS_ADDR,6) RP1; +BIT_AT(STATUS_ADDR,5) RP0; +BIT_AT(STATUS_ADDR,4) NOT_TO; +BIT_AT(STATUS_ADDR,3) NOT_PD; +BIT_AT(STATUS_ADDR,2) Z; +BIT_AT(STATUS_ADDR,1) DC; +BIT_AT(STATUS_ADDR,0) C; + +//----- INTCON Bits -------------------------------------------------------- + +BIT_AT(INTCON_ADDR,7) GIE; +BIT_AT(INTCON_ADDR,6) PEIE; +BIT_AT(INTCON_ADDR,5) T0IE; +BIT_AT(INTCON_ADDR,4) INTE; +BIT_AT(INTCON_ADDR,3) RBIE; +BIT_AT(INTCON_ADDR,2) T0IF; +BIT_AT(INTCON_ADDR,1) INTF; +BIT_AT(INTCON_ADDR,0) RBIF; + +//----- PIR1 Bits ---------------------------------------------------------- +BIT_AT(PIR1_ADDR,6) ADIF; +BIT_AT(PIR1_ADDR,5) RCIF; +BIT_AT(PIR1_ADDR,4) TXIF; +BIT_AT(PIR1_ADDR,3) SSPIF; +BIT_AT(PIR1_ADDR,2) CCP1IF; +BIT_AT(PIR1_ADDR,1) TMR2IF; +BIT_AT(PIR1_ADDR,0) TMR1IF; + +//----- PIR2 Bits ---------------------------------------------------------- + +BIT_AT(PIR2_ADDR,6) CMIF; +BIT_AT(PIR2_ADDR,4) EEIF; +BIT_AT(PIR2_ADDR,3) BCLIF; +BIT_AT(PIR2_ADDR,0) CCP2IF; + +//----- T1CON Bits --------------------------------------------------------- + +BIT_AT(T1CON_ADDR,5) T1CKPS1; +BIT_AT(T1CON_ADDR,4) T1CKPS0; +BIT_AT(T1CON_ADDR,3) T1OSCEN; +BIT_AT(T1CON_ADDR,2) NOT_T1SYNC; +BIT_AT(T1CON_ADDR,2) T1INSYNC; // Backward compatibility only +BIT_AT(T1CON_ADDR,2) T1SYNC; +BIT_AT(T1CON_ADDR,1) TMR1CS; +BIT_AT(T1CON_ADDR,0) TMR1ON; + +//----- T2CON Bits --------------------------------------------------------- + +BIT_AT(T2CON_ADDR,6) TOUTPS3; +BIT_AT(T2CON_ADDR,5) TOUTPS2; +BIT_AT(T2CON_ADDR,4) TOUTPS1; +BIT_AT(T2CON_ADDR,3) TOUTPS0; +BIT_AT(T2CON_ADDR,2) TMR2ON; +BIT_AT(T2CON_ADDR,1) T2CKPS1; +BIT_AT(T2CON_ADDR,0) T2CKPS0; + +//----- SSPCON Bits -------------------------------------------------------- + +BIT_AT(SSPCON_ADDR,7) WCOL; +BIT_AT(SSPCON_ADDR,6) SSPOV; +BIT_AT(SSPCON_ADDR,5) SSPEN; +BIT_AT(SSPCON_ADDR,4) CKP; +BIT_AT(SSPCON_ADDR,3) SSPM3; +BIT_AT(SSPCON_ADDR,2) SSPM2; +BIT_AT(SSPCON_ADDR,1) SSPM1; +BIT_AT(SSPCON_ADDR,0) SSPM0; + +//----- CCP1CON Bits ------------------------------------------------------- + +BIT_AT(CCP1CON_ADDR,5) CCP1X; +BIT_AT(CCP1CON_ADDR,4) CCP1Y; +BIT_AT(CCP1CON_ADDR,3) CCP1M3; +BIT_AT(CCP1CON_ADDR,2) CCP1M2; +BIT_AT(CCP1CON_ADDR,1) CCP1M1; +BIT_AT(CCP1CON_ADDR,0) CCP1M0; + +//----- RCSTA Bits --------------------------------------------------------- + +BIT_AT(RCSTA_ADDR,7) SPEN; +BIT_AT(RCSTA_ADDR,6) RX9; +BIT_AT(RCSTA_ADDR,6) RC9; // Backward compatibility only +BIT_AT(RCSTA_ADDR,6) NOT_RC8; // Backward compatibility only +BIT_AT(RCSTA_ADDR,6) RC8_9; // Backward compatibility only +BIT_AT(RCSTA_ADDR,5) SREN; +BIT_AT(RCSTA_ADDR,4) CREN; +BIT_AT(RCSTA_ADDR,3) ADDEN; +BIT_AT(RCSTA_ADDR,2) FERR; +BIT_AT(RCSTA_ADDR,1) OERR; +BIT_AT(RCSTA_ADDR,0) RX9D; +BIT_AT(RCSTA_ADDR,0) RCD8; // Backward compatibility only + +//----- CCP2CON Bits ------------------------------------------------------- + +BIT_AT(CCP2CON_ADDR,5) CCP2X; +BIT_AT(CCP2CON_ADDR,4) CCP2Y; +BIT_AT(CCP2CON_ADDR,3) CCP2M3; +BIT_AT(CCP2CON_ADDR,2) CCP2M2; +BIT_AT(CCP2CON_ADDR,1) CCP2M1; +BIT_AT(CCP2CON_ADDR,0) CCP2M0; + +//----- ADCON0 Bits -------------------------------------------------------- + +BIT_AT(ADCON0_ADDR,7) ADCS1; +BIT_AT(ADCON0_ADDR,6) ADCS0; +BIT_AT(ADCON0_ADDR,5) CHS2; +BIT_AT(ADCON0_ADDR,4) CHS1; +BIT_AT(ADCON0_ADDR,3) CHS0; +BIT_AT(ADCON0_ADDR,2) GO; +BIT_AT(ADCON0_ADDR,2) NOT_DONE; +BIT_AT(ADCON0_ADDR,2) GO_DONE; +BIT_AT(ADCON0_ADDR,0) ADON; + +//----- OPTION_REG Bits ---------------------------------------------------- + +BIT_AT(OPTION_REG_ADDR,7) NOT_RBPU; +BIT_AT(OPTION_REG_ADDR,6) INTEDG; +BIT_AT(OPTION_REG_ADDR,5) T0CS; +BIT_AT(OPTION_REG_ADDR,4) T0SE; +BIT_AT(OPTION_REG_ADDR,3) PSA; +BIT_AT(OPTION_REG_ADDR,2) PS2; +BIT_AT(OPTION_REG_ADDR,1) PS1; +BIT_AT(OPTION_REG_ADDR,0) PS0; + +//----- PIE1 Bits ---------------------------------------------------------- + +BIT_AT(PIE1_ADDR,6) ADIE; +BIT_AT(PIE1_ADDR,5) RCIE; +BIT_AT(PIE1_ADDR,4) TXIE; +BIT_AT(PIE1_ADDR,3) SSPIE; +BIT_AT(PIE1_ADDR,2) CCP1IE; +BIT_AT(PIE1_ADDR,1) TMR2IE; +BIT_AT(PIE1_ADDR,0) TMR1IE; + +//----- PIE2 Bits ---------------------------------------------------------- + +BIT_AT(PIE2_ADDR,4) EEIE; +BIT_AT(PIE2_ADDR,3) BCLIE; +BIT_AT(PIE2_ADDR,0) CCP2IE; + +//----- PCON Bits ---------------------------------------------------------- + +BIT_AT(PCON_ADDR,1) NOT_POR; +BIT_AT(PCON_ADDR,0) NOT_BO; +BIT_AT(PCON_ADDR,0) NOT_BOR; + +//----- SSPCON2 Bits -------------------------------------------------------- + +BIT_AT(SSPCON2_ADDR,7) GCEN; +BIT_AT(SSPCON2_ADDR,6) ACKSTAT; +BIT_AT(SSPCON2_ADDR,5) ACKDT; +BIT_AT(SSPCON2_ADDR,4) ACKEN; +BIT_AT(SSPCON2_ADDR,3) RCEN; +BIT_AT(SSPCON2_ADDR,2) PEN; +BIT_AT(SSPCON2_ADDR,1) RSEN; +BIT_AT(SSPCON2_ADDR,0) SEN; + +//----- SSPSTAT Bits ------------------------------------------------------- + +BIT_AT(SSPSTAT_ADDR,7) SMP; +BIT_AT(SSPSTAT_ADDR,6) CKE; +BIT_AT(SSPSTAT_ADDR,5) D; +BIT_AT(SSPSTAT_ADDR,5) I2C_DATA; +BIT_AT(SSPSTAT_ADDR,5) NOT_A; +BIT_AT(SSPSTAT_ADDR,5) NOT_ADDRESS; +BIT_AT(SSPSTAT_ADDR,5) D_A; +BIT_AT(SSPSTAT_ADDR,5) DATA_ADDRESS; +BIT_AT(SSPSTAT_ADDR,4) P; +BIT_AT(SSPSTAT_ADDR,4) I2C_STOP; +BIT_AT(SSPSTAT_ADDR,3) S; +BIT_AT(SSPSTAT_ADDR,3) I2C_START; +BIT_AT(SSPSTAT_ADDR,2) R; +BIT_AT(SSPSTAT_ADDR,2) I2C_READ; +BIT_AT(SSPSTAT_ADDR,2) NOT_W; +BIT_AT(SSPSTAT_ADDR,2) NOT_WRITE; +BIT_AT(SSPSTAT_ADDR,2) R_W; +BIT_AT(SSPSTAT_ADDR,2) READ_WRITE; +BIT_AT(SSPSTAT_ADDR,1) UA; +BIT_AT(SSPSTAT_ADDR,0) BF; + +//----- TXSTA Bits --------------------------------------------------------- + +BIT_AT(TXSTA_ADDR,7) CSRC; +BIT_AT(TXSTA_ADDR,6) TX9; +BIT_AT(TXSTA_ADDR,6) NOT_TX8; // Backward compatibility only +BIT_AT(TXSTA_ADDR,6) TX8_9; // Backward compatibility only +BIT_AT(TXSTA_ADDR,5) TXEN; +BIT_AT(TXSTA_ADDR,4) SYNC; +BIT_AT(TXSTA_ADDR,2) BRGH; +BIT_AT(TXSTA_ADDR,1) TRMT; +BIT_AT(TXSTA_ADDR,0) TX9D; +BIT_AT(TXSTA_ADDR,0) TXD8; // Backward compatibility only + +//----- ADCON1 Bits -------------------------------------------------------- + +BIT_AT(ADCON1_ADDR,7) ADFM; +BIT_AT(ADCON1_ADDR,3) PCFG3; +BIT_AT(ADCON1_ADDR,2) PCFG2; +BIT_AT(ADCON1_ADDR,1) PCFG1; +BIT_AT(ADCON1_ADDR,0) PCFG0; + +//----- EECON1 Bits -------------------------------------------------------- + +BIT_AT(EECON1_ADDR,7) EEPGD; +BIT_AT(EECON1_ADDR,3) WRERR; +BIT_AT(EECON1_ADDR,2) WREN; +BIT_AT(EECON1_ADDR,1) WR; +BIT_AT(EECON1_ADDR,0) RD; + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'19F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x0FCF +#define _CP_HALF 0x1FDF +#define _CP_UPPER_256 0x2FEF +#define _CP_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _DEBUG_OFF 0x3FFF +#define _WRT_ENABLE_ON 0x3FFF +#define _WRT_ENABLE_OFF 0x3DFF +#define _CPD_ON 0x3EFF +#define _CPD_OFF 0x3FFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST +#endif diff --git a/test/sdcc/standalone_blinker.c b/test/sdcc/standalone_blinker.c new file mode 100644 index 0000000..b4049e6 --- /dev/null +++ b/test/sdcc/standalone_blinker.c @@ -0,0 +1,35 @@ +#define __16F873 +#include "pic16f873.h" + +typedef unsigned int word; +word at 0x2007 __CONFIG = _CP_OFF & _WDT_OFF & _BODEN_ON & \ + _PWRTE_ON & _HS_OSC & _WRT_ENABLE_ON & \ + _LVP_OFF & _DEBUG_OFF & _CPD_OFF; + +unsigned char count, x; +unsigned char ms_delay; + +void Intr() interrupt 0 { + ms_delay++; + PIR1 = 0; + PEIE = 1; +} + +void main() { + NOT_RBPU=0; + T2CON=0x7f; + GIE = 1; + PEIE = 1; + //INTCON=0xc0; + PIR1 = 0; + PIE1 = 2; + PR2 = 200; + + TRISB = 0; + ms_delay = 0; + while(1) { + count = ms_delay; + x = PIE1; + PORTB = (count & 0xf0) | (x & 0xf); + } +} diff --git a/test/sdcc18/test18.c b/test/sdcc18/test18.c new file mode 100644 index 0000000..00dc375 --- /dev/null +++ b/test/sdcc18/test18.c @@ -0,0 +1,14 @@ +#include <pic18f452.h> + +void main(void) +{ + float f = TRISA; + int a = TRISB; + LATA = 0xFF; + LATAbits.LATA1 = 0; +// UIE = 0x55; + f /= a; + a = f; + TRISA = a; + while(1); +} diff --git a/test/sdcc18/test18.piklab b/test/sdcc18/test18.piklab new file mode 100644 index 0000000..d9e688d --- /dev/null +++ b/test/sdcc18/test18.piklab @@ -0,0 +1,17 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>18F452</device> + <tool>sdcc</tool> + <files> + <item>test18.c</item> + </files> + <opened_files> + <item>test18.c</item> + </opened_files> + <watched_registers> + <item>0 2 </item> + </watched_registers> + </general> + <editors/> +</piklab> diff --git a/test/sdcc18/usart_test.c b/test/sdcc18/usart_test.c new file mode 100644 index 0000000..1b611d9 --- /dev/null +++ b/test/sdcc18/usart_test.c @@ -0,0 +1,105 @@ +// read and write eeprom of PIC18F2550 (and 18F2455, 18F4455, 18F4550) +// EEPROM size is 256 bytes +// (c) Raphael Wimmer. Licensed under GNU GPL v2 or higher +#include <pic18f452.h> +//#include <pic18fregs.h> +#include <stdio.h> +#include <usart.h> +#include <adc.h> + +code char at __CONFIG1H config1h = 0xFF & _OSC_XT_1H & _OSCS_OFF_1H; +code char at __CONFIG2L config2l = 0xFF & _PUT_ON_2L & _BODEN_OFF_2L & _BODENV_2_7V_2L; +code char at __CONFIG2H config2h = 0xFF & _WDT_OFF_2H; +code char at __CONFIG3H config3h = 0xFF & _CCP2MUX_RC1_3H; +code char at __CONFIG4L config4l = 0xFF & _LVP_OFF_4L & _BACKBUG_ON_4L & _STVR_OFF_4L; +code char at __CONFIG5L config5l = 0xFF & _CP_0_OFF_5L & _CP_1_OFF_5L; +code char at __CONFIG5H config5h = 0xFF & _CPD_OFF_5H & _CPB_OFF_5H; +code char at __CONFIG6L config6l = 0xFF & _WRT_0_OFF_6L & _WRT_1_OFF_6L; +code char at __CONFIG6H config6h = 0xFF & _WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H; +code char at __CONFIG7L config7l = 0xFF & _EBTR_0_OFF_7L & _EBTR_1_OFF_7L; +code char at __CONFIG7H config7h = 0xFF & _EBTRB_OFF_7H; + +#pragma stack 0x300 0xff // set 64 byte stack at 0x300, needed by sdcc + +static void isr(void) interrupt 1 { +/* +n Interrupt Vector Interrupt Vector Address +0 RESET vector 0x000000 +1 HIGH priority interrupts 0x000008 +2 LOW priority interrupts 0x000018 +*/ +} + +void ee_write_byte(unsigned char address, unsigned char *_data){ + + EEDATA = *_data; + EEADR = address; + // start write sequence as described in datasheet, page 91 + EECON1bits.EEPGD = 0; + EECON1bits.CFGS = 0; + EECON1bits.WREN = 1; // enable writes to data EEPROM + INTCONbits.GIE = 0; // disable interrupts + EECON2 = 0x55; + EECON2 = 0x0AA; + EECON1bits.WR = 1; // start writing + while(EECON1bits.WR){ + _asm nop _endasm;} + if(EECON1bits.WRERR){ + // printf("ERROR: writing to EEPROM failed!\n"); + } + EECON1bits.WREN = 0; + INTCONbits.GIE = 1; // enable interrupts +} + +void adc_start() { + + adc_open(ADC_CHN_1, ADC_FOSC_4, ADC_CFG_5A_0R, ADC_FRM_RJUST); + while (adc_busy()) ; + adc_read(); +//unsigned char channel, unsigned char fosc, unsigned char pcfg, unsigned char config + +} + +void ee_read_byte(unsigned char address, unsigned char *_data){ + EEADR = address; + EECON1bits.CFGS = 0; + EECON1bits.EEPGD = 0; + EECON1bits.RD = 1; + *_data = EEDATA; +} + +void initUsart() +{ + usart_open( // Use USART library to initialise the hardware + USART_TX_INT_OFF + & USART_RX_INT_OFF + & USART_BRGH_HIGH + & USART_ASYNCH_MODE + & USART_EIGHT_BIT, + 10 // '10' = 115200 Baud with 20 MHz oscillator and BRGH=1 + ); + stdout = STREAM_USART; +} + + + +// very simple example. use on an erased eeprom + +void main(){ + + char save_me = 'c'; + char from_eeprom; + adc_start(); + initUsart(); + + printf("E"); + ee_read_byte(0x00, &from_eeprom); + printf("%c", from_eeprom); + + ee_write_byte(0x00, &save_me); + printf("%c", save_me); + + ee_read_byte(0x00, &from_eeprom); + printf("%c", from_eeprom); +while (1){} +} diff --git a/test/sdcc18/usart_test.piklab b/test/sdcc18/usart_test.piklab new file mode 100644 index 0000000..71da3cf --- /dev/null +++ b/test/sdcc18/usart_test.piklab @@ -0,0 +1,51 @@ +<!DOCTYPE piklab> +<piklab> + <general> + <device>18F452</device> + <tool>sdcc</tool> + <files> + <item>usart_test.c</item> + <item>/usr/share/sdcc/lib/pic16/libio18f452.lib</item> + <item>/usr/share/sdcc/lib/pic16/libc18f.lib</item> + </files> + <description/> + <version>0.1</version> + </general> + <compiler> + <has_custom_arguments>false</has_custom_arguments> + <custom_options/> + <custom_arguments> + <item>-m%FAMILY</item> + <item>-%DEVICE</item> + <item>-V</item> + <item>--debug</item> + <item>-I$(SRCPATH)</item> + <item>-c</item> + <item>%I</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </compiler> + <linker> + <has_custom_arguments>false</has_custom_arguments> + <custom_options/> + <format>inhx32</format> + <custom_arguments> + <item>-m%FAMILY</item> + <item>-%DEVICE</item> + <item>-V</item> + <item>--debug</item> + <item>-Wl-c</item> + <item>$LKR(-Wl-s%LKR)</item> + <item>-I$(SRCPATH)</item> + <item>-o%O</item> + <item>%OBJS</item> + <item>%LIBS</item> + </custom_arguments> + <includes> + <item>$(SRCPATH)</item> + </includes> + </linker> + <editors/> +</piklab> diff --git a/test/test_hex_32/test_16F871_inhx32.hex b/test/test_hex_32/test_16F871_inhx32.hex new file mode 100644 index 0000000..a872486 --- /dev/null +++ b/test/test_hex_32/test_16F871_inhx32.hex @@ -0,0 +1,271 @@ +:020000040000FA +:10000000000000308A001A280528F4000308F500D3 +:10001000F10B14280A30F10072082F3AF200850023 +:1000200073083F3AF30086000B1175088300F40E45 +:10003000740E090081018B0185018601831603136B +:1000400085018601D530810006309F00831203139D +:100050008B168B172530F2001530F3000A30F100B3 +:10006000302800340034FF3FFF3FFF3FFF3FFF3F9A +:10007000FF3FFF3FFF3FFF3FFF3FFF3FFF3FFF3F90 +:10008000FF3FFF3FFF3FFF3FFF3FFF3FFF3FFF3F80 +:10009000FF3FFF3FFF3FFF3FFF3FFF3FFF3FFF3F70 +:1000A000FF3FFF3FFF3FFF3FFF3FFF3FFF3FFF3F60 +:1000B000FF3FFF3FFF3FFF3FFF3FFF3FFF3FFF3F50 +:1000C000FF3FFF3FFF3FFF3FFF3FFF3FFF3FFF3F40 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HEX FILES (10F200 12C508A 16F877 17C42A 18F452 30F2010): + - for each devices with hex file from "dummy_hex_32" directory: + * load with correct device type: display should be as described in "dummy_hex.txt" + * save with same hex format: check the file is the same + * optionnally: load with incorrect device type: should not crash (may warn about incorrect memory ranges) + +2. STANDALONE ASM FILES: + - load "test_asm_standalone.asm" and compile + +3. PROJECT: + - load project "test_project" and compile + - save/create new: #### TODO + +3. GUI + COMMAND-LINE PROGRAMMING (serial + USB ICD2 with 16F871 and 18F452): + - for each available devices with hex file from "test_hex_32" directory: + * connect: check correct ids are detected + * blank: should be ok + * blank_check: should be ok + * load hex file + * verify: should fail + * program: should be ok + * verify: should be ok (should warn if some blocks are protected) + * blank_check: should fail + * release reset: should run program + * hold reset: should stop program + * read: should be ok + * verify: should be ok |