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| author | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2011-12-16 09:57:30 -0600 |
|---|---|---|
| committer | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2011-12-16 09:57:30 -0600 |
| commit | ad1fc5fc8eadb9b63e8767e57ac41cbac84f7eb7 (patch) | |
| tree | c47273eb6595f763c282d33fb89affe1f8866120 /src/devices/pic/prog/pic_debug.cpp | |
| parent | 9d6927a7d6a543332f828bffedf65eecf6774c6d (diff) | |
| download | piklab-ad1fc5fc8eadb9b63e8767e57ac41cbac84f7eb7.tar.gz piklab-ad1fc5fc8eadb9b63e8767e57ac41cbac84f7eb7.zip | |
Revert "Rename a number of old tq methods that are no longer tq specific"
This reverts commit 9d6927a7d6a543332f828bffedf65eecf6774c6d.
Diffstat (limited to 'src/devices/pic/prog/pic_debug.cpp')
| -rw-r--r-- | src/devices/pic/prog/pic_debug.cpp | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/devices/pic/prog/pic_debug.cpp b/src/devices/pic/prog/pic_debug.cpp index eef84cc..9434a74 100644 --- a/src/devices/pic/prog/pic_debug.cpp +++ b/src/devices/pic/prog/pic_debug.cpp @@ -20,7 +20,7 @@ Register::TypeData Debugger::PicBase::registerTypeData(const TQString &name) con return Register::TypeData(rdata.sfrs[name].address, rdata.nbChars()); } -bool Debugger::PicBase::updatePortStatus(uint index, TQMap<uint, Device::PortBitData> &bits) +bool Debugger::PicBase::updatePorttqStatus(uint index, TQMap<uint, Device::PortBitData> &bits) { const Pic::RegistersData &rdata = device()->registersData(); BitValue tris; @@ -65,7 +65,7 @@ const Debugger::PicBase &Debugger::PicSpecific::base() const return static_cast<PicBase &>(_base); } -bool Debugger::PicSpecific::updateStatus() +bool Debugger::PicSpecific::updatetqStatus() { if ( !Debugger::manager->readRegister(base().pcTypeData()) ) return false; if ( !Debugger::manager->readRegister(base().registerTypeData("STATUS")) ) return false; @@ -86,15 +86,15 @@ TQString Debugger::P16FSpecific::statusString() const uint bank = (status.bit(5) ? 1 : 0) + (status.bit(6) ? 2 : 0); BitValue wreg = Register::list().value(wregTypeData()); return TQString("W:%1 %2 %3 %4 PC:%5 Bank:%6") - .arg(toHexLabel(wreg, rdata.nbChars())).arg(status.bit(2) ? "Z" : "z") - .arg(status.bit(1) ? "DC" : "dc").arg(status.bit(0) ? "C" : "c") - .arg(toHexLabel(_base.pc(), device().nbCharsAddress())).arg(bank); + .tqarg(toHexLabel(wreg, rdata.nbChars())).tqarg(status.bit(2) ? "Z" : "z") + .tqarg(status.bit(1) ? "DC" : "dc").tqarg(status.bit(0) ? "C" : "c") + .tqarg(toHexLabel(_base.pc(), device().nbCharsAddress())).tqarg(bank); } //---------------------------------------------------------------------------- -bool Debugger::P18FSpecific::updateStatus() +bool Debugger::P18FSpecific::updatetqStatus() { - if ( !PicSpecific::updateStatus() ) return false; + if ( !PicSpecific::updatetqStatus() ) return false; if ( !Debugger::manager->readRegister(base().registerTypeData("BSR")) ) return false; return true; } @@ -111,8 +111,8 @@ TQString Debugger::P18FSpecific::statusString() const BitValue bsr = Register::list().value(base().registerTypeData("BSR")); BitValue wreg = Register::list().value(wregTypeData()); return TQString("W:%1 %2 %3 %4 %5 %6 PC:%7 Bank:%8") - .arg(toHexLabel(wreg, rdata.nbChars())).arg(status.bit(4) ? "N" : "n") - .arg(status.bit(3) ? "OV" : "ov").arg(status.bit(2) ? "Z" : "z") - .arg(status.bit(1) ? "DC" : "dc").arg(status.bit(0) ? "C" : "c") - .arg(toHexLabel(base().pc(), device().nbCharsAddress())).arg(toLabel(bsr)); + .tqarg(toHexLabel(wreg, rdata.nbChars())).tqarg(status.bit(4) ? "N" : "n") + .tqarg(status.bit(3) ? "OV" : "ov").tqarg(status.bit(2) ? "Z" : "z") + .tqarg(status.bit(1) ? "DC" : "dc").tqarg(status.bit(0) ? "C" : "c") + .tqarg(toHexLabel(base().pc(), device().nbCharsAddress())).tqarg(toLabel(bsr)); } |