Added KDE3 version of PikLab

git-svn-id: svn://anonsvn.kde.org/home/kde/branches/trinity/applications/piklab@1095639 283d02a7-25f6-0310-bc7c-ecb5cbfe19da

574 files changed, 150750 insertions, 0 deletions

diff --git a/src/devices/Makefile.am b/src/devices/Makefile.am
new file mode 100644
index 0000000..00ec7c1
--- /dev/null
+++ b/src/devices/Makefile.am
@@ -0,0 +1 @@
+SUBDIRS = base gui pic mem24 list
diff --git a/src/devices/base/Makefile.am b/src/devices/base/Makefile.am
new file mode 100644
index 0000000..836da68
--- /dev/null
+++ b/src/devices/base/Makefile.am
@@ -0,0 +1,9 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+noinst_LTLIBRARIES = libdevicebase.la
+libdevicebase_la_LDFLAGS = $(all_libraries)
+libdevicebase_la_SOURCES = generic_device.cpp hex_buffer.cpp generic_memory.cpp \
+		register.cpp device_group.cpp
+
+
diff --git a/src/devices/base/base.pro b/src/devices/base/base.pro
new file mode 100644
index 0000000..f74efc6
--- /dev/null
+++ b/src/devices/base/base.pro
@@ -0,0 +1,6 @@
+STOPDIR = ../../..
+include($${STOPDIR}/lib.pro)
+
+TARGET   = devicebase
+HEADERS += generic_device.h hex_buffer.h generic_memory.h device_group.h register.h
+SOURCES += generic_device.cpp hex_buffer.cpp generic_memory.cpp register.cpp
diff --git a/src/devices/base/device_group.cpp b/src/devices/base/device_group.cpp
new file mode 100644
index 0000000..df230d1
--- /dev/null
+++ b/src/devices/base/device_group.cpp
@@ -0,0 +1,362 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "device_group.h"
+
+#if !defined(NO_KDE)
+#  include <qpainter.h>
+#  include <kglobal.h>
+
+QColor Device::statusColor(Status status)
+{
+  switch (status.type()) {
+    case Status::Future:         return Qt::blue;
+    case Status::InProduction:   return Qt::green;
+    case Status::Mature:
+    case Status::NotRecommended: return QColor("orange");
+    case Status::EOL:            return Qt::red;
+    case Status::Unknown:
+    case Status::Nb_Types: break;
+  }
+  return Qt::black;
+}
+
+QString coloredString(const QString &text, QColor color)
+{
+  return QString("<font color=\"") + color.name() + "\">" + text + "</font>";
+}
+
+QString supportedString(bool supported)
+{
+  return coloredString(supported ? i18n("Supported") : i18n("Unsupported"),
+                       supported ? Qt::green :  Qt::red);
+}
+
+class Tick {
+public:
+  Tick() {}
+  Tick(double value, double oValue) {
+    s = KGlobal::locale()->formatNumber(value, 1);
+    min = oValue;
+  }
+  QString s;
+  double min;
+};
+
+class TickMap : public QMap<double, Tick>
+{
+public:
+  TickMap() {}
+  void add(double value, double oValue) {
+    insert(value, Tick(value, oValue), false);
+    (*this)[value].min = QMIN((*this)[value].min, oValue);
+  }
+};
+
+QPixmap drawGraph(const QValueVector<Device::RangeBox> &boxes)
+{
+  const uint w = 300, h = 200;
+  QPixmap pixmap(w, h);
+  pixmap.fill(Qt::white);
+  QPainter p(&pixmap);
+  QFontMetrics f(p.font());
+  TickMap xTicks, yTicks;
+  xTicks.add(0.0, 0.0);
+  yTicks.add(0.0, 0.0);
+  for (uint i=0; i<boxes.count(); i++) {
+//    qDebug("box #%i: %f=[%f %f] %f=[%f %f]", i, boxes[i].start.x, boxes[i].start.yMin,
+//           boxes[i].start.yMax, boxes[i].end.x, boxes[i].end.yMin, boxes[i].end.yMax);
+    xTicks.add(boxes[i].start.x, boxes[i].start.yMin);
+    xTicks.add(boxes[i].start.x, boxes[i].start.yMax);
+    xTicks.add(boxes[i].end.x, boxes[i].end.yMin);
+    xTicks.add(boxes[i].end.x, boxes[i].end.yMax);
+    yTicks.add(boxes[i].start.yMin, boxes[i].start.x);
+    yTicks.add(boxes[i].start.yMax, boxes[i].start.x);
+    yTicks.add(boxes[i].end.yMin, boxes[i].end.x);
+    yTicks.add(boxes[i].end.yMax, boxes[i].end.x);
+  }
+  double xMax = 0.0, yMax = 0.0;
+  int xStart = 0;
+  int yStart = h-1 - f.lineSpacing();
+  TickMap::const_iterator it = xTicks.begin();
+  for (; it!=xTicks.end(); ++it) {
+    xStart = QMAX(xStart, f.width(it.data().s));
+    xMax = QMAX(xMax, it.key());
+  }
+  for (it = yTicks.begin(); it!=yTicks.end(); ++it)
+    yMax = QMAX(yMax, it.key());
+  int xEnd = w-1 - f.width(xTicks[xMax].s)/2;
+  QRect rect = f.boundingRect(yTicks[yMax].s);
+  int yEnd = rect.height()/2;
+
+  // draw boxes
+  p.setPen(Qt::lightGray);
+  p.setBrush(Qt::lightGray);
+  for (uint i=0; i<boxes.count(); i++) {
+    double ax = double(xEnd - xStart)/xMax;
+    double ay = double(yEnd - yStart)/yMax;
+    QPointArray pa(4);
+    pa.setPoint(0, qRound(ax*boxes[i].start.x), qRound(ay*boxes[i].start.yMin));
+    pa.setPoint(1, qRound(ax*boxes[i].end.x), qRound(ay*boxes[i].end.yMin));
+    pa.setPoint(2, qRound(ax*boxes[i].end.x), qRound(ay*boxes[i].end.yMax));
+    pa.setPoint(3, qRound(ax*boxes[i].start.x), qRound(ay*boxes[i].start.yMax));
+    pa.translate(xStart, yStart);
+    p.drawPolygon(pa);
+  }
+
+  // draw axis
+  p.setPen(Qt::black);
+  p.drawLine(xStart, yStart, w-1, yStart);
+  p.drawLine(xStart, yStart, xStart, 0);
+
+  // draw ticks and lines
+  p.setPen(Qt::DotLine);
+  for (it = yTicks.begin(); it!=yTicks.end(); ++it) {
+    int y1 = yStart + qRound(it.key()*(yEnd-yStart)/yMax);
+    QRect rect = f.boundingRect(it.data().s);
+    p.drawText(xStart/2-rect.width()/2 , y1+rect.height()/2, it.data().s);
+    int xmin = xStart + qRound(it.data().min*(xEnd-xStart)/xMax);
+    p.drawLine(xStart, y1, xmin, y1);
+  }
+  for (it = xTicks.begin(); it!=xTicks.end(); ++it) {
+    int x1 = xStart + qRound(it.key()*(xEnd-xStart)/xMax);
+    QRect rect = f.boundingRect(it.data().s);
+    p.drawText(x1-rect.width()/2, h-1, it.data().s);
+    int ymin = yStart + qRound(it.data().min*(yEnd-yStart)/yMax);
+    p.drawLine(x1, yStart, x1, ymin);
+  }
+
+  return pixmap;
+}
+
+QPixmap Device::vddGraph(const QString &xLabel, const QString &yLabel,
+                         const QValueVector<Device::RangeBox> &boxes)
+{
+  uint sp = 10;
+  QPixmap graph = drawGraph(boxes);
+  QPainter p;
+  QFontMetrics f(p.font());
+  QPixmap pixmap(graph.width() + sp + f.width(xLabel), graph.height() + sp + f.lineSpacing());
+  pixmap.fill(Qt::white);
+  copyBlt(&pixmap, 0, f.lineSpacing() + sp, &graph, 0, 0, graph.width(), graph.height());
+  p.begin(&pixmap);
+  p.setPen(Qt::black);
+  p.drawText(0, f.lineSpacing(), yLabel);
+  p.drawText(pixmap.width()-1-f.width(xLabel), pixmap.height()-1, xLabel);
+  return pixmap;
+}
+
+const Device::Package *Device::barPackage(const char *name, const Device::Data &data)
+{
+  for (uint i=0; i<data.packages().count(); i++)
+    for (uint k=0; k<data.packages()[i].types.count(); k++)
+      if ( Package::TYPE_DATA[data.packages()[i].types[k]].name==name ) return &data.packages()[i];
+  return 0;
+}
+
+QPixmap Device::pinsGraph(const Device::Package &package)
+{
+  QPixmap pixmap;
+  QPainter p;
+  QFontMetrics fm(p.font());
+  uint nb = package.pins.count();
+  const int hspacing = 3, wspacing = 3, wmark = 10, wpin = 4;
+  int theight = fm.ascent() + (fm.ascent()%2==0 ? 1 : 0);
+  int height = hspacing + (nb/2)*(hspacing + theight);
+  int wnumber = fm.width("1");
+  wnumber = QMAX(wnumber, fm.width(QString::number(nb/2)));
+  wnumber = QMAX(wnumber, fm.width(QString::number(nb/2+1)));
+  wnumber = QMAX(wnumber, fm.width(QString::number(nb)));
+  int bwidth = 4*wspacing + 2*wnumber + wmark;
+  int lwidth = 0, rwidth = 0;
+  for (uint k=0; k<nb/2; k++) {
+    lwidth = QMAX(lwidth, fm.width(package.pins[k]));
+    rwidth = QMAX(rwidth, fm.width(package.pins[nb-k-1]));
+  }
+  int bx = lwidth + wspacing + wpin;
+  int width = bx + bwidth + wpin + wspacing + rwidth;
+  pixmap.resize(width, height);
+  pixmap.fill(Qt::white);
+  p.begin(&pixmap);
+  p.setPen(QPen(Qt::black, 2));
+  p.drawRect(bx, 1, bwidth, height-1);
+  p.drawArc(bx+wspacing+wnumber+wspacing, -wmark/2+2, wmark, wmark, 0, -180*16);
+  for (uint k=0; k<nb/2; k++) {
+    int h = hspacing + theight/2 + k*(hspacing + theight);
+    p.drawLine(bx-wpin-1, h, bx, h);
+    p.drawLine(bx+bwidth, h, bx+bwidth+wpin, h);
+    h += theight/2;
+    QString label = package.pins[k];
+    p.drawText(bx-wpin-wspacing-fm.width(label), h, label);
+    p.drawText(bx+bwidth+wpin+wspacing, h, package.pins[nb-k-1]);
+    uint pin = (k+1);
+    if ( pin==1 || pin==(nb/2) ) {
+      p.drawText(bx+wspacing, h, QString::number(pin));
+      label = QString::number(nb-k);
+      p.drawText(bx+bwidth-wspacing-fm.width(label), h, label);
+    }
+  }
+  p.end();
+  return pixmap;
+}
+
+QString Device::htmlInfo(const Device::Data &data, const QString &deviceHref, const QString &documentHtml)
+{
+  QString doc;
+
+  // title
+  doc += "<h1>";
+  bool first = true;
+  FOR_EACH(Special, special) {
+    for (uint k=0; k<data.frequencyRanges().count(); k++) {
+      if ( data.frequencyRanges()[k].special!=special ) continue;
+      if (first) first = false;
+      else doc += " / ";
+      doc += data.fname(special);
+      break;
+    }
+  }
+  doc += "</h1>";
+
+  doc += "<table>";
+  QString status = coloredString(data.status().label(), statusColor(data.status()));
+  doc += htmlTableRow(i18n("Status"), status);
+  if ( data.alternatives().count() ) {
+    QString s;
+    for (uint i=0; i<data.alternatives().count(); i++) {
+      if ( i!=0 ) s += ", ";
+      if ( deviceHref.isEmpty() ) s += data.alternatives()[i].upper();
+      else {
+        QString href = deviceHref.arg(data.alternatives()[i].upper());
+        s += QString("<a href=\"%1\">%2</a>").arg(href).arg(data.alternatives()[i].upper());
+      }
+    }
+    doc += htmlTableRow(i18n("Alternatives"), s);
+  }
+  doc += documentHtml;
+  doc += "</table>";
+
+  doc += "<hr />";
+  doc += "<table>";
+  doc += data.group().informationHtml(data);
+  QString s;
+  for (uint i=0; i<data.packages().count(); i++)
+    for (uint k=0; k<data.packages()[i].types.count(); k++)
+      s += i18n(Package::TYPE_DATA[data.packages()[i].types[k]].label) + QString("[%1] ").arg(data.packages()[i].pins.count());
+  doc += htmlTableRow(i18n("Packaging"), s);
+  doc += "</table>";
+
+  return doc;
+}
+
+QString Device::htmlPinDiagrams(const Device::Data &data, const QString &imagePrefix, QMimeSourceFactory *msf)
+{
+  QString doc;
+  // pins
+  const Package *package = 0;
+  for (uint i=0; Package::TYPE_DATA[i].name; i++) {
+    if ( Package::TYPE_DATA[i].shape!=Package::Bar ) continue;
+    package = barPackage(Package::TYPE_DATA[i].name, data);
+    if (package) break;
+  }
+  if (package) {
+    QPixmap pix = pinsGraph(*package);
+    doc += "<table cellpadding=\"3\"><tr bgcolor=\"gray\"><th align=\"center\">";
+    for (uint k=0; k<package->types.count(); k++) {
+      if ( k!=0 ) doc += " ";
+      doc += i18n(Package::TYPE_DATA[package->types[k]].label);
+      doc += "(" + QString::number(package->pins.count()) + ")";
+    }
+    doc += "</th></tr><tr><td align=\"center\">";
+    QString label = data.name() + "_pins_graph.png";
+    doc += "<img src=\"" + imagePrefix + label + "\" />";
+    if (msf) msf->setPixmap(label, pix);
+    doc += "</td></tr></table>";
+  }
+  return doc;
+}
+
+QString Device::htmlVoltageFrequencyGraphs(const Device::Data &data, const QString &imagePrefix, QMimeSourceFactory *msf)
+{
+  QString doc;
+  FOR_EACH(Special, special) {
+    for (uint k=0; k<data.frequencyRanges().count(); k++) {
+      const Device::FrequencyRange &fr = data.frequencyRanges()[k];
+      if ( fr.special!=special ) continue;
+      doc += "<h3>" + data.fname(special) + " - " + i18n("Temperature range: ") + fr.operatingCondition.label() + "</h3>";
+      QString label = data.name() + "_" + data.fname(special) + "_"
+        + fr.operatingCondition.key() + ".png";
+      doc += "<img src=\"" + imagePrefix + label + "\" />";
+      if (msf) msf->setPixmap(label, Device::vddGraph(i18n("F (MHz)"), i18n("Vdd (V)"), fr.vdds));
+    }
+  }
+  return doc;
+}
+
+QPixmap Device::memoryGraph(const QValueList<MemoryGraphData> &r)
+{
+  QValueList<MemoryGraphData> ranges = r;
+  QPixmap pixmap;
+  QPainter p;
+  QFontMetrics fm(p.font());
+  // order
+  qHeapSort(ranges);
+  // add empty ranges
+  QValueList<MemoryGraphData>::iterator it;
+  for (it=ranges.begin(); it!=ranges.end(); ) {
+    QValueList<MemoryGraphData>::iterator prev = it;
+    ++it;
+    if ( it==ranges.end() ) break;
+    if ( (*prev).endAddress+1==(*it).startAddress ) continue;
+    MemoryGraphData data;
+    data.startAddress = (*prev).endAddress + 1;
+    data.endAddress = (*it).startAddress-1;
+    ranges.insert(it, data);
+  }
+  // compute widths and total height
+  int theight = fm.ascent() + (fm.ascent()%2==0 ? 1 : 0);
+  int hspacing = 5;
+  int height = 1;
+  int w1 = 0, w2 = 0;
+  for (it=ranges.begin(); it!=ranges.end(); ++it) {
+    w1 = QMAX(w1, fm.width((*it).start));
+    w1 = QMAX(w1, fm.width((*it).end));
+    w2 = QMAX(w2, fm.width((*it).label));
+    (*it).height = 2*hspacing + theight;
+    if ( (*it).startAddress!=(*it).endAddress ) (*it).height += 2*theight;
+    height += (*it).height;
+  }
+  int wspacing = 4;
+  int width = wspacing + w1 + wspacing + wspacing + w2;
+  pixmap.resize(width, height);
+  pixmap.fill(Qt::white);
+  p.begin(&pixmap);
+  int h = 0;
+  // draw ranges
+  for (it=ranges.begin(); it!=ranges.end(); ++it) {
+    p.setPen(QPen(Qt::black, 1, Qt::DotLine));
+    p.drawLine(0,h, width-1,h);
+    p.setPen(QPen(Qt::black, 1));
+    p.setBrush((*it).label.isEmpty() ? Qt::gray : Qt::white);
+    p.drawRect(0,h, wspacing+w1+wspacing,(*it).height+1);
+    int hmid = h+(*it).height/2+theight/2;
+    p.drawText(wspacing+w1+wspacing+wspacing,hmid, (*it).label);
+    if ( (*it).startAddress==(*it).endAddress ) p.drawText(wspacing,hmid, (*it).start);
+    else {
+      p.drawText(wspacing,h+theight, (*it).start);
+      p.drawText(wspacing,h+(*it).height-3, (*it).end);
+    }
+    h += (*it).height;
+    p.setPen(QPen(Qt::black, 1, Qt::DotLine));
+    p.drawLine(0,h, width-1,h);
+  }
+  p.end();
+  return pixmap;
+}
+
+#endif
diff --git a/src/devices/base/device_group.h b/src/devices/base/device_group.h
new file mode 100644
index 0000000..087ca99
--- /dev/null
+++ b/src/devices/base/device_group.h
@@ -0,0 +1,87 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef DEVICE_GROUP_H
+#define DEVICE_GROUP_H
+
+#if !defined(NO_KDE)
+#  include <qcolor.h>
+#endif
+
+#include "generic_device.h"
+#include "common/common/group.h"
+#include "common/common/streamer.h"
+namespace Debugger { class DeviceSpecific; class Base; }
+
+namespace Device
+{
+class Memory;
+
+//----------------------------------------------------------------------------
+class MemoryRange {
+public:
+  MemoryRange() {}
+  virtual ~MemoryRange() {}
+  virtual bool all() const { return true; }
+};
+
+//----------------------------------------------------------------------------
+class GroupBase : public ::Group::Base
+{
+public:
+  virtual Memory *createMemory(const Device::Data &data) const = 0;
+  virtual QString informationHtml(const Device::Data &data) const = 0;
+#if !defined(NO_KDE)
+  virtual QPixmap memoryGraph(const Device::Data &data) const = 0;
+#endif
+
+protected:
+  virtual void addDevice(const QString &name, const Device::Data *data, ::Group::Support support) {
+    const_cast<Device::Data *>(data)->_group = this;
+    ::Group::Base::addDevice(name, data, support);
+  }
+};
+
+template <class DataType>
+class Group : public GroupBase, public DataStreamer<DataType>
+{
+protected:
+  virtual void initSupported() {
+    QValueList<DataType *> list = fromCppString(dataStream(), dataSize());
+    for (uint i=0; i<uint(list.count()); i++) addDevice(list[i]->name(), list[i], ::Group::Support::Tested);
+  }
+  virtual uint dataSize() const = 0;
+  virtual const char *dataStream() const = 0;
+};
+
+//----------------------------------------------------------------------------
+#if !defined(NO_KDE)
+extern QColor statusColor(Status status);
+extern QPixmap vddGraph(const QString &xLabel, const QString &yLabel, const QValueVector<RangeBox> &boxes);
+extern const Package *barPackage(const char *name, const Data &data);
+extern QPixmap pinsGraph(const Package &package);
+
+extern QString htmlInfo(const Data &data, const QString &deviceHref, const QString &documentHtml);
+extern QString htmlPinDiagrams(const Device::Data &data, const QString &imagePrefix, QMimeSourceFactory *msf);
+extern QString htmlVoltageFrequencyGraphs(const Device::Data &data, const QString &imagePrefix, QMimeSourceFactory *msf);
+
+class MemoryGraphData
+{
+public:
+  Address startAddress, endAddress;
+  QString start, end, label;
+  int height;
+  bool operator <(const MemoryGraphData &data) const { return ( startAddress < data.startAddress ); }
+};
+extern QPixmap memoryGraph(const QValueList<MemoryGraphData> &ranges);
+
+#endif
+
+} // namespace
+
+#endif
diff --git a/src/devices/base/generic_device.cpp b/src/devices/base/generic_device.cpp
new file mode 100644
index 0000000..bf69dce
--- /dev/null
+++ b/src/devices/base/generic_device.cpp
@@ -0,0 +1,216 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "generic_device.h"
+
+#include "common/global/global.h"
+#include "device_group.h"
+#include "register.h"
+
+//-----------------------------------------------------------------------------
+const Device::Status::Data Device::Status::DATA[Nb_Types] = {
+  { "IP",       I18N_NOOP("In Production")                  },
+  { "Future",   I18N_NOOP("Future Product")                 },
+  { "NR",       I18N_NOOP("Not Recommended for New Design") },
+  { "EOL",      I18N_NOOP("End Of Life"  )                  },
+  { "?",        I18N_NOOP("Unknown")                        },
+  { "Mature",   I18N_NOOP("Mature")                         }
+};
+
+const Device::MemoryTechnology::Data Device::MemoryTechnology::DATA[Nb_Types] = {
+  { "FLASH",   I18N_NOOP("Flash")          },
+  { "EPROM",   I18N_NOOP("EPROM (OTP)")    },
+  { "ROM",     I18N_NOOP("ROM")            },
+  { "ROMLESS", I18N_NOOP("ROM-less")       }
+};
+
+const Device::OperatingCondition::Data Device::OperatingCondition::DATA[Nb_Types] = {
+  { "commercial", I18N_NOOP("Commercial") },
+  { "industrial", I18N_NOOP("Industrial") },
+  { "extended",   I18N_NOOP("Extended")   }
+};
+
+const Device::Special::Data Device::Special::DATA[Nb_Types] = {
+  { "",             I18N_NOOP("Normal")       },
+  { "low_power",    I18N_NOOP("Low Power")    },
+  { "low_voltage",  I18N_NOOP("Low Voltage")  },
+  { "high_voltage", I18N_NOOP("High Voltage") }
+};
+
+const Device::Package::TypeData Device::Package::TYPE_DATA[] = {
+  { "pdip",  I18N_NOOP("PDIP"),   Bar,    {  8, 14, 18, 20, 28, 40,  0,  0,   0 } },
+  { "sdip",  I18N_NOOP("SDIP"),   Bar,    {  0,  0,  0,  0, 28,  0,  0,  0,   0 } }, // skinny
+  { "spdip", I18N_NOOP("SPDIP"),  Bar,    {  0,  0,  0,  0, 28,  0, 64,  0,   0 } }, // shrink
+  { "sot23", I18N_NOOP("SOT-23"), Bar,    {  5,  6,  0,  0,  0,  0,  0,  0,   0 } },
+  { "msop",  I18N_NOOP("MSOP"),   Bar,    {  8,  0,  0,  0,  0,  0,  0,  0,   0 } },
+  { "ssop",  I18N_NOOP("SSOP"),   Bar,    {  0,  0,  0, 20, 28,  0,  0,  0,   0 } },
+  { "tssop", I18N_NOOP("TSSOP"),  Bar,    {  8, 14,  0,  0,  0,  0,  0,  0,   0 } },
+  { "soic",  I18N_NOOP("SOIC"),   Bar,    {  8, 14, 18, 20, 28,  0,  0,  0,   0 } },
+  { "tqfp",  I18N_NOOP("TQFP"),   Square, {  0,  0,  0,  0,  0, 44, 64, 80, 100 } },
+  { "mqfp",  I18N_NOOP("MQFP"),   Square, {  0,  0,  0,  0,  0, 44,  0,  0,   0 } },
+  { "dfns",  I18N_NOOP("DFN-S"),  Bar,    {  8,  0,  0,  0,  0,  0,  0,  0,   0 } },
+  { "qfn",   I18N_NOOP("QFN"),    Square, {  0, 16,  0, 20, 28, 44,  0,  0,   0 } },
+  { "qfns",  I18N_NOOP("QFN-S"),  Bar,    {  0,  0,  0,  0, 28,  0,  0,  0,   0 } },
+  { "plcc",  I18N_NOOP("PLCC"),   Square, {  0,  0,  0,  0,  0, 44, 68, 84,   0 } },
+  { "mlf",   I18N_NOOP("MLF"),    Square, {  0,  0,  0,  0, 28,  0,  0,  0,   0 } },
+  { "dfn",   I18N_NOOP("DFN"),    Bar,    {  8,  0,  0,  0,  0,  0,  0,  0,   0 } },
+  {     0,                  0,    Square, {  0,  0,  0,  0,  0,  0,  0,  0,   0 } }
+};
+
+//-----------------------------------------------------------------------------
+double Device::FrequencyRange::vddMin() const
+{
+  double vdd = 0.0;
+  for (uint i=0; i<uint(vdds.count()); i++) {
+    if ( i==0 ) vdd = vdds[i].yMin();
+    vdd = qMin(vdd, vdds[i].yMin());
+  }
+  return vdd;
+}
+
+double Device::FrequencyRange::vddMax() const
+{
+  double vdd = 0.0;
+  for (uint i=0; i<uint(vdds.count()); i++) {
+    if ( i==0 ) vdd = vdds[i].yMax();
+    vdd = qMax(vdd, vdds[i].yMax());
+  }
+  return vdd;
+}
+
+//-----------------------------------------------------------------------------
+Device::Array::Array(const Array &array)
+{
+  _data = array._data.copy();
+}
+
+Device::Array &Device::Array::operator +=(const Array &a)
+{
+  uint s = _data.size();
+  _data.resize(s + a.size());
+  for (uint i=0; i<a.size(); i++) _data[s+i] = a[i];
+  return *this;
+}
+
+void Device::Array::append(uint v)
+{
+  uint s = _data.size();
+  _data.resize(s+1);
+  _data[s] = v;
+}
+
+Device::Array Device::Array::mid(uint index, int s) const
+{
+  CRASH_ASSERT( index<=size() && s<=int(size()-index) && s>=-1 );
+  Array array(s==-1 ? size()-index : s);
+  for (uint i=0; i<array.size(); i++) array[i] = _data[index+i];
+  return array;
+}
+
+Device::Array &Device::Array::operator =(const Array &array)
+{
+  _data = array._data.copy();
+  return *this;
+}
+
+//-----------------------------------------------------------------------------
+Device::Data::~Data()
+{
+  delete _registersData;
+}
+
+double Device::Data::vddMin() const
+{
+  double vdd = 0.0;
+  for (uint i=0; i<uint(_frequencyRanges.count()); i++) {
+    if ( i==0 ) vdd = _frequencyRanges[i].vddMin();
+    vdd = qMin(vdd, _frequencyRanges[i].vddMin());
+  }
+  return vdd;
+}
+
+double Device::Data::vddMax() const
+{
+  double vdd = 0.0;
+  for (uint i=0; i<uint(_frequencyRanges.count()); i++) {
+    if ( i==0 ) vdd = _frequencyRanges[i].vddMax();
+    vdd = qMax(vdd, _frequencyRanges[i].vddMax());
+  }
+  return vdd;
+}
+
+//-----------------------------------------------------------------------------
+QDataStream &Device::operator <<(QDataStream &s, const RangeBox::Value &rbv)
+{
+  s << rbv.x << rbv.yMin << rbv.yMax;
+  return s;
+}
+QDataStream &Device::operator >>(QDataStream &s, RangeBox::Value &rbv)
+{
+  s >> rbv.x >> rbv.yMin >> rbv.yMax;
+  return s;
+}
+
+QDataStream &Device::operator <<(QDataStream &s, const RangeBox &rb)
+{
+  s << rb.start << rb.end << rb.osc << rb.mode << rb.special;
+  return s;
+}
+QDataStream &Device::operator >>(QDataStream &s, RangeBox &rb)
+{
+  s >> rb.start >> rb.end >> rb.osc >> rb.mode >> rb.special;
+  return s;
+}
+
+QDataStream &Device::operator <<(QDataStream &s, const FrequencyRange &frange)
+{
+  s << frange.operatingCondition << frange.special << frange.vdds;
+  return s;
+}
+QDataStream &Device::operator >>(QDataStream &s, FrequencyRange &frange)
+{
+  s >> frange.operatingCondition >> frange.special >> frange.vdds;
+  return s;
+}
+
+QDataStream &Device::operator <<(QDataStream &s, const Package &package)
+{
+  s << package.types << package.pins;
+  return s;
+}
+QDataStream &Device::operator >>(QDataStream &s, Package &package)
+{
+  s >> package.types >> package.pins;
+  return s;
+}
+
+QDataStream &Device::operator <<(QDataStream &s, const Documents &documents)
+{
+  s << documents.webpage << documents.datasheet << documents.progsheet << documents.erratas;
+  return s;
+}
+QDataStream &Device::operator >>(QDataStream &s, Documents &documents)
+{
+  s >> documents.webpage >> documents.datasheet >> documents.progsheet >> documents.erratas;
+  return s;
+}
+
+QDataStream &Device::operator <<(QDataStream &s, const Data &data)
+{
+  s << data._name << data._documents << data._alternatives << data._status
+    << data._frequencyRanges << data._memoryTechnology
+    << data._packages;
+  return s;
+}
+QDataStream &Device::operator >>(QDataStream &s, Data &data)
+{
+  s >> data._name >> data._documents >> data._alternatives >> data._status
+    >> data._frequencyRanges >> data._memoryTechnology
+    >> data._packages;
+  return s;
+}
diff --git a/src/devices/base/generic_device.h b/src/devices/base/generic_device.h
new file mode 100644
index 0000000..e3cbec9
--- /dev/null
+++ b/src/devices/base/generic_device.h
@@ -0,0 +1,171 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef GENERIC_DEVICE_H
+#define GENERIC_DEVICE_H
+
+#include <qstringlist.h>
+
+#include "common/common/misc.h"
+#include "common/common/bitvalue.h"
+#include "common/common/key_enum.h"
+#include "common/global/global.h"
+
+namespace Device
+{
+//----------------------------------------------------------------------------
+BEGIN_DECLARE_ENUM(Status)
+  InProduction = 0, Future, NotRecommended, EOL, Unknown, Mature
+END_DECLARE_ENUM_STD(Status)
+
+BEGIN_DECLARE_ENUM(MemoryTechnology)
+  Flash = 0, Eprom, Rom, Romless
+END_DECLARE_ENUM_STD(MemoryTechnology)
+
+class RangeBox {
+public:
+  struct Value { double x, yMin, yMax; };
+  Value start, end;
+  QString osc, mode, special;
+  double yMin() const { return qMin(start.yMin, end.yMin); }
+  double yMax() const { return qMax(start.yMax, end.yMax); }
+};
+
+BEGIN_DECLARE_ENUM(OperatingCondition)
+  Commercial = 0, Industrial, Extended
+END_DECLARE_ENUM_STD(OperatingCondition)
+
+BEGIN_DECLARE_ENUM(Special)
+  Normal = 0, LowPower, LowVoltage, HighVoltage
+END_DECLARE_ENUM_STD(Special)
+
+class FrequencyRange {
+public:
+  OperatingCondition operatingCondition;
+  Special special;
+  QValueVector<RangeBox> vdds;
+  double vddMin() const;
+  double vddMax() const;
+};
+
+class IdData {
+public:
+  BitValue revision, minorRevision, process;
+  Special special;
+};
+
+class Package
+{
+public:
+  QValueVector<uint> types;
+  QValueVector<QString> pins;
+
+public:
+  enum Shape { Bar, Square };
+  enum { MAX_NB = 9 };
+  struct TypeData {
+    const char *name, *label;
+    Shape shape;
+    uint nbPins[MAX_NB];
+  };
+  static const TypeData TYPE_DATA[];
+};
+
+class Documents
+{
+public:
+  QString webpage, datasheet, progsheet;
+  QStringList erratas;
+};
+
+//----------------------------------------------------------------------------
+class XmlToDataBase;
+class GroupBase;
+class RegistersData;
+
+//----------------------------------------------------------------------------
+// we don't want implicit sharing
+class Array
+{
+public:
+  Array(uint size = 0) : _data(size) {}
+  Array(const Array &array);
+  Array &operator =(const Array &);
+  Array &operator +=(const Array &a);
+  void append(uint v);
+  Array mid(uint index, int size = -1) const;
+  void resize(uint s) { _data.resize(s); }
+  uint size() const { return _data.size(); }
+  uint count() const { return _data.size(); }
+  BitValue operator [](uint i) const { return _data[i]; }
+  BitValue &operator [](uint i) { return _data[i]; }
+  bool operator ==(const Array &array) const { return _data==array._data; }
+  bool operator !=(const Array &array) const { return _data!=array._data; }
+
+private:
+  QMemArray<BitValue> _data;
+};
+
+//----------------------------------------------------------------------------
+class Data
+{
+public:
+  Data(RegistersData *rdata) : _group(0), _registersData(rdata) {}
+  virtual ~Data();
+  const GroupBase &group() const { return *_group; }
+  virtual QString name() const { return _name; }
+  virtual QString fname(Special) const { return _name; }
+  virtual QString listViewGroup() const = 0;
+  Status status() const { return _status; }
+  const Documents &documents() const { return _documents; }
+  const QStringList &alternatives() const { return _alternatives; }
+  MemoryTechnology memoryTechnology() const { return _memoryTechnology; }
+  virtual bool matchId(BitValue rawId, IdData &idata) const = 0;
+  const QValueVector<FrequencyRange> &frequencyRanges() const { return _frequencyRanges; }
+  double vddMin() const;
+  double vddMax() const;
+  virtual uint nbBitsAddress() const = 0;
+  uint nbBytesAddress() const { return nbBitsAddress()/8 + (nbBitsAddress()%8 ? 1 : 0); }
+  uint nbCharsAddress() const { return nbBitsAddress()/4 + (nbBitsAddress()%4 ? 1 : 0); }
+  virtual bool canWriteCalibration() const = 0; // #### REMOVE ME
+  const RegistersData *registersData() const { return _registersData; }
+  const QValueVector<Package> &packages() const { return _packages; }
+
+protected:
+  const GroupBase *_group;
+  QString _name;
+  Documents _documents;
+  QStringList _alternatives;
+  Status _status;
+  QValueVector<FrequencyRange> _frequencyRanges;
+  MemoryTechnology _memoryTechnology;
+  RegistersData *_registersData;
+  QValueVector<Package> _packages;
+
+  friend class XmlToDataBase;
+  friend class GroupBase;
+  friend QDataStream &operator <<(QDataStream &s, const Data &data);
+  friend QDataStream &operator >>(QDataStream &s, Data &data);
+};
+
+QDataStream &operator <<(QDataStream &s, const RangeBox::Value &rbv);
+QDataStream &operator >>(QDataStream &s, RangeBox::Value &rbv);
+QDataStream &operator <<(QDataStream &s, const RangeBox &rb);
+QDataStream &operator >>(QDataStream &s, RangeBox &rb);
+QDataStream &operator <<(QDataStream &s, const FrequencyRange &frange);
+QDataStream &operator >>(QDataStream &s, FrequencyRange &frange);
+QDataStream &operator <<(QDataStream &s, const Package &package);
+QDataStream &operator >>(QDataStream &s, Package &package);
+QDataStream &operator <<(QDataStream &s, const Documents &documents);
+QDataStream &operator >>(QDataStream &s, Documents &documents);
+QDataStream &operator <<(QDataStream &s, const Data &data);
+QDataStream &operator >>(QDataStream &s, Data &data);
+
+} // namespace
+
+#endif
diff --git a/src/devices/base/generic_memory.cpp b/src/devices/base/generic_memory.cpp
new file mode 100644
index 0000000..78c4dd6
--- /dev/null
+++ b/src/devices/base/generic_memory.cpp
@@ -0,0 +1,48 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "generic_memory.h"
+
+bool Device::Memory::load(QTextStream &stream, QStringList &errors,
+			  WarningTypes &warningTypes, QStringList &warnings)
+{
+  HexBuffer hb;
+  if ( !hb.load(stream, errors) ) return false;
+  warningTypes = fromHexBuffer(hb, warnings);
+  return true;
+}
+
+Device::Memory::WarningTypes Device::Memory::fromHexBuffer(const HexBuffer &hb, QStringList &warnings)
+{
+  clear();
+  WarningTypes result = NoWarning;
+  warnings.clear();
+  QMap<uint, bool> inRange;
+  fromHexBuffer(hb, result, warnings, inRange);
+
+   // check that all values in FragBuffer are within memory ranges
+  HexBuffer::const_iterator it = hb.begin();
+  for (; it!=hb.end(); ++it) {
+    if ( !it.data().isInitialized() || inRange[it.key()] ) continue;
+    if ( !(result & ValueOutsideRange) ) {
+      result |= ValueOutsideRange;
+      warnings += i18n("At least one value (at address %1) is defined outside memory ranges.").arg(toHexLabel(it.key(), 8));
+    }
+    break;
+  }
+
+  return result;
+}
+
+bool Device::Memory::save(QTextStream &stream, HexBuffer::Format format) const
+{
+  savePartial(stream, format);
+  HexBuffer hb;
+  hb.saveEnd(stream);
+  return true;
+}
diff --git a/src/devices/base/generic_memory.h b/src/devices/base/generic_memory.h
new file mode 100644
index 0000000..74bd938
--- /dev/null
+++ b/src/devices/base/generic_memory.h
@@ -0,0 +1,47 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef GENERIC_MEMORY_H
+#define GENERIC_MEMORY_H
+
+#include "devices/base/generic_device.h"
+#include "devices/base/hex_buffer.h"
+
+namespace Device
+{
+
+class Memory
+{
+public:
+  const Data &device() const { return _device; }
+  virtual ~Memory() {}
+  virtual void fill(BitValue value) = 0;
+  virtual void clear() { fill(BitValue()); }
+  virtual void copyFrom(const Memory &memory) = 0;
+  virtual BitValue checksum() const = 0;
+
+  virtual HexBuffer toHexBuffer() const = 0;
+  bool save(QTextStream &stream, HexBuffer::Format format) const;
+  enum WarningType { NoWarning = 0, ValueTooLarge = 1, ValueOutsideRange = 2 };
+  Q_DECLARE_FLAGS(WarningTypes, WarningType)
+  WarningTypes fromHexBuffer(const HexBuffer &hb, QStringList &warnings);
+  bool load(QTextStream &stream, QStringList &errors, WarningTypes &warningTypes, QStringList &warnings);
+
+protected:
+  const Data &_device;
+
+  Memory(const Data &device) : _device(device) {}
+  virtual void fromHexBuffer(const HexBuffer &hb, WarningTypes &warningTypes,
+                             QStringList &warnings, QMap<uint, bool> &inRange) = 0;
+  virtual void savePartial(QTextStream &stream, HexBuffer::Format format) const = 0;
+};
+Q_DECLARE_OPERATORS_FOR_FLAGS(Memory::WarningTypes)
+
+} // namespace
+
+#endif
diff --git a/src/devices/base/hex_buffer.cpp b/src/devices/base/hex_buffer.cpp
new file mode 100644
index 0000000..a63554d
--- /dev/null
+++ b/src/devices/base/hex_buffer.cpp
@@ -0,0 +1,290 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>             *
+ *             (C) 2003 by Alain Gibaud                                    *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "hex_buffer.h"
+
+#include <qtextstream.h>
+
+#include "devices/base/generic_device.h"
+
+//-----------------------------------------------------------------------------
+const char * const HexBuffer::FORMATS[Nb_Formats] = {
+  "inhx8m", /*"inhx8s", */"inhx16", "inhx32"
+};
+
+void HexBuffer::savePartial(QTextStream &stream, Format format) const
+{
+  BitValue oldseg;
+  const_iterator block = begin();
+  int len;
+  while ( fetchNextBlock(block, end(), &len) ) {
+    // block found, write it
+    BitValue seg = block.key() >> 15 ; // 2 * seg address
+    if ( format==IHX32 && seg!=oldseg ) {
+      char buf[50];
+      BitValue check = 0x02 + 0x04 + seg.byte(1) + seg.byte(0);
+      sprintf(buf, ":02000004%04X%02X\n", seg.toUInt(), check.twoComplement().byte(0));
+      stream << buf;
+      oldseg = seg;
+    }
+    writeHexBlock(stream, len, block, format);
+  }
+}
+
+void HexBuffer::saveEnd(QTextStream &stream) const
+{
+  stream << ":00000001FF\n";
+}
+
+/* Write one line of Intel-hex file
+ * Original code source from Timo Rossi,
+ * modified by Alain Gibaud to support large blocks write
+ */
+void HexBuffer::writeHexBlock(QTextStream &stream, int reclen, // length (in words)
+			  const_iterator& data, // pointer to 1st data word (incremented by function)
+                          Format format)
+{
+    while ( reclen>HEXBLKSIZE ) {
+      writeHexBlock(stream, HEXBLKSIZE, data, format);
+      reclen -= HEXBLKSIZE;
+    }
+    if ( reclen<=0 ) return; /* Oops, block has just a HEXBLKSIZE * n size */
+
+    char buf[20];
+    BitValue check = 0x0;
+
+    // line start
+    uint loc =  data.key();
+    switch (format) {
+      case IHX8M:
+      case IHX32:
+        loc *= 2;
+        sprintf(buf,  ":%02X%04X00", 2*reclen, loc & 0xFFFF);
+        check += ((loc) & 0xff) + (((loc) >> 8) & 0xff) + 2*reclen;
+        break;
+      case IHX16:
+        sprintf(buf, ":%02X%04X00", reclen, loc & 0xFFFF);
+        check += (loc & 0xff) + ((loc >> 8) & 0xff) + reclen;
+        break;
+      case Nb_Formats: Q_ASSERT(false); break;
+    }
+    stream << buf;
+
+    // data
+    for (; reclen > 0; ++data, --reclen) {
+      BitValue word =  data.data();
+      switch (format) {
+        case IHX8M:
+        case IHX32:
+          sprintf(buf, "%02X%02X", word.byte(0), word.byte(1));
+          break;
+        case IHX16:
+          sprintf(buf, "%02X%02X", word.byte(1), word.byte(0));
+          break;
+        case Nb_Formats: Q_ASSERT(false); break;
+      }
+      stream << buf;
+      check += word.byte(0) + word.byte(1);
+    }
+
+    // checksum, assumes 2-complement
+    sprintf(buf, "%02X\n", check.twoComplement().byte(0));
+    stream << buf;
+}
+
+/* -------------------------------------------------------------------------
+    This routine detects the next block to output
+    A block is a set of consecutive addresse words not
+    containing 0xFFFFFFFF
+    @return true if a block has been detected
+    'it' is updated to point to the first address of the block
+    '*len' contains the size of the block
+*/
+bool HexBuffer::fetchNextBlock(const_iterator& it, const const_iterator &end, int *len)
+{
+    uint startadr, curadr;
+    // for( i = *start ; (i < MAXPICSIZE) && (Mem[i] == INVALID) ; ++i) ;
+    // skip non-used words
+
+    // Search block start
+    while ( it!=end && !it.data().isInitialized() ) ++it;
+
+    // if(i >= MAXPICSIZE ) return false ;
+    if ( it==end ) return false;
+
+    //for( *start = i ; (i < MAXPICSIZE) && (Mem[i] != INVALID) ; ++i) ;
+    //*len = i - *start ;
+    // search block end - a block may not cross a segment boundary
+    const_iterator itt(it) ;
+    for (curadr = startadr = itt.key(), ++itt; itt!=end; ++itt) {
+      if ( itt.key()!=curadr+1 ) break;    // non contiguous addresses
+      if ( !itt.data().isInitialized() ) break;   // unused word found
+      if ( ((itt.key()) & 0xFFFF0000U)!=(curadr & 0xFFFF0000U) ) break; // cross segment boundary
+      curadr = itt.key();
+    }
+    *len = curadr - startadr + 1 ;
+
+    return *len != 0  ;
+}
+
+QString HexBuffer::ErrorData::message() const
+{
+  switch (type) {
+    case UnrecognizedFormat: return i18n("Unrecognized format (line %1).").arg(line);
+    case UnexpectedEOF: return i18n("Unexpected end-of-file.");
+    case UnexpectedEOL: return i18n("Unexpected end-of-line (line %1).").arg(line);
+    case WrongCRC: return i18n("CRC mismatch (line %1).").arg(line);
+  }
+  Q_ASSERT(false);
+  return QString::null;
+}
+
+bool HexBuffer::load(QTextStream &stream, QStringList &errors)
+{
+  Format format;
+  QValueList<ErrorData> list = load(stream, format);
+  if ( list.isEmpty() ) return true;
+  errors.clear();
+  for (uint i=0; i<uint(list.count()); i++) errors += list[i].message();
+  return false;
+}
+
+QValueList<HexBuffer::ErrorData> HexBuffer::load(QTextStream &stream, Format &format)
+{
+  clear();
+  format = Nb_Formats;
+  QValueList<HexBuffer::ErrorData> errors;
+  load(stream, format, errors);
+  if ( format==Nb_Formats ) format = IHX8M; // default
+  return errors;
+}
+
+/* -------------------------------------------------------------------------
+   Read a Intel HEX file of either INHX16 or INHX8M format type, detecting
+   the format automagicly by the wordcount and length of the line
+   Tested in 8 and 16 bits modes
+   ------------------------------------------------------------------------ */
+void HexBuffer::load(QTextStream &stream, Format &format, QValueList<ErrorData> &errors)
+{
+    uint addrH = 0; // upper 16 bits of 32 bits address (inhx32 format)
+    uint line = 1;
+
+    for (; !stream.atEnd(); line++) { // read each line
+        QString s = stream.readLine();
+        if ( !s.startsWith(":") ) continue; // skip invalid intel hex line
+        s = s.stripWhiteSpace(); // clean-up white spaces at end-of-line
+        if ( s==":" ) continue; // skip empty line
+
+        const char *p = s.latin1();
+        p += 1; // skip ':'
+        uint bytecount = (s.length()-11) / 2; // number of data bytes of this record
+
+        // get the byte count, the address and the type for this line.
+        uint count, addr, type;
+        if ( sscanf(p, "%02X%04X%02X", &count , &addr, &type)!=3 ) {
+          errors += ErrorData(line, UnrecognizedFormat);
+          return;
+        }
+        p += 8;
+        uint cksum = count + (addr >> 8) + (addr & 0xFF) + type;
+
+        if( type==0x01 ) { // EOF field :00 0000 01 FF
+            uint data;
+            if ( sscanf(p, "%02X", &data)!=1 ) errors += ErrorData(line, UnexpectedEOL);
+            else if ( ((cksum+data) & 0xFF)!=0 ) errors += ErrorData(line, WrongCRC);
+            return;
+        }
+
+        if ( type==0x04 ) { // linear extended record (for 0x21xxxx, :02 0000 04 0021 D9)
+            if( sscanf(p, "%04X", &addrH)!=1 ) {
+              errors += ErrorData(line, UnrecognizedFormat); // bad address record
+              return;
+            }
+            p += 4;
+            cksum += (addrH & 0xFF);
+            cksum += (addrH >> 8);
+            if ( format==Nb_Formats || format==IHX8M ) format = IHX32;
+            else if ( format!=IHX32 ) {
+              errors += ErrorData(line, UnrecognizedFormat); // inconsistent format
+              return;
+            }
+            uint data;
+            if ( sscanf(p, "%02X", &data)!=1 ) errors += ErrorData(line, UnexpectedEOL);
+            else if ( ((cksum+data) & 0xFF)!=0 ) errors += ErrorData(line, WrongCRC);
+            //qDebug("new address high: %s", toHex(addrH<<16, 8).data());
+            continue; // goto next record
+        }
+
+        /* Figure out if its INHX16 or INHX8M
+            if count is a 16 bits words count => INHX16
+            if count is a byte count => INHX8M or INHX32 */
+        if ( bytecount==count ) {
+            if ( format==Nb_Formats ) format = IHX8M;
+            else if ( format!=IHX8M && format!=IHX32 ) {
+              errors += ErrorData(line, UnrecognizedFormat); // inconsistent format
+              return;
+            }
+            /* Processing a INHX8M line */
+            /* Modified to be able to read fuses from hexfile created by C18 toolchain */
+            /* changed by Tobias Schoene 9 April 2005, */
+            /* modified by A.G, because low and hi bytes was swapped in Tobias's code , 8 may 2005
+            */
+            uint addrbase = ((addrH << 16) | addr);
+            //qDebug("line %i: address %s", line, toHex(addrbase, 8).data());
+            for (uint x = 0; x<count; x++) {
+              uint data;
+              if ( sscanf(p, "%02X", &data)!=1 ) {
+                errors += ErrorData(line, UnexpectedEOL);
+                break;
+              }
+              p += 2;
+              // A.G: I suspect possible initialization problem
+              // if block begins at odd address
+              // because |= works on an uninitalized word
+              // however, I  don't know if such a situation can occurs
+              uint a = addrbase+x >> 1;
+              BitValue value = (*this)[a];
+              if ( addrbase+x & 1 ) insert(a, value.maskWith(0x00FF) | data << 8); // Odd addr => Hi byte
+              else insert(a, value.maskWith(0xFF00) | data); // Low byte
+              //if ( x==0 ) qDebug("fb@%s: %s", toHex(addrbase+x >> 1, 8).data(), toHex(fb[addrbase+x >> 1], 8).data());
+              cksum += data;
+            }
+        } else if ( bytecount==count*2 ) {
+            if ( format==Nb_Formats ) format = IHX16;
+            else if ( format!=IHX16 ) {
+                errors += ErrorData(line, UnrecognizedFormat); // inconsistent format
+                return;
+            }
+            /* Processing a INHX16 line */
+            for(uint x=0; x<count; x++) {
+                uint datal, datah;
+                if( sscanf(p, "%02X%02X", &datah, &datal)!=2 ) {
+                  errors += ErrorData(line, UnexpectedEOL);
+                  break;
+                }
+                p += 4;
+                //qDebug("%s: %s", toHexLabel(addr+x, 4).latin1(), toHexLabel(datal | (datah << 8), 4).latin1());
+                insert(addr+x, datal | (datah << 8));
+                cksum += datah;
+                cksum += datal;
+            }
+        } else {
+            errors += ErrorData(line, UnrecognizedFormat); // Brrrr !! Strange format.
+            return;
+        }
+
+        /* Process the checksum */
+        uint data;
+        if( sscanf(p, "%02X", &data)!=1 ) errors += ErrorData(line, UnexpectedEOL);
+        else if( ((data + cksum) & 0xFF)!=0 ) errors += ErrorData(line, WrongCRC);
+    }
+
+    errors += ErrorData(line, UnexpectedEOF);
+    return;
+}
diff --git a/src/devices/base/hex_buffer.h b/src/devices/base/hex_buffer.h
new file mode 100644
index 0000000..93b0640
--- /dev/null
+++ b/src/devices/base/hex_buffer.h
@@ -0,0 +1,51 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>             *
+ *             (C) 2003 by Alain Gibaud                                    *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef HEX_BUFFER_H
+#define HEX_BUFFER_H
+
+#include "common/global/global.h"
+#include "common/common/bitvalue.h"
+class QTextStream;
+
+class HexBuffer : public QMap<uint, BitValue>
+{
+public:
+  enum Format { /// Differents flavors of Intel HEX file formats
+    IHX8M = 0,  ///< 8 bits "swapped" format
+    //    IHX8S,
+    IHX16,      ///< 16 bits format
+    IHX32,      ///< 8 bit format with 32 bits addresses
+    Nb_Formats
+  };
+  static const char * const FORMATS[Nb_Formats];
+
+  void savePartial(QTextStream &s, Format format) const;
+  void saveEnd(QTextStream &s) const;
+  enum ErrorType { UnrecognizedFormat, WrongCRC, UnexpectedEOF, UnexpectedEOL };
+  class ErrorData {
+  public:
+    ErrorData() {}
+    ErrorData(uint _line, ErrorType _type) : line(_line), type(_type) {}
+    QString message() const;
+    uint line;
+    ErrorType type;
+  };
+  QValueList<ErrorData> load(QTextStream &stream, Format &format);
+  bool load(QTextStream &stream, QStringList &errors);
+
+private:
+  enum { HEXBLKSIZE = 8 }; // line size in HEX files
+
+  static bool fetchNextBlock(const_iterator& start, const const_iterator &end, int *len);
+  static void writeHexBlock(QTextStream &stream, int reclen, const_iterator& data, Format format);
+  void load(QTextStream &stream, Format &format, QValueList<ErrorData> &errors);
+};
+
+#endif
diff --git a/src/devices/base/register.cpp b/src/devices/base/register.cpp
new file mode 100644
index 0000000..85fc013
--- /dev/null
+++ b/src/devices/base/register.cpp
@@ -0,0 +1,156 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "register.h"
+
+//----------------------------------------------------------------------------
+namespace Register
+{
+  List *_list = 0;
+}
+Register::List &Register::list()
+{
+  if ( _list==0 ) _list = new List;
+  return *_list;
+}
+
+//----------------------------------------------------------------------------
+Register::TypeData::TypeData(Address address, uint nbChars)
+  : _nbChars(nbChars), _address(address)
+{
+  Q_ASSERT( address.isValid() && nbChars!=0 );
+}
+Register::TypeData::TypeData(const QString &name, uint nbChars)
+  : _nbChars(nbChars), _name(name)
+{
+  Q_ASSERT( !name.isEmpty() && nbChars!=0 );
+}
+Register::TypeData::TypeData(const QString &name, Address address, uint nbChars)
+  : _nbChars(nbChars), _address(address), _name(name)
+{
+  Q_ASSERT( address.isValid() && nbChars!=0 && !name.isEmpty() );
+}
+
+Register::Type Register::TypeData::type() const
+{
+  if ( !_address.isValid() ) {
+    if ( _name.isEmpty() ) return Invalid;
+    return Special;
+  }
+  if ( _name.isEmpty() ) return Regular;
+  return Combined;
+}
+
+QString Register::TypeData::toString() const
+{
+  return QString("%1 %2 %3").arg(toLabel(_address)).arg(_nbChars).arg(_name);
+}
+
+Register::TypeData Register::TypeData::fromString(const QString &s)
+{
+  QStringList list = QStringList::split(" ", s);
+  if ( list.count()<2 || list.count()>3 ) return TypeData();
+  bool ok;
+  Address address = list[0].toUInt(&ok);
+  if ( !ok ) return TypeData();
+  uint nbChars = list[1].toUInt(&ok);
+  if ( !ok || nbChars==0 || (nbChars%2)!=0 ) return TypeData();
+  QString name;
+  if ( list.count()==3 ) name = list[2];
+  if ( !address.isValid() ) {
+    if ( name.isEmpty() ) return TypeData();
+    return TypeData(name, nbChars);
+  }
+  if ( name.isEmpty() ) return TypeData(address, nbChars);
+  return TypeData(name, address, nbChars);
+}
+
+//----------------------------------------------------------------------------
+void Register::List::init()
+{
+  _regulars.clear();
+  _specials.clear();
+  _watched.clear();
+  _portDatas.clear();
+  delayedChanged();
+}
+
+void Register::List::setWatched(const TypeData &data, bool watched)
+{
+  if (watched) {
+    if ( _watched.contains(data) ) return;
+    _watched.append(data);
+  } else _watched.remove(data);
+  delayedChanged();
+}
+
+void Register::List::clearWatched()
+{
+  _watched.clear();
+  delayedChanged();
+}
+
+void Register::List::setValue(const TypeData &data, BitValue value)
+{
+  if ( !data.address().isValid() ) {
+    _specials[data.name()].old = _specials[data.name()].current;
+    _specials[data.name()].current = value;
+  } else {
+    Q_ASSERT( (data.nbChars()%2)==0 );
+    uint nb = data.nbChars()/2;
+    for (uint i=0; i<nb; i++) {
+      Address address = data.address() + i;
+      _regulars[address].old = _regulars[address].current;
+      _regulars[address].current = value.byte(i);
+    }
+  }
+  delayedChanged();
+}
+
+void Register::List::setPortData(uint index, const QMap<uint, Device::PortBitData> &data)
+{
+  _portDatas[index].old = _portDatas[index].current;
+  _portDatas[index].current = data;
+  delayedChanged();
+}
+
+BitValue Register::List::value(const TypeData &data) const
+{
+  if ( !data.address().isValid() ) {
+    if ( !_specials.contains(data.name()) ) return BitValue();
+    return _specials[data.name()].current;
+  }
+  Q_ASSERT( (data.nbChars()%2)==0 );
+  uint nb = data.nbChars()/2;
+  BitValue value = 0;
+  for (int i=nb-1; i>=0; i--) {
+    value <<= 8;
+    BitValue v = _regulars[data.address() + i].current;
+    if ( !v.isInitialized() ) return BitValue();
+    value += v;
+  }
+  return value;
+}
+
+BitValue Register::List::oldValue(const TypeData &data) const
+{
+  if ( !data.address().isValid() ) {
+    if ( !_specials.contains(data.name()) ) return BitValue();
+    return _specials[data.name()].old;
+  }
+  Q_ASSERT( (data.nbChars()%2)==0 );
+  uint nb = data.nbChars()/2;
+  BitValue value = 0;
+  for (int i=nb-1; i>=0; i--) {
+    value <<= 8;
+    BitValue v = _regulars[data.address() + i].old;
+    if ( !v.isInitialized() ) return BitValue();
+    value += v;
+  }
+  return value;
+}
diff --git a/src/devices/base/register.h b/src/devices/base/register.h
new file mode 100644
index 0000000..1c587e2
--- /dev/null
+++ b/src/devices/base/register.h
@@ -0,0 +1,130 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef REGISTER_H
+#define REGISTER_H
+
+#include "common/common/storage.h"
+#include "devices/base/generic_device.h"
+namespace Register { class TypeData; }
+
+namespace Device
+{
+enum RegisterProperty { NotAccessible = 0x0, Readable = 0x1, Writable = 0x2 };
+Q_DECLARE_FLAGS(RegisterProperties, RegisterProperty)
+Q_DECLARE_OPERATORS_FOR_FLAGS(RegisterProperties)
+
+enum { MAX_NB_PORTS = 8 };
+enum { MAX_NB_PORT_BITS = 16 };
+enum BitState { Low = 0, High, WeakPullUp, WeakPullDown, HighImpedance, Unknown };
+enum IoState { IoLow = 0, IoHigh, IoUnknown };
+class PortBitData {
+public:
+  PortBitData() : state(Unknown), driving(false), drivenState(IoUnknown), drivingState(IoUnknown) {}
+  BitState state;
+  bool driving;
+  IoState drivenState, drivingState;
+  bool operator !=(const PortBitData &pdb) const {
+    return ( state!=pdb.state || driving!=pdb.driving || drivenState!=pdb.drivenState || drivingState!=pdb.drivingState );
+  }
+};
+
+} // namespace
+
+namespace Register
+{
+//----------------------------------------------------------------------------
+enum Type { Regular, Special, Combined, Invalid };
+class TypeData {
+public:
+  TypeData() : _nbChars(0) {}
+  TypeData(Address address, uint nbChars);
+  TypeData(const QString &name, uint nbChars);
+  TypeData(const QString &name, Address address, uint nbChars);
+  bool operator ==(const TypeData &data) const { return _name==data._name && _address==data._address && _nbChars==data._nbChars; }
+  Type type() const;
+  QString name() const { return _name; }
+  Address address() const { return _address; }
+  uint nbChars() const { return _nbChars; }
+  QString toString() const;
+  static TypeData fromString(const QString &s);
+
+private:
+  uint    _nbChars;
+  Address _address;
+  QString _name;
+};
+
+} // namespace
+
+namespace Device
+{
+//----------------------------------------------------------------------------
+class RegistersData
+{
+public:
+  RegistersData() {}
+  virtual ~RegistersData() {}
+  virtual uint nbRegisters() const = 0;
+  virtual uint nbBits() const = 0;
+  uint nbBytes() const { return nbBitsToNbBytes(nbBits()); }
+  uint nbChars() const { return nbBitsToNbChars(nbBits()); }
+  virtual uint addressFromIndex(uint i) const = 0;
+  virtual uint indexFromAddress(Address address) const = 0;
+  virtual RegisterProperties properties(Address address) const = 0;
+  virtual QValueList<Register::TypeData> relatedRegisters(const Register::TypeData &data) const = 0;
+  virtual bool hasPort(uint index) const = 0;
+  virtual int portIndex(Address address) const = 0;
+  virtual QString portName(uint index) const = 0;
+  virtual bool hasPortBit(uint index, uint bit) const = 0;
+  virtual QString portBitName(uint index, uint bit) const = 0;
+};
+
+} // namespace
+
+namespace Register
+{
+//----------------------------------------------------------------------------
+class List;
+extern List &list();
+
+class List : public GenericStorage
+{
+Q_OBJECT
+public:
+  List() : GenericStorage(0, "register_list") {}
+  void init();
+  void setWatched(const TypeData &data, bool watched);
+  void clearWatched();
+  const QValueList<TypeData> &watched() const { return _watched; }
+  bool isWatched(const TypeData &data) const { return _watched.contains(data); }
+  void setValue(const TypeData &data, BitValue value);
+  BitValue value(const TypeData &data) const;
+  BitValue oldValue(const TypeData &data) const;
+  void setPortData(uint index, const QMap<uint, Device::PortBitData> &data);
+  QMap<uint, Device::PortBitData> portData(uint index) const { return _portDatas[index].current; }
+  QMap<uint, Device::PortBitData> oldPortData(uint index) const { return _portDatas[index].old; }
+
+private:
+  class StateData {
+  public:
+    BitValue current, old;
+  };
+  QMap<Address, StateData> _regulars; // registers with address
+  QMap<QString, StateData> _specials; // registers with no address
+  class PortData {
+  public:
+    QMap<uint, Device::PortBitData> current, old;
+  };
+  QMap<uint, PortData> _portDatas; // port index
+  QValueList<TypeData> _watched;
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/devices.pro b/src/devices/devices.pro
new file mode 100644
index 0000000..136930d
--- /dev/null
+++ b/src/devices/devices.pro
@@ -0,0 +1,2 @@
+TEMPLATE = subdirs
+SUBDIRS = base list pic mem24
diff --git a/src/devices/gui/Makefile.am b/src/devices/gui/Makefile.am
new file mode 100644
index 0000000..ae92163
--- /dev/null
+++ b/src/devices/gui/Makefile.am
@@ -0,0 +1,7 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+libdeviceui_la_LDFLAGS = $(all_libraries)
+noinst_LTLIBRARIES = libdeviceui.la
+libdeviceui_la_SOURCES = hex_word_editor.cpp memory_editor.cpp \
+		register_view.cpp hex_view.cpp device_group_ui.cpp
diff --git a/src/devices/gui/device_group_ui.cpp b/src/devices/gui/device_group_ui.cpp
new file mode 100644
index 0000000..64b5c14
--- /dev/null
+++ b/src/devices/gui/device_group_ui.cpp
@@ -0,0 +1,9 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "device_group_ui.h"
diff --git a/src/devices/gui/device_group_ui.h b/src/devices/gui/device_group_ui.h
new file mode 100644
index 0000000..3b2fa91
--- /dev/null
+++ b/src/devices/gui/device_group_ui.h
@@ -0,0 +1,45 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef DEVICE_GROUP_UI_H
+#define DEVICE_GROUP_UI_H
+
+#include <qpixmap.h>
+class QWidget;
+class KPopupMenu;
+class KListViewItem;
+class KAction;
+
+#include "devices/base/generic_device.h"
+#include "devices/base/device_group.h"
+#include "devices/base/register.h"
+namespace Register { class View; class ListViewItem; }
+class HexEditor;
+class ListContainer;
+
+namespace Device
+{
+class Memory;
+class HexView;
+class MemoryEditor;
+
+class GroupUI : public ::Group::BaseGui
+{
+public:
+  virtual HexView *createHexView(const HexEditor &editor, QWidget *parent) const = 0;
+  virtual Register::View *createRegisterView(QWidget *parent) const = 0;
+  virtual MemoryEditor *createConfigEditor(Device::Memory &memory, QWidget *parent) const = 0;
+  virtual void fillWatchListContainer(ListContainer *container, QValueVector<Register::TypeData> &ids) const = 0;
+  virtual Register::ListViewItem *createWatchItem(const Register::TypeData &data, KListViewItem *parent) const = 0;
+};
+
+inline const Device::GroupUI &groupui(const Device::Data &data) { return static_cast<const Device::GroupUI &>(*data.group().gui()); }
+
+} // namespace
+
+#endif
diff --git a/src/devices/gui/hex_view.cpp b/src/devices/gui/hex_view.cpp
new file mode 100644
index 0000000..6b26b0a
--- /dev/null
+++ b/src/devices/gui/hex_view.cpp
@@ -0,0 +1,23 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *   Copyright (C) 2003 Alain Gibaud <alain.gibaud@free.fr>                *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "hex_view.h"
+
+Device::HexView::HexView(const HexEditor &editor, QWidget *parent, const char *name)
+  : MemoryEditorGroup(0, parent, name), _editor(editor)
+{}
+
+void Device::HexView::display(Memory *memory)
+{
+  _memory = memory;
+  for (uint i=0; i<_editors.count(); i++) delete _editors[i];
+  _editors.clear();
+  if ( _memory==0 ) return;
+  display();
+}
diff --git a/src/devices/gui/hex_view.h b/src/devices/gui/hex_view.h
new file mode 100644
index 0000000..d73710e
--- /dev/null
+++ b/src/devices/gui/hex_view.h
@@ -0,0 +1,39 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *   Copyright (C) 2003 Alain Gibaud <alain.gibaud@free.fr>                *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef HEX_VIEW_H
+#define HEX_VIEW_H
+
+#include "memory_editor.h"
+#include "libgui/hex_editor.h"
+
+namespace Device
+{
+
+class HexView : public MemoryEditorGroup
+{
+Q_OBJECT
+public:
+  HexView(const HexEditor &editor, QWidget *parent, const char *name);
+  virtual void display(Memory *memory);
+  virtual uint nbChecksumChars() const = 0;
+  virtual BitValue checksum() const = 0;
+  bool isModified() const { return _editor.isModified(); }
+  const Memory *originalMemory() const { return _editor.originalMemory(); }
+
+protected:
+  virtual void display() = 0;
+
+private:
+  const HexEditor &_editor;
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/gui/hex_word_editor.cpp b/src/devices/gui/hex_word_editor.cpp
new file mode 100644
index 0000000..fd64e13
--- /dev/null
+++ b/src/devices/gui/hex_word_editor.cpp
@@ -0,0 +1,42 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *   Copyright (C) 2003-2004 Alain Gibaud <alain.gibaud@free.fr>           *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "hex_word_editor.h"
+
+#include <qframe.h>
+#include <qgroupbox.h>
+#include <qlabel.h>
+#include <qapplication.h>
+#include <qtimer.h>
+
+//-----------------------------------------------------------------------------
+Device::HexWordEditor::HexWordEditor(Memory &memory, uint nbChars, QWidget *parent)
+  : GenericHexWordEditor(nbChars, true, parent), _memory(memory)
+{
+  setOffset(-1);
+}
+
+void Device::HexWordEditor::setOffset(int offset)
+{
+  _offset = offset;
+  set();
+}
+
+//-----------------------------------------------------------------------------
+Device::RegisterHexWordEditor::RegisterHexWordEditor(QWidget *parent, uint nbChars, BitValue mask)
+  : GenericHexWordEditor(nbChars, true, parent), _mask(mask)
+{
+  clear();
+}
+
+void Device::RegisterHexWordEditor::setValue(BitValue word)
+{
+  _word = word;
+  set();
+}
diff --git a/src/devices/gui/hex_word_editor.h b/src/devices/gui/hex_word_editor.h
new file mode 100644
index 0000000..bd9fadb
--- /dev/null
+++ b/src/devices/gui/hex_word_editor.h
@@ -0,0 +1,64 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>             *
+ *   Copyright (C) 2003-2004 Alain Gibaud <alain.gibaud@free.fr>           *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef HEX_WORD_EDITOR_H
+#define HEX_WORD_EDITOR_H
+
+#include "common/gui/hexword_gui.h"
+#include "devices/base/generic_memory.h"
+
+namespace Device
+{
+//-----------------------------------------------------------------------------
+class HexWordEditor : public GenericHexWordEditor
+{
+Q_OBJECT
+public:
+  HexWordEditor(Memory &memory, uint nbChars, QWidget *parent);
+  void setOffset(int offset);
+  int offset() const { return _offset; }
+
+protected:
+  Device::Memory &_memory;
+  int _offset;
+
+  virtual bool isValid() const { return _offset!=-1; }
+  virtual BitValue mask() const = 0;
+  virtual BitValue normalizeWord(BitValue value) const = 0;
+  virtual BitValue word() const = 0;
+  virtual void setWord(BitValue value) = 0;
+  virtual BitValue blankValue() const { return BitValue(); }
+};
+
+//-----------------------------------------------------------------------------
+class RegisterHexWordEditor : public GenericHexWordEditor
+{
+Q_OBJECT
+public:
+  RegisterHexWordEditor(QWidget *parent, uint nbChars, BitValue mask);
+  void clear() { setValue(BitValue()); }
+  void setValue(BitValue word);
+  BitValue value() const { return _word; }
+  void setColor(QColor color) { setPaletteForegroundColor(color); }
+  void unsetColor() { unsetPalette(); }
+
+private:
+  BitValue _mask, _word;
+
+  virtual bool isValid() const { return true; }
+  virtual BitValue mask() const { return _mask; }
+  virtual BitValue normalizeWord(BitValue value) const { return value.maskWith(_mask); }
+  virtual BitValue word() const { return _word; }
+  virtual void setWord(BitValue value) { _word = value; }
+  virtual BitValue blankValue() const { return BitValue(); }
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/gui/memory_editor.cpp b/src/devices/gui/memory_editor.cpp
new file mode 100644
index 0000000..175f011
--- /dev/null
+++ b/src/devices/gui/memory_editor.cpp
@@ -0,0 +1,369 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *   Copyright (C) 2003-2004 Alain Gibaud <alain.gibaud@free.fr>           *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "memory_editor.h"
+
+#include <qlabel.h>
+#include <qscrollbar.h>
+#include <qlayout.h>
+#include <qgrid.h>
+#include <qtimer.h>
+#include <qpopupmenu.h>
+#include <klocale.h>
+#include <kpushbutton.h>
+#include <kaction.h>
+
+#include "common/common/misc.h"
+#include "hex_word_editor.h"
+#include "device_group_ui.h"
+#include "libgui/toplevel.h"
+#include "libgui/main_global.h"
+#include "hex_view.h"
+#include "libgui/gui_prog_manager.h"
+
+//-----------------------------------------------------------------------------
+Device::MemoryEditor::MemoryEditor(Device::Memory *memory, QWidget *parent, const char *name)
+  : QFrame(parent, name), _memory(memory)
+{
+  _top = new QVBoxLayout(this, 5, 10);
+}
+
+//-----------------------------------------------------------------------------
+Device::MemoryRangeEditor::MemoryRangeEditor(Device::Memory &memory,
+                    uint nbLines, uint nbCols, uint offset, int nb,
+                    QWidget *parent, const char *name)
+  : MemoryEditor(&memory, parent, name),
+    _nbLines(nbLines), _nbCols(nbCols), _offset(offset), _nb(nb)
+{}
+
+void Device::MemoryRangeEditor::init()
+{
+  if ( _nb==-1 ) _nb = nbWords();
+  uint totalNbLines = _nb / _nbCols;
+  if ( (_nb % _nbCols)!=0 ) totalNbLines++;
+
+  QHBoxLayout *hbox = new QHBoxLayout(_top);
+
+  QVBoxLayout *vbox = new QVBoxLayout(hbox);
+  QFrame *frame = new QFrame(this);
+  frame->setFrameStyle(QFrame::Panel | QFrame::Raised);
+  frame->setMargin(5);
+  vbox->addWidget(frame);
+  vbox->addStretch(1);
+  QHBoxLayout *fbox = new QHBoxLayout(frame, 5, 5);
+  QGrid *grid = new QGrid(3+_nbCols, QGrid::Horizontal, frame, "memory_range_editor_grid");
+  fbox->addWidget(grid);
+  grid->setSpacing(0);
+  grid->setMargin(3);
+  QFont f("courier", font().pointSize());
+  grid->setFont(f);
+  for (uint k=0; k<_nbLines; ++k) {
+    // addresses
+    QWidget *w = new QWidget(grid);
+    w->setFixedWidth(10);
+    _blocks.append(w);
+    QLabel *label = new QLabel(toHex(0, 2*_memory->device().nbBytesAddress()), grid, "address_label");
+    _addresses.append(label);
+    label = new QLabel(":", grid);
+    // memory
+    for (uint i = 0; i<_nbCols; ++i) {
+      HexWordEditor *h = createHexWordEditor(grid);
+      _editors.append(h);
+      connect(h, SIGNAL(modified()), SIGNAL(modified()));
+      connect(h, SIGNAL(moveNext()), SLOT(moveNext()));
+      connect(h, SIGNAL(movePrev()), SLOT(movePrev()));
+      connect(h, SIGNAL(moveFirst()), SLOT(moveFirst()));
+      connect(h, SIGNAL(moveLast()), SLOT(moveLast()));
+      connect(h, SIGNAL(moveUp()), SLOT(moveUp()));
+      connect(h, SIGNAL(moveDown()), SLOT(moveDown()));
+      connect(h, SIGNAL(moveNextPage()), SLOT(moveNextPage()));
+      connect(h, SIGNAL(movePrevPage()), SLOT(movePrevPage()));
+    }
+  }
+
+  //  scrollbar if there are more lines to display than visible
+  _scrollbar = new QScrollBar(0, QMAX(_nbLines, totalNbLines)-_nbLines, 1, _nbLines, 0,
+                              QScrollBar::Vertical, frame, "memory_range_editor_scrollbar");
+  connect(_scrollbar, SIGNAL(valueChanged(int)), SLOT(setIndex(int))) ;
+  if ( totalNbLines<=_nbLines ) _scrollbar->hide();
+  fbox->addWidget(_scrollbar);
+  fbox->addStretch(1);
+
+  vbox->addStretch(1);
+  QVBoxLayout *vboxc = new QVBoxLayout(hbox);
+  vboxc->setSpacing(0);
+  _comment = new QLabel(this);
+  _comment->hide();
+  vboxc->addWidget(_comment);
+  _spacer = new QLabel(this);
+  _spacer->setFixedHeight(10);
+  _spacer->hide();
+  vboxc->addWidget(_spacer);
+  addLegend(vboxc);
+  vboxc->addStretch(1);
+  hbox->addStretch(1);
+
+  setReadOnly(false);
+  setIndex(0);
+}
+
+void Device::MemoryRangeEditor::setComment(const QString &text)
+{
+  _comment->setText(text);
+  _comment->show();
+  _spacer->show();
+}
+
+void Device::MemoryRangeEditor::setReadOnly(bool readOnly)
+{
+  for (uint i=0; i<_editors.count(); i++)
+    _editors[i]->setReadOnly(readOnly || isRangeReadOnly());
+}
+
+void Device::MemoryRangeEditor::updateDisplay()
+{
+  setIndex(_scrollbar->value());
+}
+
+void Device::MemoryRangeEditor::setStartWord(int index)
+{
+  setIndex(index / _nbCols / addressIncrement());
+}
+
+void Device::MemoryRangeEditor::setEndWord(int index)
+{
+  uint i = index / _nbCols / addressIncrement();
+  i = (i<_nbLines ? 0 : i - _nbLines + 1);
+  setIndex(i);
+}
+
+void Device::MemoryRangeEditor::setIndex(int index)
+{
+  _scrollbar->blockSignals(true);
+  _scrollbar->setValue(index);
+  _scrollbar->blockSignals(false);
+
+  // memory
+  for (uint i=0; i<_editors.count(); i++) {
+    int offset = wordOffset() + i;
+    _editors[i]->setOffset(offset<int(nbWords()) ? offset : -1);
+  }
+
+  // adresses
+  uint inc = addressIncrement();
+  Address address = startAddress() + inc * wordOffset();
+  for (uint i=0; i<_addresses.count(); i++) {
+    _addresses[i]->setText(toHex(address, 2*_memory->device().nbBytesAddress()));
+    updateAddressColor(i, address);
+    address += inc * _nbCols;
+  }
+}
+
+void Device::MemoryRangeEditor::moveNext()
+{
+  QValueList<HexWordEditor *>::iterator it = _editors.find((HexWordEditor *)sender());
+  ++it;
+  if ( it==_editors.end() || (*it)->offset()==-1 ) {
+    if ( current()==uint(_scrollbar->maxValue()) ) return; // at end
+    setIndex(current()+1);
+    _editors[_editors.count()-_nbCols]->setFocus();
+  } else (*it)->setFocus();
+}
+
+void Device::MemoryRangeEditor::movePrev()
+{
+  QValueList<HexWordEditor *>::iterator it = _editors.find((HexWordEditor *)sender());
+  if ( it==_editors.begin() ) {
+    if ( current()==0 ) return; // at beginning
+    setIndex(current()-1);
+    _editors[_nbCols-1]->setFocus();
+  } else {
+    --it;
+    (*it)->setFocus();
+  }
+}
+
+void Device::MemoryRangeEditor::moveFirst()
+{
+  if ( _editors[0]==0 ) return;
+  setIndex(0);
+  _editors[0]->setFocus();
+}
+
+void Device::MemoryRangeEditor::moveLast()
+{
+  if ( _editors.count()==0 ) return;
+  setIndex(_scrollbar->maxValue());
+  for (uint i=1; i<=_nbCols; i++) {
+    if ( _editors[_editors.count()-i]->offset()==-1 ) continue;
+    _editors[_editors.count()-i]->setFocus();
+    break;
+  }
+}
+
+void Device::MemoryRangeEditor::moveUp()
+{
+  int i = _editors.findIndex((HexWordEditor *)sender());
+  uint line = i / _nbCols;
+  if ( line==0 ) {
+    if ( current()==0 ) return; // on first line
+    setIndex(current()-1);
+    _editors[i]->setFocus();
+  } else _editors[i-_nbCols]->setFocus();
+}
+
+void Device::MemoryRangeEditor::moveDown()
+{
+  int i = _editors.findIndex((HexWordEditor *)sender());
+  uint line = i / _nbCols;
+  if ( line+1==_nbLines ) {
+    if ( current()==uint(_scrollbar->maxValue()) ) return; // on last line
+    setIndex(current()+1);
+    if ( _editors[i]->offset()==-1 ) _editors[i-_nbCols]->setFocus();
+    else _editors[i]->setFocus();
+  } else _editors[i+_nbCols]->setFocus();
+}
+
+void Device::MemoryRangeEditor::moveNextPage()
+{
+  int i = _editors.findIndex((HexWordEditor *)sender());
+  if ( _nbLines>(uint(_scrollbar->maxValue()) - current()) ) i = (_nbLines-1) * _nbCols + (i % _nbCols);
+  else setIndex(current()+_nbLines);
+  if ( _editors[i]->offset()==-1 ) _editors[i-_nbCols]->setFocus();
+  else _editors[i]->setFocus();
+}
+
+void Device::MemoryRangeEditor::movePrevPage()
+{
+  int i = _editors.findIndex((HexWordEditor *)sender());
+  if ( current()<_nbLines ) i = (i % _nbCols);
+  else setIndex(current()-_nbLines);
+  _editors[i]->setFocus();
+}
+
+//-----------------------------------------------------------------------------
+Device::MemoryEditorGroup::MemoryEditorGroup(Device::Memory *memory, QWidget *parent, const char *name)
+  : MemoryEditor(memory, parent, name)
+{}
+
+void Device::MemoryEditorGroup::addEditor(MemoryEditor *editor)
+{
+  connect(editor, SIGNAL(modified()), SIGNAL(modified()));
+  _editors.append(editor);
+}
+
+void Device::MemoryEditorGroup::setReadOnly(bool readOnly)
+{
+  for (uint i=0; i<_editors.count(); i++)
+    _editors[i]->setReadOnly(readOnly);
+}
+
+void Device::MemoryEditorGroup::updateDisplay()
+{
+  for (uint i=0; i<_editors.count(); i++)
+    _editors[i]->updateDisplay();
+}
+
+//-----------------------------------------------------------------------------
+const Device::ActionData Device::ACTION_DATA[Nb_Actions] = {
+  { I18N_NOOP("&Clear"),       "fileclose",         NeedWrite },
+  { I18N_NOOP("&Zero"),        0,                   NeedWrite },
+  { I18N_NOOP("For checksum check"), 0,             NeedWrite },
+  { I18N_NOOP("Re&load"),      "reload",            SeparatorAfter | NeedModified },
+  { I18N_NOOP("&Program"),     "piklab_burnchip",   NeedProgrammer },
+  { I18N_NOOP("&Verify"),      "piklab_verifychip", NeedProgrammer },
+  { I18N_NOOP("&Read"),        "piklab_readchip",   NeedProgrammer | NeedWrite },
+  { I18N_NOOP("&Erase"),       "piklab_erasechip",  NeedProgrammer },
+  { I18N_NOOP("&Blank Check"), "piklab_blankcheck", NeedProgrammer }
+};
+
+Device::MemoryTypeEditor::MemoryTypeEditor(const HexView *hexview, Device::Memory &memory,
+                                            QWidget *parent, const char *name)
+  : MemoryEditorGroup(&memory, parent, name),
+    _title(0), _comment(0), _hexview(hexview)
+{
+  for (uint i=0; i<Nb_Actions; i++) _actions[i] = 0;
+}
+
+void Device::MemoryTypeEditor::init(bool first)
+{
+  if ( !first ) _top->addWidget(new SeparatorWidget(this));
+  QHBoxLayout *hbox = new QHBoxLayout(_top);
+
+  _title = new PopupButton(this);
+  for (uint i=0; i<Nb_Actions; i++) {
+    if ( hasAction(Action(i)) ) {
+      _actions[i] = new KAction(i18n(ACTION_DATA[i].label), ACTION_DATA[i].icon, 0,
+                                this, SLOT(doAction()), Main::toplevel().actionCollection());
+      addAction(_actions[i]);
+    }
+    if ( ACTION_DATA[i].properties & SeparatorAfter ) _title->appendSeparator();
+  }
+  _title->appendSeparator();
+  hbox->addWidget(_title);
+
+  _comment = new QLabel(this);
+  hbox->addWidget(_comment);
+  hbox->addStretch(1);
+
+  connect(&Main::toplevel(), SIGNAL(stateChanged()), SLOT(stateChanged()));
+}
+
+void Device::MemoryTypeEditor::addAction(KAction *action)
+{
+  _title->appendAction(action);
+}
+
+void Device::MemoryTypeEditor::doAction()
+{
+  for (uint i=0; i<Nb_Actions; i++) {
+    if ( sender()==_actions[i] ) {
+      doAction(Action(i));
+      break;
+    }
+  }
+}
+
+void Device::MemoryTypeEditor::doAction(Action action)
+{
+  if ( (ACTION_DATA[action].properties & NeedProgrammer)
+       && !Programmer::manager->initProgramming(false) ) return;
+  bool ok = internalDoAction(action);
+  if ( ACTION_DATA[action].properties & NeedProgrammer )
+    Programmer::manager->endProgramming();
+  if (ok) {
+    updateDisplay();
+    modified();
+  }
+}
+
+void Device::MemoryTypeEditor::stateChanged()
+{
+  bool idle = ( Main::state()==Main::Idle );
+  for (uint i=0; i<Nb_Actions; i++) {
+    if ( _actions[i]==0 ) continue;
+    bool on = true;
+    if ( (ACTION_DATA[i].properties & NeedProgrammer) && !idle ) on = false;
+    if ( (ACTION_DATA[i].properties & NeedWrite) && _readOnly ) on = false;
+    if ( (ACTION_DATA[i].properties & NeedModified) && (_hexview==0 || !_hexview->isModified()) ) on = false;
+    _actions[i]->setEnabled(on);
+  }
+}
+
+void Device::MemoryTypeEditor::setReadOnly(bool readOnly)
+{
+  _readOnly = readOnly;
+  MemoryEditorGroup::setReadOnly(readOnly);
+  stateChanged();
+}
+
+const Device::Memory *Device::MemoryTypeEditor::originalMemory() const
+{
+  return (_hexview ? _hexview->originalMemory() : 0);
+}
diff --git a/src/devices/gui/memory_editor.h b/src/devices/gui/memory_editor.h
new file mode 100644
index 0000000..9836261
--- /dev/null
+++ b/src/devices/gui/memory_editor.h
@@ -0,0 +1,156 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef MEMORY_EDITOR_H
+#define MEMORY_EDITOR_H
+
+#include <qframe.h>
+#include <qscrollbar.h>
+#include <qlabel.h>
+#include "common/common/qflags.h"
+#include "common/common/bitvalue.h"
+class QVBoxLayout;
+class QHBoxLayout;
+class QHBox;
+class KAction;
+class PopupButton;
+
+namespace Device
+{
+class HexView;
+class HexWordEditor;
+class Memory;
+
+enum Action { Clear = 0, Zero, ChecksumCheck, Reload,
+              Program, Verify, Read, Erase, BlankCheck, Nb_Actions };
+enum ActionProperty { NoProperty = 0, SeparatorAfter = 1, NeedProgrammer = 2,
+                      NeedWrite = 4, NeedModified = 8 };
+Q_DECLARE_FLAGS(ActionProperties, ActionProperty)
+Q_DECLARE_OPERATORS_FOR_FLAGS(ActionProperties)
+struct ActionData {
+  const char *label, *icon;
+  ActionProperties properties;
+};
+extern const ActionData ACTION_DATA[Nb_Actions];
+
+//----------------------------------------------------------------------------
+class MemoryEditor : public QFrame
+{
+Q_OBJECT
+public:
+  MemoryEditor(Device::Memory *memory, QWidget *parent, const char *name);
+  virtual void setReadOnly(bool readOnly) = 0;
+
+public slots:
+  virtual void updateDisplay() = 0;
+
+signals:
+  void modified();
+
+protected:
+  Device::Memory *_memory;
+  QVBoxLayout    *_top;
+};
+
+//----------------------------------------------------------------------------
+class MemoryRangeEditor : public MemoryEditor
+{
+Q_OBJECT
+public:
+  MemoryRangeEditor(Device::Memory &memory, uint nbLines, uint nbCols,
+                    uint offset, int nb, QWidget *parent, const char *name);
+  virtual void init();
+  virtual void setReadOnly(bool readOnly);
+  void setComment(const QString &text);
+
+public slots:
+  virtual void updateDisplay();
+  void moveNext();
+  void movePrev();
+  void moveFirst();
+  void moveLast();
+  void moveUp();
+  void moveDown();
+  void moveNextPage();
+  void movePrevPage();
+
+protected slots:
+  void setStartWord(int index);
+  void setEndWord(int index);
+  void setIndex(int index);
+
+protected:
+  uint _nbLines, _nbCols, _offset;
+  int  _nb;
+  QValueList<QLabel *> _addresses;
+  QValueList<QWidget *> _blocks;
+  QValueList<HexWordEditor *> _editors;
+  QScrollBar *_scrollbar;
+  QLabel     *_comment;
+  QWidget    *_spacer;
+
+  uint wordOffset() const { return _offset + current() * _nbCols; }
+  uint current() const { return _scrollbar->value(); }
+  virtual uint nbWords() const = 0;
+  virtual uint addressIncrement() const = 0;
+  virtual Address startAddress() const = 0;
+  virtual HexWordEditor *createHexWordEditor(QWidget *parent) = 0;
+  virtual bool isRangeReadOnly() const = 0;
+  virtual void updateAddressColor(uint i, Address address) { Q_UNUSED(i); Q_UNUSED(address); }
+  virtual void addLegend(QVBoxLayout *vbox) { Q_UNUSED(vbox); }
+};
+
+//----------------------------------------------------------------------------
+class MemoryEditorGroup : public MemoryEditor
+{
+Q_OBJECT
+public:
+  MemoryEditorGroup(Device::Memory *memory, QWidget *parent, const char *name);
+  void addEditor(MemoryEditor *editor);
+  virtual void setReadOnly(bool readOnly);
+
+public slots:
+  virtual void updateDisplay();
+
+protected:
+  bool _modified;
+  QValueList<MemoryEditor *> _editors;
+};
+
+//----------------------------------------------------------------------------
+class MemoryTypeEditor : public MemoryEditorGroup
+{
+Q_OBJECT
+public:
+  MemoryTypeEditor(const HexView *hexview, Device::Memory &memory, QWidget *parent, const char *name);
+  virtual void init(bool first);
+  virtual void setReadOnly(bool readOnly);
+
+protected slots:
+  void doAction();
+  void stateChanged();
+
+protected:
+  PopupButton   *_title;
+  QLabel        *_comment;
+  const HexView *_hexview;
+  virtual bool internalDoAction(Action action) = 0; // return true if memory modified
+  virtual bool hasAction(Action) const { return true; }
+  void addAction(KAction *action);
+  const Device::Memory *originalMemory() const;
+
+private:
+  bool     _readOnly;
+  KAction *_actions[Nb_Actions];
+
+  void doAction(Action action);
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/gui/register_view.cpp b/src/devices/gui/register_view.cpp
new file mode 100644
index 0000000..70dedc9
--- /dev/null
+++ b/src/devices/gui/register_view.cpp
@@ -0,0 +1,208 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "register_view.h"
+
+#include "libgui/main_global.h"
+#include "libgui/gui_debug_manager.h"
+
+//----------------------------------------------------------------------------
+Register::PortBitListViewItem::PortBitListViewItem(uint index, uint bit, KListViewItem *parent)
+  : KListViewItem(parent), _index(index), _bit(bit)
+{
+  const Device::RegistersData *rdata = Main::deviceData()->registersData();
+  setText(1, rdata->portBitName(_index, _bit));
+  setSelectable(false);
+}
+
+void Register::PortBitListViewItem::updateView()
+{
+  const QMap<uint, Device::PortBitData> &pdata = Register::list().portData(_index);
+  QString text;
+  if ( pdata.isEmpty() ) text = "--";
+  else {
+/*
+    switch (pdata[_bit].state) {
+      case Device::High: text = " 1"; break;
+      case Device::Low: text = " 0"; break;
+      case Device::WeakPullUp: text = "w1"; break;
+      case Device::WeakPullDown: text = "w0"; break;
+      case Device::HighImpedance: text = "HZ"; break;
+      case Device::Unknown: text = "  "; break;
+    }
+*/
+    if ( pdata[_bit].drivingState==Device::IoUnknown ) text = " ";
+    else text += (pdata[_bit].drivingState==Device::IoHigh ? "1" : "0");
+    text += (pdata[_bit].driving ? " > " : " < ");
+    if ( pdata[_bit].drivenState==Device::IoUnknown ) text += " ";
+    else text += (pdata[_bit].drivenState==Device::IoHigh ? "1" : "0");
+  }
+  setText(2, text);
+  repaint();
+}
+
+void Register::PortBitListViewItem::paintCell(QPainter *p, const QColorGroup &cg, int column, int width, int align)
+{
+  QColorGroup ncg = cg;
+  const QMap<uint, Device::PortBitData> &data = Register::list().portData(_index);
+  const QMap<uint, Device::PortBitData> &odata = Register::list().oldPortData(_index);
+  bool changed = ( !data.isEmpty() && data[_bit]!=odata[_bit] );
+  if ( column==2 && changed ) ncg.setColor(QColorGroup::Text, red);
+  KListViewItem::paintCell(p, ncg, column, width, align);
+}
+
+QString Register::PortBitListViewItem::tooltip(int col) const
+{
+  if ( col!=2 ) return QString::null;
+  const QMap<uint, Device::PortBitData> &pdata = Register::list().portData(_index);
+  if ( pdata.isEmpty() ) return QString::null;
+  QString s = text(1) + ": ";
+  if (pdata[_bit].driving) {
+    if ( pdata[_bit].drivingState!=Device::IoUnknown ) s += i18n("unknown state");
+    else s += (pdata[_bit].drivingState==Device::IoHigh ? i18n("driving high") : i18n("driving low"));
+    s += i18n(" (output)");
+  } else {
+    if ( pdata[_bit].drivenState==Device::IoUnknown ) s += i18n("unknown state");
+    else s += (pdata[_bit].drivenState==Device::IoHigh ? i18n("driven high") : i18n("driven low"));
+    s += i18n(" (input)");
+  }
+  return s;
+}
+
+//-----------------------------------------------------------------------------
+Register::ListViewItem::ListViewItem(const TypeData &data, KListViewItem *parent)
+  : EditListViewItem(parent), _data(data), _base(NumberBase::Hex)
+{
+  setSelectable(false);
+  const Device::RegistersData *rdata = Main::deviceData()->registersData();
+  if ( data.type()==Regular && rdata ) {
+    int i = rdata->portIndex(data.address());
+    if ( i!=-1 ) {
+      for (int k=Device::MAX_NB_PORT_BITS-1; k>=0; k--) {
+        if ( !rdata->hasPortBit(i, k) ) continue;
+        PortBitListViewItem *item = new PortBitListViewItem(i, k, this);
+        _items.append(item);
+      }
+    }
+  }
+}
+
+QString Register::ListViewItem::text() const
+{
+  BitValue value = Register::list().value(_data);
+  uint nbChars = convertNbChars(_data.nbChars(), NumberBase::Hex, _base);
+  return (value.isInitialized() ? toLabel(_base, value, nbChars) : "--");
+}
+
+int Register::ListViewItem::compare(QListViewItem *item, int, bool) const
+{
+  const TypeData &data = static_cast<ListViewItem *>(item)->data();
+  int i1 = list().watched().findIndex(data);
+  Q_ASSERT( i1!=-1 );
+  int i2 = list().watched().findIndex(_data);
+  Q_ASSERT( i2!=-1 );
+  return ( i1-i2 );
+}
+
+void Register::ListViewItem::updateView()
+{
+  if ( _data.type()!=Special ) setText(0, toHexLabel(_data.address(), nbCharsAddress()) + ":");
+  setText(1, label());
+  setText(2, text());
+  repaint();
+  for (uint i=0; i<_items.count(); i++) _items[i]->updateView();
+}
+
+void Register::ListViewItem::setBase(NumberBase base)
+{
+  _base = base;
+  updateView();
+}
+
+void Register::ListViewItem::paintCell(QPainter *p, const QColorGroup &cg, int column, int width, int align)
+{
+  QColorGroup ncg = cg;
+  BitValue value = Register::list().value(_data);
+  BitValue oldValue = Register::list().oldValue(_data);
+  if ( column==2 && value!=oldValue ) ncg.setColor(QColorGroup::Text, red);
+  EditListViewItem::paintCell(p, ncg, column, width, align);
+}
+
+QString Register::ListViewItem::tooltip(int col) const
+{
+  if ( col!=2 ) return QString::null;
+  BitValue value = Register::list().value(_data);
+  if ( !value.isInitialized() ) return QString::null;
+  BitValue v = value;
+  QString s;
+  for (uint i=0; i<_data.nbChars(); i++) {
+    char c = v.nybble(i);
+    if ( isprint(c) ) s = c + s;
+    else s = "." + s;
+  }
+  return QString("%1 - %2 - \"%3\"").arg(toHexLabel(value, _data.nbChars()))
+         .arg(toLabel(NumberBase::Bin, value, 4*_data.nbChars())).arg(s);
+}
+
+QWidget *Register::ListViewItem::editWidgetFactory(int col) const
+{
+  if ( col!=2 || Main::programmerState()!=Programmer::Halted ) return 0;
+  return new NumberLineEdit(text(), 0);
+}
+
+void Register::ListViewItem::editDone(int col, const QWidget *edit)
+{
+  if ( col!=2 ) return;
+  bool ok;
+  ulong value = static_cast<const NumberLineEdit *>(edit)->value(&ok);
+  if (ok) Debugger::manager->writeRegister(_data, value);
+}
+
+//----------------------------------------------------------------------------
+Register::LineEdit::LineEdit(QWidget *parent, const char *name)
+  : NumberLineEdit(parent, name), _base(NumberBase::Nb_Types)
+{
+  connect(this, SIGNAL(lostFocus()), SLOT(updateText()));
+  connect(this, SIGNAL(returnPressed()), SLOT(returnPressedSlot()));
+}
+
+void Register::LineEdit::updateText()
+{
+  setText(_value.isInitialized() ? toLabel(_base, _value, _nbChars) : "--");
+  uint w = 2*frameWidth() + maxLabelWidth(_base, _nbChars, font());
+  setFixedWidth(w+5);
+  setFixedHeight(minimumSizeHint().height());
+}
+
+void Register::LineEdit::setValue(NumberBase base, BitValue value, uint nbChars)
+{
+  _base = base;
+  _value = value;
+  _nbChars = nbChars;
+  updateText();
+}
+
+void Register::LineEdit::returnPressedSlot()
+{
+  bool ok;
+  uint v = fromAnyLabel(text(), &ok);
+  if (ok) _value = v;
+  updateText();
+  emit modified();
+}
+
+void Register::LineEdit::keyPressEvent(QKeyEvent *e)
+{
+  if ( e->key()==Key_Escape ) clearFocus();
+  else NumberLineEdit::keyPressEvent(e);
+}
+
+//----------------------------------------------------------------------------
+Register::View::View(QWidget *parent, const char *name)
+ : QFrame(parent, name), GenericView(list())
+{}
diff --git a/src/devices/gui/register_view.h b/src/devices/gui/register_view.h
new file mode 100644
index 0000000..7ef8a54
--- /dev/null
+++ b/src/devices/gui/register_view.h
@@ -0,0 +1,105 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef REGISTER_VIEW_H
+#define REGISTER_VIEW_H
+
+#include <qframe.h>
+
+#include "devices/base/register.h"
+#include "common/gui/number_gui.h"
+#include "common/gui/list_view.h"
+
+namespace Register
+{
+enum { PortBitRtti = 1000, RegisterRtti = 1001 };
+
+//-----------------------------------------------------------------------------
+class PortBitListViewItem : public KListViewItem
+{
+public:
+  PortBitListViewItem(uint address, uint bit, KListViewItem *parent);
+  virtual int rtti() const { return PortBitRtti; }
+  void updateView();
+  QString tooltip(int column) const;
+
+private:
+  uint _index, _bit;
+
+  virtual void paintCell(QPainter *p, const QColorGroup &cg, int column, int width, int align);
+};
+
+//-----------------------------------------------------------------------------
+class ListViewItem : public EditListViewItem
+{
+public:
+  ListViewItem(const TypeData &data, KListViewItem *item);
+  virtual int rtti() const { return RegisterRtti; }
+  virtual void updateView();
+  const TypeData &data() const { return _data; }
+  QString tooltip(int column) const;
+  NumberBase base() const { return _base; }
+  void setBase(NumberBase base);
+  virtual QString label() const = 0;
+  virtual int compare(QListViewItem *item, int, bool) const;
+
+protected:
+  TypeData _data;
+  QValueList<PortBitListViewItem *> _items;
+  NumberBase _base;
+
+  virtual void paintCell(QPainter *p, const QColorGroup &cg, int column, int width, int align);
+  virtual QWidget *editWidgetFactory(int col) const;
+  virtual bool alwaysAcceptEdit(int) const { return false; }
+  virtual void editDone(int col, const QWidget *editWidget);
+  virtual uint nbCharsAddress() const = 0;
+  virtual QString text() const;
+  virtual void activate() {}
+};
+
+//-----------------------------------------------------------------------------
+class LineEdit : public NumberLineEdit
+{
+Q_OBJECT
+public:
+  LineEdit(QWidget *parent, const char *name = 0);
+  void setValue(NumberBase base, BitValue value, uint nbChars);
+  BitValue value() const { return _value; }
+
+signals:
+  void modified();
+
+protected:
+  virtual void keyPressEvent(QKeyEvent *e);
+
+private slots:
+  void updateText();
+  void returnPressedSlot();
+
+private:
+  NumberBase _base;
+  BitValue   _value;
+  uint       _nbChars;
+};
+
+//-----------------------------------------------------------------------------
+class View : public QFrame, public GenericView
+{
+Q_OBJECT
+public:
+  View(QWidget *parent, const char *name);
+
+signals:
+  void readSignal(uint address);
+  void writeSignal(uint address, uint value);
+  void setWatchedSignal(uint address, bool watched);
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/list/Makefile.am b/src/devices/list/Makefile.am
new file mode 100644
index 0000000..ce1c03a
--- /dev/null
+++ b/src/devices/list/Makefile.am
@@ -0,0 +1,11 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+
+noinst_LTLIBRARIES = libdevicelistnoui.la libdevicelistui.la
+
+libdevicelistnoui_la_LDFLAGS = $(all_libraries)
+libdevicelistnoui_la_SOURCES = device_list.cpp device_list_noui.cpp
+
+libdevicelistui_la_LDFLAGS = $(all_libraries)
+libdevicelistui_la_SOURCES = device_list.cpp device_list_ui.cpp
diff --git a/src/devices/list/device_list.cpp b/src/devices/list/device_list.cpp
new file mode 100644
index 0000000..1434ec8
--- /dev/null
+++ b/src/devices/list/device_list.cpp
@@ -0,0 +1,40 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "device_list.h"
+
+#include <qregexp.h>
+
+#include "devices/pic/pic/pic_group.h"
+#include "devices/mem24/mem24/mem24_group.h"
+
+const Device::AutoData Device::AUTO_DATA = { "*", I18N_NOOP("<auto>") };
+
+const Device::Data *Device::Lister::data(const QString &device) const
+{
+  for (ConstIterator it=begin(); it!=end(); it++) {
+    const Data *data = static_cast<const Data *>(it.data()->deviceData(device).data);
+    if (data) return data;
+  }
+  return 0;
+}
+
+QString Device::Lister::checkName(const QString &device) const
+{
+  if ( device==AUTO_DATA.name ) return device;
+  if ( isSupported(device) ) return device;
+  if ( device.startsWith("p") ) // compat mode for PiKdev
+    return checkName(device.mid(1));
+  return "16F871"; // default...
+}
+
+namespace Device
+{
+  Lister _lister;
+  const Lister &lister() { return _lister; }
+}
diff --git a/src/devices/list/device_list.h b/src/devices/list/device_list.h
new file mode 100644
index 0000000..3d9fb78
--- /dev/null
+++ b/src/devices/list/device_list.h
@@ -0,0 +1,34 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef DEVICE_LIST_H
+#define DEVICE_LIST_H
+
+#include "devices/base/generic_device.h"
+#include "common/common/lister.h"
+
+namespace Device
+{
+
+struct AutoData {
+  const char *name, *label;
+};
+extern const AutoData AUTO_DATA;
+
+class Lister : public ::Group::Lister<GroupBase>
+{
+public:
+  Lister();
+  const Data *data(const QString &device) const;
+  QString checkName(const QString &device) const;
+};
+extern const Lister &lister();
+
+} // namespace
+
+#endif
diff --git a/src/devices/list/device_list_noui.cpp b/src/devices/list/device_list_noui.cpp
new file mode 100644
index 0000000..46d909e
--- /dev/null
+++ b/src/devices/list/device_list_noui.cpp
@@ -0,0 +1,18 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "device_list.h"
+
+#include "devices/pic/pic/pic_group.h"
+#include "devices/mem24/mem24/mem24_group.h"
+
+Device::Lister::Lister()
+{
+  addGroup(new Pic::Group, 0);
+  addGroup(new Mem24::Group, 0);
+}
diff --git a/src/devices/list/device_list_ui.cpp b/src/devices/list/device_list_ui.cpp
new file mode 100644
index 0000000..ebcd7ea
--- /dev/null
+++ b/src/devices/list/device_list_ui.cpp
@@ -0,0 +1,20 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "device_list.h"
+
+#include "devices/pic/pic/pic_group.h"
+#include "devices/pic/gui/pic_group_ui.h"
+#include "devices/mem24/mem24/mem24_group.h"
+#include "devices/mem24/gui/mem24_group_ui.h"
+
+Device::Lister::Lister()
+{
+  addGroup(new Pic::Group, new Pic::GroupUI);
+  addGroup(new Mem24::Group, new Mem24::GroupUI);
+}
diff --git a/src/devices/list/list.pro b/src/devices/list/list.pro
new file mode 100644
index 0000000..02f07b0
--- /dev/null
+++ b/src/devices/list/list.pro
@@ -0,0 +1,6 @@
+STOPDIR = ../../..
+include($${STOPDIR}/lib.pro)
+
+TARGET   = devicelist
+HEADERS += device_list.h
+SOURCES += device_list.cpp device_list_noui.cpp
diff --git a/src/devices/mem24/Makefile.am b/src/devices/mem24/Makefile.am
new file mode 100644
index 0000000..7c80d86
--- /dev/null
+++ b/src/devices/mem24/Makefile.am
@@ -0,0 +1,3 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+SUBDIRS = base xml xml_data mem24 prog gui
diff --git a/src/devices/mem24/base/Makefile.am b/src/devices/mem24/base/Makefile.am
new file mode 100644
index 0000000..336afca
--- /dev/null
+++ b/src/devices/mem24/base/Makefile.am
@@ -0,0 +1,6 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+noinst_LTLIBRARIES = libmem24base.la
+libmem24base_la_LDFLAGS = $(all_libraries)
+libmem24base_la_SOURCES = mem24.cpp
diff --git a/src/devices/mem24/base/base.pro b/src/devices/mem24/base/base.pro
new file mode 100644
index 0000000..a42b768
--- /dev/null
+++ b/src/devices/mem24/base/base.pro
@@ -0,0 +1,6 @@
+STOPDIR = ../../../..
+include($${STOPDIR}/lib.pro)
+
+TARGET   = mem24base
+HEADERS += mem24.h
+SOURCES += mem24.cpp
diff --git a/src/devices/mem24/base/mem24.cpp b/src/devices/mem24/base/mem24.cpp
new file mode 100644
index 0000000..03bffe3
--- /dev/null
+++ b/src/devices/mem24/base/mem24.cpp
@@ -0,0 +1,22 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "mem24.h"
+
+QDataStream &Mem24::operator <<(QDataStream &s, const Data &data)
+{
+  s << static_cast<const Device::Data &>(data);
+  s << data._nbBytes << data._nbBlocks << data._nbBytesPage;
+  return s;
+}
+QDataStream &Mem24::operator >>(QDataStream &s, Data &data)
+{
+  s >> static_cast<Device::Data &>(data);
+  s >> data._nbBytes >> data._nbBlocks >> data._nbBytesPage;
+  return s;
+}
diff --git a/src/devices/mem24/base/mem24.h b/src/devices/mem24/base/mem24.h
new file mode 100644
index 0000000..d66ff47
--- /dev/null
+++ b/src/devices/mem24/base/mem24.h
@@ -0,0 +1,47 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef MEM24_H
+#define MEM24_H
+
+#include "common/common/misc.h"
+#include "devices/base/generic_device.h"
+
+namespace Mem24
+{
+class XmlToData;
+class Group;
+
+//-----------------------------------------------------------------------------
+class Data : public Device::Data
+{
+public:
+  Data() : Device::Data(0) {}
+  virtual QString listViewGroup() const { return i18n("24 EEPROM"); }
+  uint nbBytes() const { return _nbBytes; }
+  virtual bool matchId(BitValue, Device::IdData &) const { return false; }
+  virtual uint nbBitsAddress() const { return nbBits(_nbBytes-1); }
+  virtual bool canWriteCalibration() const { return false; }
+  uint nbBlocks() const { return _nbBlocks; }
+  uint nbBytesPage() const { return _nbBytesPage; }
+
+private:
+  uint _nbBytes, _nbBlocks, _nbBytesPage;
+
+  friend class XmlToData;
+  friend class Group;
+  friend QDataStream &operator <<(QDataStream &s, const Data &data);
+  friend QDataStream &operator >>(QDataStream &s, Data &data);
+};
+
+QDataStream &operator <<(QDataStream &s, const Data &data);
+QDataStream &operator >>(QDataStream &s, Data &data);
+
+} // namespace
+
+#endif
diff --git a/src/devices/mem24/gui/Makefile.am b/src/devices/mem24/gui/Makefile.am
new file mode 100644
index 0000000..6838d57
--- /dev/null
+++ b/src/devices/mem24/gui/Makefile.am
@@ -0,0 +1,7 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+noinst_LTLIBRARIES = libmem24ui.la
+libmem24ui_la_SOURCES = mem24_hex_view.cpp mem24_memory_editor.cpp \
+	mem24_group_ui.cpp
+libmem24ui_la_LDFLAGS = $(all_libraries)
diff --git a/src/devices/mem24/gui/mem24_group_ui.cpp b/src/devices/mem24/gui/mem24_group_ui.cpp
new file mode 100644
index 0000000..751e5a7
--- /dev/null
+++ b/src/devices/mem24/gui/mem24_group_ui.cpp
@@ -0,0 +1,16 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "mem24_group_ui.h"
+
+#include "mem24_hex_view.h"
+
+Device::HexView *Mem24::GroupUI::createHexView(const HexEditor &editor, QWidget *parent) const
+{
+  return new HexView(editor, parent);
+}
diff --git a/src/devices/mem24/gui/mem24_group_ui.h b/src/devices/mem24/gui/mem24_group_ui.h
new file mode 100644
index 0000000..37766b5
--- /dev/null
+++ b/src/devices/mem24/gui/mem24_group_ui.h
@@ -0,0 +1,28 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef MEM24_GROUP_UI_H
+#define MEM24_GROUP_UI_H
+
+#include "devices/gui/device_group_ui.h"
+
+namespace Mem24
+{
+class GroupUI : public Device::GroupUI
+{
+public:
+  virtual Device::HexView *createHexView(const HexEditor &editor, QWidget *parent) const;
+  virtual Register::View *createRegisterView(QWidget *) const { return 0; }
+  virtual Device::MemoryEditor *createConfigEditor(Device::Memory &, QWidget *) const { return 0; }
+  virtual void fillWatchListContainer(ListContainer *, QValueVector<Register::TypeData> &) const {}
+  virtual Register::ListViewItem *createWatchItem(const Register::TypeData &, KListViewItem *) const { return 0; }
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/mem24/gui/mem24_hex_view.cpp b/src/devices/mem24/gui/mem24_hex_view.cpp
new file mode 100644
index 0000000..0ada8d0
--- /dev/null
+++ b/src/devices/mem24/gui/mem24_hex_view.cpp
@@ -0,0 +1,38 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "mem24_hex_view.h"
+
+#include <qlayout.h>
+#include <qlabel.h>
+#include <klocale.h>
+
+#include "mem24_memory_editor.h"
+
+Mem24::HexView::HexView(const HexEditor &editor, QWidget *parent)
+  : Device::HexView(editor, parent, "mem24_hex_view")
+{}
+
+void Mem24::HexView::display()
+{
+  Memory *pmemory = static_cast<Memory *>(_memory);
+  MemoryTypeEditor *e = new MemoryTypeEditor(this, *pmemory, this);
+  e->init(true);
+  e->show();
+  _top->addWidget(e);
+  addEditor(e);
+}
+
+BitValue Mem24::HexView::checksum() const
+{
+  if ( _memory==0 ) return 0x0000;
+  BitValue cs = 0x0000;
+  for (uint i=0; i<static_cast<const Data &>(_memory->device()).nbBytes(); i++)
+    cs += static_cast<const Memory *>(_memory)->byte(i);
+  return cs.maskWith(0xFFFF);
+}
diff --git a/src/devices/mem24/gui/mem24_hex_view.h b/src/devices/mem24/gui/mem24_hex_view.h
new file mode 100644
index 0000000..378a25e
--- /dev/null
+++ b/src/devices/mem24/gui/mem24_hex_view.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef MEM24_HEX_VIEW_H
+#define MEM24_HEX_VIEW_H
+
+class QVBoxLayout;
+
+#include "devices/gui/hex_view.h"
+
+namespace Mem24
+{
+
+class HexView : public Device::HexView
+{
+Q_OBJECT
+public:
+  HexView(const HexEditor &editor, QWidget *parent);
+  virtual uint nbChecksumChars() const { return 4; }
+  virtual BitValue checksum() const;
+
+private:
+  virtual void display();
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/mem24/gui/mem24_memory_editor.cpp b/src/devices/mem24/gui/mem24_memory_editor.cpp
new file mode 100644
index 0000000..61f98fe
--- /dev/null
+++ b/src/devices/mem24/gui/mem24_memory_editor.cpp
@@ -0,0 +1,80 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "mem24_memory_editor.h"
+
+#include <qlayout.h>
+#include <klocale.h>
+#include <kpushbutton.h>
+
+#include "common/gui/misc_gui.h"
+#include "mem24_hex_view.h"
+#include "progs/base/generic_prog.h"
+#include "libgui/main_global.h"
+#include "devices/base/device_group.h"
+
+//-----------------------------------------------------------------------------
+Mem24::MemoryRangeEditor::MemoryRangeEditor(Memory &memory, QWidget *parent)
+  : Device::MemoryRangeEditor(memory, 16, 16, 0, -1, parent, "mem24_memory_range_editor"),
+    MemoryCaster(memory)
+{}
+
+Device::HexWordEditor *Mem24::MemoryRangeEditor::createHexWordEditor(QWidget *parent)
+{
+  return new HexWordEditor(memory(), parent);
+}
+
+//-----------------------------------------------------------------------------
+Mem24::MemoryTypeEditor::MemoryTypeEditor(const HexView *hexview, Memory &memory, QWidget *parent)
+  : Device::MemoryTypeEditor(hexview, memory, parent, "mem24_memory_type_editor"),
+    MemoryCaster(memory)
+{}
+
+void Mem24::MemoryTypeEditor::init(bool first)
+{
+  Device::MemoryTypeEditor::init(first);
+  _title->setText(i18n("EEPROM Memory"));
+  MemoryRangeEditor *mre = new MemoryRangeEditor(memory(), this);
+  mre->init();
+  addEditor(mre);
+  _top->addWidget(mre);
+}
+
+bool Mem24::MemoryTypeEditor::internalDoAction(Device::Action action)
+{
+  switch (action) {
+    case Device::Clear:
+    case Device::ChecksumCheck:
+      memory().clear(); return true;
+    case Device::Zero:  memory().fill(0);  return true;
+    case Device::Reload:
+      Q_ASSERT(originalMemory());
+      memory().copyFrom(*originalMemory()); return true;
+    case Device::Program:
+      Main::programmer()->program(memory(), Device::MemoryRange());
+      return false;
+    case Device::Verify:
+      Main::programmer()->verify(memory(), Device::MemoryRange());
+      return false;
+    case Device::Read: {
+      Memory mem(device());
+      if ( !Main::programmer()->read(mem, Device::MemoryRange()) ) return false;
+      memory().copyFrom(mem);
+      return true;
+    }
+    case Device::Erase:
+      Main::programmer()->erase(Device::MemoryRange());
+      return false;
+    case Device::BlankCheck:
+      Main::programmer()->blankCheck(Device::MemoryRange());
+      return false;
+    case Device::Nb_Actions: break;
+  }
+  Q_ASSERT(false);
+  return false;
+}
diff --git a/src/devices/mem24/gui/mem24_memory_editor.h b/src/devices/mem24/gui/mem24_memory_editor.h
new file mode 100644
index 0000000..eb99e97
--- /dev/null
+++ b/src/devices/mem24/gui/mem24_memory_editor.h
@@ -0,0 +1,77 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef MEM24_MEMORY_EDITOR_H
+#define MEM24_MEMORY_EDITOR_H
+
+#include "devices/gui/memory_editor.h"
+#include "devices/gui/hex_word_editor.h"
+#include "devices/mem24/mem24/mem24_memory.h"
+
+namespace Mem24
+{
+class HexView;
+
+//-----------------------------------------------------------------------------
+class MemoryCaster
+{
+public:
+  MemoryCaster(Memory &memory) : _memory(memory) {}
+  const Data &device() const { return static_cast<const Data &>(_memory.device()); }
+  const Memory &memory() const { return static_cast<Memory &>(_memory); }
+  Memory &memory() { return static_cast<Memory &>(_memory); }
+
+private:
+  Memory &_memory;
+};
+
+//-----------------------------------------------------------------------------
+class HexWordEditor : public Device::HexWordEditor, public MemoryCaster
+{
+Q_OBJECT
+public:
+  HexWordEditor(Memory &memory, QWidget *parent)
+    : Device::HexWordEditor(memory, 2, parent), MemoryCaster(memory) {}
+
+private:
+  virtual BitValue mask() const { return 0xFF; }
+  virtual BitValue normalizeWord(BitValue value) const { return value; }
+  virtual BitValue word() const { return memory().byte(_offset); }
+  virtual void setWord(BitValue value) { memory().setByte(_offset, value); }
+};
+
+//-----------------------------------------------------------------------------
+class MemoryRangeEditor : public Device::MemoryRangeEditor, public MemoryCaster
+{
+Q_OBJECT
+public:
+  MemoryRangeEditor(Memory &memory, QWidget *parent);
+
+private:
+  virtual uint nbWords() const { return device().nbBytes(); }
+  virtual uint addressIncrement() const { return 1; }
+  virtual Address startAddress() const { return 0x0; }
+  virtual Device::HexWordEditor *createHexWordEditor(QWidget *parent);
+  virtual bool isRangeReadOnly() const { return false; }
+};
+
+//-----------------------------------------------------------------------------
+class MemoryTypeEditor : public Device::MemoryTypeEditor, public MemoryCaster
+{
+Q_OBJECT
+public:
+  MemoryTypeEditor(const HexView *hexview, Memory &memory, QWidget *parent);
+  virtual void init(bool first);
+
+private:
+  virtual bool internalDoAction(Device::Action action);
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/mem24/mem24.pro b/src/devices/mem24/mem24.pro
new file mode 100644
index 0000000..0602143
--- /dev/null
+++ b/src/devices/mem24/mem24.pro
@@ -0,0 +1,2 @@
+TEMPLATE = subdirs
+SUBDIRS = base xml mem24 xml_data prog
diff --git a/src/devices/mem24/mem24/Makefile.am b/src/devices/mem24/mem24/Makefile.am
new file mode 100644
index 0000000..3c7e9a8
--- /dev/null
+++ b/src/devices/mem24/mem24/Makefile.am
@@ -0,0 +1,6 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+noinst_LTLIBRARIES = libmem24.la
+libmem24_la_LDFLAGS = $(all_libraries)
+libmem24_la_SOURCES = mem24_memory.cpp mem24_group.cpp
diff --git a/src/devices/mem24/mem24/mem24.pro b/src/devices/mem24/mem24/mem24.pro
new file mode 100644
index 0000000..4bdbea4
--- /dev/null
+++ b/src/devices/mem24/mem24/mem24.pro
@@ -0,0 +1,6 @@
+STOPDIR = ../../../..
+include($${STOPDIR}/lib.pro)
+
+TARGET   = mem24
+HEADERS += mem24_memory.h mem24_group.h
+SOURCES += mem24_memory.cpp mem24_group.cpp
diff --git a/src/devices/mem24/mem24/mem24_group.cpp b/src/devices/mem24/mem24/mem24_group.cpp
new file mode 100644
index 0000000..53cad5b
--- /dev/null
+++ b/src/devices/mem24/mem24/mem24_group.cpp
@@ -0,0 +1,43 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "mem24_group.h"
+
+#include "mem24_memory.h"
+
+Device::Memory *Mem24::Group::createMemory(const Device::Data &data) const
+{
+  return new Memory(static_cast<const Mem24::Data &>(data));
+}
+
+QString Mem24::Group::informationHtml(const Device::Data &data) const
+{
+  const Mem24::Data &mdata = static_cast<const Mem24::Data &>(data);
+  QString tmp = i18n("%1 bytes").arg(formatNumber(mdata.nbBytes()));
+  return htmlTableRow(i18n("Memory Size"), tmp);
+}
+
+#if !defined(NO_KDE)
+QPixmap Mem24::Group::memoryGraph(const Device::Data &data) const
+{
+  const Mem24::Data &mdata = static_cast<const Mem24::Data &>(data);
+  uint offset = 0x0;
+  QValueList<Device::MemoryGraphData> ranges;
+  for (uint i=0; i<mdata.nbBlocks(); i++) {
+    Device::MemoryGraphData data;
+    data.startAddress = offset;
+    offset += mdata.nbBytes() / mdata.nbBlocks();
+    data.endAddress = offset - 1;
+    data.start = toHexLabel(data.startAddress, mdata.nbCharsAddress());
+    data.end = toHexLabel(data.endAddress, mdata.nbCharsAddress());
+    data.label = i18n("Block #%1").arg(i+1);
+    ranges.append(data);
+  }
+  return Device::memoryGraph(ranges);
+}
+#endif
diff --git a/src/devices/mem24/mem24/mem24_group.h b/src/devices/mem24/mem24/mem24_group.h
new file mode 100644
index 0000000..46a1234
--- /dev/null
+++ b/src/devices/mem24/mem24/mem24_group.h
@@ -0,0 +1,39 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef MEM24_GROUP_H
+#define MEM24_GROUP_H
+
+#include "common/global/global.h"
+#include "devices/base/device_group.h"
+#include "devices/mem24/base/mem24.h"
+
+namespace Mem24
+{
+extern const uint DATA_SIZE;
+extern const char *DATA_STREAM;
+
+class Group : public Device::Group<Data>
+{
+public:
+  virtual QString name() const { return "mem24"; }
+  virtual QString label() const { return i18n("Serial Memory 24"); }
+  virtual Device::Memory *createMemory(const Device::Data &data) const;
+  virtual QString informationHtml(const Device::Data &data) const;
+#if !defined(NO_KDE)
+  virtual QPixmap memoryGraph(const Device::Data &data) const;
+#endif
+
+private:
+  virtual uint dataSize() const { return DATA_SIZE; }
+  virtual const char *dataStream() const { return DATA_STREAM; }
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/mem24/mem24/mem24_memory.cpp b/src/devices/mem24/mem24/mem24_memory.cpp
new file mode 100644
index 0000000..a4296ea
--- /dev/null
+++ b/src/devices/mem24/mem24/mem24_memory.cpp
@@ -0,0 +1,92 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "mem24_memory.h"
+
+#include <qfile.h>
+
+#include "common/global/global.h"
+#include "common/common/misc.h"
+
+Mem24::Memory::Memory(const Data &data)
+  : Device::Memory(data)
+{
+  fill(BitValue());
+}
+
+void Mem24::Memory::fill(BitValue value)
+{
+  _data = Device::Array(device().nbBytes());
+  for (uint i=0; i<_data.count(); i++) _data[i] = value;
+}
+
+void Mem24::Memory::copyFrom(const Device::Memory &memory)
+{
+  Q_ASSERT( device().name()==memory.device().name() );
+  _data = static_cast<const Memory &>(memory)._data;
+}
+
+Device::Array Mem24::Memory::arrayForWriting() const
+{
+  Device::Array data(_data.count());
+  for (uint i=0; i<data.count(); i++) data[i] = _data[i].maskWith(0xFF);
+  return data;
+}
+
+BitValue Mem24::Memory::byte(uint offset) const
+{
+  Q_ASSERT( _data.size()>offset );
+  return _data[offset];
+}
+
+void Mem24::Memory::setByte(uint offset, BitValue value)
+{
+  Q_ASSERT( _data.size()>offset );
+  Q_ASSERT( value<=0xFF );
+  _data[offset] = value;
+}
+
+BitValue Mem24::Memory::checksum() const
+{
+  BitValue cs = 0x0000;
+  for (uint i=0; i<_data.count(); i++) cs += _data[i];
+  return cs.maskWith(0xFFFF);
+}
+
+//-----------------------------------------------------------------------------
+void Mem24::Memory::savePartial(QTextStream &stream, HexBuffer::Format format) const
+{
+  HexBuffer hb = toHexBuffer();
+  hb.savePartial(stream, format);
+}
+
+//-----------------------------------------------------------------------------
+HexBuffer Mem24::Memory::toHexBuffer() const
+{
+  HexBuffer hb;
+  for (uint k=0; k<device().nbBytes(); k++) hb.insert(k, _data[k]);
+  return hb;
+}
+
+void Mem24::Memory::fromHexBuffer(const HexBuffer &hb, WarningTypes &result,
+                                      QStringList &warnings, QMap<uint, bool> &inRange)
+{
+  BitValue mask = 0xFF;
+  for (uint k=0; k<device().nbBytes(); k++) {
+    _data[k] = hb[k];
+    if ( _data[k].isInitialized() ) {
+      inRange[k] = true;
+      if ( !(result & ValueTooLarge) && !_data[k].isInside(mask) ) {
+        result |= ValueTooLarge;
+        warnings += i18n("At least one word (at offset %1) is larger (%2) than the corresponding mask (%3).")
+                    .arg(toHexLabel(k, 8)).arg(toHexLabel(_data[k], 8)).arg(toHexLabel(mask, 8));
+      }
+      _data[k] = _data[k].maskWith(mask);
+    }
+  }
+}
diff --git a/src/devices/mem24/mem24/mem24_memory.h b/src/devices/mem24/mem24/mem24_memory.h
new file mode 100644
index 0000000..fbd6c64
--- /dev/null
+++ b/src/devices/mem24/mem24/mem24_memory.h
@@ -0,0 +1,45 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef MEM24_MEMORY_H
+#define MEM24_MEMORY_H
+
+#include "common/global/global.h"
+#include "devices/base/generic_memory.h"
+#include "devices/base/hex_buffer.h"
+#include "devices/mem24/base/mem24.h"
+
+namespace Mem24
+{
+
+class Memory : public Device::Memory
+{
+public:
+  Memory(const Data &data);
+  const Data &device() const { return static_cast<const Data &>(_device); }
+  virtual void fill(BitValue value);
+  virtual void checksumCheckFill() { clear(); }
+  Device::Array arrayForWriting() const;
+  BitValue byte(uint offset) const;
+  void setByte(uint offset, BitValue value);
+  virtual BitValue checksum() const;
+
+  virtual HexBuffer toHexBuffer() const;
+  virtual void copyFrom(const Device::Memory &memory);
+
+private:
+  Device::Array _data;
+
+  virtual void savePartial(QTextStream &stream, HexBuffer::Format format) const;
+  virtual void fromHexBuffer(const HexBuffer &hb, WarningTypes &warningTypes,
+                             QStringList &warnings, QMap<uint, bool> &inRange);
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/mem24/prog/Makefile.am b/src/devices/mem24/prog/Makefile.am
new file mode 100644
index 0000000..1c1a55e
--- /dev/null
+++ b/src/devices/mem24/prog/Makefile.am
@@ -0,0 +1,5 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+noinst_LTLIBRARIES = libmem24prog.la
+libmem24prog_la_SOURCES = mem24_prog.cpp
diff --git a/src/devices/mem24/prog/mem24_prog.cpp b/src/devices/mem24/prog/mem24_prog.cpp
new file mode 100644
index 0000000..4c4b201
--- /dev/null
+++ b/src/devices/mem24/prog/mem24_prog.cpp
@@ -0,0 +1,88 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "mem24_prog.h"
+
+#include "common/global/global.h"
+#include "devices/list/device_list.h"
+#include "progs/base/prog_config.h"
+
+//-----------------------------------------------------------------------------
+bool Programmer::Mem24DeviceSpecific::read(Device::Array &data, const VerifyData *vdata)
+{
+  setPowerOn();
+  doRead(data, vdata);
+  setPowerOff();
+  return !hasError();
+}
+
+bool Programmer::Mem24DeviceSpecific::write(const Device::Array &data)
+{
+  setPowerOn();
+  doWrite(data);
+  setPowerOff();
+  return !hasError();
+}
+
+bool Programmer::Mem24DeviceSpecific::verifyByte(uint index, BitValue d, const VerifyData &vdata)
+{
+  BitValue v = static_cast<const Mem24::Memory &>(vdata.memory).byte(index);
+  v = v.maskWith(0xFF);
+  d = d.maskWith(0xFF);
+  if ( v==d ) return true;
+  Address address = index;
+  if ( vdata.actions & BlankCheckVerify )
+    log(Log::LineType::Error, i18n("Device memory is not blank (at address %1: reading %2 and expecting %3).")
+                    .arg(toHexLabel(address, device().nbCharsAddress())).arg(toHexLabel(d, 2)).arg(toHexLabel(v, 2)));
+  else log(Log::LineType::Error, i18n("Device memory doesn't match hex file (at address %1: reading %2 and expecting %3).")
+                       .arg(toHexLabel(address, device().nbCharsAddress())).arg(toHexLabel(d, 2)).arg(toHexLabel(v, 2)));
+  return false;
+}
+
+//----------------------------------------------------------------------------
+uint Programmer::Mem24Base::nbSteps(Task task, const Device::MemoryRange *) const
+{
+  uint nb = device()->nbBytes();
+  if ( task==Task::Write && readConfigEntry(Config::VerifyAfterProgram).toBool() ) nb += device()->nbBytes();
+  return nb;
+}
+
+bool Programmer::Mem24Base::internalErase(const Device::MemoryRange &)
+{
+  initProgramming();
+  Mem24::Memory memory(*device());
+  return specific()->write(memory.arrayForWriting());
+}
+
+bool Programmer::Mem24Base::internalRead(Device::Memory *memory, const Device::MemoryRange &, const VerifyData *vdata)
+{
+  initProgramming();
+  Device::Array data;
+  if ( !specific()->read(data, vdata) ) return false;
+  if (memory) for (uint i=0; i<data.count(); i++) static_cast<Mem24::Memory *>(memory)->setByte(i, data[i]);
+  return true;
+}
+
+bool Programmer::Mem24Base::internalProgram(const Device::Memory &memory, const Device::MemoryRange &)
+{
+  initProgramming();
+  const Mem24::Memory &pmemory = static_cast<const Mem24::Memory &>(memory);
+  const Device::Array &data = pmemory.arrayForWriting();
+  if ( !specific()->write(data) ) return false;
+  if ( !readConfigEntry(Config::VerifyAfterProgram).toBool() ) return true;
+  VerifyActions actions = IgnoreProtectedVerify;
+  if ( readConfigEntry(Config::OnlyVerifyProgrammed).toBool() ) actions |= OnlyProgrammedVerify;
+  VerifyData vdata(actions, pmemory);
+  Device::Array adata;
+  return specific()->read(adata, &vdata);
+}
+
+bool Programmer::Mem24Base::verifyDeviceId()
+{
+  return specific()->verifyPresence();
+}
diff --git a/src/devices/mem24/prog/mem24_prog.h b/src/devices/mem24/prog/mem24_prog.h
new file mode 100644
index 0000000..86948c2
--- /dev/null
+++ b/src/devices/mem24/prog/mem24_prog.h
@@ -0,0 +1,63 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef MEM24_PROG_H
+#define MEM24_PROG_H
+
+#include "progs/base/generic_prog.h"
+#include "devices/mem24/mem24/mem24_memory.h"
+
+namespace Programmer
+{
+//-----------------------------------------------------------------------------
+class Mem24DeviceSpecific : public DeviceSpecific
+{
+public:
+  Mem24DeviceSpecific(::Programmer::Base &base) : DeviceSpecific(base) {}
+  const Mem24::Data &device() const { return static_cast<const Mem24::Data &>(*_base.device()); }
+  bool read(Device::Array &data, const VerifyData *vdata);
+  bool write(const Device::Array &data);
+  bool verifyByte(uint index, BitValue d, const VerifyData &vdata);
+  virtual bool verifyPresence() = 0;
+
+protected:
+  virtual bool doRead(Device::Array &data, const VerifyData *vdata) = 0;
+  virtual bool doWrite(const Device::Array &data) = 0;
+};
+
+//-----------------------------------------------------------------------------
+class Mem24Hardware : public Hardware
+{
+public:
+  Mem24Hardware(::Programmer::Base &base, Port::Base *port, const QString &name) : Hardware(base, port, name) {}
+  const Mem24::Data &device() const { return static_cast<const Mem24::Data &>(*_base.device()); }
+};
+
+//-----------------------------------------------------------------------------
+class Mem24Base : public Base
+{
+public:
+  Mem24Base(const Group &group, const Mem24::Data *data, const char *name) : Base(group, data, name) {}
+  const Mem24::Data *device() const { return static_cast<const Mem24::Data *>(_device); }
+
+protected:
+  Mem24DeviceSpecific *specific() const { return static_cast<Mem24DeviceSpecific *>(_specific); }
+  virtual bool verifyDeviceId();
+  virtual uint nbSteps(Task task, const Device::MemoryRange *range) const;
+  virtual bool initProgramming() { return true; }
+  virtual bool checkErase() { return true; }
+  virtual bool internalErase(const Device::MemoryRange &range);
+  virtual bool checkRead() { return true; }
+  virtual bool internalRead(Device::Memory *memory, const Device::MemoryRange &range, const VerifyData *vdata);
+  virtual bool checkProgram(const Device::Memory &) { return true; }
+  virtual bool internalProgram(const Device::Memory &memory, const Device::MemoryRange &range);
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/mem24/prog/prog.pro b/src/devices/mem24/prog/prog.pro
new file mode 100644
index 0000000..2acd347
--- /dev/null
+++ b/src/devices/mem24/prog/prog.pro
@@ -0,0 +1,6 @@
+STOPDIR = ../../../..
+include($${STOPDIR}/lib.pro)
+
+TARGET   = mem24prog
+HEADERS += mem24_prog.h
+SOURCES += mem24_prog.cpp
diff --git a/src/devices/mem24/xml/Makefile.am b/src/devices/mem24/xml/Makefile.am
new file mode 100644
index 0000000..88a4305
--- /dev/null
+++ b/src/devices/mem24/xml/Makefile.am
@@ -0,0 +1,12 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+noinst_PROGRAMS = mem24_xml_to_data
+
+mem24_xml_to_data_SOURCES = mem24_xml_to_data.cpp
+mem24_xml_to_data_DEPENDENCIES = $(top_builddir)/src/devices/mem24/base/libmem24base.la \
+	$(top_builddir)/src/xml_to_data/libxmltodata.la $(top_builddir)/src/devices/base/libdevicebase.la \
+	$(top_builddir)/src/common/common/libcommon.la
+mem24_xml_to_data_LDADD = $(top_builddir)/src/devices/mem24/base/libmem24base.la \
+	$(top_builddir)/src/xml_to_data/libxmltodata.la $(top_builddir)/src/devices/base/libdevicebase.la \
+	$(top_builddir)/src/common/common/libcommon.la $(LIB_KDECORE)
diff --git a/src/devices/mem24/xml/mem24_xml_to_data.cpp b/src/devices/mem24/xml/mem24_xml_to_data.cpp
new file mode 100644
index 0000000..734ebca
--- /dev/null
+++ b/src/devices/mem24/xml/mem24_xml_to_data.cpp
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *   Copyright (C) 2006-2007 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include <qfile.h>
+#include <qtextstream.h>
+
+#include "xml_to_data/device_xml_to_data.h"
+#include "common/common/misc.h"
+#include "devices/mem24/base/mem24.h"
+
+namespace Mem24
+{
+
+class XmlToData : public Device::XmlToData<Data>
+{
+private:
+  virtual uint nbOutputFiles(uint) const { return 1; }
+  virtual bool isIncluded(uint, uint) const { return true; }
+  virtual QString namespaceName() const { return "Mem24"; }
+
+virtual void processDevice(QDomElement device)
+{
+  Device::XmlToDataBase::processDevice(device);
+
+  QDomElement e = findUniqueElement(device, "memory", "name", QString::null);
+  bool ok;
+  data()->_nbBytes = fromHexLabel(e.attribute("size"), &ok);
+  if ( !ok ) qFatal("Missing or invalid size");
+  data()->_nbBlocks = e.attribute("nb_blocks").toUInt(&ok);
+  if ( !ok || data()->_nbBlocks==0 ) qFatal("Missing, zero, or invalid nb_blocks");
+  if ( (data()->_nbBytes % data()->_nbBlocks)!=0 ) qFatal("nb_blocks should divide size");
+  if ( data()->_nbBlocks>8 ) qFatal("nb_blocks is too large (>8)");
+  data()->_nbBytesPage = e.attribute("page_size").toUInt(&ok);
+  if ( !ok || data()->_nbBytesPage==0 ) qFatal("Missing, zero, or invalid page_size");
+  if ( ((data()->_nbBytes/data()->_nbBlocks) % data()->_nbBytesPage)!=0 ) qFatal("page_size should divide size/nb_blocks");
+  QStringList names;
+  names.append(QString::null);
+  checkTagNames(device, "memory", names);
+}
+
+virtual void checkPins(const QMap<QString, uint> &pinLabels) const
+{
+  if ( !pinLabels.contains("VCC") ) qFatal("No VDD pin specified");
+  if ( !pinLabels.contains("VSS") ) qFatal("No VSS pin specified");
+  QMap<QString, uint>::const_iterator it;
+  for (it=pinLabels.begin(); it!=pinLabels.end(); ++it)
+    if ( it.data()!=1 ) qFatal(QString("Duplicated pin %1").arg(it.key()));
+}
+
+}; // class
+
+} // namespace
+
+//-----------------------------------------------------------------------------
+XML_MAIN(Mem24::XmlToData)
diff --git a/src/devices/mem24/xml/xml.pro b/src/devices/mem24/xml/xml.pro
new file mode 100644
index 0000000..9730b29
--- /dev/null
+++ b/src/devices/mem24/xml/xml.pro
@@ -0,0 +1,13 @@
+STOPDIR = ../../../..
+include($${STOPDIR}/app.pro)
+
+TARGET   = mem24_xml_to_data
+SOURCES += mem24_xml_to_data.cpp
+LIBS    += ../../../devices/mem24/base/libmem24base.a ../../../xml_to_data/libxmltodata.a \
+           ../../../devices/base/libdevicebase.a ../../../common/global/libglobal.a \
+           ../../../common/nokde/libnokde.a ../../../common/common/libcommon.a
+
+unix:QMAKE_POST_LINK = cd ../xml_data && ../xml/mem24_xml_to_data
+unix:QMAKE_CLEAN += ../xml_data/mem24_data.cpp
+win32:QMAKE_POST_LINK = cd ..\xml_data && ..\xml\mem24_xml_to_data.exe
+win32:QMAKE_CLEAN += ..\xml_data\mem24_data.cpp
diff --git a/src/devices/mem24/xml_data/24AA00.xml b/src/devices/mem24/xml_data/24AA00.xml
new file mode 100644
index 0000000..6b9e114
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA00.xml
@@ -0,0 +1,41 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA00" document="010770" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x10" nb_blocks="1" page_size="1" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop dfns" nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="N/C" />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="N/C" />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="sot23"                nb_pins="5" >
+    <pin index="1" name="SCL" />
+    <pin index="2" name="VSS" />
+    <pin index="3" name="SDA" />
+    <pin index="4" name="N/C" />
+    <pin index="5" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA01.xml b/src/devices/mem24/xml_data/24AA01.xml
new file mode 100644
index 0000000..f3aa59d
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA01.xml
@@ -0,0 +1,41 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA01" document="010771" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x80" nb_blocks="1" page_size="8" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="N/C" />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="sot23"                     nb_pins="5" >
+    <pin index="1" name="SCL" />
+    <pin index="2" name="VSS" />
+    <pin index="3" name="SDA" />
+    <pin index="4" name="VCC" />
+    <pin index="5" name="WP"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA014.xml b/src/devices/mem24/xml_data/24AA014.xml
new file mode 100644
index 0000000..91b93ca
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA014.xml
@@ -0,0 +1,33 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA014" document="010772" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x80" nb_blocks="1" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA02.xml b/src/devices/mem24/xml_data/24AA02.xml
new file mode 100644
index 0000000..a4c3174
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA02.xml
@@ -0,0 +1,41 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA02" document="010774" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x100" nb_blocks="1" page_size="8" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="N/C" />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="sot23"                     nb_pins="5" >
+    <pin index="1" name="SCL" />
+    <pin index="2" name="VSS" />
+    <pin index="3" name="SDA" />
+    <pin index="4" name="VCC" />
+    <pin index="5" name="WP"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA024.xml b/src/devices/mem24/xml_data/24AA024.xml
new file mode 100644
index 0000000..7d2bfe5
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA024.xml
@@ -0,0 +1,33 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA024" document="010775" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x100" nb_blocks="1" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA025.xml b/src/devices/mem24/xml_data/24AA025.xml
new file mode 100644
index 0000000..174c163
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA025.xml
@@ -0,0 +1,33 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA025" document="020310" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x100" nb_blocks="1" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="N/C" />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA04.xml b/src/devices/mem24/xml_data/24AA04.xml
new file mode 100644
index 0000000..18ca2ac
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA04.xml
@@ -0,0 +1,41 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA04" document="010777" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x200" nb_blocks="2" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="N/C" />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="sot23"                     nb_pins="5" >
+    <pin index="1" name="SCL" />
+    <pin index="2" name="VSS" />
+    <pin index="3" name="SDA" />
+    <pin index="4" name="VCC" />
+    <pin index="5" name="WP"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA08.xml b/src/devices/mem24/xml_data/24AA08.xml
new file mode 100644
index 0000000..84852f2
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA08.xml
@@ -0,0 +1,41 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA08" document="010779" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x400" nb_blocks="4" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="N/C" />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="sot23"                     nb_pins="5" >
+    <pin index="1" name="SCL" />
+    <pin index="2" name="VSS" />
+    <pin index="3" name="SDA" />
+    <pin index="4" name="VCC" />
+    <pin index="5" name="WP"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA1025.xml b/src/devices/mem24/xml_data/24AA1025.xml
new file mode 100644
index 0000000..54940f3
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA1025.xml
@@ -0,0 +1,33 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA1025" document="024638" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x20000" nb_blocks="2" page_size="128" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="N/C" />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA128.xml b/src/devices/mem24/xml_data/24AA128.xml
new file mode 100644
index 0000000..bf113e8
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA128.xml
@@ -0,0 +1,44 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA128" document="010781" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x4000" nb_blocks="1" page_size="64" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="msop"                 nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA16.xml b/src/devices/mem24/xml_data/24AA16.xml
new file mode 100644
index 0000000..fb471b5
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA16.xml
@@ -0,0 +1,41 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA16" document="010783" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x800" nb_blocks="8" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="N/C" />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="sot23"                     nb_pins="5" >
+    <pin index="1" name="SCL" />
+    <pin index="2" name="VSS" />
+    <pin index="3" name="SDA" />
+    <pin index="4" name="VCC" />
+    <pin index="5" name="WP"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA164.xml b/src/devices/mem24/xml_data/24AA164.xml
new file mode 100644
index 0000000..76ac031
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA164.xml
@@ -0,0 +1,33 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA164" document="010349" status="EOL" alternatives="24AA16" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="6"   />
+    <frequency start="0.1" end="0.4" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x800" nb_blocks="8" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA256.xml b/src/devices/mem24/xml_data/24AA256.xml
new file mode 100644
index 0000000..899389d
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA256.xml
@@ -0,0 +1,44 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA256" document="010785" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x8000" nb_blocks="1" page_size="64" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="msop"                 nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA32A.xml b/src/devices/mem24/xml_data/24AA32A.xml
new file mode 100644
index 0000000..bc8d0f4
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA32A.xml
@@ -0,0 +1,33 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA32A" document="010787" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x1000" nb_blocks="1" page_size="32" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA512.xml b/src/devices/mem24/xml_data/24AA512.xml
new file mode 100644
index 0000000..baa575e
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA512.xml
@@ -0,0 +1,50 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA512" document="010789" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x10000" nb_blocks="1" page_size="128" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic dfns" nb_pins="8"  >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="tssop"          nb_pins="14" >
+    <pin index="1"  name="A0"  />
+    <pin index="2"  name="A1"  />
+    <pin index="3"  name="N/C" />
+    <pin index="4"  name="N/C" />
+    <pin index="5"  name="N/C" />
+    <pin index="6"  name="A2"  />
+    <pin index="7"  name="VSS" />
+    <pin index="8"  name="SDA" />
+    <pin index="9"  name="SCL" />
+    <pin index="10" name="N/C" />
+    <pin index="11" name="N/C" />
+    <pin index="12" name="N/C" />
+    <pin index="13" name="WP"  />
+    <pin index="14" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA515.xml b/src/devices/mem24/xml_data/24AA515.xml
new file mode 100644
index 0000000..b80a53a
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA515.xml
@@ -0,0 +1,33 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA515" document="010791" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x10000" nb_blocks="1" page_size="64" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA64.xml b/src/devices/mem24/xml_data/24AA64.xml
new file mode 100644
index 0000000..0d52b6b
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA64.xml
@@ -0,0 +1,33 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA64" document="010793" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x2000" nb_blocks="1" page_size="32" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24AA65.xml b/src/devices/mem24/xml_data/24AA65.xml
new file mode 100644
index 0000000..b35b50b
--- /dev/null
+++ b/src/devices/mem24/xml_data/24AA65.xml
@@ -0,0 +1,33 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24AA65" document="010795" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"   end="0.1" vdd_min="1.8" vdd_max="6" />
+    <frequency start="0.1" end="0.4" vdd_min="4.5" vdd_max="6" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x2000" nb_blocks="1" page_size="64" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="N/C" />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24C00.xml b/src/devices/mem24/xml_data/24C00.xml
new file mode 100644
index 0000000..13bc0f7
--- /dev/null
+++ b/src/devices/mem24/xml_data/24C00.xml
@@ -0,0 +1,43 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24C00" document="010796" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="0.4" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="0.1" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x10" nb_blocks="1" page_size="1" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop dfns" nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="N/C" />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="N/C" />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="sot23"                nb_pins="5" >
+    <pin index="1" name="SCL" />
+    <pin index="2" name="VSS" />
+    <pin index="3" name="SDA" />
+    <pin index="4" name="N/C" />
+    <pin index="5" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24C01C.xml b/src/devices/mem24/xml_data/24C01C.xml
new file mode 100644
index 0000000..3526522
--- /dev/null
+++ b/src/devices/mem24/xml_data/24C01C.xml
@@ -0,0 +1,35 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24C01C" document="010797" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="0.4" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="0.1" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x80" nb_blocks="1" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="A0"   />
+    <pin index="2" name="A1"   />
+    <pin index="3" name="A2"   />
+    <pin index="4" name="VSS"  />
+    <pin index="5" name="SDA"  />
+    <pin index="6" name="SCL"  />
+    <pin index="7" name="TEST" />
+    <pin index="8" name="VCC"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24C02C.xml b/src/devices/mem24/xml_data/24C02C.xml
new file mode 100644
index 0000000..f4ce091
--- /dev/null
+++ b/src/devices/mem24/xml_data/24C02C.xml
@@ -0,0 +1,35 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24C02C" document="010798" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="0.4" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="0.1" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x100" nb_blocks="1" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24C65.xml b/src/devices/mem24/xml_data/24C65.xml
new file mode 100644
index 0000000..6f9be98
--- /dev/null
+++ b/src/devices/mem24/xml_data/24C65.xml
@@ -0,0 +1,32 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24C65" document="010799" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="0.4" vdd_min="4.5" vdd_max="6" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x2000" nb_blocks="1" page_size="64" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="N/C" />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24FC1025.xml b/src/devices/mem24/xml_data/24FC1025.xml
new file mode 100644
index 0000000..c783952
--- /dev/null
+++ b/src/devices/mem24/xml_data/24FC1025.xml
@@ -0,0 +1,32 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FC1025" document="024639" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="1" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x20000" nb_blocks="2" page_size="128" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="N/C" />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24FC128.xml b/src/devices/mem24/xml_data/24FC128.xml
new file mode 100644
index 0000000..88b0c8e
--- /dev/null
+++ b/src/devices/mem24/xml_data/24FC128.xml
@@ -0,0 +1,44 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FC128" document="010800" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.4" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.4" end="1"   vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x4000" nb_blocks="1" page_size="64" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="msop"                 nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24FC256.xml b/src/devices/mem24/xml_data/24FC256.xml
new file mode 100644
index 0000000..08595ed
--- /dev/null
+++ b/src/devices/mem24/xml_data/24FC256.xml
@@ -0,0 +1,44 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FC256" document="010801" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.4" vdd_min="1.8" vdd_max="5.5" />
+    <frequency start="0.4" end="1"   vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x8000" nb_blocks="1" page_size="64" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="msop"                 nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24FC512.xml b/src/devices/mem24/xml_data/24FC512.xml
new file mode 100644
index 0000000..0811a8d
--- /dev/null
+++ b/src/devices/mem24/xml_data/24FC512.xml
@@ -0,0 +1,49 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FC512" document="010802" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="1" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x10000" nb_blocks="1" page_size="128" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic dfns" nb_pins="8"  >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="tssop"          nb_pins="14" >
+    <pin index="1"  name="A0"  />
+    <pin index="2"  name="A1"  />
+    <pin index="3"  name="N/C" />
+    <pin index="4"  name="N/C" />
+    <pin index="5"  name="N/C" />
+    <pin index="6"  name="A2"  />
+    <pin index="7"  name="VSS" />
+    <pin index="8"  name="SDA" />
+    <pin index="9"  name="SCL" />
+    <pin index="10" name="N/C" />
+    <pin index="11" name="N/C" />
+    <pin index="12" name="N/C" />
+    <pin index="13" name="WP"  />
+    <pin index="14" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24FC515.xml b/src/devices/mem24/xml_data/24FC515.xml
new file mode 100644
index 0000000..9469c8c
--- /dev/null
+++ b/src/devices/mem24/xml_data/24FC515.xml
@@ -0,0 +1,32 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FC515" document="010803" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="1" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x10000" nb_blocks="1" page_size="64" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC00.xml b/src/devices/mem24/xml_data/24LC00.xml
new file mode 100644
index 0000000..b6b588e
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC00.xml
@@ -0,0 +1,41 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC00" document="010804" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x10" nb_blocks="1" page_size="1" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop dfns" nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="N/C" />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="N/C" />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="sot23"                nb_pins="5" >
+    <pin index="1" name="SCL" />
+    <pin index="2" name="VSS" />
+    <pin index="3" name="SDA" />
+    <pin index="4" name="N/C" />
+    <pin index="5" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC014.xml b/src/devices/mem24/xml_data/24LC014.xml
new file mode 100644
index 0000000..f3dd3e7
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC014.xml
@@ -0,0 +1,32 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC014" document="010805" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x80" nb_blocks="1" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC01B.xml b/src/devices/mem24/xml_data/24LC01B.xml
new file mode 100644
index 0000000..f96bc6d
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC01B.xml
@@ -0,0 +1,40 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC01B" document="010806" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x80" nb_blocks="1" page_size="8" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="N/C" />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="sot23"                     nb_pins="5" >
+    <pin index="1" name="SCL" />
+    <pin index="2" name="VSS" />
+    <pin index="3" name="SDA" />
+    <pin index="4" name="VCC" />
+    <pin index="5" name="WP"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC024.xml b/src/devices/mem24/xml_data/24LC024.xml
new file mode 100644
index 0000000..7fa84bf
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC024.xml
@@ -0,0 +1,32 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC024" document="010808" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x100" nb_blocks="1" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC025.xml b/src/devices/mem24/xml_data/24LC025.xml
new file mode 100644
index 0000000..8f5df38
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC025.xml
@@ -0,0 +1,32 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC025" document="010809" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x100" nb_blocks="1" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="N/C" />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC02B.xml b/src/devices/mem24/xml_data/24LC02B.xml
new file mode 100644
index 0000000..3e34cde
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC02B.xml
@@ -0,0 +1,40 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC02B" document="010810" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x100" nb_blocks="1" page_size="8" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="N/C" />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="sot23"                     nb_pins="5" >
+    <pin index="1" name="SCL" />
+    <pin index="2" name="VSS" />
+    <pin index="3" name="SDA" />
+    <pin index="4" name="VCC" />
+    <pin index="5" name="WP"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC04B.xml b/src/devices/mem24/xml_data/24LC04B.xml
new file mode 100644
index 0000000..0f83be9
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC04B.xml
@@ -0,0 +1,40 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC04B" document="010812" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x200" nb_blocks="2" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="N/C" />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="sot23"                     nb_pins="5" >
+    <pin index="1" name="SCL" />
+    <pin index="2" name="VSS" />
+    <pin index="3" name="SDA" />
+    <pin index="4" name="VCC" />
+    <pin index="5" name="WP"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC08B.xml b/src/devices/mem24/xml_data/24LC08B.xml
new file mode 100644
index 0000000..a617e0c
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC08B.xml
@@ -0,0 +1,40 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC08B" document="010814" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x400" nb_blocks="4" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="N/C" />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="sot23"                     nb_pins="5" >
+    <pin index="1" name="SCL" />
+    <pin index="2" name="VSS" />
+    <pin index="3" name="SDA" />
+    <pin index="4" name="VCC" />
+    <pin index="5" name="WP"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC1025.xml b/src/devices/mem24/xml_data/24LC1025.xml
new file mode 100644
index 0000000..79ba144
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC1025.xml
@@ -0,0 +1,32 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC1025" document="024636" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x20000" nb_blocks="2" page_size="128" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="N/C" />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC128.xml b/src/devices/mem24/xml_data/24LC128.xml
new file mode 100644
index 0000000..b850eac
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC128.xml
@@ -0,0 +1,43 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC128" document="010817" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x4000" nb_blocks="1" page_size="64" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="msop"                 nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC16B.xml b/src/devices/mem24/xml_data/24LC16B.xml
new file mode 100644
index 0000000..f07bd5e
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC16B.xml
@@ -0,0 +1,40 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC16B" document="010819" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x800" nb_blocks="8" page_size="16" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="N/C" />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="sot23"                     nb_pins="5" >
+    <pin index="1" name="SCL" />
+    <pin index="2" name="VSS" />
+    <pin index="3" name="SDA" />
+    <pin index="4" name="VCC" />
+    <pin index="5" name="WP"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC21A.xml b/src/devices/mem24/xml_data/24LC21A.xml
new file mode 100644
index 0000000..010b3a2
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC21A.xml
@@ -0,0 +1,33 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC21A" document="010821" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x80" nb_blocks="1" page_size="8" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="N/C"  />
+    <pin index="2" name="N/C"  />
+    <pin index="3" name="N/C"  />
+    <pin index="4" name="VSS"  />
+    <pin index="5" name="SDA"  />
+    <pin index="6" name="SCL"  />
+    <pin index="7" name="VCLK" />
+    <pin index="8" name="VCC"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC22A.xml b/src/devices/mem24/xml_data/24LC22A.xml
new file mode 100644
index 0000000..237b47e
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC22A.xml
@@ -0,0 +1,33 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC22A" document="010822" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x100" nb_blocks="1" page_size="8" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="N/C"  />
+    <pin index="2" name="N/C"  />
+    <pin index="3" name="N/C"  />
+    <pin index="4" name="VSS"  />
+    <pin index="5" name="SDA"  />
+    <pin index="6" name="SCL"  />
+    <pin index="7" name="VCLK" />
+    <pin index="8" name="VCC"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC256.xml b/src/devices/mem24/xml_data/24LC256.xml
new file mode 100644
index 0000000..5a49ee9
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC256.xml
@@ -0,0 +1,43 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC256" document="010823" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x8000" nb_blocks="1" page_size="64" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="msop"                 nb_pins="8" >
+    <pin index="1" name="N/C" />
+    <pin index="2" name="N/C" />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC32A.xml b/src/devices/mem24/xml_data/24LC32A.xml
new file mode 100644
index 0000000..abd17f2
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC32A.xml
@@ -0,0 +1,32 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC32A" document="010825" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x1000" nb_blocks="1" page_size="32" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC512.xml b/src/devices/mem24/xml_data/24LC512.xml
new file mode 100644
index 0000000..f643c99
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC512.xml
@@ -0,0 +1,49 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC512" document="010828" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x10000" nb_blocks="1" page_size="128" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic dfns" nb_pins="8"  >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+  <package types="tssop"          nb_pins="14" >
+    <pin index="1"  name="A0"  />
+    <pin index="2"  name="A1"  />
+    <pin index="3"  name="N/C" />
+    <pin index="4"  name="N/C" />
+    <pin index="5"  name="N/C" />
+    <pin index="6"  name="A2"  />
+    <pin index="7"  name="VSS" />
+    <pin index="8"  name="SDA" />
+    <pin index="9"  name="SCL" />
+    <pin index="10" name="N/C" />
+    <pin index="11" name="N/C" />
+    <pin index="12" name="N/C" />
+    <pin index="13" name="WP"  />
+    <pin index="14" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC515.xml b/src/devices/mem24/xml_data/24LC515.xml
new file mode 100644
index 0000000..55482b3
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC515.xml
@@ -0,0 +1,32 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC515" document="010830" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x10000" nb_blocks="1" page_size="64" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC64.xml b/src/devices/mem24/xml_data/24LC64.xml
new file mode 100644
index 0000000..d35cf1a
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC64.xml
@@ -0,0 +1,32 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC64" document="010831" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="0.4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x2000" nb_blocks="1" page_size="32" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop msop dfns" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="WP"  />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LC65.xml b/src/devices/mem24/xml_data/24LC65.xml
new file mode 100644
index 0000000..3fb3fbb
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LC65.xml
@@ -0,0 +1,33 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LC65" document="010833" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="2.5" vdd_max="6"   />
+    <frequency start="0.1" end="0.4" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x2000" nb_blocks="1" page_size="64" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="A0"  />
+    <pin index="2" name="A1"  />
+    <pin index="3" name="A2"  />
+    <pin index="4" name="VSS" />
+    <pin index="5" name="SDA" />
+    <pin index="6" name="SCL" />
+    <pin index="7" name="N/C" />
+    <pin index="8" name="VCC" />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/24LCS21A.xml b/src/devices/mem24/xml_data/24LCS21A.xml
new file mode 100644
index 0000000..0cb4846
--- /dev/null
+++ b/src/devices/mem24/xml_data/24LCS21A.xml
@@ -0,0 +1,33 @@
+<!DOCTYPE piklab_device>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24LCS21A" document="010834" status="IP" memory_technology="FLASH" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="0.1" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="0.1" end="0.4" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+<!--* Memory ***************************************************************-->
+  <memory size="0x80" nb_blocks="1" page_size="8" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="N/C"  />
+    <pin index="2" name="N/C"  />
+    <pin index="3" name="WP"   />
+    <pin index="4" name="VSS"  />
+    <pin index="5" name="SDA"  />
+    <pin index="6" name="SCL"  />
+    <pin index="7" name="VCLK" />
+    <pin index="8" name="VCC"  />
+  </package>
+
+</device>
diff --git a/src/devices/mem24/xml_data/Makefile.am b/src/devices/mem24/xml_data/Makefile.am
new file mode 100644
index 0000000..42cacaa
--- /dev/null
+++ b/src/devices/mem24/xml_data/Makefile.am
@@ -0,0 +1,12 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+noinst_LTLIBRARIES = libmem24xml.la
+libmem24xml_la_LDFLAGS = $(all_libraries)
+libmem24xml_la_SOURCES = mem24_data.cpp
+libmem24xml_la_DEPENDENCIES = mem24_data.cpp
+
+include deps.mak
+mem24_data.cpp: ../xml/mem24_xml_to_data $(noinst_DATA)
+	../xml/mem24_xml_to_data
+CLEANFILES = mem24_data.cpp
diff --git a/src/devices/mem24/xml_data/deps.mak b/src/devices/mem24/xml_data/deps.mak
new file mode 100644
index 0000000..5c1f243
--- /dev/null
+++ b/src/devices/mem24/xml_data/deps.mak
@@ -0,0 +1,6 @@
+noinst_DATA = \
+     24AA00.xml 24AA01.xml 24AA014.xml 24AA02.xml 24AA024.xml 24AA025.xml 24AA04.xml 24AA08.xml 24AA1025.xml 24AA128.xml\
+     24AA16.xml 24AA164.xml 24AA256.xml 24AA32A.xml 24AA512.xml 24AA515.xml 24AA64.xml 24AA65.xml 24C00.xml 24C01C.xml\
+     24C02C.xml 24C65.xml 24FC1025.xml 24FC128.xml 24FC256.xml 24FC512.xml 24FC515.xml 24LC00.xml 24LC014.xml 24LC01B.xml\
+     24LC024.xml 24LC025.xml 24LC02B.xml 24LC04B.xml 24LC08B.xml 24LC1025.xml 24LC128.xml 24LC16B.xml 24LC21A.xml 24LC22A.xml\
+     24LC256.xml 24LC32A.xml 24LC512.xml 24LC515.xml 24LC64.xml 24LC65.xml 24LCS21A.xml
diff --git a/src/devices/mem24/xml_data/xml_data.pro b/src/devices/mem24/xml_data/xml_data.pro
new file mode 100644
index 0000000..4842ae2
--- /dev/null
+++ b/src/devices/mem24/xml_data/xml_data.pro
@@ -0,0 +1,5 @@
+STOPDIR = ../../../..
+include($${STOPDIR}/lib.pro)
+
+TARGET   = mem24xml
+SOURCES += mem24_data.cpp
diff --git a/src/devices/pic/Makefile.am b/src/devices/pic/Makefile.am
new file mode 100644
index 0000000..13e5611
--- /dev/null
+++ b/src/devices/pic/Makefile.am
@@ -0,0 +1,3 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+SUBDIRS = base xml xml_data pic prog gui
diff --git a/src/devices/pic/base/Makefile.am b/src/devices/pic/base/Makefile.am
new file mode 100644
index 0000000..ebade1c
--- /dev/null
+++ b/src/devices/pic/base/Makefile.am
@@ -0,0 +1,6 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+noinst_LTLIBRARIES = libpicbase.la
+libpicbase_la_SOURCES = pic.cpp pic_config.cpp pic_protection.cpp \
+	pic_register.cpp
diff --git a/src/devices/pic/base/base.pro b/src/devices/pic/base/base.pro
new file mode 100644
index 0000000..621d6d3
--- /dev/null
+++ b/src/devices/pic/base/base.pro
@@ -0,0 +1,6 @@
+STOPDIR = ../../../..
+include($${STOPDIR}/lib.pro)
+
+TARGET   = picbase
+HEADERS += pic_protection.h pic_config.h pic_register.h pic.h
+SOURCES += pic_protection.cpp pic_config.cpp pic_register.cpp pic.cpp
diff --git a/src/devices/pic/base/pic.cpp b/src/devices/pic/base/pic.cpp
new file mode 100644
index 0000000..8f81540
--- /dev/null
+++ b/src/devices/pic/base/pic.cpp
@@ -0,0 +1,426 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic.h"
+
+#include "common/global/global.h"
+#include "common/common/misc.h"
+#include "common/global/purl.h"
+#include "pic_register.h"
+#include "pic_config.h"
+
+//------------------------------------------------------------------------------
+const Pic::ProgVoltageType::Data Pic::ProgVoltageType::DATA[Nb_Types] = {
+  { "vpp",            0 },
+  { "vdd_prog",       0 },
+  { "vdd_prog_write", 0 }
+};
+
+const Pic::MemoryRangeType::Data Pic::MemoryRangeType::DATA[Nb_Types] = {
+  { "code",               I18N_NOOP("Code memory"),         Writable },
+  { "calibration",        I18N_NOOP("Calibration"),         Writable },
+  { "user_ids",           I18N_NOOP("User IDs"),            Writable },
+  { "device_id",          I18N_NOOP("Device ID"),           ReadOnly },
+  { "config",             I18N_NOOP("Configuration Bits"),  Writable },
+  { "eeprom",             I18N_NOOP("Data EEPROM"),         Writable },
+  { "debug_vector",       I18N_NOOP("Debug Vector"),        Writable },
+  { "hardware_stack",     I18N_NOOP("Hardware Stack"),      ReadOnly },
+  { "calibration_backup", I18N_NOOP("Calibration Backup"),  Writable },
+  { "program_executive",  I18N_NOOP("Program Executive"),   Writable }
+};
+
+const Pic::SelfWrite::Data Pic::SelfWrite::DATA[Nb_Types] = {
+  { "yes", 0 },
+  { "no",  0 }
+};
+
+const Pic::DeviceType::Data Pic::DeviceType::DATA[Nb_Types] = {
+  { 0, I18N_NOOP("Normal") },
+  { 0, I18N_NOOP("J")      },
+  { 0, I18N_NOOP("K")      }
+};
+
+const Pic::Architecture::Data Pic::Architecture::DATA[Nb_Types] = {
+//  name family_label nbBytesPC nbBytesWord packed nbBitsRegister registerBankLength
+//  {Code, Cal, UserID, DevId, Conf, EEPROM, DebugVec, HardStack, CalBackup, Program Executive} randomAccess
+  { "10X", I18N_NOOP("Baseline Family"),  0, 2, false,  8, 0x020, { 12, 12, 12, 12, 12,  8, 12,  0, 12,  0 }, false, SelfWrite::No,       DeviceType::Normal }, // 9, 10, 11 or 12-bit program counter
+  { "16X", I18N_NOOP("Midrange Family"), 13, 2, false,  8, 0x080, { 14, 14, 14, 14, 14,  8, 14,  0, 14,  0 }, false, SelfWrite::Nb_Types, DeviceType::Normal }, // max eeprom: 256 words
+  { "17C", I18N_NOOP("17C Family"),      16, 2, false,  8, 0x100, { 16,  0,  0,  0, 16,  8,  0,  0,  0,  0 }, true,  SelfWrite::No,       DeviceType::Normal },
+  { "18C", I18N_NOOP("18C Family"),      21, 2, true,   8, 0x100, { 16,  8,  8,  8,  8,  8, 16,  0,  8,  0 }, true,  SelfWrite::No,       DeviceType::Normal },
+  { "18F", I18N_NOOP("18F Family"),      21, 2, true,   8, 0x100, { 16,  8,  8,  8,  8,  8, 16,  0,  8,  0 }, true,  SelfWrite::Nb_Types, DeviceType::Normal },
+  { "18J", I18N_NOOP("18J Family"),      21, 2, true,   8, 0x100, { 16,  8,  8,  8,  8,  8, 16,  0,  8,  0 }, true,  SelfWrite::Yes,      DeviceType::J      },
+  { "24F", I18N_NOOP("24F Family"),      23, 4, false, 16, 0x800, { 24,  0,  0, 16, 24,  0, 24,  0,  0, 24 }, true,  SelfWrite::Yes,      DeviceType::J      },
+  { "24H", I18N_NOOP("24H Family"),      23, 4, false, 16, 0x800, { 24,  0,  8, 16,  8,  0, 24,  0,  0, 24 }, true,  SelfWrite::Yes,      DeviceType::J      },
+  { "30F", I18N_NOOP("30F Family"),      23, 4, false, 16, 0xA00, { 24,  0, 24, 16, 16, 16, 24,  0,  0, 24 }, true,  SelfWrite::Yes,      DeviceType::Normal }, // dsPIC: eeprom max = 2 kwords = 4 kbytes
+  { "33F", I18N_NOOP("33F Family"),      23, 4, false, 16, 0x800, { 24,  0,  8, 16,  8,  0, 24,  0,  0, 24 }, true,  SelfWrite::Yes,      DeviceType::J      }
+};
+
+const Pic::Checksum::Algorithm::Data Pic::Checksum::Algorithm::DATA[Nb_Types] = {
+  { "",      0 },
+  { "XOR4",  0 },
+  { "XNOR7", 0 },
+  { "XNOR8", 0 }
+};
+
+const Pic::Feature::Data Pic::Feature::DATA[Nb_Types] = {
+  { "ccp", I18N_NOOP("CCP")      },
+  { "adc", I18N_NOOP("ADC")      },
+  { "ssp", I18N_NOOP("SSP")      },
+  { "lvd", I18N_NOOP("Low Voltage Detect") },
+  { "usb", I18N_NOOP("USB")      },
+  { "usart",           I18N_NOOP("USART")    },
+  { "can",             I18N_NOOP("CAN")      },
+  { "ecan",            I18N_NOOP("ECAN")     },
+  { "ethernet",        I18N_NOOP("Ethernet") },
+  { "lcd",             I18N_NOOP("LCD")      },
+  { "motor_control",   I18N_NOOP("Motor Control") },
+  { "motion_feedback", I18N_NOOP("Motion Feeback") },
+  { "self_write",      I18N_NOOP("Self-Write") }
+};
+
+//-----------------------------------------------------------------------------
+Pic::Data::Data()
+  : Device::Data(new RegistersData(*this))
+{
+  FOR_EACH(ProgVoltageType, type) {
+    _voltages[type].min = 0.0;
+    _voltages[type].max = 0.0;
+    _voltages[type].nominal = 0.0;
+  }
+  FOR_EACH(MemoryRangeType, type) {
+    _ranges[type].properties = NotPresent;
+    _ranges[type].start = 0;
+    _ranges[type].end = 0;
+    _ranges[type].hexFileOffset = 0;
+  }
+  _config = new Config(*this);
+  _calibration.opcode = 0;
+  _calibration.opcodeMask = 0;
+}
+
+Pic::Data::~Data()
+{
+  delete _config;
+}
+
+bool Pic::Data::isReadable(MemoryRangeType type) const
+{
+  return ( range(type).properties & Programmable );
+}
+
+bool Pic::Data::isWritable(MemoryRangeType type) const
+{
+  return ( (type.data().properties & Writable) && (range(type).properties & Programmable) );
+}
+
+uint Pic::Data::addressIncrement(MemoryRangeType type) const
+{
+  uint inc = _architecture.data().nbBytesWord;
+  if ( _architecture.data().packed
+       && ( type==MemoryRangeType::Code || type==MemoryRangeType::DebugVector ) ) return inc;
+  return inc / 2;
+}
+
+uint Pic::Data::nbWords(MemoryRangeType type) const
+{
+  if ( !isPresent(type) ) return 0;
+  return nbAddresses(type) / addressIncrement(type);
+}
+
+uint Pic::Data::nbAddresses(MemoryRangeType type) const
+{
+  if ( !isPresent(type) ) return 0;
+  return (range(type).end - range(type).start + 1);
+}
+
+QString Pic::Data::fname(Device::Special special) const
+{
+  QString s = name();
+  switch (special.type()) {
+    case Device::Special::Normal: break;
+    case Device::Special::LowPower:
+      // assume name is of form "NNX..."
+      s.insert(2, 'L');
+      break;
+    case Device::Special::LowVoltage:
+      // assume name is of form "NNXN..."
+      s.replace(2, 1, "LV");
+      break;
+    case Device::Special::HighVoltage:
+      // assume name is of form "NNXN..."
+      s.replace(2, 1, "HV");
+      break;
+    case Device::Special::Nb_Types: Q_ASSERT(false); break;
+  }
+  return s;
+}
+
+bool Pic::Data::matchId(BitValue rawId, Device::IdData &idata) const
+{
+  if ( !isPresent(MemoryRangeType::DeviceId) ) return false;
+  QMap<Device::Special, BitValue>::const_iterator it;
+  for (it=_ids.begin(); it!=_ids.end(); ++it) {
+    idata.special = it.key();
+    BitValue nid = 0x0;
+    switch (architecture().type()) {
+      case Architecture::P10X:
+      case Architecture::P16X:
+      case Architecture::P17C:
+      case Architecture::P18C:
+      case Architecture::P18F:
+      case Architecture::P18J:
+        nid = rawId.clearMaskBits(0x1F);
+        idata.revision = rawId.maskWith(0x1F);
+        break;
+      case Architecture::P24F:
+        nid = (rawId >> 16).maskWith(0x3FFF);
+        idata.revision = (rawId >> 6).maskWith(0x7);
+        idata.minorRevision = rawId.maskWith(0x7);
+        break;
+      case Architecture::P30F:
+        nid = (rawId >> 16).maskWith(0xFFFF);
+        idata.revision = (rawId >> 6).maskWith(0x3F);
+        idata.minorRevision = rawId.maskWith(0x3F);
+        idata.process = (rawId >> 12).maskWith(0xF);
+        break;
+      case Architecture::P24H:
+      case Architecture::P33F:
+        nid = (rawId >> 16).maskWith(0xFFFF);
+        idata.revision = rawId.maskWith(0xFFFF); // ??
+        break;
+      case Architecture::Nb_Types: Q_ASSERT(false); break;
+    }
+    if ( nid==it.data() ) return true;
+  }
+  return false;
+}
+
+QStringList Pic::Data::idNames(const QMap<QString, Device::IdData> &ids) const
+{
+  QStringList list;
+  QMap<QString, Device::IdData>::const_iterator it;
+  for (it=ids.begin(); it!=ids.end(); ++it) {
+    switch (_architecture.type()) {
+      case Architecture::P10X:
+      case Architecture::P16X:
+      case Architecture::P17C:
+      case Architecture::P18C:
+      case Architecture::P18F:
+      case Architecture::P18J:
+        list += i18n("%1 (rev. %2)").arg(it.key()).arg(toLabel(it.data().revision));
+        break;
+      case Architecture::P24F:
+        list += i18n("%1 (rev. %2.%3)").arg(it.key()).arg(toLabel(it.data().revision)).arg(toLabel(it.data().minorRevision));
+        break;
+      case Architecture::P30F:
+        list += i18n("%1 (proc. %2; rev. %3.%4)").arg(it.key()).arg(toLabel(it.data().process)).arg(toLabel(it.data().revision)).arg(toLabel(it.data().minorRevision));
+        break;
+      case Architecture::P24H:
+      case Architecture::P33F:
+        list += i18n("%1 (rev. %2)").arg(it.key()).arg(toLabel(it.data().revision));
+        break;
+      case Architecture::Nb_Types: Q_ASSERT(false); break;
+    }
+  }
+  return list;
+}
+
+bool Pic::Data::checkCalibration(const Device::Array &data, QString *message) const
+{
+  Q_ASSERT( nbWords(MemoryRangeType::Cal)==data.count() );
+  for (uint i=0; i<data.count(); i++) {
+    QString address = toHexLabel(range(MemoryRangeType::Cal).start + i*addressIncrement(MemoryRangeType::Cal), nbCharsAddress());
+    if ( data[i]==mask(MemoryRangeType::Cal) ) {
+      if (message) *message = i18n("Calibration word at address %1 is blank.").arg(address);
+      return false;
+    }
+  }
+  if ( data.count()==1 ) {
+    if ( data[0].maskWith(_calibration.opcodeMask)!=_calibration.opcode ) {
+      if (message) *message = i18n("Calibration word is not a compatible opcode (%2).")
+                              .arg(toHexLabel(_calibration.opcode, nbCharsWord(MemoryRangeType::Code)));
+      return false;
+    }
+  }
+  return true;
+}
+
+const Pic::RegistersData &Pic::Data::registersData() const
+{
+  return static_cast<const RegistersData &>(*_registersData);
+}
+
+bool Pic::Data::hasFeature(Feature feature, bool *unknown) const
+{
+  bool ok = ( registersData().nbBanks!=0 );
+  if (unknown) *unknown = !ok;
+  if (!ok) return false;
+  switch (feature.type()) {
+    case Feature::CCP: return registersData().sfrs.contains("CCP1CON");
+    case Feature::ADC: return registersData().sfrs.contains("ADCON0");
+    case Feature::SSP: return registersData().sfrs.contains("SSPCON");
+    case Feature::LVD: return registersData().sfrs.contains("LVDCON");
+    case Feature::USB: return registersData().sfrs.contains("UCON");
+    case Feature::USART:
+      return ( registersData().sfrs.contains("TXSTA")        // 16F
+               || registersData().sfrs.contains("TXSTA1")    // 18F
+               || registersData().sfrs.contains("U1MODE") ); // 30F
+    case Feature::CAN: return registersData().sfrs.contains("CANCON") && !registersData().sfrs.contains("ECANCON");
+    case Feature::ECAN: return registersData().sfrs.contains("ECANCON");
+    case Feature::Ethernet: return registersData().sfrs.contains("ETHCON1");
+    case Feature::LCD: return registersData().sfrs.contains("LCDCON");
+    case Feature::MotorControl: return registersData().sfrs.contains("PWMCON0");
+    case Feature::MotionFeedback: return registersData().sfrs.contains("CAP1CON");
+    case Feature::SelfWrite: return _selfWrite==SelfWrite::Yes;
+    case Feature::Nb_Types: Q_ASSERT(false); break;
+  }
+  return false;
+}
+
+Device::Array Pic::Data::gotoInstruction(Address address, bool withPageSelection) const
+{
+  Q_ASSERT( address<addressIncrement(MemoryRangeType::Code)*nbWords(MemoryRangeType::Code) );
+  Device::Array a;
+  switch (_architecture.type()) {
+  case Architecture::P10X:
+    if ( nbWords(MemoryRangeType::Code)>0x1FF && withPageSelection)
+      a.append(0x4A3 | (address>0x1FF ? 0x100 : 0x000)); // bsf STATUS,PA0 or bcf STATUS,PA0
+    a.append(0xA00 | (address.toUInt() & 0x1FF)); // goto
+    break;
+  case Architecture::P16X:
+    if ( nbWords(MemoryRangeType::Code)>0x7FF && withPageSelection ) {
+      if ( address<=0x7FF ) a.append(0x018A); // clrf PCLATH
+      else {
+        a.append(0x3000 | (address.toUInt() >> 8)); // movl high address
+        a.append(0x008A); // movwf PCLATH
+      }
+    }
+    a.append(0x2800 | (address.toUInt() & 0x7FF));
+    break;
+  case Architecture::P17C:
+    a.append(0xC000 | (address.toUInt() & 0x1FFF));
+    break;
+  case Architecture::P18C:
+  case Architecture::P18F:
+  case Architecture::P18J:
+    a.append(0xEF00 | ((address.toUInt()/2) & 0xFF));
+    a.append(0xF000 | ((address.toUInt()/2) >> 8));
+    break;
+  case Architecture::P24F:
+  case Architecture::P24H:
+  case Architecture::P30F:
+  case Architecture::P33F:
+    a.append(0x040000 | (address.toUInt() & 0x00FFFE));
+    a.append(0X000000 | (address.toUInt() >> 16));
+    break;
+  case Architecture::Nb_Types: Q_ASSERT(false); break;
+  }
+  return a;
+}
+
+bool Pic::Data::isGotoInstruction(BitValue instruction) const
+{
+  switch (_architecture.type()) {
+  case Architecture::P10X: return ( instruction.maskWith(0xE00)==0xA00 );
+  case Architecture::P16X: return ( instruction.maskWith(0xF800)==0x2800 );
+  case Architecture::P17C: return ( instruction.maskWith(0xE000)==0xC000 );
+  case Architecture::P18C:
+  case Architecture::P18F:
+  case Architecture::P18J: return ( instruction.maskWith(0xFF00)==0xEF00 );
+  case Architecture::P24F:
+  case Architecture::P24H:
+  case Architecture::P30F:
+  case Architecture::P33F: return ( instruction.maskWith(0xFF0000)==0x040000 );
+  case Architecture::Nb_Types: Q_ASSERT(false); break;
+  }
+  return false;
+}
+
+uint Pic::Data::nbWordsWriteAlignment(MemoryRangeType type) const
+{
+  if ( type!=MemoryRangeType::Code ) return 1;
+  return QMAX(_nbWordsCodeWrite, uint(16));
+}
+
+//----------------------------------------------------------------------------
+QDataStream &operator <<(QDataStream &s, const Pic::VoltageData &vd)
+{
+  s << vd.min << vd.max << vd.nominal;
+  return s;
+}
+QDataStream &operator >>(QDataStream &s, Pic::VoltageData &vd)
+{
+  s >> vd.min >> vd.max >> vd.nominal;
+  return s;
+}
+
+QDataStream &operator <<(QDataStream &s, const Pic::MemoryRangeData &mrd)
+{
+  s << Q_UINT8(mrd.properties) << mrd.start << mrd.end << mrd.hexFileOffset;
+  return s;
+}
+QDataStream &operator >>(QDataStream &s, Pic::MemoryRangeData &mrd)
+{
+  Q_UINT8 properties;
+  s >> properties >> mrd.start >> mrd.end >> mrd.hexFileOffset;
+  mrd.properties = Pic::MemoryRangeProperties(properties);
+  return s;
+}
+
+QDataStream &operator <<(QDataStream &s, const Pic::Checksum::Data &cd)
+{
+  s << cd.constant << cd.bbsize << cd.algorithm << cd.protectedMaskNames;
+  s << cd.blankChecksum << cd.checkChecksum;
+  return s;
+}
+QDataStream &operator >>(QDataStream &s, Pic::Checksum::Data &cd)
+{
+  s >> cd.constant >> cd.bbsize >> cd.algorithm >> cd.protectedMaskNames;
+  s >> cd.blankChecksum >> cd.checkChecksum;
+  return s;
+}
+
+QDataStream &operator <<(QDataStream &s, const Pic::CalibrationData &cd)
+{
+  s << cd.opcode << cd.opcodeMask;
+  return s;
+}
+QDataStream &operator >>(QDataStream &s, Pic::CalibrationData &cd)
+{
+  s >> cd.opcode >> cd.opcodeMask;
+  return s;
+}
+
+QDataStream &Pic::operator <<(QDataStream &s, const Pic::Data &data)
+{
+  s << static_cast<const Device::Data &>(data);
+  s << data._architecture << data._ids << data._nbBitsPC;
+  s << data._voltages << data._ranges;
+  s << data._userIdRecommendedMask;
+  s << *data._config;
+  s << data._checksums;
+  s << data._calibration;
+  s << static_cast<const Pic::RegistersData &>(*data._registersData);
+  s << data._nbWordsCodeWrite << data._nbWordsCodeRowErase;
+  s << data._selfWrite;
+  return s;
+}
+QDataStream &Pic::operator >>(QDataStream &s, Pic::Data &data)
+{
+  s >> static_cast<Device::Data &>(data);
+  s >> data._architecture >> data._ids >> data._nbBitsPC;
+  s >> data._voltages >> data._ranges;
+  s >> data._userIdRecommendedMask;
+  s >> *data._config;
+  s >> data._checksums;
+  s >> data._calibration;
+  s >> static_cast<Pic::RegistersData &>(*data._registersData);
+  s >> data._nbWordsCodeWrite >> data._nbWordsCodeRowErase;
+  s >> data._selfWrite;
+  return s;
+}
diff --git a/src/devices/pic/base/pic.h b/src/devices/pic/base/pic.h
new file mode 100644
index 0000000..7b0dfc4
--- /dev/null
+++ b/src/devices/pic/base/pic.h
@@ -0,0 +1,179 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_H
+#define PIC_H
+
+#include <qstringlist.h>
+#include <qmap.h>
+
+#include "common/global/global.h"
+#include "common/common/bitvalue.h"
+#include "devices/base/generic_device.h"
+
+namespace Pic
+{
+class XmlToData;
+class Group;
+class Config;
+class RegistersData;
+
+//-----------------------------------------------------------------------------
+struct VoltageData {
+  double min, max, nominal;
+};
+inline bool operator ==(const Pic::VoltageData &v1, const Pic::VoltageData &v2) { return ( v1.min==v2.min && v1.max==v2.max && v1.nominal==v2.nominal ); }
+
+BEGIN_DECLARE_ENUM(ProgVoltageType)
+  Vpp = 0, VddBulkErase, VddWrite
+END_DECLARE_ENUM_STD(ProgVoltageType)
+
+struct CalibrationData {
+  BitValue opcode, opcodeMask;
+};
+
+enum MemoryRangeTypeProperty { ReadOnly = 0, Writable = 1 };
+Q_DECLARE_FLAGS(MemoryRangeTypeProperties, MemoryRangeTypeProperty)
+Q_DECLARE_OPERATORS_FOR_FLAGS(MemoryRangeTypeProperties)
+struct MemoryRangeTypeData {
+  const char *key, *label;
+  MemoryRangeTypeProperties properties;
+};
+BEGIN_DECLARE_ENUM(MemoryRangeType)
+  Code = 0, Cal, UserId, DeviceId, Config, Eeprom, DebugVector, HardwareStack, CalBackup, ProgramExecutive
+END_DECLARE_ENUM(MemoryRangeType, MemoryRangeTypeData)
+
+BEGIN_DECLARE_ENUM(SelfWrite)
+  Yes, No
+END_DECLARE_ENUM_STD(SelfWrite)
+
+BEGIN_DECLARE_ENUM(DeviceType)
+  Normal, J, K
+END_DECLARE_ENUM_STD(DeviceType)
+
+struct ArchitectureData {
+  const char *key, *label;
+  uint nbBitsPC;                     // nb bits program counter
+  uint nbBytesWord;                  // nb bytes per word (hex file and icd2)
+  bool packed;                       // addressIncrement = (packed ? nbBytesWord : nbBytesWord/2)
+  uint nbBitsRegister;
+  uint registerBankLength;
+  uint nbBits[MemoryRangeType::Nb_Types];  // nb bits per word
+  bool hasAddressAccess;             // memory can be accessed randomly
+  SelfWrite::Type selfWrite;
+  DeviceType::Type deviceType;
+};
+BEGIN_DECLARE_ENUM(Architecture)
+  P10X = 0, P16X, P17C, P18C, P18F, P18J, P24F, P24H, P30F, P33F
+END_DECLARE_ENUM(Architecture, ArchitectureData)
+
+enum MemoryRangeProperty { NotPresent = 0, Present = 1, Programmable = 2 };
+Q_DECLARE_FLAGS(MemoryRangeProperties, MemoryRangeProperty)
+Q_DECLARE_OPERATORS_FOR_FLAGS(MemoryRangeProperties)
+struct MemoryRangeData {
+  MemoryRangeProperties properties;
+  Address start, end;
+  uint hexFileOffset;
+};
+
+namespace Checksum
+{
+  BEGIN_DECLARE_ENUM(Algorithm)
+    Normal = 0, XOR4, XNOR7, XNOR8
+  END_DECLARE_ENUM_STD(Algorithm)
+  class Data {
+  public:
+    BitValue constant;
+    Algorithm algorithm;
+    QStringList protectedMaskNames;
+    QString bbsize;
+    BitValue blankChecksum, checkChecksum;
+  };
+} // namespace
+
+BEGIN_DECLARE_ENUM(Feature)
+  CCP, ADC, SSP, LVD, USB, USART, CAN, ECAN, Ethernet, LCD, MotorControl,
+  MotionFeedback, SelfWrite
+END_DECLARE_ENUM_STD(Feature)
+
+//-----------------------------------------------------------------------------
+class Data : public Device::Data
+{
+public:
+  Data();
+  virtual ~Data();
+  virtual QString fname(Device::Special special) const;
+  virtual QString listViewGroup() const { return _architecture.label(); }
+  bool isPresent(MemoryRangeType type) const { return (range(type).properties & Present); }
+  bool isReadable(MemoryRangeType type) const;
+  bool isWritable(MemoryRangeType type) const;
+  uint nbAddresses(MemoryRangeType type) const;
+  uint nbWords(MemoryRangeType type) const;
+  uint addressIncrement(MemoryRangeType type) const;
+  uint nbWordsWriteAlignment(MemoryRangeType type) const;
+  MemoryRangeData range(MemoryRangeType type) const { return _ranges[type]; }
+  virtual uint nbBitsAddress() const { return _nbBitsPC; }
+  uint nbBitsWord(MemoryRangeType type) const { return _architecture.data().nbBits[type.type()]; }
+  uint nbBytesWord(MemoryRangeType type) const { return nbBitsToNbBytes(nbBitsWord(type)); }
+  uint nbCharsWord(MemoryRangeType type) const { return nbBitsToNbChars(nbBitsWord(type)); }
+  BitValue mask(MemoryRangeType type) const { return uint(1 << nbBitsWord(type))-1; }
+  BitValue userIdRecommendedMask() const { return _userIdRecommendedMask; }
+  const Config &config() const { return *_config; }
+  Architecture architecture() const { return _architecture; }
+  bool is18Family() const { return ( _architecture==Architecture::P18C || _architecture==Architecture::P18F || _architecture==Architecture::P18J); }
+  bool is16bitFamily() const { return ( _architecture.data().nbBitsRegister==16 ); }
+  VoltageData voltage(ProgVoltageType type) const { return _voltages[type]; }
+  virtual bool canWriteCalibration() const { return isWritable(MemoryRangeType::Cal); }
+  bool checkCalibration(const Device::Array &data, QString *message = 0) const;
+  const QMap<Device::Special, BitValue> ids() const { return _ids; }
+  virtual bool matchId(BitValue rawId, Device::IdData &data) const;
+  QStringList idNames(const QMap<QString, Device::IdData> &ids) const;
+  const QMap<QString, Checksum::Data> checksums() const { return _checksums; }
+  const RegistersData &registersData() const;
+  const CalibrationData &calibrationData() const { return _calibration; }
+
+  bool hasFeature(Feature feature, bool *unknown = 0) const;
+  BitValue nopInstruction() const { return 0x0; }
+  Device::Array gotoInstruction(Address address, bool withPageSelection) const;
+  bool isGotoInstruction(BitValue instruction) const;
+
+private:
+  Architecture _architecture;
+  QMap<Device::Special, BitValue> _ids;
+  uint             _nbBitsPC;
+  uint             _nbWordsCodeWrite;    // #### only for 18F/18J devices [0 for other devices]
+  uint             _nbWordsCodeRowErase; // #### only for 18F/18J devices [0 for other devices or if not available]
+  QMap<ProgVoltageType, VoltageData>     _voltages;
+  QMap<MemoryRangeType, MemoryRangeData> _ranges;
+  BitValue         _userIdRecommendedMask;
+  Config          *_config;
+  QMap<QString, Checksum::Data> _checksums;
+  CalibrationData  _calibration;
+  SelfWrite        _selfWrite;
+
+  friend class XmlToData;
+  friend class Group;
+  friend QDataStream &operator <<(QDataStream &s, const Data &data);
+  friend QDataStream &operator >>(QDataStream &s, Data &data);
+};
+
+QDataStream &operator <<(QDataStream &s, const Data &data);
+QDataStream &operator >>(QDataStream &s, Data &data);
+
+} // namespace
+
+QDataStream &operator <<(QDataStream &s, const Pic::VoltageData &vd);
+QDataStream &operator >>(QDataStream &s, Pic::VoltageData &vd);
+QDataStream &operator <<(QDataStream &s, const Pic::MemoryRangeData &mrd);
+QDataStream &operator >>(QDataStream &s, Pic::MemoryRangeData &mrd);
+QDataStream &operator <<(QDataStream &s, const Pic::Checksum::Data &cd);
+QDataStream &operator >>(QDataStream &s, Pic::Checksum::Data &cd);
+QDataStream &operator <<(QDataStream &s, const Pic::CalibrationData &cd);
+QDataStream &operator >>(QDataStream &s, Pic::CalibrationData &cd);
+
+#endif
diff --git a/src/devices/pic/base/pic_config.cpp b/src/devices/pic/base/pic_config.cpp
new file mode 100644
index 0000000..6672794
--- /dev/null
+++ b/src/devices/pic/base/pic_config.cpp
@@ -0,0 +1,456 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_config.h"
+
+#include <qregexp.h>
+
+const Pic::ConfigNameType::Data Pic::ConfigNameType::DATA[Nb_Types] = {
+  { "cname", 0 },
+  { "ecname", 0 },
+  { "sdcc_cname", 0 }
+};
+
+const Pic::Config::Data Pic::Config::DATA[] = {
+  { { "CP",    I18N_NOOP("Code code-protection")         }, MemoryRange, { { 0, 0 } } },
+  { { "CPD",   I18N_NOOP("Data code-protection")         }, MemoryRange, { { 0, 0 } } },
+  { { "CPC",   I18N_NOOP("Calibration code-protection")  }, MemoryRange, { { 0, 0 } } },
+  { { "CPB",   I18N_NOOP("Boot code-protection")         }, MemoryRange, { { 0, 0 } } },
+
+  { { "WRT",   I18N_NOOP("Code write-protection")           }, MemoryRange, { { 0, 0 } } },
+  { { "WRTD",  I18N_NOOP("Data write-protection")           }, MemoryRange, { { 0, 0 } } },
+  { { "WRTB",  I18N_NOOP("Boot write-protection")           }, MemoryRange, { { 0, 0 } } },
+  { { "WRTC",  I18N_NOOP("Configuration write-protection")  }, MemoryRange, { { 0, 0 } } },
+
+  { { "EBTR",  I18N_NOOP("Table read-protection")      }, MemoryRange, { { 0, 0 } } },
+  { { "EBTRB", I18N_NOOP("Boot table read-protection") }, MemoryRange, { { 0, 0 } } },
+
+  { { "WDT",  I18N_NOOP("Watchdog timer") }, Toggle, { { 0, 0 } } },
+  { { "MCLRE", I18N_NOOP("Master clear reset"), }, Fixed, {
+    { "External", I18N_NOOP("External"),                   },
+    { "Internal", I18N_NOOP("Disabled (connected to Vdd)") }, { 0, 0 } } },
+  { { "PWRTE", I18N_NOOP("Power-up timer") }, Toggle, { { 0, 0 } } },
+
+  { { "FOSC",  I18N_NOOP("Oscillator") }, Fixed,  {
+    { "EXTRC", I18N_NOOP("External RC oscillator")                   },
+    { "EXTRC_CLKOUT", I18N_NOOP("External RC oscillator with CLKOUT") },
+    { "EXTRC_IO", I18N_NOOP("External RC oscillator (no CLKOUT)")   },
+    { "INTRC", I18N_NOOP("Internal oscillator")                      },
+    { "INTRC_CLKOUT", I18N_NOOP("Internal oscillator with CLKOUT")   },
+    { "INTRC_IO", I18N_NOOP("Internal oscillator (no CLKOUT)")       },
+    { "XT", I18N_NOOP("Crystal/resonator")                          },
+    { "XTPLL", I18N_NOOP("Crystal/resonator, PLL enabled") },
+    { "LP", I18N_NOOP("Low power crystal")                           },
+    { "EC", I18N_NOOP("External clock")                              },
+    { "EC_CLKOUT", I18N_NOOP("External clock with CLKOUT")           },
+    { "EC_IO", I18N_NOOP("External clock (no CLKOUT)")               },
+    { "ECPLL_CLKOUT", I18N_NOOP("External clock with CLKOUT, PLL enabled")           },
+    { "ECPLL_IO", I18N_NOOP("External clock (no CLKOUT), PLL enabled")               },
+    { "E4_CLKOUT", I18N_NOOP("External clock with 4x PLL and with CLKOUT") },
+    { "E4_IO", I18N_NOOP("External clock with 4x PLL (no CLKOUT)")   },
+    { "E4S_IO", I18N_NOOP("External clock with software controlled 4x PLL (no CLKOUT)") },
+    { "ER", I18N_NOOP("External resistor")                           },
+    { "ER_CLKOUT", I18N_NOOP("External resistor with CLKOUT")        },
+    { "ER_IO", I18N_NOOP("External resistor (no CLKOUT)")            },
+    { "HS", I18N_NOOP("High speed crystal/resonator")                },
+    { "HSPLL", I18N_NOOP("High speed crystal/resonator, PLL enabled") },
+    { "H4", I18N_NOOP("High speed crystal/resonator with 4x PLL")    },
+    { "H4S", I18N_NOOP("High speed crystal/resonator with software controlled 4x PLL") },
+    { "INTXT", I18N_NOOP("Internal oscillator, XT used by USB") },
+    { "INTHS", I18N_NOOP("Internal oscillator, HS used by USB") },
+    { 0, 0 } } },
+
+  { { "BG",    I18N_NOOP("Bandgap voltage calibration") }, Fixed, {
+    { "Lowest",   I18N_NOOP("Lowest")   },
+    { "Mid/Low",  I18N_NOOP("Mid/Low")  },
+    { "Mid/High", I18N_NOOP("Mid/High") },
+    { "Highest",  I18N_NOOP("Highest")  }, { 0, 0 } } },
+  { { "TRIM", I18N_NOOP("Internal Trim") }, Fixed, {
+    { "00", I18N_NOOP("00") }, { "01", I18N_NOOP("01") },
+    { "10", I18N_NOOP("10") }, { "11", I18N_NOOP("11") }, { 0, 0 } } },
+  { { "BODEN", I18N_NOOP("Brown-out detect")       }, Toggle, {
+    { "On_run",   I18N_NOOP("Enabled in run - Disabled in sleep") },
+    { "Software", I18N_NOOP("SBODEN controls BOD function")       }, { 0, 0 } } },
+  { { "FCMEN", I18N_NOOP("Fail-safe clock monitor")      }, Toggle, { { 0, 0 } } },
+  { { "IESO",  I18N_NOOP("Internal-external switchover") }, Toggle, { { 0, 0 } } },
+  { { "WUREN",  I18N_NOOP("Wake-up reset")               }, Toggle, { { 0, 0 } } },
+  { { "DEBUG", I18N_NOOP("In-circuit debugger")          }, Toggle, { { 0, 0 } } },
+  { { "MPEEN", I18N_NOOP("Memory parity error")          }, Toggle, { { 0, 0 } } },
+  { { "BORV",  I18N_NOOP("Brown-out reset voltage") }, ValueDouble, {
+    { "0", I18N_NOOP("Undefined")  }, { 0, 0 } } },
+  { { "LVP",   I18N_NOOP("Low voltage programming")   }, Toggle, { { 0, 0 } } },
+  { { "CCP2MX", I18N_NOOP("CCP2 multiplex")           }, Pin, { { 0, 0 } } },
+  { { "CCP1MX", I18N_NOOP("CCP1 multiplex")           }, Pin, { { 0, 0 } } },
+  { { "BORSEN", I18N_NOOP("Brown-out reset software") }, Toggle, { { 0, 0 } } },
+  { { "WDTPS", I18N_NOOP("WDT post-scaler") }, Ratio, {
+    { "Disabled", I18N_NOOP("Disabled") }, { 0, 0 } } },
+  { { "PM",    I18N_NOOP("Processor mode") }, Fixed, {
+    { "Extended microcontroller", I18N_NOOP("Extended microcontroller")            },
+    { "Microcontroller", I18N_NOOP("Microcontroller")                              },
+    { "Microprocessor", I18N_NOOP("Microprocessor")                                },
+    { "Code-protected microcontroller", I18N_NOOP("Code protected microcontroller") },
+    { "Microprocessor with boot", I18N_NOOP("Microprocessor with boot block")       },
+    { 0, 0 } } },
+
+  { { "OSCSEN", I18N_NOOP("Oscillator system clock switch") }, Toggle, { { 0, 0 } } },
+  { { "STVREN", I18N_NOOP("Stack full/underflow reset") }, Toggle, { { 0, 0 } } },
+  { { "BW",    I18N_NOOP("External bus data width (in bits)") }, ValueUInt, { { 0, 0 } } },
+  { { "PBADEN", I18N_NOOP("PORTB A/D")              }, Fixed, {
+      { "digital", I18N_NOOP("Digital") },
+      { "analog",  I18N_NOOP("Analog")  }, { 0, 0 } } },
+  { { "WINEN", I18N_NOOP("Watchdog timer window")   }, Toggle, { { 0, 0 } } },
+  { { "HPOL", I18N_NOOP("Odd PWM output polarity")  }, Fixed, {
+    { "high", I18N_NOOP("Active high")  },
+    { "low",  I18N_NOOP("Active low")   }, { 0, 0 } } },
+  { { "LPOL", I18N_NOOP("Even PWM output polarity") }, Fixed, {
+    { "high", I18N_NOOP("Active high")  },
+    { "low",  I18N_NOOP("Active low")   }, { 0, 0 } } },
+  { { "PWMPIN", I18N_NOOP("PWM output pin reset state") }, Toggle, { { 0, 0 } } },
+  { { "T1OSCMX", I18N_NOOP("Timer1 oscillator mode") }, Fixed, {
+    { "Legacy",    I18N_NOOP("Standard operation")      },
+    { "Low Power", I18N_NOOP("Low power in sleep mode") },
+    { "RA6",       I18N_NOOP("T1OSO/T1CKI on RA6") },
+    { "RB2",       I18N_NOOP("T1OSO/T1CKI on RB2") }, { 0, 0 } } },
+  { { "EXCLKMX", I18N_NOOP("TMR0/T5CKI external clock mux") }, Pin, { { 0, 0 } } },
+  { { "FLTAMX", I18N_NOOP("FLTA mux")               }, Pin, { { 0, 0 } } },
+  { { "PWM4MX", I18N_NOOP("PWM4 mux")               }, Pin, { { 0, 0 } } },
+  { { "SSPMX", I18N_NOOP("SSP I/O mux (SCK/SLC, SDA/SDI, SD0)") }, Pins, { { 0, 0 } } },
+  { { "LPT1OSC", I18N_NOOP("Low-power timer1 oscillator") }, Toggle, { { 0, 0 } } },
+  { { "XINST", I18N_NOOP("Extended instruction set") }, Toggle, { { 0, 0 } } },
+  { { "BBSIZ", I18N_NOOP("Boot block size") }, ValueUInt, { { 0, 0 } } },
+  { { "ICPORT", I18N_NOOP("Dedicated in-circuit port") }, Toggle, { { 0, 0 } } },
+  { { "VREGEN", I18N_NOOP("USB voltage regulator")  }, Toggle, { { 0, 0 } } },
+  { { "WAIT", I18N_NOOP("External bus data wait")   }, Toggle, { { 0, 0 } } },
+  { { "ABW", I18N_NOOP("Address bus width (in bits)") }, ValueUInt, { { 0, 0 } } },
+  { { "ECCPMX", I18N_NOOP("ECCP mux") }, Fixed, {
+    { "RE6-RE3", I18N_NOOP("PWM multiplexed onto RE6 and RE3") },
+    { "RH7-RH4", I18N_NOOP("PWM multiplexed onto RH7 and RH4") },
+    { "RE6-RE5", I18N_NOOP("PWM multiplexed onto RE6 and RE5") },
+    { "RH7-RH6", I18N_NOOP("PWM multiplexed onto RH7 and RH6") }, { 0, 0 } } },
+
+  { { "FCKSM", I18N_NOOP("Clock switching mode") }, Fixed, {
+    { "Switching off, monitor off", I18N_NOOP("Switching off, monitor off") },
+    { "Switching on, monitor off",  I18N_NOOP("Switching on, monitor off")  },
+    { "Switching on, monitor on",   I18N_NOOP("Switching on, monitor on")   }, { 0, 0 } } },
+  { { "FOS", I18N_NOOP("Oscillator source") }, Fixed, {
+    { "INTRC_F",  I18N_NOOP("Internal fast RC")      },
+    { "INTRC_LP", I18N_NOOP("Internal low-power RC") },
+    { "PRIM",     I18N_NOOP("Primary")               },
+    { "TMR1",     I18N_NOOP("Timer1")                }, { 0, 0 } } },
+  { { "FPR", I18N_NOOP("Primary oscillator mode") }, Fixed, {
+    { "XTL",          I18N_NOOP("Low-power/low-frequency crystal") },
+    { "HS",           I18N_NOOP("High speed crystal") },
+    { "XT",           I18N_NOOP("XT Crystal") },
+    { "XT4",           I18N_NOOP("XT Crystal with 4x PLL") },
+    { "XT8",           I18N_NOOP("XT Crystal with 8x PLL") },
+    { "XT16",          I18N_NOOP("XT Crystal with 16x PLL") },
+    { "EC_CLKOUT",    I18N_NOOP("External clock with CLKOUT") },
+    { "EC_IO",        I18N_NOOP("External clock (no CLKOUT)") },
+    { "EC4",    I18N_NOOP("External clock with 4x PLL") },
+    { "EC8",    I18N_NOOP("External clock with 8x PLL") },
+    { "EC16",   I18N_NOOP("External clock with 16x PLL") },
+    { "FRC8",    I18N_NOOP("Internal fast RC oscillator with 8x PLL") },
+    { "EXTRC_CLKOUT", I18N_NOOP("External RC oscillator with CLKOUT") },
+    { "EXTRC_IO",     I18N_NOOP("External RC oscillator (no CLKOUT)") }, { 0, 0 } } },
+  { { "FOSFPR", I18N_NOOP("Oscillator mode") }, Fixed, {
+    { "XTL",          I18N_NOOP("Low-power/low-frequency crystal") },
+    { "HS",           I18N_NOOP("High speed crystal") },
+    { "XT",           I18N_NOOP("XT Crystal") },
+    { "XT4",           I18N_NOOP("XT Crystal with 4x PLL") },
+    { "XT8",           I18N_NOOP("XT Crystal with 8x PLL") },
+    { "XT16",          I18N_NOOP("XT Crystal with 16x PLL") },
+    { "HS2_4",           I18N_NOOP("HS/2 Crystal with 4x PLL") },
+    { "HS2_8",           I18N_NOOP("HS/2 Crystal with 8x PLL") },
+    { "HS2_16",          I18N_NOOP("HS/2 Crystal with 16x PLL") },
+    { "HS3_4",           I18N_NOOP("HS/3 Crystal with 4x PLL") },
+    { "HS3_8",           I18N_NOOP("HS/3 Crystal with 8x PLL") },
+    { "HS3_16",          I18N_NOOP("HS/3 Crystal with 16x PLL") },
+    { "EC_CLKOUT",    I18N_NOOP("External clock with CLKOUT") },
+    { "EC_IO",        I18N_NOOP("External clock (no CLKOUT)") },
+    { "EC4",    I18N_NOOP("External clock with 4x PLL") },
+    { "EC8",    I18N_NOOP("External clock with 8x PLL") },
+    { "EC16",   I18N_NOOP("External clock with 16x PLL") },
+    { "FRC4",    I18N_NOOP("Internal fast RC oscillator with 4x PLL") },
+    { "FRC8",    I18N_NOOP("Internal fast RC oscillator with 8x PLL") },
+    { "FRC16",   I18N_NOOP("Internal fast RC oscillator with 16x PLL") },
+    { "TMR1",   I18N_NOOP("Low-power 32 kHz oscillator (TMR1 oscillator)") },
+    { "INTRC_F", I18N_NOOP("Internal fast RC oscillator (no PLL)") },
+    { "INTRC_LP", I18N_NOOP("Internal low-power RC oscillator") },
+    { "EXTRC_CLKOUT", I18N_NOOP("External RC oscillator with CLKOUT") },
+    { "EXTRC_IO",     I18N_NOOP("External RC oscillator (no CLKOUT)") }, { 0, 0 } } },
+  { { "FWPSA", I18N_NOOP("Watchdog timer prescaler A") }, Ratio, { { 0, 0 } } },
+  { { "FWPSB", I18N_NOOP("Watchdog timer prescaler B") }, Ratio, { { 0, 0 } } },
+  { { "FWDTEN", I18N_NOOP("Watchdog") }, Toggle, {
+    { "Software", I18N_NOOP("Software") }, { 0, 0 } } },
+  { { "FPWRT", I18N_NOOP("Power-on reset timer value (ms)") }, ValueUInt, {
+    { "0", I18N_NOOP("Disabled") }, { 0, 0 } } },
+  { { "GCP", I18N_NOOP("General code segment read-protection") }, MemoryRange, { { 0, 0 } } },
+  { { "GWRP", I18N_NOOP("General code segment write-protection") }, MemoryRange, { { 0, 0 } } },
+  { { "COE", I18N_NOOP("Reset into clip on emulation mode") }, Toggle, { { 0, 0 } } },
+  { { "ICS", I18N_NOOP("ICD communication channel") }, Pins, { { 0, 0 } } },
+
+  { { "USBDIV", I18N_NOOP("USB clock (PLL divided by)") }, ValueUInt, {
+    { "1", I18N_NOOP("not divided") }, { 0, 0 } } },
+  { { "CPUDIV", I18N_NOOP("CPU system clock (divided by)") }, ValueUInt, {
+    { "1", I18N_NOOP("not divided") }, { 0, 0 } } },
+  { { "PLLDIV", I18N_NOOP("PLL clock (divided by)") }, ValueUInt, {
+    { "1", I18N_NOOP("not divided") }, { 0, 0 } } },
+
+  { { "MCPU", I18N_NOOP("Master clear pull-up resistor") }, Toggle, { { 0, 0 } } },
+  { { "IOSCFS", I18N_NOOP("Internal oscillator speed") }, Fixed, {
+    { "8MHZ", I18N_NOOP("8 MHz") },
+    { "4MHZ", I18N_NOOP("4 MHz") }, { 0, 0 } } },
+
+  // 18J specific
+  { { "ETHLED", I18N_NOOP("Ethernet LED enable") }, Toggle, { { 0, 0 } } },
+  { { "FOSC2", I18N_NOOP("Default system clock select") }, Fixed, {
+    { "FOSC1:FOSC0", I18N_NOOP("FOSC1:FOSC0") },
+    { "INTRC", I18N_NOOP("INTRC") }, { 0, 0 } } },
+  { { "EMB", I18N_NOOP("External memory bus") }, Fixed, {
+    { "Disabled", I18N_NOOP("Disabled") },
+    { "12BIT", I18N_NOOP("12-bit external bus") },
+    { "16BIT", I18N_NOOP("16-bit external bus") },
+    { "20BIT", I18N_NOOP("20-bit external bus") }, { 0, 0 } } },
+  { { "EASHFT", I18N_NOOP("External address bus shift") }, Toggle, { { 0, 0 } } },
+  { { "MSSPSEL", I18N_NOOP("MSSP address select bit") }, Fixed, {
+    { "7BIT", I18N_NOOP("7-bit address mask mode") },
+    { "5BIT", I18N_NOOP("5-bit address mask mode") }, { 0, 0 } } },
+  { { "PMPMX", I18N_NOOP("PMP pin select bit") }, Fixed, {
+    { "Connected", I18N_NOOP("Connected to EMB") },
+    { "NotConnected", I18N_NOOP("Not connected to EMB") }, { 0, 0 } } },
+
+  // 24X specific / 30F1010 / 30F202X
+  { { "WRTBS", I18N_NOOP("Boot segment write-protection") }, MemoryRange, { { 0, 0 } } },
+  { { "BSSIZ", I18N_NOOP("Boot segment size") }, ValueUInt, { { 0, 0 } } },
+  { { "BSSEC", I18N_NOOP("Boot segment security") }, Fixed, {
+    { "High Security",     I18N_NOOP("High Security") },
+    { "Standard Security", I18N_NOOP("Standard Security") }, { 0, 0 } } },
+  { { "EBSSIZ", I18N_NOOP("Boot segment EEPROM size") }, ValueUInt, { { 0, 0 } } },
+  { { "RBSSIZ", I18N_NOOP("Boot segment RAM size") }, ValueUInt, { { 0, 0 } } },
+  { { "WRTSS", I18N_NOOP("Secure segment write-protection") }, MemoryRange, { { 0, 0 } } },
+  { { "SSSIZ", I18N_NOOP("Secure segment size") }, ValueUInt, { { 0, 0 } } },
+  { { "SSSEC", I18N_NOOP("Secure segment security") }, Fixed, {
+    { "High Security",     I18N_NOOP("High Security") },
+    { "Standard Security", I18N_NOOP("Standard Security") }, { 0, 0 } } },
+  { { "ESSSIZ", I18N_NOOP("Secure segment EEPROM size") }, ValueUInt, { { 0, 0 } } },
+  { { "RSSSIZ", I18N_NOOP("Secure segment RAM size") }, ValueUInt, { { 0, 0 } } },
+  { { "WRTGS", I18N_NOOP("General segment write-protection") }, MemoryRange, { { 0, 0 } } },
+  { { "GSSEC", I18N_NOOP("General segment security") }, Fixed, {
+    { "Off",                I18N_NOOP("Off") },
+    { "High Security",     I18N_NOOP("High security") },
+    { "Standard Security", I18N_NOOP("Standard security") }, { 0, 0 } } },
+  { { "FNOSC", I18N_NOOP("Initial oscillator source") }, Fixed, {
+    { "EXTRC_F" ,    I18N_NOOP("Fast RC oscillator") },
+    { "INTRC_F",     I18N_NOOP("Internal fast RC oscillator") },
+    { "INTRC_F_PLL", I18N_NOOP("Internal fast RC oscillator with PLL") },
+    { "PRIM",        I18N_NOOP("Primary oscillator") },
+    { "PRIM_PLL",    I18N_NOOP("Primary oscillator with PLL") },
+    { "SECOND",      I18N_NOOP("Secondary oscillator (LP)") },
+    { "EXTRC_LP",    I18N_NOOP("Low power RC oscillator") },
+    { "INTRC_F_POST",  I18N_NOOP("Internal fast RC oscillator with postscaler") }, { 0, 0 } } },
+  { { "POSCMD", I18N_NOOP("Primary oscillator mode") }, Fixed, {
+    { "Off", I18N_NOOP("Off") },
+    { "HS",  I18N_NOOP("HS crystal oscillator") },
+    { "XT",  I18N_NOOP("XT crystal oscillator") },
+    { "EC",  I18N_NOOP("External clock") }, { 0, 0 } } },
+  { { "TEMP", I18N_NOOP("Temperature protection") }, Toggle, { { 0, 0 } } },
+  { { "OSCIOFNC", I18N_NOOP("OSC2 pin function") }, Fixed, {
+    { "IO", I18N_NOOP("Digital I/O") },
+    { "Clock", I18N_NOOP("Clock output") }, { 0, 0 } } },
+  { { "WINDIS", I18N_NOOP("Watchdog timer window") }, Toggle, { { 0, 0 } } },
+  { { "WDTPRE", I18N_NOOP("Watchdog timer prescaler") }, Ratio, { { 0, 0 } } },
+  { { "WDTPOST", I18N_NOOP("Watchdog timer postscaler") }, Ratio, { { 0, 0 } } },
+  { { "JTAGEN", I18N_NOOP("JTAG port enabled") }, Toggle, { { 0, 0 } } },
+  { { "IOL1WAY", I18N_NOOP("Peripheral pin select configuration") }, Fixed, {
+    { "One reconfiguration", I18N_NOOP("Allow only one reconfiguration") },
+    { "Multiple reconfigurations", I18N_NOOP("Allow multiple reconfigurations") }, { 0, 0 } } },
+  { { "ALTI2C", I18N_NOOP("Alternate I2C pins") }, Pin, { { 0, 0 } } },
+  { { "I2C1SEL", I18N_NOOP("I2C pins selection") }, Fixed, {
+    { "Default", I18N_NOOP("Default") },
+    { "Alternate", I18N_NOOP("Alternate") }, { 0, 0 } } },
+  { { "FRANGE", I18N_NOOP("Frequency range selection for FRC oscillator") }, Fixed, {
+    { "High range", I18N_NOOP("High range (nominal FRC frequency is 14.1 MHz)") },
+    { "Low range", I18N_NOOP("Low range (nominal FRC frequency is 9.7 MHz)") }, { 0, 0 } } },
+
+  { { 0, 0 }, Fixed, { { 0, 0 } } }
+};
+
+QMap<QString, Pic::Config::MapData> *Pic::Config::_masks = 0;
+QMap<QString, Pic::Config::MapData> &Pic::Config::masks()
+{
+  if ( _masks==0 ) {
+    _masks = new QMap<QString, MapData>;
+    for (uint i=0; DATA[i].mask.name; i++) {
+      (*_masks)[DATA[i].mask.name] = MapData(i, -1);
+      if ( DATA[i].type==MemoryRange ) {
+        for (uint k=0; k<Protection::MAX_NB_BLOCKS; k++)
+          (*_masks)[QString("%1_%2").arg(DATA[i].mask.name).arg(k)] = MapData(i, k);
+      }
+    }
+  }
+  return *_masks;
+}
+
+bool Pic::Config::hasMaskName(const QString &mask)
+{
+  return masks().contains(mask);
+}
+
+QString Pic::Config::maskLabel(const QString &mask)
+{
+  const MapData &mp = masks()[mask];
+  QString s = i18n(DATA[mp.index].mask.label);
+  if ( mp.block>=0 ) return i18n("%1 for block %2").arg(s).arg(mp.block);
+  return s;
+}
+
+const Pic::Config::Mask *Pic::Config::findMask(const QString &mask, uint *wordIndex) const
+{
+  for (uint i=0; i<uint(_words.count()); i++)
+    for (uint k=0; k<uint(_words[i].masks.count()); k++) {
+      if ( _words[i].masks[k].name==mask ) {
+        if (wordIndex) *wordIndex = i;
+        return &_words[i].masks[k];
+      }
+    }
+  return 0;
+}
+
+const Pic::Config::Value *Pic::Config::findValue(const QString &mask, const QString &value) const
+{
+  const Mask *cmask = findMask(mask);
+  if ( cmask==0 ) return 0;
+  for (uint i=0; i<uint(cmask->values.count()); i++)
+    if ( cmask->values[i].name==value ) return &cmask->values[i];
+  return 0;
+}
+
+bool Pic::Config::checkValueName(const QString &mask, const QString &name) const
+{
+  const Data &data = DATA[masks()[mask].index];
+  QString pinRegexp = "[A-Z]+\\d*(/[A-Z]+\\d*)?";
+  switch (data.type) {
+    case Fixed: break;
+    case ValueDouble: {
+      bool ok;
+      (void)name.toDouble(&ok);
+      if (ok) return true;
+      break;
+    }
+    case ValueUInt: {
+      bool ok;
+      (void)name.toUInt(&ok);
+      if (ok) return true;
+      break;
+    }
+    case Ratio: {
+      QRegExp regexp("(\\d+):(\\d+)");
+      if ( regexp.exactMatch(name) ) {
+        bool ok1, ok2;
+        (void)regexp.cap(1).toUInt(&ok1);
+        (void)regexp.cap(2).toUInt(&ok2);
+        if ( ok1 && ok2 ) return true;
+      }
+      break;
+    }
+    case MemoryRange:
+      return _protection.checkRange(mask, name);
+    case Toggle:
+      if ( name=="On" || name=="Off" ) return true;
+      break;
+    case Pin: {
+      QRegExp regexp(pinRegexp);
+      if ( regexp.exactMatch(name) ) return true;
+      break;
+    }
+    case Pins: {
+      QRegExp regexp(pinRegexp + "(, " + pinRegexp + ")+");
+      if ( regexp.exactMatch(name) ) return true;
+      break;
+    }
+  }
+  for (uint i=0; data.values[i].name; i++)
+    if ( data.values[i].name==name ) return true;
+  return false;
+}
+
+QString Pic::Config::valueLabel(const QString &mask, const QString &name)
+{
+  const Data &data = DATA[masks()[mask].index];
+  switch (data.type) {
+    case Fixed:
+    case ValueDouble:
+    case ValueUInt:
+    case Pin:
+    case Pins:
+    case Ratio: break;
+    case MemoryRange:
+      if ( name=="All" ) return i18n("All");
+      if ( name=="Off" ) return i18n("Disabled");
+      break;
+    case Toggle:
+      if ( name=="On" ) return i18n("Enabled");
+      if ( name=="Off" ) return i18n("Disabled");
+      break;
+  }
+  for (uint i=0; data.values[i].name; i++)
+    if ( data.values[i].name==name ) return i18n(data.values[i].label);
+  return name;
+}
+
+BitValue Pic::Config::Word::usedMask() const
+{
+  BitValue mask = 0x0;
+  for (uint i=0; i<uint(masks.count()); i++) mask |= masks[i].value;
+  return mask;
+}
+
+//-----------------------------------------------------------------------------
+QDataStream &Pic::operator <<(QDataStream &s, const Config::Value &value)
+{
+  s << value.name << value.configNames << value.value;
+  return s;
+}
+QDataStream &Pic::operator >>(QDataStream &s, Config::Value &value)
+{
+  s >> value.name >> value.configNames >> value.value;
+  return s;
+}
+
+QDataStream &Pic::operator <<(QDataStream &s, const Config::Mask &mask)
+{
+  s << mask.name << mask.value << mask.values;
+  return s;
+}
+QDataStream &Pic::operator >>(QDataStream &s, Config::Mask &mask)
+{
+  s >> mask.name >> mask.value >> mask.values;
+  return s;
+}
+
+QDataStream &Pic::operator <<(QDataStream &s, const Config::Word &word)
+{
+  s << word.name << word.ignoredCNames << word.wmask << word.pmask << word.cmask << word.bvalue << word.masks;
+  return s;
+}
+QDataStream &Pic::operator >>(QDataStream &s, Config::Word &word)
+{
+  s >> word.name >> word.ignoredCNames >> word.wmask >> word.pmask >> word.cmask >> word.bvalue >> word.masks;
+  return s;
+}
+
+QDataStream &Pic::operator <<(QDataStream &s, const Config &config)
+{
+  s << config._words;
+  return s;
+}
+QDataStream &Pic::operator >>(QDataStream &s, Config &config)
+{
+  s >> config._words;
+  return s;
+}
diff --git a/src/devices/pic/base/pic_config.h b/src/devices/pic/base/pic_config.h
new file mode 100644
index 0000000..185a19e
--- /dev/null
+++ b/src/devices/pic/base/pic_config.h
@@ -0,0 +1,107 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_CONFIG_H
+#define PIC_CONFIG_H
+
+#include <qmap.h>
+#include <qstringlist.h>
+
+#include "common/common/bitvalue.h"
+#include "pic_protection.h"
+#include "pic.h"
+
+namespace Pic
+{
+class Data;
+
+BEGIN_DECLARE_ENUM(ConfigNameType)
+  Default = 0, Extra, SDCC
+END_DECLARE_ENUM_STD(ConfigNameType)
+
+class Config
+{
+public:
+  class Value {
+  public:
+    QString name;
+    QMap<ConfigNameType, QStringList> configNames;
+    BitValue value;
+    bool operator <(const Value &cv) const { return value<cv.value; }
+    bool isValid() const { return !name.isEmpty(); }
+  };
+
+  class Mask {
+  public:
+    QString name;
+    BitValue value;
+    QValueVector<Value> values; // ordered from lower to higher
+    bool operator <(const Mask &cm) const { return value<cm.value; }
+  };
+
+  class Word {
+  public:
+    QString name;
+    QStringList ignoredCNames;
+    BitValue wmask, pmask, cmask; // write, protected, and checksum bits masks
+    BitValue bvalue;              // blank value
+    QValueVector<Mask> masks; // ordered from lower to higher
+    BitValue usedMask() const;
+  };
+
+public:
+  Config(const Pic::Data &data) : _data(data), _protection(data, *this) {}
+  QValueVector<Word> _words;
+  const Protection &protection() const { return _protection; }
+
+  const Value *findValue(const QString &mask, const QString &value) const;
+  const Mask *findMask(const QString &mask, uint *wordIndex = 0) const;
+  static bool hasMaskName(const QString &mask);
+  static QString maskLabel(const QString &mask);
+  bool checkValueName(const QString &mask, const QString &name) const;
+  static QString valueLabel(const QString &mask, const QString &name);
+
+private:
+  class MapData {
+  public:
+    MapData() {}
+    MapData(int i, int b) : index(i), block(b) {}
+    int index, block;
+  };
+  static QMap<QString, MapData> &masks();
+  static QMap<QString, MapData> *_masks; // mask name -> index in DATA
+
+  struct NameData {
+    const char *name, *label;
+  };
+  enum Type { Fixed, ValueDouble, ValueUInt, Ratio, MemoryRange, Toggle, Pin, Pins };
+  class Data {
+  public:
+    const NameData mask;
+    Type type;
+    const NameData values[50];
+  };
+  static const Data DATA[];
+
+private:
+  const Pic::Data &_data;
+  Protection _protection;
+};
+
+QDataStream &operator <<(QDataStream &s, const Config::Value &value);
+QDataStream &operator >>(QDataStream &s, Config::Value &value);
+QDataStream &operator <<(QDataStream &s, const Config::Mask &mask);
+QDataStream &operator >>(QDataStream &s, Config::Mask &mask);
+QDataStream &operator <<(QDataStream &s, const Config::Word &word);
+QDataStream &operator >>(QDataStream &s, Config::Word &word);
+QDataStream &operator <<(QDataStream &s, const Config &config);
+QDataStream &operator >>(QDataStream &s, Config &config);
+
+} //namespace
+
+#endif
diff --git a/src/devices/pic/base/pic_protection.cpp b/src/devices/pic/base/pic_protection.cpp
new file mode 100644
index 0000000..da77881
--- /dev/null
+++ b/src/devices/pic/base/pic_protection.cpp
@@ -0,0 +1,361 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_protection.h"
+
+#include "pic_config.h"
+
+#include <qregexp.h>
+
+bool Pic::Protection::isNoneProtectedValueName(const QString &name) const
+{
+  if ( name=="Off" ) return true;
+  if ( _data.architecture()==Architecture::P17C ) return !isAllProtectedValueName(name);
+  return false;
+}
+
+bool Pic::Protection::isAllProtectedValueName(const QString &name) const
+{
+  if ( name=="All" ) return true;
+  if ( _data.architecture()==Architecture::P17C ) return ( name=="Code-protected microcontroller" );
+  return false;
+}
+
+Pic::Protection::Family Pic::Protection::family() const
+{
+  if ( _config.findMask("WRTBS") ) return CodeGuard;
+  QString mask = maskName(ProgramProtected, MemoryRangeType::Code);
+  if ( _config.findMask(QString("%1_%2").arg(mask).arg(0)) ) return BlockProtection;
+  if ( _config.findMask(mask) ) return BasicProtection;
+  return NoProtection;
+}
+
+QString Pic::Protection::securityValueName(Type type) const
+{
+  if ( type==StandardSecurity ) return "Standard Security";
+  if ( type==HighSecurity ) return "High Security";
+  Q_ASSERT( type==Nb_Types );
+  return "Off";
+}
+
+QString Pic::Protection::bootSizeMaskName() const
+{
+  return (family()==CodeGuard ? "BSSIZ" : "BBSIZ");
+}
+
+QString Pic::Protection::bootMaskName(Type type) const
+{
+  Q_ASSERT( type!=Nb_Types );
+  if ( family()==CodeGuard ) {
+    if ( type==WriteProtected ) return "WRTBS";
+    if ( type==StandardSecurity || type==HighSecurity ) return "BSSEC";
+  } else {
+    if ( type==ProgramProtected ) return "CPB";
+    if ( type==WriteProtected ) return "WRTB";
+    if ( type==ReadProtected ) return "EBTRB";
+  }
+  return QString::null;
+}
+
+QString Pic::Protection::blockSizeMaskName(uint block) const
+{
+  if ( family()==CodeGuard ) {
+    Q_ASSERT( block==0 );
+    return "SSSIZ";
+  }
+  return blockMaskName(ProgramProtected, block);
+}
+
+QString Pic::Protection::blockMaskName(Type type, uint block) const
+{
+  Q_ASSERT( type!=Nb_Types );
+  if ( family()==CodeGuard ) {
+    if ( type==WriteProtected ) return (block==0 ? "WRTSS" : "WRTGS");
+    if ( type==StandardSecurity || type==HighSecurity ) return (block==0 ? "SSSEC" : "GSSEC");
+    return QString::null;
+  }
+  return QString("%1_%2").arg(maskName(type, MemoryRangeType::Code)).arg(block);
+}
+
+QString Pic::Protection::maskName(Type type, MemoryRangeType mtype) const
+{
+  Q_ASSERT( type!=Nb_Types );
+  switch (mtype.type()) {
+    case MemoryRangeType::Code:
+      if ( type==ProgramProtected ) {
+        if ( _data.architecture()==Architecture::P17C ) return "PM";
+        if ( _data.architecture()==Architecture::P30F || _data.architecture()==Architecture::P24F ) return "GCP";
+        return "CP";
+      }
+      if ( type==WriteProtected ) {
+        if ( _data.architecture()==Architecture::P30F || _data.architecture()==Architecture::P24F ) return "GWRP";
+        return "WRT";
+      }
+      if ( type==ReadProtected ) return "EBTR";
+      break;
+    case MemoryRangeType::Eeprom:
+      if ( type==ProgramProtected ) return "CPD";
+      if ( type==WriteProtected ) return "WRTD";
+      break;
+    case MemoryRangeType::Cal:
+      if ( type==ProgramProtected ) return "CPC";
+      break;
+    case MemoryRangeType::Config:
+      if ( type==WriteProtected ) return "WRTC";
+      if ( type==ReadProtected ) return "EBTRC";
+      break;
+    case MemoryRangeType::Nb_Types: Q_ASSERT(false); break;
+    default: break;
+  }
+  return QString::null;
+}
+
+bool Pic::Protection::extractRanges(const QString &name, QValueVector<Address> &starts, Address &end, bool &ok)
+{
+  ok = false;
+  QRegExp regexp("([A-F0-9]+)(/[A-F0-9]+)?(/[A-F0-9]+)?:([A-F0-9]+)");
+  if ( !regexp.exactMatch(name) ) return false;
+  bool ok1;
+  end = fromHex(regexp.cap(regexp.numCaptures()), &ok1);
+  if ( !ok1 ) {
+    qDebug("Malformed end address");
+    return true;
+  }
+  starts.clear();
+  for (int i=1; i<regexp.numCaptures(); i++) {
+    if ( regexp.cap(i).isEmpty() ) break;
+    bool ok1;
+    QString s = (i==1 ? regexp.cap(i) : regexp.cap(i).mid(1));
+    Address start = fromHex(s, &ok1);
+    if ( !ok1 ) {
+      qDebug("Malformed start address %s", s.latin1());
+      return true;
+    }
+    if ( start>=end && (starts.count()==0 || starts[starts.count()-1]<start) ) {
+      qDebug("Start addresses should be ordered");
+      return true;
+    }
+    starts.append(start);
+  }
+  ok = true;
+  return true;
+}
+
+AddressRangeVector Pic::Protection::extractRanges(const QString &name, MemoryRangeType type) const
+{
+  if ( isNoneProtectedValueName(name) ) return AddressRange();
+  if ( isAllProtectedValueName(name) ) {
+    const MemoryRangeData &rdata = _data.range(type);
+    return AddressRange(rdata.start, rdata.end);
+  }
+  bool ok1;
+  QValueVector<Address> starts;
+  Address end;
+  bool ok2 = extractRanges(name, starts, end, ok1);
+  Q_ASSERT(ok1);
+  Q_ASSERT(ok2);
+  Q_UNUSED(ok2);
+  AddressRangeVector rv;
+  for (uint i=0; i<uint(starts.count()); i++) rv.append(AddressRange(starts[i], end));
+  return rv;
+}
+
+bool Pic::Protection::checkRange(const QString &mask, const QString &name) const
+{
+  if ( family()!=CodeGuard ) {
+    bool ok;
+    (void)extractRange(mask, name, ok);
+    return ok;
+  }
+
+  bool isBootBlock = false;
+  int block = 0;
+  Type ptype = Nb_Types;
+  for (uint i=0; i<3; i++) {
+    isBootBlock = ( i==0 );
+    block = i - 1;
+    for (uint k=0; k<Nb_Types; k++) {
+      QString mname = (isBootBlock ? bootMaskName(Type(k)) : blockMaskName(Type(k), block));
+      if ( mask!=mname ) continue;
+      ptype = Type(k);
+      break;
+    }
+    if ( ptype!=Nb_Types ) break;
+  }
+  if ( ptype==Nb_Types ) {
+    qDebug("Unknown protected memory range");
+    return false;
+  }
+  // #### TODO
+  return true;
+}
+
+Pic::Protection::ProtectedRange Pic::Protection::extractRange(const QString &mask, const QString &name, bool &ok) const
+{
+  Q_ASSERT( family()!=CodeGuard );
+  //qDebug("extract range %s %s", mask.latin1(), name.latin1());
+  ProtectedRange pr;
+  ok = false;
+
+  QRegExp rexp("([A-Z]+)(?:_([0-9])|)");
+  if ( !rexp.exactMatch(mask) ) {
+    qDebug("Malformed block range");
+    return pr;
+  }
+
+  bool isBootBlock = false;
+  MemoryRangeType rtype = MemoryRangeType::Nb_Types;
+  Type ptype = Nb_Types;
+
+  for (MemoryRangeType type; type<=MemoryRangeType::Nb_Types; ++type) { // #### danger: <=
+    isBootBlock = ( type==MemoryRangeType::Nb_Types );
+    for (uint k=0; k<Nb_Types; k++) {
+      QString mname = (isBootBlock ? bootMaskName(Type(k)) : maskName(Type(k), type));
+      if ( rexp.cap(1)!=mname ) continue;
+      rtype = (isBootBlock ? MemoryRangeType(MemoryRangeType::Code) : type);
+      ptype = Type(k);
+      if ( !rexp.cap(2).isEmpty() ) {
+        if ( isBootBlock || (rtype!=MemoryRangeType::Code && rtype!=MemoryRangeType::Eeprom) ) {
+          qDebug("Multiple blocks only for code and eeprom");
+          return pr;
+        }
+      }
+      break;
+    }
+    if ( rtype!=MemoryRangeType::Nb_Types ) break;
+  }
+  if ( rtype==MemoryRangeType::Nb_Types ) {
+    qDebug("Unknown protected memory range");
+    return pr;
+  }
+
+  if ( isNoneProtectedValueName(name) ) {
+    ok = true;
+    return pr;
+  }
+
+  const Config::Mask *bmask = _config.findMask(bootMaskName(ptype));
+  const Config::Mask *bsmask = _config.findMask(bootSizeMaskName());
+  const MemoryRangeData &rdata = _data.range(rtype);
+  if ( isAllProtectedValueName(name) ) {
+    if ( rtype==MemoryRangeType::Code && !isBootBlock && bmask ) {
+      qDebug("Protected range should be explicit with boot block");
+      return pr;
+    }
+    if (isBootBlock) {
+      if ( bsmask==0 ) {
+        qDebug("Protected range should be explicit when boot size not present");
+        return pr;
+      }
+      Address start = _data.range(MemoryRangeType::Code).start;
+      pr.starts.append(start);
+      for (uint k=0; k<uint(bsmask->values.count()); k++) {
+        bool ok1;
+        uint size = bsmask->values[k].name.toUInt(&ok1);
+        if ( !ok1 ) {
+          qDebug("Could not recognize boot size value");
+          return pr;
+        }
+        if ( size==0 ) {
+          qDebug("Boot size cannot be zero");
+          return pr;
+        }
+        Address end = 2 * size - 1; // instruction words
+        if ( pr.ends.count()!=0 && end==pr.ends[pr.ends.count()-1] ) continue;
+        pr.ends.append(end);
+        qHeapSort(pr.ends);
+      }
+    } else {
+      pr.starts.append(rdata.start);
+      pr.ends.append(rdata.end);
+    }
+    ok = true;
+    return pr;
+  }
+  if ( isBootBlock && bsmask ) {
+    qDebug("Protected range should not be explicit when boot size is present");
+    return pr;
+  }
+
+  // extract start and end
+  Address end;
+  bool ok1;
+  if ( !extractRanges(name, pr.starts, end, ok1) ) {
+    qDebug("Could not recognized explicit range");
+    return pr;
+  }
+  if ( !ok1 ) return pr;
+  if ( end>rdata.end ) {
+    qDebug("End is beyond memory range");
+    return pr;
+  }
+  if ( (rtype!=MemoryRangeType::Code || isBootBlock) && (pr.starts.count()>1 || !rexp.cap(2).isEmpty() || bmask==0)  ) {
+    qDebug("Only code with blocks and boot can have multiple protected ranges");
+    return pr;
+  }
+  if ( isBootBlock && pr.starts[0]!=0 ) {
+    qDebug("Boot block start should be zero");
+    return pr;
+  }
+  pr.ends.append(end);
+
+  // check with boot block
+  if ( pr.starts.count()>1 ) {
+    if ( bmask==0 ) {
+      qDebug("No boot mask");
+      return pr;
+    }
+    for (uint i=0; i<uint(bmask->values.count()); i++) {
+      if ( bmask->values[i].name=="Off" ) continue;
+      bool ok1;
+      ProtectedRange bpr = extractRange(bmask->name, bmask->values[i].name, ok1);
+      if ( !ok1 ) return pr;
+      if ( bpr.ends.count()!=pr.starts.count() ) {
+        qDebug("Boot number of ends (%i) should be the same as code number of starts (%i)", int(bpr.ends.count()), int(pr.starts.count()));
+        return pr;
+      }
+      for (uint k=0; k<uint(bpr.ends.count()); k++) {
+        if ( bpr.ends[k]+1!=pr.starts[k] ) {
+          qDebug("%i: End of boot block (%s) doesn't match start of code block (%s)", k, toHexLabelAbs(bpr.ends[k]).latin1(), toHexLabelAbs(pr.starts[k]).latin1());
+          return pr;
+        }
+      }
+    }
+  }
+
+  ok = true;
+  return pr;
+}
+
+bool Pic::Protection::hasBootBlock() const
+{
+  return ( _config.findMask("CPB") || _config.findMask(bootSizeMaskName()) );
+}
+
+uint Pic::Protection::nbBlocks() const
+{
+  if ( family()==CodeGuard ) return 2; // codeguard : secure segment + general segment
+  for (uint i=0; i<MAX_NB_BLOCKS; i++)
+    if ( _config.findMask(QString("CP_%1").arg(i))==0 ) return i;
+  return MAX_NB_BLOCKS;
+}
+
+QString Pic::Protection::bootLabel() const
+{
+  if ( family()==CodeGuard ) return i18n("Boot Segment");
+  return i18n("Boot Block");
+}
+
+QString Pic::Protection::blockLabel(uint i) const
+{
+  if ( family()==CodeGuard ) {
+    if ( i==0 ) return i18n("Secure Segment");
+    return i18n("General Segment");
+  }
+  return i18n("Block #%1").arg(i);
+}
diff --git a/src/devices/pic/base/pic_protection.h b/src/devices/pic/base/pic_protection.h
new file mode 100644
index 0000000..67ff667
--- /dev/null
+++ b/src/devices/pic/base/pic_protection.h
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_PROTECTION_H
+#define PIC_PROTECTION_H
+
+#include "pic.h"
+
+namespace Pic
+{
+class Data;
+
+//----------------------------------------------------------------------------
+class Protection
+{
+public:
+  enum { MAX_NB_BLOCKS = 8 };
+  enum Family { NoProtection = 0, BasicProtection, BlockProtection, CodeGuard, Nb_Families };
+  enum Type { ProgramProtected = 0, WriteProtected, ReadProtected,
+              StandardSecurity, HighSecurity, Nb_Types };
+
+public:
+  Protection(const Pic::Data &data, const Config &config) : _data(data), _config(config) {}
+  Family family() const;
+  QString securityValueName(Type type) const;
+  bool hasBootBlock() const;
+  QString bootSizeMaskName() const;
+  QString bootMaskName(Type ptype) const;
+  QString bootLabel() const;
+  uint nbBlocks() const;
+  QString blockSizeMaskName(uint i) const;
+  QString blockMaskName(Type ptype, uint i) const;
+  QString blockLabel(uint i) const;
+  AddressRangeVector extractRanges(const QString &name, MemoryRangeType type) const;
+  bool checkRange(const QString &mask, const QString &name) const;
+  QString maskName(Type type, MemoryRangeType mtype) const;
+  bool isAllProtectedValueName(const QString &valueName) const;
+  bool isNoneProtectedValueName(const QString &valueName) const;
+
+private:
+  const Pic::Data &_data;
+  const Config    &_config;
+
+  enum SegmentType { BootSegment = 0, SecureSegment, GeneralSegment, Nb_SegmentTypes };
+  static bool extractRanges(const QString &name, QValueVector<Address> &starts, Address &end, bool &ok);
+  class ProtectedRange {
+  public:
+    QValueVector<Address> starts, ends;
+  };
+  ProtectedRange extractRange(const QString &mask, const QString &name, bool &ok) const;
+};
+
+} //namespace
+
+#endif
diff --git a/src/devices/pic/base/pic_register.cpp b/src/devices/pic/base/pic_register.cpp
new file mode 100644
index 0000000..fcfe5ef
--- /dev/null
+++ b/src/devices/pic/base/pic_register.cpp
@@ -0,0 +1,287 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_register.h"
+
+#include "pic.h"
+
+//-----------------------------------------------------------------------------
+Pic::RegistersData::RegistersData(const Data &data)
+  : nbBanks(0), accessBankSplit(0), _data(data)
+{}
+
+Address Pic::RegistersData::mirroredAddress(Address address) const
+{
+  Address mirror = address;
+  for (uint i=0; i<uint(mirrored.count()); i++) {
+    int delta = -1;
+    for (uint k=0; k<uint(mirrored[i].count()); k++) {
+      if ( address<mirrored[i][k].start
+           || address>=mirrored[i][k].start+mirrored[i][k].length ) continue;
+      delta = address - mirrored[i][k].start;
+      break;
+    }
+    if ( delta==-1 ) continue;
+    for (uint k=0; k<uint(mirrored[i].count()); k++)
+      mirror = QMIN(mirrored[i][k].start + delta, mirror);
+    break;
+  }
+  return mirror;
+}
+
+Device::RegisterProperties Pic::RegistersData::properties(Address address) const
+{
+  switch ( type(address) ) {
+    case Mirrored:
+    case UnusedRegister: return Device::NotAccessible;
+    case Gpr: return (Device::Readable | Device::Writable);
+    case Sfr: {
+      Device::RegisterProperties properties = Device::NotAccessible;
+      RegisterBitProperties rbp = RegisterBitUnused;
+      QMap<QString, RegisterData>::const_iterator it;
+      for (it=sfrs.begin(); it!=sfrs.end(); ++it) {
+        if ( it.data().address!=address ) continue;
+        for (uint i=0; i<Device::MAX_NB_PORT_BITS; i++) rbp |= it.data().bits[i].properties;
+        if ( rbp & RegisterBitRead ) properties |= Device::Readable;
+        if ( rbp & RegisterBitWrite ) properties |= Device::Writable;
+        break;
+      }
+      return properties;
+    }
+  }
+  Q_ASSERT(false);
+  return Device::NotAccessible;
+}
+
+Pic::RegisterType Pic::RegistersData::type(Address address) const
+{
+  for (uint i=0; i<uint(unused.count()); i++)
+    if ( address>=unused[i].start && address<unused[i].start+unused[i].length ) return UnusedRegister;
+  if ( !sfrNames[address].isEmpty() ) return Sfr;
+  Address mirror = mirroredAddress(address);
+  if ( !sfrNames[mirror].isEmpty() ) return Mirrored;
+  if ( address==mirror ) return Gpr;
+  return Mirrored;
+}
+
+QString Pic::RegistersData::label(Address address) const
+{
+  switch ( type(address) ) {
+    case UnusedRegister: return "---";
+    case Mirrored: return i18n("Mirror of %1").arg(toHexLabel(mirroredAddress(address), nbCharsAddress()));
+    case Gpr: return "<GPR>";
+    case Sfr: return sfrNames[address];
+  }
+  Q_ASSERT(false);
+  return QString::null;
+}
+
+bool Pic::RegistersData::hasPort(uint index) const
+{
+  Q_ASSERT( index<Device::MAX_NB_PORTS );
+  if ( sfrs.contains("GPIO") ) return ( index==0 );
+  if ( !sfrs.contains(portName(index)) ) return false;
+  return true;
+}
+
+int Pic::RegistersData::portIndex(Address address) const
+{
+  QString name = sfrNames[address];
+  if ( name.isEmpty() ) return -1;
+  for (uint i=0; i<Device::MAX_NB_PORTS; i++) {
+    if ( !hasPort(i) ) continue;
+    if ( name==portName(i) || name==trisName(i) || name==latchName(i) ) return i;
+  }
+  return -1;
+}
+
+bool Pic::RegistersData::hasPortBit(uint index, uint bit) const
+{
+  if ( !hasPort(index) ) return false;
+  const RegisterData &port = sfrs[portName(index)];
+  return ( port.bits[bit].properties!=RegisterBitUnused );
+}
+
+QString Pic::RegistersData::portName(uint index) const
+{
+  if ( sfrs.contains("GPIO") ) {
+    if ( index!=0 ) return QString::null;
+    return "GPIO";
+  }
+  return QString("PORT") + char('A' + index);
+}
+
+QString Pic::RegistersData::trisName(uint index) const
+{
+  if ( sfrs.contains("GPIO") ) {
+    if ( index!=0 ) return QString::null;
+    return "TRISIO";
+  }
+  if ( _data.architecture()==Architecture::P17C ) {
+    if ( index==0 ) return QString::null;
+    return QString("DDR") + char('A' + index);
+  }
+  return QString("TRIS") + char('A' + index);
+}
+
+bool Pic::RegistersData::hasTris(uint index) const
+{
+  QString name = trisName(index);
+  if ( name.isEmpty() ) return false;
+  return sfrs.contains(name);
+}
+
+QString Pic::RegistersData::latchName(uint index) const
+{
+  if ( _data.architecture()==Architecture::P10X || _data.architecture()==Architecture::P16X || _data.architecture()==Architecture::P17C )
+    return QString::null;
+  return QString("LAT") + char('A' + index);
+}
+
+bool Pic::RegistersData::hasLatch(uint index) const
+{
+  QString name = latchName(index);
+  if ( name.isEmpty() ) return false;
+  return sfrs.contains(name);
+}
+
+QString Pic::RegistersData::portBitName(uint index, uint bit) const
+{
+  if ( sfrs.contains("GPIO") ) return QString("GP") + QString::number(bit);
+  return QString("R") + char('A' + index) + QString::number(bit);
+}
+
+QValueList<Register::TypeData> Pic::RegistersData::relatedRegisters(const Register::TypeData &data) const
+{
+  QValueList<Register::TypeData> list;
+  if ( data.type()==Register::Regular ) {
+    int i = portIndex(data.address());
+    if ( i==-1 ) list.append(data);
+    else {
+      list.append(Register::TypeData(sfrs[portName(i)].address, nbChars()));
+      if ( hasTris(i) ) list.append(Register::TypeData(sfrs[trisName(i)].address, nbChars()));
+      if ( hasLatch(i) ) list.append(Register::TypeData(sfrs[latchName(i)].address, nbChars()));
+    }
+  } else if ( data.type()==Register::Combined ) {
+    uint nb = nbBitsToNbBytes(4*data.nbChars()) / nbBytes();
+    for (uint i=0; i<nb; i++) list.append(Register::TypeData(data.address() + i*nbBytes(), nbChars()));
+  } else list.append(data);
+  return list;
+}
+
+bool Pic::RegistersData::isBankUsed(uint i) const
+{
+  Q_ASSERT( i<nbBanks );
+  return !(unusedBankMask & (1 << i));
+}
+
+bool Pic::RegistersData::bankHasSfrs(uint i) const
+{
+  if ( i==0 ) return true;
+  if ( (_data.architecture()==Pic::Architecture::P18F || _data.architecture()==Pic::Architecture::P18J) && i==15 ) return true;
+  if ( !isBankUsed(i) ) return false;
+  QMap<Address, QString>::const_iterator it;
+  for (it=sfrNames.begin(); it!=sfrNames.end(); ++it)
+    if ( bankFromAddress(it.key())==i ) return true;
+  return false;
+}
+
+bool Pic::RegistersData::hasSharedGprs(uint &firstIndex, bool &all) const
+{
+  bool ok = false;
+  all = true;
+  for (uint i=0; i<nbRegistersPerBank(); i++) {
+    Address address = addressFromIndex(i);
+    if ( type(address)!=Gpr ) continue;
+    uint k = 1;
+    for (; k<nbBanks; k++) {
+      RegisterType t = type(address + k*nbBytesPerBank());
+      if ( t!=Mirrored ) break;
+    }
+    if ( k==nbBanks ) {
+      if ( !ok ) firstIndex = i;
+      ok = true;
+    } else all = false;
+  }
+  return ok;
+}
+
+uint Pic::RegistersData::firstGprIndex() const
+{
+  for (uint i=0; i<nbRegistersPerBank(); i++)
+    if ( type(addressFromIndex(i))==Gpr ) return i;
+  Q_ASSERT(false);
+  return 0;
+}
+
+//----------------------------------------------------------------------------
+QDataStream &Pic::operator <<(QDataStream &s, const RangeData &rd)
+{
+  s << rd.start << rd.length;
+  return s;
+}
+QDataStream &Pic::operator >>(QDataStream &s, RangeData &rd)
+{
+  s >> rd.start >> rd.length;
+  return s;
+}
+
+QDataStream &Pic::operator <<(QDataStream &s, const RegisterBitData &rbd)
+{
+  s << Q_UINT8(rbd.properties) << Q_UINT8(rbd.por) << Q_UINT8(rbd.mclr);
+  return s;
+}
+QDataStream &Pic::operator >>(QDataStream &s, RegisterBitData &rbd)
+{
+  Q_UINT8 properties, por, mclr;
+  s >> properties >> por >> mclr;
+  rbd.properties = RegisterBitProperties(properties);
+  rbd.por = RegisterBitState(por);
+  rbd.mclr = RegisterBitState(mclr);
+  return s;
+}
+
+QDataStream &Pic::operator <<(QDataStream &s, const RegisterData &rd)
+{
+  s << rd.address;
+  for (int i=0; i<Device::MAX_NB_PORT_BITS; i++) s << rd.bits[i];
+  return s;
+}
+QDataStream &Pic::operator >>(QDataStream &s, RegisterData &rd)
+{
+  s >> rd.address;
+  for (int i=0; i<Device::MAX_NB_PORT_BITS; i++) s >> rd.bits[i];
+  return s;
+}
+
+QDataStream &Pic::operator <<(QDataStream &s, const CombinedData &rd)
+{
+  s << rd.address << rd.nbChars;
+  return s;
+}
+QDataStream &Pic::operator >>(QDataStream &s, CombinedData &rd)
+{
+  s >> rd.address >> rd.nbChars;
+  return s;
+}
+
+QDataStream &Pic::operator <<(QDataStream &s, const RegistersData &rd)
+{
+  s << rd.nbBanks << rd.accessBankSplit << rd.unusedBankMask;
+  s << rd.sfrs << rd.mirrored << rd.unused << rd.combined;
+  return s;
+}
+QDataStream &Pic::operator >>(QDataStream &s, RegistersData &rd)
+{
+  s >> rd.nbBanks >> rd.accessBankSplit >> rd.unusedBankMask;
+  s >> rd.sfrs >> rd.mirrored >> rd.unused >> rd.combined;
+  rd.sfrNames.clear();
+  QMap<QString, RegisterData>::const_iterator it;
+  for(it=rd.sfrs.begin(); it!=rd.sfrs.end(); ++it) rd.sfrNames[it.data().address] = it.key();
+  return s;
+}
diff --git a/src/devices/pic/base/pic_register.h b/src/devices/pic/base/pic_register.h
new file mode 100644
index 0000000..41da020
--- /dev/null
+++ b/src/devices/pic/base/pic_register.h
@@ -0,0 +1,115 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_REGISTER_H
+#define PIC_REGISTER_H
+
+#include <qmap.h>
+
+#include "devices/base/register.h"
+#include "pic.h"
+
+namespace Pic
+{
+class Data;
+struct RangeData {
+  Address start;
+  uint length;
+};
+
+//-----------------------------------------------------------------------------
+enum RegisterType { UnusedRegister, Sfr, Gpr, Mirrored};
+enum RegisterBitProperty { RegisterBitUnused = 0x0,
+  RegisterBitRead = 0x1, RegisterBitWrite = 0x2,
+  RegisterBitOnlySoftwareClear = 0x4, RegisterBitOnlySoftwareSet = 0x8,
+  MaxRegisterBitProperty = 0x15
+};
+Q_DECLARE_FLAGS(RegisterBitProperties, RegisterBitProperty)
+Q_DECLARE_OPERATORS_FOR_FLAGS(RegisterBitProperties)
+enum RegisterBitState { RegisterBitUnknown = 0, RegisterBitLow, RegisterBitHigh,
+  RegisterBitUnchanged, RegisterBitDepends, RegisterBitDependsConfig, Nb_RegisterBitStates
+};
+
+//-----------------------------------------------------------------------------
+class RegisterBitData
+{
+public:
+  RegisterBitData() : properties(RegisterBitUnused) {}
+  RegisterBitProperties properties;
+  RegisterBitState por, mclr;
+};
+struct RegisterData
+{
+  Address address;
+  RegisterBitData bits[Device::MAX_NB_PORT_BITS];
+};
+struct CombinedData
+{
+  Address address;
+  uint    nbChars;
+};
+
+class RegistersData : public Device::RegistersData
+{
+public:
+  RegistersData(const Data &data);
+  virtual uint nbBits() const { return _data.architecture().data().nbBitsRegister; }
+  uint nbBytesPerBank() const { return _data.architecture().data().registerBankLength; }
+  uint nbRegistersPerBank() const { return nbBytesPerBank() / nbBytes(); }
+  uint nbCharsAddress() const { return ::nbChars(nbRegisters() - 1); }
+  virtual uint nbRegisters() const { return nbBanks * nbRegistersPerBank(); }
+  virtual uint addressFromIndex(uint i) const { return nbBytes() * i; }
+  virtual uint indexFromAddress(Address address) const { return address.toUInt() / nbBytes(); }
+  bool isBankUsed(uint i) const;
+  uint bankFromAddress(Address address) const { return indexFromAddress(address) / nbRegistersPerBank(); }
+  bool bankHasSfrs(uint i) const; // slow
+  bool hasSharedGprs(uint &firstIndex, bool &all) const; // i.e. mirrored in all banks (all is for first bank only)
+  uint firstGprIndex() const; // in first bank
+
+  uint nbBanks, accessBankSplit, unusedBankMask;
+  QMap<QString, RegisterData> sfrs;
+  QMap<Address, QString> sfrNames; // address -> name
+  QValueVector<QValueVector<RangeData> > mirrored;
+  QValueVector<RangeData> unused;
+  QMap<QString, CombinedData> combined;
+
+  virtual Device::RegisterProperties properties(Address address) const;
+  RegisterType type(Address address) const;
+  QString label(Address address) const;
+  virtual QValueList<Register::TypeData> relatedRegisters(const Register::TypeData &data) const;
+
+  virtual bool hasPort(uint index) const;
+  virtual int portIndex(Address address) const;
+  virtual QString portName(uint index) const;
+  bool hasTris(uint index) const;
+  QString trisName(uint index) const;
+  bool hasLatch(uint index) const;
+  QString latchName(uint index) const;
+  virtual bool hasPortBit(uint index, uint bit) const;
+  virtual QString portBitName(uint index, uint bit) const;
+
+private:
+  const Data &_data;
+  Address mirroredAddress(Address address) const;
+};
+
+//-----------------------------------------------------------------------------
+QDataStream &operator <<(QDataStream &s, const RangeData &rd);
+QDataStream &operator >>(QDataStream &s, RangeData &rd);
+QDataStream &operator <<(QDataStream &s, const RegisterBitData &rbd);
+QDataStream &operator >>(QDataStream &s, RegisterBitData &rbd);
+QDataStream &operator <<(QDataStream &s, const RegisterData &rd);
+QDataStream &operator >>(QDataStream &s, RegisterData &rd);
+QDataStream &operator <<(QDataStream &s, const CombinedData &rd);
+QDataStream &operator >>(QDataStream &s, CombinedData &rd);
+QDataStream &operator <<(QDataStream &s, const RegistersData &rd);
+QDataStream &operator >>(QDataStream &s, RegistersData &rd);
+
+} // namespace
+
+#endif
diff --git a/src/devices/pic/gui/Makefile.am b/src/devices/pic/gui/Makefile.am
new file mode 100644
index 0000000..72f3165
--- /dev/null
+++ b/src/devices/pic/gui/Makefile.am
@@ -0,0 +1,9 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+libpicui_la_LDFLAGS = $(all_libraries)
+noinst_LTLIBRARIES = libpicui.la
+
+
+libpicui_la_SOURCES = pic_config_editor.cpp \
+		pic_config_word_editor.cpp	pic_hex_view.cpp pic_memory_editor.cpp pic_register_view.cpp pic_group_ui.cpp \
+	pic_prog_group_ui.cpp
diff --git a/src/devices/pic/gui/pic_config_editor.cpp b/src/devices/pic/gui/pic_config_editor.cpp
new file mode 100644
index 0000000..1812bbf
--- /dev/null
+++ b/src/devices/pic/gui/pic_config_editor.cpp
@@ -0,0 +1,68 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_config_editor.h"
+
+#include <qlayout.h>
+#include <qvgroupbox.h>
+#include <qapplication.h>
+
+#include "pic_config_word_editor.h"
+#include "common/common/misc.h"
+#include "common/gui/misc_gui.h"
+
+//----------------------------------------------------------------------------
+Pic::MemoryConfigEditorWidget::MemoryConfigEditorWidget(Memory &memory, bool withWordEditor, QWidget *parent)
+  : Device::MemoryEditorGroup(&memory, parent, "pic_config_editor_widget"),
+    MemoryCaster(MemoryRangeType::Config, memory)
+{
+  QHBoxLayout *hb = new QHBoxLayout(_top);
+
+  TabWidget *tabw = 0;
+  uint nbWords = device().nbWords(MemoryRangeType::Config);
+  if ( nbWords>1 ) {
+    tabw = new TabWidget(this);
+    tabw->setIgnoreWheelEvent(true);
+    hb->addWidget(tabw);
+  }
+
+  for(uint i=0; i<nbWords; ++i) {
+    //qDebug("BinWordsEditor for config word #%i", i);
+    //uint address = device().range(Device::MemoryConfig).start + device().addressIncrement(Device::MemoryConfig) * i;
+    //qDebug("address: %s %s nb: %i", toHex(address, 8).data(), device().configWord(i).name.latin1(), device().configWord(i).masks.count());
+    if ( device().config()._words[i].masks.count()==0 ) continue;
+    QWidget *page = 0;
+    if ( nbWords>1 ) {
+      page = new QWidget(tabw);
+      tabw->addTab(page, device().config()._words[i].name);
+    } else {
+      page = new QGroupBox(this);
+      hb->addWidget(page);
+    }
+    QVBoxLayout *vbox = new QVBoxLayout(page, 10, 10);
+    QHBoxLayout *hbox = new QHBoxLayout(vbox);
+    ConfigWordEditor *we = new ConfigWordEditor(memory, i, withWordEditor, page);
+    addEditor(we);
+    hbox->addWidget(we);
+    hbox->addStretch(1);
+    vbox->addStretch(1);
+  }
+}
+
+//----------------------------------------------------------------------------
+Pic::MemoryConfigEditor::MemoryConfigEditor(const HexView *hexview, Memory &memory, QWidget *parent)
+  : MemoryTypeEditor(hexview, MemoryRangeType::Config, memory, parent, "pic_config_editor")
+{}
+
+void Pic::MemoryConfigEditor::init(bool first)
+{
+  MemoryTypeEditor::init(first);
+  MemoryConfigEditorWidget *w = new MemoryConfigEditorWidget(memory(), true, this);
+  addEditor(w);
+  _top->addWidget(w);
+}
diff --git a/src/devices/pic/gui/pic_config_editor.h b/src/devices/pic/gui/pic_config_editor.h
new file mode 100644
index 0000000..888debf
--- /dev/null
+++ b/src/devices/pic/gui/pic_config_editor.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_CONFIG_EDITOR_H
+#define PIC_CONFIG_EDITOR_H
+
+#include "pic_memory_editor.h"
+
+//----------------------------------------------------------------------------
+namespace Pic
+{
+class HexView;
+
+class MemoryConfigEditorWidget : public Device::MemoryEditorGroup, public MemoryCaster
+{
+Q_OBJECT
+public:
+  MemoryConfigEditorWidget(Memory &memory, bool withWordEditor, QWidget *parent);
+};
+
+//----------------------------------------------------------------------------
+class MemoryConfigEditor : public MemoryTypeEditor
+{
+Q_OBJECT
+public:
+  MemoryConfigEditor(const HexView *hexview, Memory &memory, QWidget *parent);
+  virtual void init(bool first);
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/pic/gui/pic_config_word_editor.cpp b/src/devices/pic/gui/pic_config_word_editor.cpp
new file mode 100644
index 0000000..23e4bce
--- /dev/null
+++ b/src/devices/pic/gui/pic_config_word_editor.cpp
@@ -0,0 +1,196 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *   Copyright (C) 2003-2004 Alain Gibaud <alain.gibaud@free.fr>           *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_config_word_editor.h"
+
+#include <qlabel.h>
+#include <qlayout.h>
+#include <qcombobox.h>
+#include <klocale.h>
+
+#include "common/common/misc.h"
+#include "common/gui/misc_gui.h"
+
+//----------------------------------------------------------------------------
+Pic::ConfigWordComboBox::ConfigWordComboBox(QWidget *parent)
+  : ComboBox(parent)
+{
+  setIgnoreWheelEvent(true);
+}
+
+uint Pic::ConfigWordComboBox::index() const
+{
+  if ( isValid() ) return _map[currentItem()];
+  if ( currentItem()==0 ) return _invalidIndex;
+  return _map[currentItem()-1];
+}
+
+void Pic::ConfigWordComboBox::setItem(uint i)
+{
+  if ( !isValid() ) removeItem(0);
+  for (uint l=0; l<_map.count(); l++)
+    if ( _map[l]==i ) setCurrentItem(l);
+}
+
+void Pic::ConfigWordComboBox::setInvalidItem(uint i, const QString &label)
+{
+  if ( !isValid() ) changeItem(label, 0);
+  else insertItem(label, 0);
+  setCurrentItem(0);
+  _invalidIndex = i;
+}
+
+//----------------------------------------------------------------------------
+Pic::ConfigWordDialog::ConfigWordDialog(const Memory &memory, uint ci, QWidget *parent)
+  : Dialog(parent, "config_word_dialog", true, i18n("Config Word Details"), Close, Close, false)
+{
+  uint nbChars = memory.device().nbCharsWord(MemoryRangeType::Config);
+  const Config::Word &cword = memory.device().config()._words[ci];
+
+  QGridLayout *grid = new QGridLayout(mainWidget(), 0, 0, 10, 10);
+  uint row = 0;
+  QLabel *label = new QLabel(i18n("Name:"), mainWidget());
+  grid->addWidget(label, row, 0);
+  label = new QLabel(cword.name, mainWidget());
+  grid->addWidget(label, row, 1);
+  row++;
+  label = new QLabel(i18n("Index:"), mainWidget());
+  grid->addWidget(label, row, 0);
+  label = new QLabel(QString::number(ci), mainWidget());
+  grid->addWidget(label, row, 1);
+  row++;
+  label = new QLabel(i18n("Raw Value:"), mainWidget());
+  grid->addWidget(label, row, 0);
+  label = new QLabel(toHexLabel(memory.word(MemoryRangeType::Config, ci), nbChars), mainWidget());
+  grid->addWidget(label, row, 1);
+  row++;
+  label = new QLabel(i18n("Value:"), mainWidget());
+  grid->addWidget(label, row, 0);
+  label = new QLabel(toHexLabel(memory.normalizedWord(MemoryRangeType::Config, ci), nbChars), mainWidget());
+  grid->addWidget(label, row, 1);
+  row++;
+  label = new QLabel(i18n("Raw Blank Value:"), mainWidget());
+  grid->addWidget(label, row, 0);
+  label = new QLabel(toHexLabel(cword.bvalue, nbChars), mainWidget());
+  grid->addWidget(label, row, 1);
+  row++;
+  label = new QLabel(i18n("Used Mask:"), mainWidget());
+  grid->addWidget(label, row, 0);
+  label = new QLabel(toHexLabel(cword.usedMask(), nbChars), mainWidget());
+  grid->addWidget(label, row, 1);
+  row++;
+  label = new QLabel(i18n("Write Mask:"), mainWidget());
+  grid->addWidget(label, row, 0);
+  label = new QLabel(toHexLabel(cword.wmask, nbChars), mainWidget());
+  grid->addWidget(label, row, 1);
+  row++;
+  label = new QLabel(i18n("Protected Mask:"), mainWidget());
+  grid->addWidget(label, row, 0);
+  label = new QLabel(toHexLabel(cword.pmask, nbChars), mainWidget());
+  grid->addWidget(label, row, 1);
+  row++;
+  label = new QLabel(i18n("Checksum Mask:"), mainWidget());
+  grid->addWidget(label, row, 0);
+  label = new QLabel(toHexLabel(cword.cmask, nbChars), mainWidget());
+  grid->addWidget(label, row, 1);
+  row++;
+}
+
+//----------------------------------------------------------------------------
+Pic::ConfigWordEditor::ConfigWordEditor(Memory &memory, uint ci, bool withWordEditor, QWidget *parent)
+  : MemoryEditor(MemoryRangeType::Config, memory, parent, "pic_config_word_editor"), _configIndex(ci)
+{
+  if (withWordEditor) {
+    QHBoxLayout *hbox = new QHBoxLayout(_top);
+    _mdb = new MemoryRangeEditor(MemoryRangeType::Config, memory, 1, 1, ci, 1, this);
+    _mdb->init();
+    connect(_mdb, SIGNAL(modified()), SIGNAL(modified()));
+    connect(_mdb, SIGNAL(modified()), SLOT(updateDisplay()));
+    hbox->addWidget(_mdb);
+    KPushButton *button = new KPushButton(i18n("Details..."), this);
+    button->setFixedHeight(button->sizeHint().height());
+    connect(button, SIGNAL(clicked()), SLOT(showDialog()));
+    hbox->addWidget(button);
+    hbox->addStretch(1);
+  } else _mdb = 0;
+
+  QGridLayout *grid = new QGridLayout(_top);
+  grid->setColStretch(2, 1);
+  const Config::Word &cword = device().config()._words[ci];
+  _combos.resize(cword.masks.count());
+  uint nbChars = device().nbCharsWord(MemoryRangeType::Config);
+  for (uint k=0; k<_combos.count(); k++) {
+    const Config::Mask &cmask = cword.masks[k];
+    QLabel *label = new QLabel(Config::maskLabel(cmask.name) + ":", this);
+    grid->addWidget(label, k, 0);
+    label = new QLabel(cmask.name, this);
+    grid->addWidget(label, k, 1);
+    _combos[k] = new ConfigWordComboBox(this);
+    for (uint i=0; i<cmask.values.count(); i++) {
+      if ( !cmask.values[i].isValid() ) continue;
+      QString label = Config::valueLabel(cmask.name, cmask.values[i].name);
+      label += " (" + toHexLabel(cmask.values[i].value, nbChars) + ")";
+      _combos[k]->appendItem(label, i);
+    }
+    connect(_combos[k], SIGNAL(activated(int)), SLOT(slotModified()));
+    grid->addWidget(_combos[k], k, 2);
+  }
+}
+
+void Pic::ConfigWordEditor::setReadOnly(bool readOnly)
+{
+  if (_mdb) _mdb->setReadOnly(readOnly);
+  const Config::Word &cword = device().config()._words[_configIndex];
+  for (uint k=0; k<_combos.count(); k++) {
+    const Config::Mask &cmask = cword.masks[k];
+    _combos[k]->setEnabled(!readOnly && !cmask.value.isOverlapping(cword.pmask) && cmask.values.count()!=1);
+  }
+}
+
+void Pic::ConfigWordEditor::slotModified()
+{
+  BitValue v = memory().word(MemoryRangeType::Config, _configIndex);
+  //qDebug("BinWordEditor::slotModified %i: %s", _configIndex, toHex(v, 4).data());
+  for (uint k=0; k<_combos.count(); k++) {
+    const Config::Mask &cmask = device().config()._words[_configIndex].masks[k];
+    v = v.clearMaskBits(cmask.value);
+    v |= cmask.values[_combos[k]->index()].value; // set value
+  }
+  memory().setWord(MemoryRangeType::Config, _configIndex, v);
+  //qDebug("  now: %s", toHex(v, 4).data());
+  if (_mdb) _mdb->updateDisplay();
+  emit modified();
+}
+
+void Pic::ConfigWordEditor::updateDisplay()
+{
+  BitValue v = memory().word(MemoryRangeType::Config, _configIndex);
+  uint nbChars = device().nbCharsWord(MemoryRangeType::Config);
+  //qDebug("BinWordEditor::updateDisplay %i: %s", _configIndex, toHex(v, 4).data());
+  for (uint k=0; k<_combos.count(); k++) {
+    const Config::Mask &cmask = device().config()._words[_configIndex].masks[k];
+    for (int i=cmask.values.count()-1; i>=0; i--) {
+      if ( cmask.values[i].value.isInside(v) ) {
+        if ( cmask.values[i].isValid() ) _combos[k]->setItem(i);
+        else {
+          QString label = i18n("<invalid>") + " (" + toHexLabel(cmask.values[i].value, nbChars) + ")";
+          _combos[k]->setInvalidItem(i, label);
+        }
+        break;
+      }
+    }
+  }
+  if (_mdb) _mdb->updateDisplay();
+}
+
+void Pic::ConfigWordEditor::showDialog()
+{
+  ConfigWordDialog dialog(memory(), _configIndex, this);
+  dialog.exec();
+}
diff --git a/src/devices/pic/gui/pic_config_word_editor.h b/src/devices/pic/gui/pic_config_word_editor.h
new file mode 100644
index 0000000..8f483c7
--- /dev/null
+++ b/src/devices/pic/gui/pic_config_word_editor.h
@@ -0,0 +1,70 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *   Copyright (C) 2003-2004 Alain Gibaud <alain.gibaud@free.fr>           *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_CONFIG_WORD_EDITOR_H
+#define PIC_CONFIG_WORD_EDITOR_H
+
+#include <qcombobox.h>
+
+#include "common/gui/dialog.h"
+#include "common/gui/misc_gui.h"
+#include "pic_memory_editor.h"
+
+namespace Pic
+{
+//----------------------------------------------------------------------------
+class ConfigWordDialog : public Dialog
+{
+Q_OBJECT
+public:
+  ConfigWordDialog(const Memory &memory, uint index, QWidget *parent);
+};
+
+//----------------------------------------------------------------------------
+class ConfigWordComboBox : public ComboBox
+{
+Q_OBJECT
+public:
+  ConfigWordComboBox(QWidget *parent);
+  void appendItem(const QString &text, uint index) { insertItem(text); _map.append(index); }
+  uint index() const;
+  void setItem(uint index);
+  void setInvalidItem(uint index, const QString &label);
+
+private:
+  QValueVector<uint> _map; // item index -> value index
+  uint _invalidIndex; // if invalid -> value index
+
+  bool isValid() const { return uint(count())==_map.count(); }
+};
+
+//----------------------------------------------------------------------------
+class ConfigWordEditor : public MemoryEditor
+{
+Q_OBJECT
+public:
+  ConfigWordEditor(Memory &memory, uint index, bool withWordEditor, QWidget *parent);
+  virtual void setReadOnly(bool readOnly);
+
+public slots:
+  virtual void updateDisplay();
+
+private slots:
+  void slotModified();
+  void showDialog();
+
+private:
+  uint _configIndex;
+  MemoryRangeEditor *_mdb;
+  QValueVector<ConfigWordComboBox *> _combos;
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/pic/gui/pic_group_ui.cpp b/src/devices/pic/gui/pic_group_ui.cpp
new file mode 100644
index 0000000..3f7a84c
--- /dev/null
+++ b/src/devices/pic/gui/pic_group_ui.cpp
@@ -0,0 +1,87 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_group_ui.h"
+
+#include <kaction.h>
+
+#include "libgui/main_global.h"
+#include "pic_hex_view.h"
+#include "pic_register_view.h"
+#include "pic_config_editor.h"
+#include "coff/base/text_coff.h"
+#include "libgui/gui_debug_manager.h"
+#include "common/gui/list_container.h"
+
+Device::HexView *Pic::GroupUI::createHexView(const HexEditor &editor, QWidget *parent) const
+{
+  return new HexView(editor, parent);
+}
+
+Register::View *Pic::GroupUI::createRegisterView(QWidget *parent) const
+{
+  return new RegisterView(parent);
+}
+
+Device::MemoryEditor *Pic::GroupUI::createConfigEditor(Device::Memory &memory, QWidget *parent) const
+{
+  return new MemoryConfigEditorWidget(static_cast<Memory &>(memory), false, parent);
+}
+
+void Pic::GroupUI::fillWatchListContainer(ListContainer *container, QValueVector<Register::TypeData> &ids) const
+{
+  ids.clear();
+  const Pic::Data &data = static_cast<const Pic::Data &>(*Main::deviceData());
+  const Pic::RegistersData &rdata = data.registersData();
+  ListContainer *branch = container->appendBranch(i18n("SFRs"));
+  QValueVector<Pic::RegisterNameData> list = Pic::sfrList(data);
+  for (uint i=0; i<list.count(); i++) {
+    branch->appendItem(list[i].label(), ids.count(), ListContainer::UnChecked);
+    ids.append(list[i].data());
+  }
+  branch = container->appendBranch(i18n("I/Os"));
+  for (uint i=0; i<Device::MAX_NB_PORTS; i++) {
+    if ( !rdata.hasPort(i) ) continue;
+    QString name = rdata.portName(i);
+    branch->appendItem(name, ids.count(), ListContainer::UnChecked);
+    ids.append(Register::TypeData(rdata.sfrs[name].address, rdata.nbChars()));
+  }
+  branch = container->appendBranch(i18n("GPRs"));
+  const Coff::Object *coff = Debugger::manager->coff();
+  list = Pic::gprList(data, coff);
+  for (uint k=0; k<rdata.nbBanks; k++) {
+    if ( !rdata.isBankUsed(k) ) continue;
+    ListContainer *bbranch = (rdata.nbBanks==1 ? branch : branch->appendBranch(i18n("Bank %1").arg(k)));
+    uint nb = 0;
+    for (uint i=0; i<list.count(); i++) {
+      if ( rdata.bankFromAddress(list[i].data().address())!=k ) continue;
+      bbranch->appendItem(list[i].label(), ids.count(), ListContainer::UnChecked);
+      ids.append(list[i].data());
+      nb++;
+    }
+  }
+  branch = container->appendBranch(i18n("Variables"));
+  if (coff) {
+    list = Pic::variableList(data, *coff);
+    if ( list.count()==0 ) {
+      branch->appendItem(i18n("No variable"), ids.count(), ListContainer::Disabled);
+      ids.append(Register::TypeData());
+    } else for (uint i=0; i<list.count(); i++) {
+      branch->appendItem(list[i].label(), ids.count(), ListContainer::UnChecked);
+      ids.append(list[i].data());
+    }
+  } else {
+    branch->appendItem(i18n("Please compile the current project"), ids.count(), ListContainer::Disabled);
+    ids.append(Register::TypeData());
+  }
+}
+
+Register::ListViewItem *Pic::GroupUI::createWatchItem(const Register::TypeData &data, KListViewItem *parent) const
+{
+  return new Pic::RegisterListViewItem(data, parent);
+}
diff --git a/src/devices/pic/gui/pic_group_ui.h b/src/devices/pic/gui/pic_group_ui.h
new file mode 100644
index 0000000..a8bee66
--- /dev/null
+++ b/src/devices/pic/gui/pic_group_ui.h
@@ -0,0 +1,29 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_GROUP_UI_H
+#define PIC_GROUP_UI_H
+
+#include "devices/gui/device_group_ui.h"
+
+namespace Pic
+{
+
+class GroupUI : public Device::GroupUI
+{
+public:
+  virtual Device::HexView *createHexView(const HexEditor &editor, QWidget *parent) const;
+  virtual Register::View *createRegisterView(QWidget *parent) const;
+  virtual Device::MemoryEditor *createConfigEditor(Device::Memory &memory, QWidget *parent) const;
+  virtual void fillWatchListContainer(ListContainer *container, QValueVector<Register::TypeData> &ids) const;
+  virtual Register::ListViewItem *createWatchItem(const Register::TypeData &data, KListViewItem *parent) const;
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/pic/gui/pic_hex_view.cpp b/src/devices/pic/gui/pic_hex_view.cpp
new file mode 100644
index 0000000..07a1938
--- /dev/null
+++ b/src/devices/pic/gui/pic_hex_view.cpp
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *   Copyright (C) 2003 Alain Gibaud <alain.gibaud@free.fr>                *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_hex_view.h"
+
+#include <qlayout.h>
+#include <qlabel.h>
+
+#include <klocale.h>
+
+#include "pic_memory_editor.h"
+#include "pic_config_editor.h"
+
+Pic::HexView::HexView(const HexEditor &editor, QWidget *parent)
+  : Device::HexView(editor, parent, "pic_hex_view")
+{}
+
+const Pic::MemoryRangeType::Type Pic::HexView::MEMORY_DATA[] = {
+  MemoryRangeType::Code, MemoryRangeType::Config, MemoryRangeType::Eeprom, MemoryRangeType::UserId,
+  MemoryRangeType::Cal, MemoryRangeType::Nb_Types
+};
+
+void Pic::HexView::display()
+{
+  bool first = true;
+  for (uint i=0; MEMORY_DATA[i]!=MemoryRangeType::Nb_Types; i++) {
+    Pic::MemoryRangeType type = MEMORY_DATA[i];
+    if ( !memory()->device().isReadable(type) ) continue;
+    Device::MemoryTypeEditor *e = 0;
+    switch (type.type()) {
+      case MemoryRangeType::Config: e = new MemoryConfigEditor(this, *memory(), this); break;
+      case MemoryRangeType::Cal:    e = new MemoryCalibrationEditor(this, *memory(), this); break;
+      case MemoryRangeType::Code:
+      case MemoryRangeType::Eeprom: e = new MemoryTypeRangeEditor(this, type, *memory(), this); break;
+      case MemoryRangeType::UserId: e = new MemoryUserIdEditor(this, *memory(), this); break;
+      case MemoryRangeType::DeviceId:
+      case MemoryRangeType::HardwareStack:
+      case MemoryRangeType::ProgramExecutive:
+      case MemoryRangeType::DebugVector:
+      case MemoryRangeType::CalBackup:
+      case MemoryRangeType::Nb_Types: Q_ASSERT(false); break;
+    }
+    e->init(first);
+    e->show();
+    _top->addWidget(e);
+    addEditor(e);
+    first = false;
+  }
+}
+
+BitValue Pic::HexView::checksum() const
+{
+  return (_memory ? memory()->checksum() : 0x0000);
+}
diff --git a/src/devices/pic/gui/pic_hex_view.h b/src/devices/pic/gui/pic_hex_view.h
new file mode 100644
index 0000000..2086ccb
--- /dev/null
+++ b/src/devices/pic/gui/pic_hex_view.h
@@ -0,0 +1,39 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *   Copyright (C) 2003 Alain Gibaud <alain.gibaud@free.fr>                *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_HEX_VIEW_H
+#define PIC_HEX_VIEW_H
+
+class QVBoxLayout;
+
+#include "devices/gui/hex_view.h"
+#include "devices/pic/pic/pic_memory.h"
+
+namespace Pic
+{
+
+class HexView : public Device::HexView
+{
+Q_OBJECT
+public:
+  HexView(const HexEditor &editor, QWidget *parent);
+  Memory *memory() { return static_cast<Memory *>(_memory); }
+  const Memory *memory() const { return static_cast<Memory *>(_memory); }
+  virtual uint nbChecksumChars() const { return 4; }
+  virtual BitValue checksum() const;
+
+private:
+  static const MemoryRangeType::Type MEMORY_DATA[];
+
+  virtual void display();
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/pic/gui/pic_memory_editor.cpp b/src/devices/pic/gui/pic_memory_editor.cpp
new file mode 100644
index 0000000..3d78097
--- /dev/null
+++ b/src/devices/pic/gui/pic_memory_editor.cpp
@@ -0,0 +1,404 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>             *
+ *   Copyright (C) 2003-2004 Alain Gibaud <alain.gibaud@free.fr>           *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_memory_editor.h"
+
+#include <qframe.h>
+#include <qgroupbox.h>
+#include <qlabel.h>
+#include <qscrollbar.h>
+#include <qgrid.h>
+#include <qhbox.h>
+#include <qtooltip.h>
+#include <qregexp.h>
+#include <qcolor.h>
+#include <qlayout.h>
+#include <qpixmap.h>
+
+#include <klocale.h>
+#include <kpushbutton.h>
+#include <kaction.h>
+
+#include "common/common/misc.h"
+#include "pic_config_editor.h"
+#include "libgui/toplevel.h"
+#include "libgui/main_global.h"
+#include "devices/pic/prog/pic_prog.h"
+#include "libgui/global_config.h"
+#include "pic_hex_view.h"
+
+//-----------------------------------------------------------------------------
+Pic::MemoryEditorLegend::Data::Data(const QString &text, QWidget *parent)
+{
+  button = new PopupButton(text, parent);
+  KActionCollection *ac = 0;
+  KAction *a = new KAction(i18n("Go to start"), "top", 0, parent, SLOT(gotoStart()), ac);
+  actions.append(a);
+  button->appendAction(a);
+  a = new KAction(i18n("Go to end"), "bottom", 0, parent, SLOT(gotoEnd()), ac);
+  actions.append(a);
+  button->appendAction(a);
+  label = new QLabel(parent);
+}
+
+void Pic::MemoryEditorLegend::Data::setProtected(bool on)
+{
+  if (on) label->setPaletteBackgroundColor(MemoryEditorLegend::protectedColor());
+  else label->unsetPalette();
+}
+
+bool Pic::MemoryEditorLegend::Data::hasAction(const KAction *action) const
+{
+  for (uint i=0; i<actions.count(); i++) if ( actions[i]==action ) return true;
+  return false;
+}
+
+//-----------------------------------------------------------------------------
+const char * const Pic::MemoryEditorLegend::BLOCK_COLORS[Protection::MAX_NB_BLOCKS] = {
+  "#88FF88", "#88FFFF", "#FFFF88", "#FF88FF", "#0088FF", "#88FF00", "#00FF88", "#FF8800"
+};
+
+Pic::MemoryEditorLegend::MemoryEditorLegend(MemoryRangeType type, Memory &memory, QWidget *parent)
+  : MemoryEditor(type, memory, parent, "memory_displayer_legend")
+{
+  QGridLayout *grid = new QGridLayout(_top);
+
+  QWidget *w = new QWidget(this);
+  w->setFixedWidth(20);
+  w->setPaletteBackgroundColor(protectedColor());
+  grid->addWidget(w, 0, 0);
+  const Protection &protection = device().config().protection();
+  QString s = (protection.family()==Protection::CodeGuard ? i18n("High Security") : i18n("Code protection"));
+  QLabel *label = new QLabel(s, this);
+  grid->addMultiCellWidget(label, 0,0, 1,2);
+  grid->addRowSpacing(1, 10);
+  uint row = 2;
+
+  if ( type==MemoryRangeType::Code && protection.hasBootBlock() ) {
+    w = new QWidget(this);
+    w->setFixedWidth(20);
+    w->setPaletteBackgroundColor(bootColor());
+    grid->addWidget(w, row, 0);
+    _boot = Data(protection.bootLabel(), this);
+    grid->addWidget(_boot.button, row, 1);
+    grid->addWidget(_boot.label, row, 2);
+    row++;
+  }
+
+  uint nb = (type==MemoryRangeType::Code ? protection.nbBlocks() : 0);
+  for (uint i=0; i<nb; i++) {
+    w = new QWidget(this);
+    w->setFixedWidth(20);
+    w->setPaletteBackgroundColor(blockColor(i));
+    grid->addWidget(w, row, 0);
+    _blocks.append(Data(protection.blockLabel(i), this));
+    grid->addWidget(_blocks[i].button, row, 1);
+    grid->addWidget(_blocks[i].label, row, 2);
+    row++;
+  }
+}
+
+void Pic::MemoryEditorLegend::updateDisplay()
+{
+  const Protection &protection = device().config().protection();
+  Protection::Type ptype = (protection.family()==Protection::CodeGuard ? Protection::HighSecurity : Protection::ProgramProtected);
+  uint nbChars = 2 * device().nbBytesAddress();
+  if (_boot.label) {
+    AddressRange r = memory().bootRange();
+    if ( r.isEmpty() ) _boot.label->setText(i18n("not present"));
+    else _boot.label->setText(QString("[%1:%2]").arg(toHex(r.start, nbChars)).arg(toHex(r.end, nbChars)));
+    _boot.button->setEnabled(!r.isEmpty());
+    _boot.setProtected(memory().isBootProtected(ptype));
+  }
+  for (uint i=0; i<_blocks.count(); i++) {
+    AddressRange r = memory().blockRange(i);
+    if ( r.isEmpty() ) _blocks[i].label->setText(i18n("not present"));
+    else _blocks[i].label->setText(QString("[%1:%2]").arg(toHex(r.start, nbChars)).arg(toHex(r.end, nbChars)));
+    _blocks[i].button->setEnabled(!r.isEmpty());
+    _blocks[i].setProtected(memory().isBlockProtected(ptype, i));
+  }
+}
+
+void Pic::MemoryEditorLegend::gotoStart()
+{
+  Address start = device().range(type()).start;
+  const KAction *action = static_cast<const KAction *>(sender());
+  if ( _boot.hasAction(action) ) {
+    AddressRange r = memory().bootRange();
+    emit setStartWord(r.start - start);
+    return;
+  }
+  for (uint i=0; i<_blocks.count(); i++) {
+    if ( _blocks[i].hasAction(action) ) {
+      AddressRange r = memory().blockRange(i);
+      emit setStartWord(r.start - start);
+      return;
+    }
+  }
+  Q_ASSERT(false);
+}
+
+void Pic::MemoryEditorLegend::gotoEnd()
+{
+  Address start = device().range(type()).start;
+  const KAction *action = static_cast<const KAction *>(sender());
+  if ( _boot.hasAction(action) ) {
+    AddressRange r = memory().bootRange();
+    emit setEndWord(r.end - start);
+    return;
+  }
+  for (uint i=0; i<_blocks.count(); i++) {
+    if ( _blocks[i].hasAction(action) ) {
+      AddressRange r = memory().blockRange(i);
+      emit setEndWord(r.end - start);
+      return;
+    }
+  }
+  Q_ASSERT(false);
+}
+
+
+//-----------------------------------------------------------------------------
+Pic::HexWordEditor::HexWordEditor(MemoryRangeType type, Memory &memory, QWidget *parent)
+  : Device::HexWordEditor(memory, memory.device().nbCharsWord(type), parent),
+    MemoryCaster(type, memory)
+{}
+
+void Pic::HexWordEditor::setWord(BitValue value)
+{
+  if ( type()==MemoryRangeType::Config ) {
+    const Config::Word &cword = device().config()._words[_offset];
+    value |= cword.usedMask().complementInMask(device().mask(MemoryRangeType::Config));
+  }
+  memory().setWord(type(), _offset, value);
+}
+
+//-----------------------------------------------------------------------------
+Pic::MemoryRangeEditor::MemoryRangeEditor(MemoryRangeType type, Memory &memory,
+                                          uint nbLines, uint nbCols,
+                                          uint wordOffset, int nbWords, QWidget *parent)
+  : Device::MemoryRangeEditor(memory, nbLines, nbCols, wordOffset, nbWords, parent, "pic_memory_range_editor"),
+    MemoryCaster(type, memory), _legend(0)
+{
+  if ( type==MemoryRangeType::Code ) _blockRanges.resize(memory.device().config().protection().nbBlocks());
+}
+
+void Pic::MemoryRangeEditor::addLegend(QVBoxLayout *vbox)
+{
+  if ( type()==MemoryRangeType::Code || type()==MemoryRangeType::Eeprom ) {
+    _legend = new MemoryEditorLegend(type(), memory(), this);
+    connect(_legend, SIGNAL(setStartWord(int)), SLOT(setStartWord(int)));
+    connect(_legend, SIGNAL(setEndWord(int)), SLOT(setEndWord(int)));
+    vbox->addWidget(_legend);
+  }
+}
+
+bool Pic::MemoryRangeEditor::isRangeReadOnly() const
+{
+  return ( (type().data().properties & ReadOnly) || type()==MemoryRangeType::CalBackup );
+}
+
+void Pic::MemoryRangeEditor::updateDisplay()
+{
+  const Protection &protection = device().config().protection();
+  if ( type()==MemoryRangeType::Code ) {
+    if ( protection.hasBootBlock() ) _bootRange = memory().bootRange();
+    for (uint k=0; k<_blockRanges.count(); k++)
+      _blockRanges[k] = memory().blockRange(k);
+  }
+  Protection::Type ptype = (protection.family()==Protection::CodeGuard ? Protection::HighSecurity : Protection::ProgramProtected);
+  _codeProtected = memory().protectedRanges(ptype, type());
+  Device::MemoryRangeEditor::updateDisplay();
+  if (_legend) _legend->updateDisplay();
+}
+
+void Pic::MemoryRangeEditor::updateAddressColor(uint i, Address address)
+{
+  if ( _codeProtected.contains(address) )
+    _addresses[i]->setPaletteBackgroundColor(MemoryEditorLegend::protectedColor());
+  else _addresses[i]->unsetPalette();
+  _blocks[i]->unsetPalette();
+  if ( type()==MemoryRangeType::Code ) {
+    if ( _bootRange.contains(address) ) _blocks[i]->setPaletteBackgroundColor(MemoryEditorLegend::bootColor());
+    else for (uint k=0; k<_blockRanges.count(); k++) {
+      if ( !_blockRanges[k].contains(address) ) continue;
+      _blocks[i]->setPaletteBackgroundColor(MemoryEditorLegend::blockColor(k));
+      break;
+    }
+  }
+}
+
+Device::HexWordEditor *Pic::MemoryRangeEditor::createHexWordEditor(QWidget *parent)
+{
+  return new HexWordEditor(type(), memory(), parent);
+}
+
+//-----------------------------------------------------------------------------
+Pic::MemoryTypeEditor::MemoryTypeEditor(const HexView *hexview, MemoryRangeType type, Memory &memory, QWidget *parent, const char *name)
+  : Device::MemoryTypeEditor(hexview, memory, parent, name), MemoryCaster(type, memory)
+{}
+
+void Pic::MemoryTypeEditor::init(bool first)
+{
+  Device::MemoryTypeEditor::init(first);
+  _title->setText(type().label());
+
+  uint nbChars = device().nbCharsWord(type());
+  QString add;
+  if ( type()==MemoryRangeType::UserId ) add = i18n(" - recommended mask: %1").arg(toHexLabel(device().userIdRecommendedMask(), nbChars));
+  if ( type()==MemoryRangeType::Cal && _hexview ) add = i18n(" - not programmed by default");
+  QString comment = i18n("%1-bit words - mask: %2")
+                   .arg(device().nbBitsWord(type())).arg(toHexLabel(device().mask(type()), nbChars));
+  _comment->setText(comment + add);
+}
+
+bool Pic::MemoryTypeEditor::internalDoAction(Device::Action action)
+{
+  Programmer::PicBase *prog = static_cast<Programmer::PicBase *>(Main::programmer());
+  switch (action) {
+    case Device::Clear: memory().clear(type()); return true;
+    case Device::Zero:  memory().fill(type(), 0);  return true;
+    case Device::ChecksumCheck : memory().checksumCheckFill(); return true;
+    case Device::Reload: {
+      const Memory *omemory = static_cast<const Memory *>(originalMemory());
+      Q_ASSERT(omemory);
+      memory().copyFrom(type(), *omemory); return true;
+    }
+    case Device::Program:
+      prog->programSingle(type(), memory());
+      return false;
+    case Device::Verify:
+      prog->verifySingle(type(), memory());
+      return false;
+    case Device::Read:
+      return prog->readSingle(type(), memory());
+    case Device::Erase:
+      prog->eraseSingle(type());
+      return false;
+    case Device::BlankCheck:
+      prog->blankCheckSingle(type());
+      return false;
+    case Device::Nb_Actions: break;
+  }
+  Q_ASSERT(false);
+  return false;
+}
+
+//-----------------------------------------------------------------------------
+Pic::MemoryTypeRangeEditor::MemoryTypeRangeEditor(const HexView *hexview, MemoryRangeType type, Memory &memory, QWidget *parent)
+  : MemoryTypeEditor(hexview, type, memory, parent, "pic_memory_type_range_editor"), _mre(0)
+{}
+
+void Pic::MemoryTypeRangeEditor::init(bool first)
+{
+  MemoryTypeEditor::init(first);
+  uint nbLines = 0;
+  if ( type()==MemoryRangeType::Code ) nbLines = 16;
+  else if ( type()==MemoryRangeType::Eeprom ) nbLines = 8;
+  else nbLines = (device().nbWords(type())/8>1 ? 2 : 1);
+  _mre = new MemoryRangeEditor(type(), memory(), nbLines, 8, 0, -1, this);
+  addEditor(_mre);
+  _top->addWidget(_mre);
+  _mre->init();
+}
+
+//-----------------------------------------------------------------------------
+Pic::MemoryUserIdEditor::MemoryUserIdEditor(const HexView *hexview, Memory &memory, QWidget *parent)
+  : MemoryTypeRangeEditor(hexview, MemoryRangeType::UserId, memory, parent), _saveReadOnly(false)
+{}
+
+void Pic::MemoryUserIdEditor::init(bool first)
+{
+  MemoryTypeRangeEditor::init(first);
+  _setToChecksum = new KToggleAction(i18n("Set to unprotected checksum"), 0, 0,
+    this, SLOT(toggleSetToChecksum()), Main::toplevel().actionCollection());
+  addAction(_setToChecksum);
+  if ( readConfigEntry(BaseGlobalConfig::UserIdSetToChecksum).toBool() && memory().isClear(MemoryRangeType::UserId) ) {
+    _setToChecksum->activate();
+    toggleSetToChecksum();
+  }
+}
+
+void Pic::MemoryUserIdEditor::toggleSetToChecksum()
+{
+  if ( _setToChecksum->isChecked() ) {
+    _mre->setComment(i18n("Set to unprotected checksum"));
+    emit modified();
+  } else _mre->setComment(QString::null);
+  setReadOnly(_saveReadOnly);
+}
+
+void Pic::MemoryUserIdEditor::updateDisplay()
+{
+  if ( _setToChecksum->isChecked() ) memory().setUserIdToUnprotectedChecksum();
+  MemoryTypeRangeEditor::updateDisplay();
+}
+
+void Pic::MemoryUserIdEditor::setReadOnly(bool readOnly)
+{
+  _saveReadOnly = readOnly;
+  MemoryTypeRangeEditor::setReadOnly(readOnly || _setToChecksum->isChecked());
+}
+
+//-----------------------------------------------------------------------------
+Pic::MemoryCalibrationEditor::MemoryCalibrationEditor(const HexView *hexview, Memory &memory, QWidget *parent)
+  : MemoryTypeEditor(hexview, MemoryRangeType::Cal, memory, parent, "pic_memory_calibration_editor")
+{}
+
+void Pic::MemoryCalibrationEditor::init(bool first)
+{
+  MemoryTypeEditor::init(first);
+  MemoryRangeEditor *mre = new MemoryRangeEditor(MemoryRangeType::Cal, memory(), 1, 8, 0, -1, this);
+  addEditor(mre);
+  _top->addWidget(mre);
+  mre->init();
+  if ( device().isReadable(MemoryRangeType::CalBackup) ) {
+    mre = new MemoryRangeEditor(MemoryRangeType::CalBackup, memory(), 1, 8, 0, -1, this);
+    addEditor(mre);
+    _top->addWidget(mre);
+    mre->init();
+    mre->setComment(i18n("(backup)"));
+  }
+}
+
+bool Pic::MemoryCalibrationEditor::hasAction(Device::Action action) const
+{
+  return ( action==Device::Read || action==Device::Verify || action==Device::Program );
+}
+
+bool Pic::MemoryCalibrationEditor::internalDoAction(Device::Action action)
+{
+  Programmer::PicBase *prog = static_cast<Programmer::PicBase *>(Main::programmer());
+  switch (action) {
+    case Device::Reload: {
+      const Memory *omemory = static_cast<const Memory *>(originalMemory());
+      Q_ASSERT(omemory);
+      memory().copyFrom(MemoryRangeType::Cal, *omemory);
+      memory().copyFrom(MemoryRangeType::CalBackup, *omemory);
+      return true;
+    }
+    case Device::Program:
+      if ( prog->programCalibration(memory().arrayForWriting(Pic::MemoryRangeType::Cal)) )
+        return prog->readSingle(MemoryRangeType::Cal, memory());
+      return false;
+    case Device::Verify:
+      prog->verifySingle(MemoryRangeType::Cal, memory());
+      return false;
+    case Device::Read:
+      return prog->readSingle(MemoryRangeType::Cal, memory());
+    case Device::Clear:
+    case Device::Zero:
+    case Device::ChecksumCheck:
+    case Device::Erase:
+    case Device::BlankCheck:
+    case Device::Nb_Actions: break;
+  }
+  Q_ASSERT(false);
+  return false;
+}
diff --git a/src/devices/pic/gui/pic_memory_editor.h b/src/devices/pic/gui/pic_memory_editor.h
new file mode 100644
index 0000000..bf67cd1
--- /dev/null
+++ b/src/devices/pic/gui/pic_memory_editor.h
@@ -0,0 +1,189 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *   Copyright (C) 2003-2004 Alain Gibaud <alain.gibaud@free.fr>           *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_MEMORY_EDITOR_H
+#define PIC_MEMORY_EDITOR_H
+
+#include <qscrollbar.h>
+#include <qgroupbox.h>
+class KToggleAction;
+
+#include "devices/gui/memory_editor.h"
+#include "devices/gui/hex_word_editor.h"
+#include "devices/pic/pic/pic_memory.h"
+class PopupButton;
+
+namespace Pic
+{
+class HexView;
+
+//-----------------------------------------------------------------------------
+class MemoryCaster
+{
+public:
+  MemoryCaster(MemoryRangeType type, Device::Memory &memory) : _type(type), _memory(memory) {}
+  MemoryRangeType type() const { return _type; }
+  const Data &device() const { return static_cast<const Data &>(_memory.device()); }
+  const Memory &memory() const { return static_cast<Memory &>(_memory); }
+  Memory &memory() { return static_cast<Memory &>(_memory); }
+
+private:
+  MemoryRangeType _type;
+  Device::Memory &_memory;
+};
+
+//-----------------------------------------------------------------------------
+class MemoryEditor : public Device::MemoryEditor, public MemoryCaster
+{
+Q_OBJECT
+public:
+  MemoryEditor(MemoryRangeType type, Memory &memory, QWidget *parent, const char *name)
+    : Device::MemoryEditor(&memory, parent, name), MemoryCaster(type, memory) {}
+};
+
+//-----------------------------------------------------------------------------
+class MemoryEditorLegend : public MemoryEditor
+{
+Q_OBJECT
+public:
+  MemoryEditorLegend(MemoryRangeType type, Memory &memory, QWidget *parent);
+  virtual void setReadOnly(bool) {}
+
+  static QColor protectedColor() { return QColor("#FF8888"); }
+  static QColor bootColor() { return QColor("#8888FF"); }
+  static QColor blockColor(uint i) { return QColor(BLOCK_COLORS[i]); }
+
+signals:
+  void setStartWord(int i);
+  void setEndWord(int i);
+
+public slots:
+  virtual void updateDisplay();
+
+private slots:
+  void gotoStart();
+  void gotoEnd();
+
+private:
+  class Data {
+  public:
+    Data() : button(0), label(0) {}
+    Data(const QString &text, QWidget *parent);
+    void setProtected(bool on);
+    bool hasAction(const KAction *action) const;
+    PopupButton *button;
+    QLabel      *label;
+    QValueVector<KAction *> actions;
+  };
+  Data _boot;
+  QValueVector<Data> _blocks;
+
+  static const char * const BLOCK_COLORS[Protection::MAX_NB_BLOCKS];
+};
+
+//-----------------------------------------------------------------------------
+class HexWordEditor : public Device::HexWordEditor, public MemoryCaster
+{
+Q_OBJECT
+public:
+  HexWordEditor(MemoryRangeType type, Memory &memory, QWidget *parent);
+
+private:
+  virtual BitValue mask() const { return memory().device().mask(type()); }
+  virtual BitValue normalizeWord(BitValue value) const { return memory().normalizeWord(type(), _offset, value); }
+  virtual BitValue word() const { return memory().word(type(), _offset); }
+  virtual void setWord(BitValue value);
+};
+
+//-----------------------------------------------------------------------------
+class MemoryRangeEditor : public Device::MemoryRangeEditor, public MemoryCaster
+{
+  Q_OBJECT
+public:
+  MemoryRangeEditor(MemoryRangeType type, Memory &memory,
+                    uint nbLines, uint nbCols, uint wordOffset, int nbWords, QWidget *parent);
+
+public slots:
+  virtual void updateDisplay();
+
+private:
+  MemoryEditorLegend *_legend;
+  AddressRange        _bootRange;
+  AddressRangeVector  _blockRanges;
+  AddressRangeVector  _codeProtected;
+
+  virtual uint nbWords() const { return device().nbWords(type()); }
+  virtual uint addressIncrement() const { return device().addressIncrement(type()); }
+  virtual Address startAddress() const { return device().range(type()).start; }
+  virtual Device::HexWordEditor *createHexWordEditor(QWidget *parent);
+  virtual void updateAddressColor(uint i, Address address);
+  virtual bool isRangeReadOnly() const;
+  virtual void addLegend(QVBoxLayout *vbox);
+};
+
+//-----------------------------------------------------------------------------
+class MemoryTypeEditor : public Device::MemoryTypeEditor, public MemoryCaster
+{
+Q_OBJECT
+public:
+  MemoryTypeEditor(const HexView *hexview, MemoryRangeType type, Memory &memory, QWidget *parent, const char *name);
+  virtual void init(bool first);
+
+private:
+  virtual bool internalDoAction(Device::Action action);
+};
+
+//-----------------------------------------------------------------------------
+class MemoryTypeRangeEditor : public MemoryTypeEditor
+{
+Q_OBJECT
+public:
+  MemoryTypeRangeEditor(const HexView *hexview, MemoryRangeType type, Memory &memory, QWidget *parent);
+  virtual void init(bool first);
+
+protected:
+  MemoryRangeEditor *_mre;
+};
+
+//-----------------------------------------------------------------------------
+class MemoryUserIdEditor : public MemoryTypeRangeEditor
+{
+Q_OBJECT
+public:
+  MemoryUserIdEditor(const HexView *hexview, Memory &memory, QWidget *parent);
+  virtual void init(bool first);
+  virtual void setReadOnly(bool readOnly);
+
+public slots:
+  virtual void updateDisplay();
+
+private slots:
+  void toggleSetToChecksum();
+
+private:
+  bool _saveReadOnly;
+  KToggleAction *_setToChecksum;
+};
+
+//-----------------------------------------------------------------------------
+class MemoryCalibrationEditor : public MemoryTypeEditor
+{
+Q_OBJECT
+public:
+  MemoryCalibrationEditor(const HexView *hexview, Memory &memory, QWidget *parent);
+  virtual void init(bool first);
+
+private:
+  virtual bool hasAction(Device::Action action) const;
+  virtual bool internalDoAction(Device::Action action);
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/pic/gui/pic_prog_group_ui.cpp b/src/devices/pic/gui/pic_prog_group_ui.cpp
new file mode 100644
index 0000000..e063b77
--- /dev/null
+++ b/src/devices/pic/gui/pic_prog_group_ui.cpp
@@ -0,0 +1,41 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_prog_group_ui.h"
+
+#include "progs/gui/prog_config_widget.h"
+#include "progs/base/prog_group.h"
+
+Programmer::PicAdvancedDialog::PicAdvancedDialog(PicBase &base, QWidget *parent, const char *name)
+  : AdvancedDialog(base, parent, name)
+{
+  if (_voltagesContainer) {
+    uint k = _voltagesContainer->numRows();
+    for (uint i=0; i<Pic::Nb_VoltageTypes; i++) {
+      if ( !base.group().canReadVoltage(Pic::VoltageType(i)) ) _voltages[i] = 0;
+      else {
+        QLabel *label = new QLabel(i18n(Pic::VOLTAGE_TYPE_LABELS[i]) + ":", _voltagesContainer);
+        _voltagesContainer->addWidget(label, k,k, 0,0);
+        _voltages[i] = new QLabel(_voltagesContainer);
+        _voltagesContainer->addWidget(_voltages[i], k,k, 1,1);
+        k++;
+      }
+    }
+  }
+}
+
+void Programmer::PicAdvancedDialog::updateDisplay()
+{
+  ::Programmer::AdvancedDialog::updateDisplay();
+  for (uint i=0; i<Pic::Nb_VoltageTypes; i++) {
+    if ( !base().group().canReadVoltage(Pic::VoltageType(i)) ) continue;
+    double v = base().voltage(Pic::VoltageType(i));
+    if ( v==::Programmer::UNKNOWN_VOLTAGE ) _voltages[i]->setText("---");
+    else _voltages[i]->setText(QString("%1 V").arg(v));
+  }
+}
diff --git a/src/devices/pic/gui/pic_prog_group_ui.h b/src/devices/pic/gui/pic_prog_group_ui.h
new file mode 100644
index 0000000..75821b5
--- /dev/null
+++ b/src/devices/pic/gui/pic_prog_group_ui.h
@@ -0,0 +1,31 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_PROG_GROUP_UI_H
+#define PIC_PROG_GROUP_UI_H
+
+#include "progs/gui/prog_group_ui.h"
+#include "devices/pic/prog/pic_prog.h"
+
+namespace Programmer
+{
+class PicAdvancedDialog : public ::Programmer::AdvancedDialog
+{
+Q_OBJECT
+public:
+  PicAdvancedDialog(PicBase &base, QWidget *parent, const char *name);
+  virtual void updateDisplay();
+
+private:
+  QLabel *_voltages[Pic::Nb_VoltageTypes];
+  PicBase &base() { return static_cast<PicBase &>(_base); }
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/pic/gui/pic_register_view.cpp b/src/devices/pic/gui/pic_register_view.cpp
new file mode 100644
index 0000000..ef7de9b
--- /dev/null
+++ b/src/devices/pic/gui/pic_register_view.cpp
@@ -0,0 +1,329 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_register_view.h"
+
+#include <qlayout.h>
+#include <qlabel.h>
+#include <qpushbutton.h>
+#include <qcheckbox.h>
+#include <qcombobox.h>
+#include <qpopupmenu.h>
+
+#include <klocale.h>
+#include <kiconloader.h>
+
+#include "libgui/main_global.h"
+#include "devices/gui/hex_word_editor.h"
+#include "common/gui/misc_gui.h"
+#include "devices/pic/base/pic.h"
+#include "progs/base/generic_prog.h"
+#include "progs/base/generic_debug.h"
+#include "progs/base/prog_group.h"
+#include "libgui/gui_debug_manager.h"
+#include "coff/base/text_coff.h"
+
+//-----------------------------------------------------------------------------
+Pic::BankWidget::BankWidget(uint i, QWidget *parent)
+  : QFrame(parent, "bank_widget"), _bindex(i), _bankCombo(0)
+{
+  setFrameStyle(WinPanel | Sunken);
+  QGridLayout *top = new QGridLayout(this, 1, 1, 5, 0);
+  top->setColSpacing(1, 4);
+  QFont f("courier", font().pointSize());
+
+  const Pic::Data &data = static_cast<const Pic::Data &>(*Main::deviceData());
+  const Pic::RegistersData &rdata = data.registersData();
+  bool debugging = Main::programmerGroup().isDebugger();
+  uint row = 0;
+  if ( rdata.nbBanks!=1 ) {
+    if ( data.is18Family() ) {
+      if ( (i/2)==0 ) {
+        QString title = ((i%2)==0 ? i18n("Access Bank (low)") : i18n("Access Bank (high)"));
+        QLabel *label = new QLabel(title, this);
+        label->setAlignment(AlignCenter);
+        top->addMultiCellWidget(label, row,row, 0,6, AlignHCenter);
+      } else {
+        _bankCombo = new QComboBox(this);
+        for (uint k=1; k<2*rdata.nbBanks-1; k++) {
+	  _bankCombo->insertItem((k%2)==0 ? i18n("Bank %1 (low)").arg(k/2) : i18n("Bank %1 (high)").arg(k/2));
+	}
+        if ( _bindex==3 ) _bankCombo->setCurrentItem(1);
+        connect(_bankCombo, SIGNAL(activated(int)), SLOT(bankChanged()));
+        top->addMultiCellWidget(_bankCombo, row,row, 0,6, AlignHCenter);
+      }
+    } else {
+      QLabel *label = new QLabel(i18n("Bank %1").arg(i), this);
+      label->setAlignment(AlignCenter);
+      top->addMultiCellWidget(label, row,row, 0,6, AlignHCenter);
+    }
+    row++;
+    top->setRowSpacing(row, 5);
+    row++;
+  }
+
+  KIconLoader loader;
+  QPixmap readIcon = loader.loadIcon("viewmag", KIcon::Small);
+  QPixmap editIcon = loader.loadIcon("edit", KIcon::Small);
+  uint nb;
+  if ( !data.is18Family() ) nb = rdata.nbRegistersPerBank();
+  else nb = kMax(rdata.accessBankSplit, rdata.nbRegistersPerBank() - rdata.accessBankSplit);
+  _registers.resize(nb);
+  for (uint k=0; k<nb; k++) {
+    _registers[k].alabel = new QLabel(this);
+    _registers[k].alabel->setFont(f);
+    top->addWidget(_registers[k].alabel, row, 0);
+    if (debugging) {
+      _registers[k].button = new PopupButton(this);
+      _registers[k].button->appendItem(i18n("Read"), readIcon, ReadId);
+      _registers[k].button->appendItem(i18n("Edit"), editIcon, EditId);
+      _registers[k].button->appendItem(i18n("Watch"), WatchId);
+      connect(_registers[k].button, SIGNAL(activated(int)), SLOT(buttonActivated(int)));
+      top->addWidget(_registers[k].button, row, 2);
+      _registers[k].edit = new Register::LineEdit(this);
+      connect(_registers[k].edit, SIGNAL(modified()), SLOT(write()));
+      _registers[k].edit->setFont(f);
+      top->addWidget(_registers[k].edit, row, 6);
+    } else {
+      _registers[k].label = new QLabel(this);
+      top->addWidget(_registers[k].label, row, 2);
+    }
+    row++;
+  }
+
+  if (debugging) {
+    top->setColSpacing(3, 5);
+    top->setColSpacing(5, 5);
+  }
+  top->setRowStretch(row, 1);
+
+  updateRegisterAddresses();
+}
+
+void Pic::BankWidget::bankChanged()
+{
+  updateRegisterAddresses();
+  updateView();
+}
+
+uint Pic::BankWidget::bank() const
+{
+  const Pic::Data &data = static_cast<const Pic::Data &>(*Main::deviceData());
+  if ( !data.is18Family() ) return _bindex;
+  if ( _bindex==0 ) return 0;
+  const Pic::RegistersData &rdata = data.registersData();
+  if ( _bindex==1 ) return rdata.nbBanks - 1;
+  return (_bankCombo->currentItem()+1)/2;
+}
+
+uint Pic::BankWidget::nbRegisters() const
+{
+  const Pic::Data &data = static_cast<const Pic::Data &>(*Main::deviceData());
+  const Pic::RegistersData &rdata = data.registersData();
+  if ( !data.is18Family() ) return rdata.nbRegistersPerBank();
+  if ( _bindex==0 || (_bankCombo && _bankCombo->currentItem()==2*int(rdata.nbBanks)-3) ) return rdata.accessBankSplit;
+  if ( _bindex==1 || (_bankCombo && _bankCombo->currentItem()==0) ) return rdata.nbRegistersPerBank() - rdata.accessBankSplit;
+  return rdata.nbRegistersPerBank() / 2;
+}
+
+uint Pic::BankWidget::indexOffset() const
+{
+  const Pic::Data &data = static_cast<const Pic::Data &>(*Main::deviceData());
+  const Pic::RegistersData &rdata = data.registersData();
+  uint offset = bank() * rdata.nbRegistersPerBank();
+  if ( !data.is18Family() ) return offset;
+  if ( _bindex==0 || (_bankCombo && (_bankCombo->currentItem()%2)==1) ) return offset;
+  if ( _bindex==1 || (_bankCombo && _bankCombo->currentItem()==0) ) return offset + rdata.accessBankSplit;
+  return offset + rdata.nbRegistersPerBank()/2;
+}
+
+void Pic::BankWidget::updateRegisterAddresses()
+{
+  const Pic::Data &data = static_cast<const Pic::Data &>(*Main::deviceData());
+  const Pic::RegistersData &rdata = data.registersData();
+  uint nbChars = rdata.nbCharsAddress();
+  uint nb = nbRegisters();
+  uint offset = indexOffset();
+  for (uint k=0; k<_registers.count(); k++) {
+    if ( k<nb ) {
+      _registers[k].alabel->show();
+      _registers[k].address = rdata.addressFromIndex(offset + k);
+      _registers[k].alabel->setText(toHexLabel(_registers[k].address, nbChars) + ":");
+    } else _registers[k].alabel->hide();
+  }
+}
+
+void Pic::BankWidget::buttonActivated(int id)
+{
+  const Pic::Data &data = static_cast<const Pic::Data &>(*Main::deviceData());
+  const Pic::RegistersData &rdata = data.registersData();
+  for (uint i=0; i<_registers.count(); i++) {
+    if ( sender()!=_registers[i].button ) continue;
+    Register::TypeData rtd(_registers[i].address, rdata.nbChars());
+    switch (id) {
+      case ReadId: Debugger::manager->readRegister(rtd); break;
+      case EditId:
+        _registers[i].edit->selectAll();
+        _registers[i].edit->setFocus();
+        break;
+      case WatchId: {
+        bool isWatched = Register::list().isWatched(rtd);
+        Debugger::manager->setRegisterWatched(rtd, !isWatched);
+        break;
+      }
+    }
+    break;
+  }
+}
+
+void Pic::BankWidget::write()
+{
+  const Pic::Data &data = static_cast<const Pic::Data &>(*Main::deviceData());
+  const Pic::RegistersData &rdata = data.registersData();
+  for (uint i=0; i<_registers.count(); i++) {
+    if ( sender()!=_registers[i].edit ) continue;
+    Register::TypeData rtd(_registers[i].address, rdata.nbChars());
+    Debugger::manager->writeRegister(rtd, _registers[i].edit->value());
+    break;
+  }
+}
+
+void Pic::BankWidget::updateView()
+{
+  const Pic::Data &data = static_cast<const Pic::Data &>(*Main::deviceData());
+  const Pic::RegistersData &rdata = data.registersData();
+  bool active = ( Main::programmerState()==Programmer::Halted );
+  const Coff::Object *coff = Debugger::manager->coff();
+  uint nb = nbRegisters();
+  for (uint i=0; i<_registers.count(); i++) {
+    uint address = _registers[i].address;
+    Device::RegisterProperties rp = rdata.properties(address);
+    QString label = rdata.label(address);
+    Register::TypeData rtd(address, rdata.nbChars());
+    bool isWatched = Register::list().isWatched(rtd);
+    if (coff) {
+      QString name = coff->variableName(address);
+      if ( !name.isEmpty() ) label = "<" + name + ">";
+    }
+    if (_registers[i].button) {
+      if ( i<nb ) {
+	_registers[i].button->show();
+	_registers[i].button->setText(label);
+	if (isWatched) {
+	  QFont f = _registers[i].button->font();
+	  f.setBold(true);
+	  _registers[i].button->setFont(f);
+	} else _registers[i].button->unsetFont();
+	_registers[i].button->popup()->setItemEnabled(ReadId, active && (rp & Device::Readable));
+	_registers[i].button->popup()->setItemEnabled(EditId, active);
+	_registers[i].button->popup()->changeItem(WatchId, isWatched ? i18n("Stop Watching") : i18n("Watch"));
+	_registers[i].button->popup()->setItemEnabled(WatchId, rp & Device::Readable);
+      } else _registers[i].button->hide();
+    }
+    if (_registers[i].label) {
+      if ( i<nb ) {
+	_registers[i].label->show();
+	_registers[i].label->setText(label);
+      } else _registers[i].label->hide();
+    }
+    if (_registers[i].edit) {
+      if ( i<nb ) {
+	_registers[i].edit->show();
+	_registers[i].edit->setEnabled(active);
+	BitValue value = Register::list().value(rtd);
+	if ( value!=Register::list().oldValue(rtd) ) _registers[i].edit->setColor(red);
+	else _registers[i].edit->unsetColor();
+	_registers[i].edit->setValue(NumberBase::Hex, value, rdata.nbChars());
+      } else _registers[i].edit->hide();
+    }
+  }
+}
+
+//-----------------------------------------------------------------------------
+Pic::RegisterView::RegisterView(QWidget *parent)
+  : Register::View(parent, "pic_register_view"),
+    _readAllButton(0), _clearAllButton(0)
+{
+  QVBoxLayout *vbox = new QVBoxLayout(this, 10, 10);
+  QHBoxLayout *hbox = new QHBoxLayout(vbox);
+
+  bool debugging = Main::programmerGroup().isDebugger();
+  const Pic::Data &data = static_cast<const Pic::Data &>(*Main::deviceData());
+  uint nb = data.registersData().nbBanks;
+  if ( debugging && nb!=0 ) {
+    QWidget *w = new QWidget(this);
+    hbox->addWidget(w);
+    QGridLayout *grid = new QGridLayout(w, 1, 1, 0, 10);
+    _readAllButton = new QPushButton(i18n("Read All"), w);
+    connect(_readAllButton, SIGNAL(clicked()), Debugger::manager, SLOT(readAllRegisters()));
+    grid->addWidget(_readAllButton, 0, 0);
+    _clearAllButton = new QPushButton(i18n("Clear all watching"), w);
+    connect(_clearAllButton, SIGNAL(clicked()), SLOT(stopWatchAllRegisters()));
+    grid->addWidget(_clearAllButton, 0, 1);
+    grid->setColStretch(2, 1);
+  }
+
+  QHBoxLayout *hbox2 = 0;
+  if ( nb==0 ) {
+    QLabel *label = new QLabel(i18n("Registers information not available."), this);
+    vbox->addWidget(label);
+  } else {
+    hbox = new QHBoxLayout(vbox);
+    hbox2 = new QHBoxLayout(hbox);
+    hbox->addStretch(1);
+    if ( data.is18Family() ) {
+      nb = 2;
+      for (uint k=1; k<data.registersData().nbBanks-1; k++) {
+        if ( !data.registersData().isBankUsed(k) ) continue;
+        nb += 2;
+        break;
+      }
+    }
+    _banks.resize(nb);
+    for (uint i=0; i<nb; i++) {
+      _banks[i] = new BankWidget(i, this);
+      _banks[i]->show();
+      hbox2->addWidget(_banks[i]);
+    }
+  }
+  vbox->addStretch(1);
+}
+
+void Pic::RegisterView::updateView()
+{
+  if (_readAllButton) _readAllButton->setEnabled(Main::programmerState()==Programmer::Halted);
+  for (uint i=0; i<_banks.count(); i++) if (_banks[i]) _banks[i]->updateView();
+}
+
+void Pic::RegisterView::stopWatchAllRegisters()
+{
+  Debugger::manager->stopWatchAll();
+}
+
+//----------------------------------------------------------------------------
+Pic::RegisterListViewItem::RegisterListViewItem(const Register::TypeData &data, KListViewItem *parent)
+  : Register::ListViewItem(data, parent)
+{}
+
+uint Pic::RegisterListViewItem::nbCharsAddress() const
+{
+  const Pic::Data &data = static_cast<const Pic::Data &>(*Main::deviceData());
+  return data.registersData().nbCharsAddress();
+}
+
+QString Pic::RegisterListViewItem::label() const
+{
+  if ( _data.type()!=Register::Regular ) return _data.name();
+  const Coff::Object *coff = Debugger::manager->coff();
+  if (coff) {
+    QString name = coff->variableName(_data.address());
+    if ( !name.isEmpty() ) return "<" + name + ">";
+  }
+  const Pic::Data &data = static_cast<const Pic::Data &>(*Main::deviceData());
+  return data.registersData().label(_data.address());
+}
diff --git a/src/devices/pic/gui/pic_register_view.h b/src/devices/pic/gui/pic_register_view.h
new file mode 100644
index 0000000..f5b9d4b
--- /dev/null
+++ b/src/devices/pic/gui/pic_register_view.h
@@ -0,0 +1,88 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_REGISTER_VIEW_H
+#define PIC_REGISTER_VIEW_H
+
+#include <qvaluevector.h>
+class QPushButton;
+class QCheckBox;
+class QLabel;
+class QComboBox;
+
+#include "devices/gui/register_view.h"
+#include "devices/pic/base/pic.h"
+#include "devices/pic/base/pic_register.h"
+class PopupButton;
+namespace Device { class RegisterHexWordEditor; }
+
+namespace Pic
+{
+//-----------------------------------------------------------------------------
+class BankWidget : public QFrame
+{
+Q_OBJECT
+public:
+  BankWidget(uint bank, QWidget *parent);
+  void updateView();
+
+private slots:
+  void buttonActivated(int id);
+  void write();
+  void bankChanged();
+
+private:
+  enum Id { ReadId, EditId, WatchId };
+  class Data {
+  public:
+    Data() : label(0), button(0), edit(0) {}
+    uint address;
+    QLabel *alabel, *label;
+    PopupButton *button;
+    Register::LineEdit *edit;
+  };
+  uint _bindex;
+  QComboBox *_bankCombo;
+  QValueVector<Data> _registers;
+
+  uint bank() const;
+  uint nbRegisters() const;
+  uint indexOffset() const;
+  void updateRegisterAddresses();
+};
+
+//-----------------------------------------------------------------------------
+class RegisterView : public Register::View
+{
+Q_OBJECT
+public:
+  RegisterView(QWidget *parent);
+  virtual void updateView();
+
+private slots:
+  void stopWatchAllRegisters();
+
+private:
+  QPushButton *_readAllButton, *_clearAllButton;
+  QValueVector<BankWidget *> _banks;
+};
+
+//-----------------------------------------------------------------------------
+class RegisterListViewItem : public Register::ListViewItem
+{
+public:
+  RegisterListViewItem(const Register::TypeData &data, KListViewItem *parent);
+
+private:
+  virtual uint nbCharsAddress() const;
+  virtual QString label() const;
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/pic/pic.pro b/src/devices/pic/pic.pro
new file mode 100644
index 0000000..cf3c06a
--- /dev/null
+++ b/src/devices/pic/pic.pro
@@ -0,0 +1,2 @@
+TEMPLATE = subdirs
+SUBDIRS = base xml pic xml_data prog
diff --git a/src/devices/pic/pic/Makefile.am b/src/devices/pic/pic/Makefile.am
new file mode 100644
index 0000000..e9deb80
--- /dev/null
+++ b/src/devices/pic/pic/Makefile.am
@@ -0,0 +1,5 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+noinst_LTLIBRARIES = libpic.la
+libpic_la_SOURCES = pic_memory.cpp pic_group.cpp
diff --git a/src/devices/pic/pic/pic.pro b/src/devices/pic/pic/pic.pro
new file mode 100644
index 0000000..8893c67
--- /dev/null
+++ b/src/devices/pic/pic/pic.pro
@@ -0,0 +1,6 @@
+STOPDIR = ../../../..
+include($${STOPDIR}/lib.pro)
+
+TARGET   = pic
+HEADERS += pic_memory.h pic_group.h
+SOURCES += pic_memory.cpp pic_group.cpp
\ No newline at end of file
diff --git a/src/devices/pic/pic/pic_group.cpp b/src/devices/pic/pic/pic_group.cpp
new file mode 100644
index 0000000..639d2cf
--- /dev/null
+++ b/src/devices/pic/pic/pic_group.cpp
@@ -0,0 +1,87 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_group.h"
+
+#if !defined(NO_KDE)
+# include <qpainter.h>
+#endif
+
+#include "pic_memory.h"
+#include "devices/pic/base/pic_register.h"
+
+Device::Memory *Pic::Group::createMemory(const Device::Data &data) const
+{
+  return new Memory(static_cast<const Pic::Data &>(data));
+}
+
+QString Pic::Group::informationHtml(const Device::Data &data) const
+{
+  const Pic::Data &pdata = static_cast<const Pic::Data &>(data);
+  // memory type
+  QString s = htmlTableRow(i18n("Memory Type"), data.memoryTechnology().label());
+  if ( pdata.isPresent(MemoryRangeType::Code) ) {
+    uint nbw = pdata.nbWords(MemoryRangeType::Code);
+    QString tmp = i18n("%1 words").arg(formatNumber(nbw));
+    tmp += i18n(" (%2 bits)").arg(pdata.nbBitsWord(MemoryRangeType::Code));
+    s += htmlTableRow(MemoryRangeType(MemoryRangeType::Code).label(), tmp);
+  }
+  if ( pdata.isPresent(MemoryRangeType::Eeprom) ) {
+    uint nbw = pdata.nbWords(MemoryRangeType::Eeprom);
+    QString tmp = i18n("%1 bytes").arg(formatNumber(nbw));
+    tmp += i18n(" (%2 bits)").arg(pdata.nbBitsWord(MemoryRangeType::Eeprom));
+    if ( !(pdata.range(MemoryRangeType::Eeprom).properties & Programmable) ) tmp += i18n(" (not programmable)");
+    s += htmlTableRow(MemoryRangeType(MemoryRangeType::Eeprom).label(), tmp);
+  }
+
+  // io ports
+  const Pic::RegistersData &rdata = pdata.registersData();
+  QString tmp;
+  if ( rdata.nbBanks!=0 ) {
+    uint nb = 0;
+    for (uint i=0; i<Device::MAX_NB_PORTS; i++) {
+      if ( !rdata.hasPort(i) ) continue;
+      uint nbBits = 0;
+      for (uint k=0; k<Device::MAX_NB_PORT_BITS; k++) if ( rdata.hasPortBit(i, k) ) nbBits++;
+      tmp += rdata.portName(i) + "[" + QString::number(nbBits) + "] ";
+      nb++;
+    }
+    if ( nb==0 ) tmp = i18n("<none>");
+    s += htmlTableRow(i18n("IO Ports"), tmp);
+  }
+
+  // features
+  tmp = QString::null;
+  FOR_EACH(Feature, feature) {
+    if ( !pdata.hasFeature(feature) ) continue;
+    if ( !tmp.isEmpty() ) tmp += ", ";
+    tmp += feature.label();
+  }
+  if ( !tmp.isEmpty() ) s += htmlTableRow(i18n("Features"), tmp);
+
+  return s;
+}
+
+#if !defined(NO_KDE)
+QPixmap Pic::Group::memoryGraph(const Device::Data &data) const
+{
+  const Pic::Data &pdata = static_cast<const Pic::Data &>(data);
+  QValueList<Device::MemoryGraphData> ranges;
+  FOR_EACH(Pic::MemoryRangeType, type) {
+    if ( type==Pic::MemoryRangeType::Eeprom || !pdata.isPresent(type) ) continue;
+    Device::MemoryGraphData data;
+    data.startAddress = pdata.range(type).start;
+    data.start = toHexLabel(pdata.range(type).start, pdata.nbCharsAddress());
+    data.endAddress = pdata.range(type).end;
+    data.end = toHexLabel(pdata.range(type).end, pdata.nbCharsAddress());
+    data.label = type.label();
+    ranges.append(data);
+  }
+  return Device::memoryGraph(ranges);
+}
+#endif
diff --git a/src/devices/pic/pic/pic_group.h b/src/devices/pic/pic/pic_group.h
new file mode 100644
index 0000000..1b95e09
--- /dev/null
+++ b/src/devices/pic/pic/pic_group.h
@@ -0,0 +1,39 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_GROUP_H
+#define PIC_GROUP_H
+
+#include "common/global/global.h"
+#include "devices/base/device_group.h"
+#include "devices/pic/base/pic.h"
+
+namespace Pic
+{
+extern const uint DATA_SIZE;
+extern const char *DATA_STREAM;
+
+class Group : public Device::Group<Data>
+{
+public:
+  virtual QString name() const { return "pic"; }
+  virtual QString label() const { return i18n("PIC"); }
+  virtual Device::Memory *createMemory(const Device::Data &data) const;
+  virtual QString informationHtml(const Device::Data &data) const;
+#if !defined(NO_KDE)
+  virtual QPixmap memoryGraph(const Device::Data &data) const;
+#endif
+
+private:
+  virtual uint dataSize() const { return DATA_SIZE; }
+  virtual const char *dataStream() const { return DATA_STREAM; }
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/pic/pic/pic_memory.cpp b/src/devices/pic/pic/pic_memory.cpp
new file mode 100644
index 0000000..cccb2f9
--- /dev/null
+++ b/src/devices/pic/pic/pic_memory.cpp
@@ -0,0 +1,560 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_memory.h"
+
+#include <qfile.h>
+
+#include "common/common/misc.h"
+
+Pic::Memory::Memory(const Data &data)
+  : Device::Memory(data)
+{
+  FOR_EACH(MemoryRangeType, i) _ranges[i].resize(device().nbWords(i));
+  fill(BitValue());
+}
+
+void Pic::Memory::fill(MemoryRangeType type, BitValue value)
+{
+  for (uint i=0; i<_ranges[type].count(); i++) {
+    if ( type==MemoryRangeType::Config && !value.isInitialized() ) _ranges[type][i] = device().config()._words[i].bvalue;
+    else _ranges[type][i] = value;
+  }
+}
+
+bool Pic::Memory::isClear(MemoryRangeType type) const
+{
+  for (uint i=0; i<_ranges[type].count(); i++) {
+    if ( type==MemoryRangeType::Config ) {
+      if ( _ranges[type][i]!=device().config()._words[i].bvalue ) return false;
+    } else if ( _ranges[type][i].isInitialized() ) return false;
+  }
+  return true;
+}
+
+void Pic::Memory::fill(BitValue value)
+{
+  FOR_EACH(MemoryRangeType, k) fill(k, value);
+}
+
+void Pic::Memory::copyFrom(MemoryRangeType type, const Memory &memory)
+{
+  Q_ASSERT( memory.device().name()==device().name() );
+  for (uint i=0; i<_ranges[type].count(); i++) _ranges[type][i] = memory._ranges[type][i];
+}
+
+void Pic::Memory::copyFrom(const Device::Memory &memory)
+{
+  Q_ASSERT( memory.device().name()==device().name() );
+  FOR_EACH(MemoryRangeType, i) copyFrom(i, static_cast<const Memory &>(memory));
+}
+
+Device::Array Pic::Memory::arrayForWriting(MemoryRangeType type) const
+{
+  Device::Array data = _ranges[type];
+  for (uint i=0; i<data.count(); i++)
+    data[i] = data[i].maskWith(type==MemoryRangeType::Config ? device().config()._words[i].wmask : device().mask(type));
+  return data;
+}
+
+BitValue Pic::Memory::word(MemoryRangeType type, uint offset) const
+{
+  CRASH_ASSERT( offset<_ranges[type].size() );
+  return _ranges[type][offset];
+}
+
+BitValue Pic::Memory::normalizeWord(MemoryRangeType type, uint offset, BitValue value) const
+{
+  if ( type==MemoryRangeType::Config) {
+    const Config::Word &cword = device().config()._words[offset];
+    return value.maskWith(cword.usedMask());
+  }
+  if ( type==MemoryRangeType::UserId ) return value.maskWith(device().userIdRecommendedMask());
+  return value.maskWith(device().mask(type));
+}
+
+BitValue Pic::Memory::normalizedWord(MemoryRangeType type, uint offset) const
+{
+  return normalizeWord(type, offset, word(type, offset));
+}
+
+void Pic::Memory::setWord(MemoryRangeType type, uint offset, BitValue value)
+{
+  if ( offset>=_ranges[type].size() ) qDebug("Memory::setWord: type=%s offset=%s size=%s value=%s", type.key(), toHexLabelAbs(offset).latin1(), toHexLabelAbs(_ranges[type].size()).latin1(), toHexLabelAbs(value).latin1());
+  CRASH_ASSERT( offset<_ranges[type].size() );
+  _ranges[type][offset] = value;
+}
+
+void Pic::Memory::setArray(MemoryRangeType type, const Device::Array &data)
+{
+  CRASH_ASSERT( _ranges[type].size()==data.size() );
+  _ranges[type] = data;
+}
+
+QString Pic::Memory::findValue(const QString &maskName) const
+{
+  if ( maskName.isEmpty() ) return QString::null;
+  uint i;
+  const Config::Mask *mask = device().config().findMask(maskName, &i);
+  if ( mask==0 ) return QString::null;
+  BitValue v = word(MemoryRangeType::Config, i).maskWith(mask->value);
+  for (uint k=0; k<uint(mask->values.count()); k++)
+    if ( v.isInside(mask->values[k].value) ) return mask->values[k].name;
+  Q_ASSERT(false);
+  return QString::null;
+}
+
+AddressRange Pic::Memory::bootRange() const
+{
+  const Protection &protection = device().config().protection();
+  // with boot size
+  QString value = findValue(protection.bootSizeMaskName());
+  if ( !value.isEmpty() ) {
+    uint size = value.toUInt();
+    if ( size==0 ) return AddressRange();
+    Address start = device().range(MemoryRangeType::Code).start;
+    if ( device().architecture()==Architecture::P30F ) start = 0x100;
+    return AddressRange(start, 2 * size - 1); // instruction words
+  }
+  // only CPB
+  QString maskName = protection.bootMaskName(Protection::ProgramProtected);
+  const Config::Mask *mask = device().config().findMask(maskName);
+  for (uint k=0; k<uint(mask->values.count()); k++) {
+    AddressRangeVector rv = protection.extractRanges(mask->values[k].name, MemoryRangeType::Code);
+    if ( !rv.isEmpty() ) return rv[0];
+  }
+  Q_ASSERT(false);
+  return AddressRange();
+}
+
+AddressRange Pic::Memory::blockRange(uint i) const
+{
+  const Protection &protection = device().config().protection();
+  Q_ASSERT( i<protection.nbBlocks() );
+  if ( protection.family()==Protection::CodeGuard && i==1 ) { // general segment
+    AddressRange previous = blockRange(0);
+    if ( previous.isEmpty() ) previous = bootRange();
+    Address start = (previous.isEmpty() ? device().range(MemoryRangeType::Code).start : previous.end + 1);
+    return AddressRange(start, device().range(MemoryRangeType::Code).end);
+  }
+  QString maskName = protection.blockSizeMaskName(i);
+  if ( protection.family()==Protection::CodeGuard ) { // secure segment
+    QString value = findValue(maskName);
+    Q_ASSERT( !value.isEmpty() );
+    uint size = value.toUInt();
+    if ( size==0 ) return AddressRange();
+    AddressRange previous = bootRange();
+    Address start = (previous.isEmpty() ? device().range(MemoryRangeType::Code).start : previous.end + 1);
+    return AddressRange(start, 2 * size - 1);
+  }
+  AddressRange previous = (i==0 ? bootRange() : blockRange(i-1));
+  const Config::Mask *mask = device().config().findMask(maskName);
+  for (uint k=0; k<uint(mask->values.count()); k++) {
+    AddressRangeVector rv = protection.extractRanges(mask->values[k].name, MemoryRangeType::Code);
+    if ( !rv.isEmpty() ) return AddressRange(previous.end + 1, rv[0].end);
+  }
+  Q_ASSERT(false);
+  return AddressRange();
+}
+
+AddressRange Pic::Memory::bootProtectedRange(Protection::Type ptype) const
+{
+  const Protection &protection = device().config().protection();
+  QString maskName = protection.bootMaskName(ptype);
+  QString value = findValue(maskName);
+  if ( value.isEmpty() ) return AddressRange();
+  if ( protection.family()!=Protection::CodeGuard ) {
+    if ( protection.extractRanges(value, MemoryRangeType::Code).isEmpty() ) return AddressRange();
+  } else {
+    if ( value!=protection.securityValueName(ptype) ) return AddressRange();
+  }
+  return bootRange();
+}
+
+AddressRange Pic::Memory::blockProtectedRange(Protection::Type ptype, uint i) const
+{
+  const Protection &protection = device().config().protection();
+  QString maskName = protection.blockMaskName(ptype, i);
+  QString value = findValue(maskName);
+  if ( value.isEmpty() ) return AddressRange();
+  if ( protection.family()!=Protection::CodeGuard ) {
+    if ( protection.extractRanges(value, MemoryRangeType::Code).isEmpty() ) return AddressRange();
+  } else {
+    if ( value!=protection.securityValueName(ptype) ) return AddressRange();
+  }
+  return blockRange(i);
+}
+
+AddressRangeVector Pic::Memory::protectedRanges(Protection::Type ptype, MemoryRangeType type) const
+{
+  const Protection &protection = device().config().protection();
+  AddressRangeVector rv;
+  if ( type==MemoryRangeType::Code ) {
+    if ( protection.hasBootBlock() ) rv.append(bootProtectedRange(ptype));
+    if ( protection.nbBlocks()!=0 ) {
+      for (uint i=0; i<protection.nbBlocks(); i++) rv.append(blockProtectedRange(ptype, i));
+      return rv;
+    }
+  }
+  if ( protection.family()!=Protection::CodeGuard ) {
+    QString maskName = protection.maskName(ptype, type);
+    QString value = findValue(maskName);
+    //qDebug("%s %s", maskName.latin1(), value.latin1());
+    if ( !value.isEmpty() ) {
+      AddressRangeVector tmp = protection.extractRanges(value, type);
+      Q_ASSERT( tmp.count()==1 );
+      rv.append(tmp[0]);
+    }
+  }
+  return rv;
+}
+
+void Pic::Memory::setBootProtection(bool on, Protection::Type ptype)
+{
+  QString maskName = device().config().protection().bootMaskName(ptype);
+  setProtection(on, maskName, ptype);
+}
+
+void Pic::Memory::setBlockProtection(bool on, Protection::Type ptype, uint block)
+{
+  QString maskName = device().config().protection().blockMaskName(ptype, block);
+  setProtection(on, maskName, ptype);
+}
+
+void Pic::Memory::setProtection(bool on, Protection::Type ptype, MemoryRangeType type)
+{
+  const Protection &protection = device().config().protection();
+  if ( type==MemoryRangeType::Code ) {
+    if ( protection.hasBootBlock() ) setBootProtection(on, ptype);
+    if ( protection.nbBlocks()!=0 ) {
+      for (uint i=0; i<protection.nbBlocks(); i++) setBlockProtection(on, ptype, i);
+      return;
+    }
+  }
+  setProtection(on, protection.maskName(ptype, type), ptype);
+}
+
+void Pic::Memory::setConfigValue(const QString &maskName, const QString &valueName)
+{
+  uint i;
+  const Config::Mask *mask = device().config().findMask(maskName, &i);
+  Q_ASSERT(mask);
+  BitValue v = word(MemoryRangeType::Config, i);
+  v = v.clearMaskBits(mask->value);
+  for (int k=mask->values.count()-1; k>=0; k--) { // important to get the highest value in case of identical values
+    if ( mask->values[k].name!=valueName ) continue;
+    setWord(MemoryRangeType::Config, i, v | mask->values[k].value);
+    return;
+  }
+  Q_ASSERT(false);
+}
+
+void Pic::Memory::setProtection(bool on, const QString &maskName, Protection::Type ptype)
+{
+  const Config::Mask *mask = device().config().findMask(maskName, 0);
+  if( mask==0 ) return;
+  const Protection &protection = device().config().protection();
+  QString valueName;
+  if ( ptype==Protection::StandardSecurity || ptype==Protection::HighSecurity )
+    valueName = protection.securityValueName(ptype);
+  else {
+    for (int k=mask->values.count()-1; k>=0; k--) {
+      if ( (on && protection.isAllProtectedValueName(mask->values[k].name))
+           || (!on && protection.isNoneProtectedValueName(mask->values[k].name)) ) valueName = mask->values[k].name;
+    }
+  }
+  setConfigValue(maskName, valueName);
+}
+
+bool Pic::Memory::hasFlagOn(const QString &maskName, bool valueIfNotPresent) const
+{
+  const Config::Mask *mask = device().config().findMask(maskName, 0);
+  if ( mask==0 ) return valueIfNotPresent;
+  Q_ASSERT(mask);
+  Q_ASSERT( mask->values.count()==2 );
+  return ( findValue(maskName)=="On" );
+}
+
+void Pic::Memory::setFlagOn(const QString &maskName, bool on)
+{
+  const Config::Mask *mask = device().config().findMask(maskName, 0);
+  Q_UNUSED(mask);
+  Q_ASSERT(mask);
+  Q_ASSERT( mask->values.count()==2 );
+  setConfigValue(maskName, on ? "On" : "Off");
+}
+
+void Pic::Memory::checksumCheckFill()
+{
+  clear();
+  switch (device().architecture().type()) {
+    case Architecture::P10X:
+      setWord(MemoryRangeType::Code, device().range(MemoryRangeType::Code).start.toUInt(), 0x723);
+      setWord(MemoryRangeType::Code, device().range(MemoryRangeType::Code).end.toUInt(), 0x723);
+      break;
+    case Architecture::P16X:
+      if ( device().name()=="16F72" || device().name()=="16F73" || device().name()=="16F74" || device().name()=="16F76" || device().name()=="16F77"
+           || device().name()=="16CR73" || device().name()=="16CR74" || device().name()=="16CR76" || device().name()=="16CR77" ) {
+        setWord(MemoryRangeType::Code, device().range(MemoryRangeType::Code).start.toUInt(), 0x05E6);
+        setWord(MemoryRangeType::Code, device().range(MemoryRangeType::Code).end.toUInt(), 0x05E6);
+      } else {
+        setWord(MemoryRangeType::Code, device().range(MemoryRangeType::Code).start.toUInt(), 0x25E6);
+        setWord(MemoryRangeType::Code, device().range(MemoryRangeType::Code).end.toUInt(), 0x25E6);
+      }
+      break;
+    case Architecture::P17C:
+      setWord(MemoryRangeType::Code, device().range(MemoryRangeType::Code).start.toUInt(), 0xC0DE);
+      setWord(MemoryRangeType::Code, device().range(MemoryRangeType::Code).end.toUInt(), 0xC0DE);
+      break;
+    case Architecture::P18C:
+    case Architecture::P18F:
+    case Architecture::P18J:
+      setWord(MemoryRangeType::Code, device().range(MemoryRangeType::Code).start.toUInt()/2, 0xAAFF);
+      setWord(MemoryRangeType::Code, device().range(MemoryRangeType::Code).end.toUInt()/2, 0xFFAA);
+      break;
+    case Architecture::P24F:
+    case Architecture::P24H:
+    case Architecture::P30F:
+    case Architecture::P33F:
+      setWord(MemoryRangeType::Code, device().range(MemoryRangeType::Code).start.toUInt(), 0xAAAAAA);
+      setWord(MemoryRangeType::Code, device().range(MemoryRangeType::Code).end.toUInt(), 0xAAAAAA);
+      break;
+    case Architecture::Nb_Types: Q_ASSERT(false); break;
+  }
+}
+
+BitValue Pic::Memory::checksum() const
+{
+  // code
+  BitValue mask = device().mask(MemoryRangeType::Code);
+  AddressRangeVector rv = protectedRanges(Protection::ProgramProtected, MemoryRangeType::Code);
+  bool isProtected = !rv.isEmpty();
+  uint inc = device().addressIncrement(MemoryRangeType::Code);
+  //uint nbChars = device().nbCharsWord(MemoryRangeType::Code);
+  //qDebug("protected: %i  nb: %s (%s)", isProtected, toHexLabelAbs(inc*device().nbWords(MemoryRangeType::Code)).latin1(), toHexLabel(mask, nbChars).latin1());
+  //for (uint i=0; i<rv.count(); i++)
+  //  qDebug("protected: %s:%s", toHex(rv[i].start, nbChars).latin1(), toHex(rv[i].end, nbChars).latin1());
+  if ( isProtected && (device().architecture()==Pic::Architecture::P18J || device().architecture()==Pic::Architecture::P24F) )
+    return 0x0000;
+  Checksum::Algorithm algorithm = Checksum::Algorithm::Normal;
+  BitValue cs = 0x0000;
+  const Protection &protection = device().config().protection();
+  if ( protection.family()==Protection::BasicProtection ) {
+    QString maskName = protection.maskName(Protection::ProgramProtected, MemoryRangeType::Code);
+    QString valueName = findValue(maskName);
+    const QMap<QString, Checksum::Data> &checksums = device().checksums();
+    if ( checksums.contains(valueName) ) { // #### REMOVE ME !!
+      algorithm = checksums[valueName].algorithm;
+      cs = checksums[valueName].constant;
+    }
+  }
+  //qDebug("constant: %s", toHexLabelAbs(cs).data());
+  //qDebug("algo: %s", Checksum::ALGORITHM_DATA[algorithm].name);
+  for (uint i=0; i<device().nbWords(MemoryRangeType::Code); i++) {
+    if ( algorithm==Checksum::Algorithm::Normal && rv.contains(inc*i) ) continue;
+    BitValue v = word(MemoryRangeType::Code, i).maskWith(mask);
+    //if ( i==0 || i==device().nbWords(MemoryRangeType::Code)-1 ) qDebug("%s %s", toHexLabel(i, 4).latin1(), toHexLabel(v, 4).latin1());
+    switch (device().architecture().type()) {
+      case Architecture::P10X:
+      case Architecture::P16X:
+      case Architecture::P17C:
+        if ( rv.contains(i) ) {
+          switch (algorithm.type()) {
+            case Checksum::Algorithm::Normal: cs += v;           break;
+            case Checksum::Algorithm::XOR4:   cs += v.XORn(4);  break;
+            case Checksum::Algorithm::XNOR7:  cs += v.XNORn(7); break;
+            case Checksum::Algorithm::XNOR8:  cs += v.XNORn(8) + (v.XNORn(8) << 8); break;
+            case Checksum::Algorithm::Nb_Types: Q_ASSERT(false); break;
+          }
+        } else cs += v;
+        break;
+      case Architecture::P18C:
+      case Architecture::P18F: // #### not true for all 18F ??
+      case Architecture::P18J:
+        cs += v.byte(0) + v.byte(1);
+        break;
+      case Architecture::P24F:
+      case Architecture::P24H:
+      case Architecture::P30F:
+      case Architecture::P33F:
+        cs += v.byte(0) + v.byte(1) + v.byte(2);
+        break;
+      case Architecture::Nb_Types: Q_ASSERT(false); break;
+    }
+  }
+  //qDebug("after code: %s", toHexLabelAbs(cs).latin1());
+  // config
+  const Config &config = device().config();
+  for (uint i=0; i<uint(config._words.count()); i++) {
+    const Config::Word &cword = config._words[i];
+    BitValue v = word(MemoryRangeType::Config, i).maskWith(cword.cmask);
+    //uint nbChars = device().nbCharsWord(MemoryRangeType::Config);
+    // qDebug("%i: %s %s", i, toHex(word(MemoryRangeType::Config, i), nbChars).latin1(), toHex(cword.cmask, nbChars).latin1());
+    if ( ( device().name()=="16C61" || device().name()=="16C71" ) && isProtected ) cs += v | 0x0060;
+    else if ( device().is16bitFamily() ) cs += v.byte(0) + v.byte(1);
+    else cs += v;
+  }
+  //qDebug("after config: %s", toHexLabelAbs(cs).latin1());
+  // user ids
+  if ( isProtected && device().isPresent(MemoryRangeType::UserId) && !device().is16bitFamily() && algorithm==Checksum::Algorithm::Normal ) {
+    BitValue id = 0x0;
+    uint nb = device().nbWords(MemoryRangeType::UserId);
+    for (uint i=0; i<nb; i++) {
+      BitValue v = word(MemoryRangeType::UserId, nb-i-1).maskWith(0xF);
+      if ( device().is18Family() ) id += v;
+      else {
+        // qDebug("id %i (%i): %s %s", i, nbb, toHex(v, 4).latin1(), toHex(v << (nbb*i), 9).latin1());
+        id += v << (4*i);
+      }
+    }
+    //qDebug("id %s", toHexLabelAbs(id).latin1());
+    cs += id;
+  }
+  //qDebug("checksum: %s %s", toHexLabelAbs(cs).latin1(), toHex(cs & 0xFFFF, 4).latin1());
+  return cs.maskWith(0xFFFF);
+}
+
+BitValue Pic::Memory::unprotectedChecksum() const
+{
+  const Protection &protection = device().config().protection();
+  Memory tmp(*this);
+  if ( protection.hasBootBlock() ) tmp.setBootProtection(false, Protection::ProgramProtected);
+  if ( protection.nbBlocks()!=0 ) {
+    for (uint i=0; i<protection.nbBlocks(); i++)
+      tmp.setBlockProtection(false, Protection::ProgramProtected, i);
+  } else tmp.setProtection(false, Protection::ProgramProtected, MemoryRangeType::Code);
+  tmp.setProtection(false, Protection::ProgramProtected, MemoryRangeType::Eeprom);
+  tmp.setProtection(false, Protection::ProgramProtected, MemoryRangeType::Config);
+  tmp.setProtection(false, Protection::ProgramProtected, MemoryRangeType::Cal);
+  return tmp.checksum();
+}
+
+void Pic::Memory::setUserIdToUnprotectedChecksum()
+{
+  BitValue cs = unprotectedChecksum();
+  uint nb = device().nbWords(MemoryRangeType::UserId);
+  for (uint i=0; i<nb; i++) setWord(MemoryRangeType::UserId, nb-i-1, cs.nybble(i));
+}
+
+//-----------------------------------------------------------------------------
+void Pic::Memory::savePartial(QTextStream &stream, HexBuffer::Format format) const
+{
+  // save memory ranges in the same order as MPLAB (for easy checking)
+  const MemoryRangeType saveOrder[] = { MemoryRangeType::Code, MemoryRangeType::Eeprom, MemoryRangeType::Config, MemoryRangeType::UserId, MemoryRangeType::Cal, MemoryRangeType::Nb_Types };
+  HexBuffer hb;
+  for (uint i=0; saveOrder[i]!=MemoryRangeType::Nb_Types; i++) {
+    hb.clear();
+    toHexBuffer(saveOrder[i], hb);
+    hb.savePartial(stream, format);
+  }
+}
+
+//-----------------------------------------------------------------------------
+void Pic::Memory::toHexBuffer(MemoryRangeType type, HexBuffer &hb) const
+{
+  if ( !device().isWritable(type) ) return;
+  uint nbBytes = device().architecture().data().nbBytesWord;
+  bool packed = device().architecture().data().packed;
+  uint offset = device().range(type).hexFileOffset;
+  if ( offset==0 ) offset = device().range(type).start.toUInt();
+  BitValue mask = device().mask(type);
+  uint wNbBytes = nbBytes;
+  if ( packed && type!=Pic::MemoryRangeType::Code ) {
+    offset /= 2;
+    wNbBytes /= 2;
+  }
+  uint byte = 0;
+  uint wOffset = 0;
+  uint wByte = 0;
+  //qDebug("%s wnb=%i snb=%i div=%i", MEMORY_RANGE_TYPE_DATA[type].label, wNbBytes, sNbBytes, div);
+  for (uint k=0; k<wNbBytes*device().nbWords(type); k++) {
+    // set byte
+    BitValue s = _ranges[type][wOffset].maskWith(mask);
+    //if ( k<4 ) qDebug("s=%s so=%s sb=%i wo=%i wb=%i", toHex(s, 8).data(), toHex(sOffset, 8).data(), sByte, wOffset, wByte);
+    s = s.byte(wByte);
+    if ( (byte%2)==0 ) hb.insert(offset, s);
+    else hb.insert(offset, hb[offset] | (s << ((byte%2)*8)));
+    // increment offsets
+    byte++;
+    if ( (byte%nbBytes)==0 ) {
+      byte = 0;
+      offset++;
+    } else if ( byte==2 ) offset++;
+    wByte++;
+    if ( (wByte%wNbBytes)==0 ) {
+      wByte = 0;
+      wOffset++;
+    }
+  }
+}
+
+HexBuffer Pic::Memory::toHexBuffer() const
+{
+  HexBuffer hb;
+  FOR_EACH(MemoryRangeType, i) toHexBuffer(i, hb);
+  return hb;
+}
+
+void Pic::Memory::fromHexBuffer(MemoryRangeType type, const HexBuffer &hb, WarningTypes &result,
+                                QStringList &warnings, QMap<uint, bool> &inRange)
+{
+  if ( !device().isWritable(type) ) return;
+  uint nbBytes = device().architecture().data().nbBytesWord;
+  bool packed = device().architecture().data().packed;
+  uint offset = device().range(type).hexFileOffset;
+  if ( offset==0 ) offset = device().range(type).start.toUInt();
+  BitValue mask = device().mask(type);
+  uint wNbBytes = nbBytes;
+  if ( packed && type!=Pic::MemoryRangeType::Code ) {
+    offset /= 2;
+    wNbBytes /= 2;
+  }
+  uint byte = 0;
+  uint wOffset = 0;
+  uint wByte = 0;
+  //qDebug("%s wnb=%i snb=%i", MEMORY_RANGE_TYPE_DATA[type].label, wNbBytes, nbBytes);
+  for (uint k=0; k<wNbBytes*device().nbWords(type); k++) {
+    // set byte
+    BitValue s = hb[offset];
+    //if ( k<4 ) qDebug("s=%s so=%s sb=%i wo=%i wb=%i", toHex(s, 8).data(), toHex(offset, 8).data(), byte, wOffset, wByte);
+    if ( !s.isInitialized() ) {
+      if ( type==MemoryRangeType::Config ) _ranges[type][wOffset] = mask;
+      else _ranges[type][wOffset] = BitValue();
+    } else {
+      inRange[offset] = true;
+      s = s.byte(byte%2);
+      if ( wByte==0 ) _ranges[type][wOffset] = s;
+      else _ranges[type][wOffset] |= (s << (wByte*8));
+    }
+    // increment offsets
+    byte++;
+    if ( (byte%nbBytes)==0 ) {
+      byte = 0;
+      offset++;
+    } else if ( byte==2 ) offset++;
+    wByte++;
+    if ( (wByte%wNbBytes)==0 ) {
+      if ( _ranges[type][wOffset].isInitialized() ) {
+        if ( !(result & ValueTooLarge) && _ranges[type][wOffset].maskWith(mask)!=_ranges[type][wOffset] ) {
+          result |= ValueTooLarge;
+          warnings += i18n("At least one word (at offset %1) is larger (%2) than the corresponding mask (%3).")
+                      .arg(toHexLabel(offset, 8)).arg(toHexLabel(_ranges[type][wOffset], 8)).arg(toHexLabel(mask, 8));
+        }
+        _ranges[type][wOffset] = _ranges[type][wOffset].maskWith(mask);
+      }
+      wByte = 0;
+      wOffset++;
+    }
+  }
+}
+
+void Pic::Memory::fromHexBuffer(const HexBuffer &hb, WarningTypes &result,
+                                QStringList &warnings, QMap<uint, bool> &inRange)
+{
+  FOR_EACH(MemoryRangeType, i) fromHexBuffer(i, hb, result, warnings, inRange);
+}
diff --git a/src/devices/pic/pic/pic_memory.h b/src/devices/pic/pic/pic_memory.h
new file mode 100644
index 0000000..f7c98ba
--- /dev/null
+++ b/src/devices/pic/pic/pic_memory.h
@@ -0,0 +1,80 @@
+/***************************************************************************
+ *   Copyright (C) 2005 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_MEMORY_H
+#define PIC_MEMORY_H
+
+#include "common/global/global.h"
+#include "devices/base/generic_memory.h"
+#include "devices/base/hex_buffer.h"
+#include "devices/pic/base/pic_config.h"
+
+namespace Pic
+{
+
+class Memory : public Device::Memory
+{
+public:
+  Memory(const Data &data);
+  const Data &device() const { return static_cast<const Data &>(_device); }
+  virtual void fill(BitValue value);
+  void checksumCheckFill(); // a special memory fill for checksum check (cf datasheets)
+  virtual void fill(MemoryRangeType type, BitValue value);
+  virtual void clear() { Device::Memory::clear(); }
+  bool isClear(MemoryRangeType type) const;
+  void clear(MemoryRangeType type) { fill(type, BitValue()); }
+  Device::Array arrayForWriting(MemoryRangeType type) const;
+  BitValue word(MemoryRangeType type, uint offset) const;
+  BitValue normalizeWord(MemoryRangeType type, uint offset, BitValue value) const;
+  BitValue normalizedWord(MemoryRangeType type, uint offset) const;
+  void setWord(MemoryRangeType type, uint offset, BitValue value);
+  void setArray(MemoryRangeType type, const Device::Array &array);
+
+  AddressRange bootRange() const;
+  AddressRange blockRange(uint i) const;
+  bool isBootProtected(Protection::Type ptype) const { return !bootProtectedRange(ptype).isEmpty(); }
+  bool isBlockProtected(Protection::Type ptype, uint i) const { return !blockProtectedRange(ptype, i).isEmpty(); }
+  bool isProtected(Protection::Type ptype, MemoryRangeType type) const { return !protectedRanges(ptype, type).isEmpty(); }
+  AddressRangeVector protectedRanges(Protection::Type ptype, MemoryRangeType type) const;
+  void setConfigValue(const QString &maskName, const QString &valueName);
+  bool hasDebugOn() const { return hasFlagOn("DEBUG", false); }
+  void setDebugOn(bool on) { setFlagOn("DEBUG", on); }
+  bool hasWatchdogTimerOn() const { return hasFlagOn("WDT", false); }
+  void setWatchdogTimerOn(bool on) { return setFlagOn("WDT", on); }
+  void setBootProtection(bool on, Protection::Type ptype);
+  void setBlockProtection(bool on, Protection::Type ptype, uint block);
+  void setProtection(bool on, Protection::Type ptype, MemoryRangeType type);
+
+  virtual BitValue checksum() const;
+  BitValue unprotectedChecksum() const;
+  void setUserIdToUnprotectedChecksum();
+
+  virtual HexBuffer toHexBuffer() const;
+  virtual void copyFrom(const Device::Memory &memory);
+  void copyFrom(MemoryRangeType type, const Memory &memory);
+  void fromHexBuffer(MemoryRangeType type, const HexBuffer &hb, WarningTypes &warningTypes,
+                     QStringList &warnings, QMap<uint, bool> &inRange);
+
+private:
+  QMap<MemoryRangeType, Device::Array> _ranges;
+
+  void toHexBuffer(MemoryRangeType type, HexBuffer &hb) const;
+  virtual void savePartial(QTextStream &stream, HexBuffer::Format format) const;
+  virtual void fromHexBuffer(const HexBuffer &hb, WarningTypes &warningTypes,
+                             QStringList &warnings, QMap<uint, bool> &inRange);
+  QString findValue(const QString &maskName) const;
+  bool hasFlagOn(const QString &maskName, bool valueIfNotPresent) const;
+  void setFlagOn(const QString &maskName, bool on);
+  void setProtection(bool on, const QString &maskName, Protection::Type ptype);
+  AddressRange bootProtectedRange(Protection::Type ptype) const;
+  AddressRange blockProtectedRange(Protection::Type ptype, uint block) const;
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/pic/prog/Makefile.am b/src/devices/pic/prog/Makefile.am
new file mode 100644
index 0000000..055d2cd
--- /dev/null
+++ b/src/devices/pic/prog/Makefile.am
@@ -0,0 +1,5 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+noinst_LTLIBRARIES = libpicprog.la
+libpicprog_la_SOURCES = pic_prog.cpp pic_prog_specific.cpp pic_debug.cpp
diff --git a/src/devices/pic/prog/pic_debug.cpp b/src/devices/pic/prog/pic_debug.cpp
new file mode 100644
index 0000000..443bb10
--- /dev/null
+++ b/src/devices/pic/prog/pic_debug.cpp
@@ -0,0 +1,118 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_debug.h"
+
+#include "common/common/misc.h"
+#include "devices/pic/base/pic_register.h"
+#include "progs/manager/debug_manager.h"
+
+//----------------------------------------------------------------------------
+Register::TypeData Debugger::PicBase::registerTypeData(const QString &name) const
+{
+  const Pic::RegistersData &rdata = device()->registersData();
+  Q_ASSERT(rdata.sfrs.contains(name));
+  return Register::TypeData(rdata.sfrs[name].address, rdata.nbChars());
+}
+
+bool Debugger::PicBase::updatePortStatus(uint index, QMap<uint, Device::PortBitData> &bits)
+{
+  const Pic::RegistersData &rdata = device()->registersData();
+  BitValue tris;
+  if ( rdata.hasTris(index) ) {
+    tris = Register::list().value(registerTypeData(rdata.trisName(index)));
+    Q_ASSERT( tris.isInitialized() );
+  }
+  BitValue port = Register::list().value(registerTypeData(rdata.portName(index)));
+  Q_ASSERT( port.isInitialized() );
+  BitValue latch;
+  if ( rdata.hasLatch(index) ) {
+    latch = Register::list().value(registerTypeData(rdata.latchName(index)));
+    Q_ASSERT( latch.isInitialized() );
+  }
+  for (uint i=0; i<Device::MAX_NB_PORT_BITS; i++) {
+    if ( !rdata.hasPortBit(index, i) ) continue;
+    bits[i].state = Device::Unknown;
+    bits[i].drivenState = Device::IoUnknown;
+    bits[i].drivingState = Device::IoUnknown;
+    if ( tris.isInitialized() ) {
+      bits[i].driving = !tris.bit(i);
+      if (bits[i].driving) {
+        bits[i].drivenState = Device::IoUnknown;
+        bits[i].drivingState = (port.bit(i) ? Device::IoHigh : Device::IoLow);
+      } else {
+        bits[i].drivenState = (port.bit(i) ? Device::IoHigh : Device::IoLow);
+        if ( latch.isInitialized() ) bits[i].drivingState = (latch.bit(i) ? Device::IoHigh : Device::IoLow);
+        else bits[i].drivingState = Device::IoUnknown;
+      }
+    }
+  }
+  return true;
+}
+
+//----------------------------------------------------------------------------
+Debugger::PicBase &Debugger::PicSpecific::base()
+{
+  return static_cast<PicBase &>(_base);
+}
+const Debugger::PicBase &Debugger::PicSpecific::base() const
+{
+  return static_cast<PicBase &>(_base);
+}
+
+bool Debugger::PicSpecific::updateStatus()
+{
+  if ( !Debugger::manager->readRegister(base().pcTypeData()) ) return false;
+  if ( !Debugger::manager->readRegister(base().registerTypeData("STATUS")) ) return false;
+  if ( !Debugger::manager->readRegister(wregTypeData()) ) return false;
+  return true;
+}
+
+//----------------------------------------------------------------------------
+Register::TypeData Debugger::P16FSpecific::wregTypeData() const
+{
+  return Register::TypeData("WREG", device().registersData().nbChars());
+}
+
+QString Debugger::P16FSpecific::statusString() const
+{
+  const Pic::RegistersData &rdata = device().registersData();
+  BitValue status = Register::list().value(base().registerTypeData("STATUS"));
+  uint bank = (status.bit(5) ? 1 : 0) + (status.bit(6) ? 2 : 0);
+  BitValue wreg = Register::list().value(wregTypeData());
+  return QString("W:%1   %2 %3 %4   PC:%5   Bank:%6")
+         .arg(toHexLabel(wreg, rdata.nbChars())).arg(status.bit(2) ? "Z" : "z")
+         .arg(status.bit(1) ? "DC" : "dc").arg(status.bit(0) ? "C" : "c")
+         .arg(toHexLabel(_base.pc(), device().nbCharsAddress())).arg(bank);
+}
+
+//----------------------------------------------------------------------------
+bool Debugger::P18FSpecific::updateStatus()
+{
+  if ( !PicSpecific::updateStatus() ) return false;
+  if ( !Debugger::manager->readRegister(base().registerTypeData("BSR")) ) return false;
+  return true;
+}
+
+Register::TypeData Debugger::P18FSpecific::wregTypeData() const
+{
+  return base().registerTypeData("WREG");
+}
+
+QString Debugger::P18FSpecific::statusString() const
+{
+  const Pic::RegistersData &rdata = device().registersData();
+  BitValue status = Register::list().value(base().registerTypeData("STATUS"));
+  BitValue bsr = Register::list().value(base().registerTypeData("BSR"));
+  BitValue wreg = Register::list().value(wregTypeData());
+  return QString("W:%1   %2 %3 %4 %5 %6  PC:%7   Bank:%8")
+         .arg(toHexLabel(wreg, rdata.nbChars())).arg(status.bit(4) ? "N" : "n")
+         .arg(status.bit(3) ? "OV" : "ov").arg(status.bit(2) ? "Z" : "z")
+         .arg(status.bit(1) ? "DC" : "dc").arg(status.bit(0) ? "C" : "c")
+         .arg(toHexLabel(base().pc(), device().nbCharsAddress())).arg(toLabel(bsr));
+}
diff --git a/src/devices/pic/prog/pic_debug.h b/src/devices/pic/prog/pic_debug.h
new file mode 100644
index 0000000..dfb8af6
--- /dev/null
+++ b/src/devices/pic/prog/pic_debug.h
@@ -0,0 +1,65 @@
+/***************************************************************************
+ *   Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_DEBUG_H
+#define PIC_DEBUG_H
+
+#include "progs/base/generic_debug.h"
+#include "pic_prog.h"
+#include "devices/base/register.h"
+
+namespace Debugger
+{
+class PicBase;
+
+//----------------------------------------------------------------------------
+class PicSpecific : public DeviceSpecific
+{
+public:
+  PicSpecific(Debugger::Base &base) : DeviceSpecific(base) {}
+  const Pic::Data &device() const { return static_cast<const Pic::Data &>(*_base.device()); }
+  PicBase &base();
+  const PicBase &base() const;
+  virtual bool updateStatus();
+  virtual Register::TypeData wregTypeData() const = 0;
+};
+
+//----------------------------------------------------------------------------
+class P16FSpecific : public PicSpecific
+{
+public:
+  P16FSpecific(Debugger::Base &base) : PicSpecific(base) {}
+  virtual QString statusString() const;
+  virtual Register::TypeData wregTypeData() const;
+};
+
+//----------------------------------------------------------------------------
+class P18FSpecific : public PicSpecific
+{
+public:
+  P18FSpecific(Debugger::Base &base) : PicSpecific(base) {}
+  virtual QString statusString() const;
+  virtual bool updateStatus();
+  virtual Register::TypeData wregTypeData() const;
+};
+
+//----------------------------------------------------------------------------
+class PicBase : public Debugger::Base
+{
+public:
+  PicBase(Programmer::PicBase &base) : Debugger::Base(base) {}
+  PicSpecific *deviceSpecific() { return static_cast<PicSpecific *>(_deviceSpecific); }
+  const PicSpecific *deviceSpecific() const { return static_cast<const PicSpecific *>(_deviceSpecific); }
+  const Pic::Data *device() const { return static_cast<const Pic::Data *>(Debugger::Base::device()); }
+  Register::TypeData registerTypeData(const QString &name) const;
+  virtual bool updatePortStatus(uint index, QMap<uint, Device::PortBitData> &bits);
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/pic/prog/pic_prog.cpp b/src/devices/pic/prog/pic_prog.cpp
new file mode 100644
index 0000000..bc7dcd1
--- /dev/null
+++ b/src/devices/pic/prog/pic_prog.cpp
@@ -0,0 +1,751 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_prog.h"
+
+#include "common/global/global.h"
+#include "devices/list/device_list.h"
+#include "progs/base/prog_config.h"
+#include "progs/base/prog_group.h"
+#include "pic_debug.h"
+
+//-----------------------------------------------------------------------------
+bool Programmer::PicGroup::canReadVoltages() const
+{
+  for (uint i=0; i<Pic::Nb_VoltageTypes; i++)
+    if ( canReadVoltage(Pic::VoltageType(i)) ) return true;
+  return false;
+}
+
+Debugger::DeviceSpecific *Programmer::PicGroup::createDebuggerDeviceSpecific(::Debugger::Base &base) const
+{
+  const Pic::Data *data = static_cast<const Pic::Data *>(base.device());
+  if ( data==0 ) return 0;
+  switch (data->architecture().type()) {
+    case Pic::Architecture::P10X:
+    case Pic::Architecture::P16X: return new ::Debugger::P16FSpecific(base);
+    case Pic::Architecture::P18C:
+    case Pic::Architecture::P18F:
+    case Pic::Architecture::P18J: return new ::Debugger::P18FSpecific(base);
+    case Pic::Architecture::P24F:
+    case Pic::Architecture::P24H:
+    case Pic::Architecture::P30F:
+    case Pic::Architecture::P33F:
+    case Pic::Architecture::P17C:
+    case Pic::Architecture::Nb_Types: break;
+  }
+  Q_ASSERT(false);
+  return 0;
+}
+
+//-----------------------------------------------------------------------------
+Programmer::PicBase::PicBase(const Group &group, const Pic::Data *data, const char *name)
+  : Base(group, data, name), _deviceMemory(0), _hasProtectedCode(false), _hasProtectedEeprom(false)
+{
+  if (data) _deviceMemory = new Pic::Memory(*data);
+}
+
+Programmer::PicBase::~PicBase()
+{
+  delete _deviceMemory;
+}
+
+void Programmer::PicBase::clear()
+{
+  ::Programmer::Base::clear();
+  for (uint i=0; i<Pic::Nb_VoltageTypes; i++) {
+    _voltages[i].error = false;
+    _voltages[i].value = UNKNOWN_VOLTAGE;
+  }
+}
+
+uint Programmer::PicBase::nbSteps(Task task, const Device::MemoryRange *range) const
+{
+  const Pic::MemoryRange *prange = static_cast<const Pic::MemoryRange *>(range);
+  switch (task.type()) {
+    case Task::Erase: return 1;
+    case Task::Read:
+    case Task::Verify:
+    case Task::BlankCheck: {
+      uint nb = 0;
+      FOR_EACH(Pic::MemoryRangeType, type) {
+        if ( type!=Pic::MemoryRangeType::Code && type!=Pic::MemoryRangeType::Eeprom ) continue;
+        if ( !device()->isReadable(type) || !specific()->canReadRange(type) ) continue;
+        if ( !prange->all() && prange->_type!=type ) continue;
+        nb += device()->nbWords(type);
+      }
+      return QMAX(nb, uint(1));
+    }
+    case Task::Write: {
+      uint nb = 0;
+      FOR_EACH(Pic::MemoryRangeType, type) {
+        if ( type!=Pic::MemoryRangeType::Code && type!=Pic::MemoryRangeType::Eeprom ) continue;
+        if ( !device()->isWritable(type) || !specific()->canWriteRange(type) ) continue;
+        if ( !prange->all() && prange->_type!=type ) continue;
+        nb += device()->nbWords(type);
+        if ( readConfigEntry(Config::VerifyAfterProgram).toBool() ) nb += device()->nbWords(type);
+      }
+      return QMAX(nb, uint(1));
+    }
+    case Task::Nb_Types: break;
+  }
+  Q_ASSERT(false);
+  return 0;
+}
+
+bool Programmer::PicBase::readVoltages()
+{
+  if ( !hardware()->readVoltages(_voltages) ) return false;
+  bool ok = true;
+  for (uint i=0; i<Pic::Nb_VoltageTypes; i++) {
+    if ( !group().canReadVoltage(Pic::VoltageType(i)) ) continue;
+    if ( _voltages[i].error==true ) {
+      ok = false;
+      log(Log::LineType::Error, i18n("  %1 = %2 V: error in voltage level.").arg(i18n(Pic::VOLTAGE_TYPE_LABELS[i])).arg(_voltages[i].value));
+    } else if ( _voltages[i].value!=UNKNOWN_VOLTAGE )
+      log(Log::DebugLevel::Normal, QString("  %1 = %2 V").arg(i18n(Pic::VOLTAGE_TYPE_LABELS[i])).arg(_voltages[i].value));
+  }
+  return ok;
+}
+
+bool Programmer::PicBase::internalSetupHardware()
+{
+  if ( !Base::internalSetupHardware() ) return false;
+  if ( group().properties() & ::Programmer::CanReleaseReset ) {
+    log(Log::DebugLevel::Normal, "  Hold reset");
+    if ( !hardware()->setTargetReset(Pic::ResetHeld) ) return false;
+  }
+  Pic::TargetMode mode;
+  if ( !getTargetMode(mode) ) return false;
+  if ( mode!=Pic::TargetInProgramming ) {
+    log(Log::LineType::Error, i18n("Device not in programming"));
+    return false;
+  }
+  return true;
+}
+
+bool Programmer::PicBase::initProgramming(Task)
+{
+/*
+  if ( vpp()!=UNKNOWN_VOLTAGE ) {
+    const Pic::VoltageData &tvpp = device()->voltage(Pic::Vpp);
+    if ( vpp()<tvpp.min )
+      log(Log::LineType::Warning, i18n("Vpp (%1 V) is lower than the minimum required voltage (%2 V).")
+                        .arg(vpp()).arg(tvpp.min));
+    if ( vpp()>tvpp.max ) {
+      QString s = i18n("Vpp (%1 V) is higher than the maximum voltage (%2 V). You may damage the device.")
+                  .arg(vpp()).arg(tvpp.max);
+      log(Log::LineType::Warning, s);
+      if ( !askContinue(s) ) {
+        logUserAbort();
+        return false;
+      }
+    }
+  }
+  if ( vdd()!=UNKNOWN_VOLTAGE ) {
+    Q_ASSERT( type!=Pic::Vpp );
+    const Pic::VoltageData &tvdd = device()->voltage(type);
+    if ( vdd()<tvdd.min ) {
+      if ( type==Pic::VddBulkErase && device()->voltage(Pic::VddWrite).min!=tvdd.min )
+        log(Log::LineType::Warning, i18n("Vdd (%1 V) is too low for high-voltage programming\n(piklab only supports high-voltage programming at the moment).\nMinimum required is %2 V.")
+                          .arg(vdd()).arg(tvdd.min));
+      else if ( type==Pic::VddRead && device()->voltage(Pic::VddWrite).min!=tvdd.min )
+        log(Log::LineType::Warning, i18n("Vdd (%1 V) is too low for reading\nMinimum required is %2 V.")
+                          .arg(vdd()).arg(tvdd.min));
+      else log(Log::LineType::Warning, i18n("Vdd (%1 V) is too low for programming\nMinimum required is %2 V.")
+                            .arg(vdd()).arg(tvdd.min));
+    } else if ( vdd()>tvdd.max ) {
+      QString s = i18n("Vdd (%1 V) is higher than the maximum voltage (%2 V). You may damage the device.")
+                  .arg(vdd()).arg(tvdd.max);
+      log(Log::LineType::Warning, s);
+      if ( !askContinue(s) ) {
+        logUserAbort();
+        return false;
+      }
+    }
+  }
+*/
+  if ( specific()->canReadRange(Pic::MemoryRangeType::Config) ) {
+    // read config
+    Device::Array data;
+    if ( !specific()->read(Pic::MemoryRangeType::Config, data, 0) ) return false;
+    _deviceMemory->setArray(Pic::MemoryRangeType::Config, data);
+    _hasProtectedCode = _deviceMemory->isProtected(Pic::Protection::ProgramProtected, Pic::MemoryRangeType::Code);
+    _hasProtectedEeprom = _deviceMemory->isProtected(Pic::Protection::ProgramProtected, Pic::MemoryRangeType::Eeprom);
+    log(Log::DebugLevel::Normal, QString("  protected: code=%1 data=%2")
+                          .arg(_hasProtectedCode ? "true" : "false").arg(_hasProtectedEeprom ? "true" : "false"));
+    // read calibration
+    if ( !readCalibration() ) return false;
+  }
+
+  return initProgramming();
+}
+
+bool Programmer::PicBase::preserveCode()
+{
+  if ( _hasProtectedCode && !askContinue(i18n("All or part of code memory is protected so it cannot be preserved. Continue anyway?")) )
+    return false;
+  return readRange(Pic::MemoryRangeType::Code, _deviceMemory, 0);
+}
+
+bool Programmer::PicBase::preserveEeprom()
+{
+  if ( _hasProtectedEeprom && !askContinue(i18n("All or part of data EEPROM is protected so it cannot be preserved. Continue anyway?")) )
+    return false;
+  return readRange(Pic::MemoryRangeType::Eeprom, _deviceMemory, 0);
+}
+
+bool Programmer::PicBase::internalRun()
+{
+  _state = ::Programmer::Running;
+  return hardware()->setTargetReset(Pic::ResetReleased);
+}
+
+bool Programmer::PicBase::internalStop()
+{
+  _state = ::Programmer::Stopped;
+  return hardware()->setTargetReset(Pic::ResetHeld);
+}
+
+bool Programmer::PicBase::getTargetMode(Pic::TargetMode &mode)
+{
+  return hardware()->getTargetMode(mode);
+}
+
+bool Programmer::PicBase::initProgramming()
+{
+  _state = ::Programmer::Stopped;
+  return hardware()->setTargetReset(Pic::ResetHeld);
+}
+
+//-----------------------------------------------------------------------------
+BitValue Programmer::PicBase::readDeviceId()
+{
+  Device::Array data;
+  if ( !specific()->read(Pic::MemoryRangeType::DeviceId, data, 0) ) return 0;
+  Q_ASSERT( data.count()!=0 );
+  BitValue id = 0x0;
+  switch (device()->architecture().type()) {
+    case Pic::Architecture::P10X:
+    case Pic::Architecture::P16X:
+    case Pic::Architecture::P17C: id = data[0]; break;
+    case Pic::Architecture::P18C:
+    case Pic::Architecture::P18F:
+    case Pic::Architecture::P18J: id = data[0] | (data[1] << 8); break;
+    case Pic::Architecture::P24F:
+    case Pic::Architecture::P24H:
+    case Pic::Architecture::P30F:
+    case Pic::Architecture::P33F: id = data[1] | (data[0] << 16); break;
+    case Pic::Architecture::Nb_Types: Q_ASSERT(false); break;
+  }
+  return id;
+}
+
+bool Programmer::PicBase::verifyDeviceId()
+{
+  if ( !specific()->canReadRange(Pic::MemoryRangeType::DeviceId ) ) return true;
+  if ( !device()->isReadable(Pic::MemoryRangeType::DeviceId) ) {
+    log(Log::LineType::Information, i18n("Device not autodetectable: continuing with the specified device name \"%1\"...").arg(device()->name()));
+    return true;
+  }
+  BitValue rawId = readDeviceId();
+  if ( hasError() ) return false;
+  uint nbChars = device()->nbWords(Pic::MemoryRangeType::DeviceId) * device()->nbCharsWord(Pic::MemoryRangeType::DeviceId);
+  if ( rawId==0x0 || rawId==device()->mask(Pic::MemoryRangeType::DeviceId) ) {
+    log(Log::LineType::Error, i18n("Missing or incorrect device (Read id is %1).").arg(toHexLabel(rawId, nbChars)));
+    return false;
+  }
+  QMap<QString, Device::IdData> ids;
+  QValueVector<QString> names = group().supportedDevices();
+  for (uint k=0; k<uint(names.count()); k++) {
+    const Pic::Data *data = static_cast<const Pic::Data *>(group().deviceData(names[k]).data);
+    if ( data->architecture()!=device()->architecture() ) continue;
+    Device::IdData idata;
+    if ( data->matchId(rawId, idata) ) ids[names[k]] = idata;
+    }
+  QString message;
+  if ( ids.count()!=0 ) {
+    log(Log::LineType::Information, i18n("Read id: %1").arg(device()->idNames(ids).join("; ")));
+    if ( ids.contains(device()->name()) ) return true;
+    message = i18n("Read id does not match the specified device name \"%1\".").arg(device()->name());
+  } else {
+    log(Log::LineType::Warning, i18n("  Unknown or incorrect device (Read id is %1).").arg(toHexLabel(rawId, nbChars)));
+    message = i18n("Unknown device.");
+  }
+  if ( !askContinue(message) ) {
+    logUserAbort();
+    return false;
+  }
+  log(Log::LineType::Information, i18n("Continue with the specified device name: \"%1\"...").arg(device()->name()));
+  return true;
+}
+
+//-----------------------------------------------------------------------------
+QString Programmer::PicBase::prettyCalibration(const Device::Array &data) const
+{
+  QString s;
+  for (uint i=0; i<data.count(); i++) {
+    if ( i!=0 ) s += ", ";
+    s += toHexLabel(data[i], device()->nbCharsWord(Pic::MemoryRangeType::Cal));
+  }
+  return s;
+}
+
+bool Programmer::PicBase::readCalibration()
+{
+  if ( device()->isReadable(Pic::MemoryRangeType::Cal) ) {
+    if ( !specific()->canReadRange(Pic::MemoryRangeType::Cal) ) {
+      log(Log::LineType::Warning, i18n("Osccal cannot be read by the selected programmer"));
+      return true;
+    }
+    Device::Array data;
+    if ( !specific()->read(Pic::MemoryRangeType::Cal, data, 0) ) return false;
+    _deviceMemory->setArray(Pic::MemoryRangeType::Cal, data);
+    log(Log::DebugLevel::Normal, QString("  Read osccal: %1").arg(prettyCalibration(data)));
+    QString message;
+    if ( !device()->checkCalibration(data, &message) ) log(Log::LineType::Warning, "  " + message);
+    if ( device()->isReadable(Pic::MemoryRangeType::CalBackup) ) {
+      if ( !specific()->canReadRange(Pic::MemoryRangeType::CalBackup) ) {
+        log(Log::LineType::Warning, i18n("Osccal backup cannot be read by the selected programmer"));
+        return true;
+      }
+      if ( !specific()->read(Pic::MemoryRangeType::CalBackup, data, 0) ) return false;
+      _deviceMemory->setArray(Pic::MemoryRangeType::CalBackup, data);
+      log(Log::DebugLevel::Normal, QString("  Read osccal backup: %1").arg(prettyCalibration(data)));
+      if ( !device()->checkCalibration(data, &message) ) log(Log::LineType::Warning, "  " + message);
+    }
+  }
+  return true;
+}
+
+bool Programmer::PicBase::restoreCalibration()
+{
+  if ( !specific()->canReadRange(Pic::MemoryRangeType::Cal) || !specific()->canWriteRange(Pic::MemoryRangeType::Cal) ) return true;
+  if ( !device()->isWritable(Pic::MemoryRangeType::Cal) ) return true;
+  Device::Array data = _deviceMemory->arrayForWriting(Pic::MemoryRangeType::Cal);
+  Device::Array bdata = _deviceMemory->arrayForWriting(Pic::MemoryRangeType::CalBackup);
+  if ( device()->isReadable(Pic::MemoryRangeType::CalBackup) && specific()->canReadRange(Pic::MemoryRangeType::CalBackup) ) {
+    if ( !device()->checkCalibration(data) && device()->checkCalibration(bdata) ) {
+      log(Log::LineType::Information, i18n("  Replace invalid osccal with backup value."));
+      data = bdata;
+    }
+  }
+  Device::Array cdata;
+  if ( !specific()->read(Pic::MemoryRangeType::Cal, cdata, 0) ) return false;
+  if ( cdata==data ) {
+    log(Log::LineType::Information, i18n("  Osccal is unchanged."));
+    return true;
+  }
+  if ( !programRange(Pic::MemoryRangeType::Cal, data) ) return false;
+  if ( !specific()->read(Pic::MemoryRangeType::Cal, cdata, 0) ) return false;
+  if ( cdata==data ) log(Log::LineType::Information, i18n("  Osccal has been preserved."));
+
+  if ( !device()->isWritable(Pic::MemoryRangeType::CalBackup) || !device()->checkCalibration(bdata) ) return true;
+  if ( !specific()->read(Pic::MemoryRangeType::CalBackup, cdata, 0) ) return false;
+  if ( cdata.count()==0 ) {
+    log(Log::LineType::Warning, i18n("Osccal backup cannot be read by selected programmer"));
+    return true;
+  }
+  if ( cdata==bdata ) {
+    log(Log::LineType::Information, i18n("  Osccal backup is unchanged."));
+    return true;
+  }
+  if ( !programRange(Pic::MemoryRangeType::CalBackup, bdata) ) return false;
+  if ( !specific()->read(Pic::MemoryRangeType::CalBackup, cdata, 0) ) return false;
+  if ( cdata==bdata ) log(Log::LineType::Information, i18n("  Osccal backup has been preserved."));
+  return true;
+}
+
+bool Programmer::PicBase::restoreBandGapBits()
+{
+  if ( !specific()->canReadRange(Pic::MemoryRangeType::Config) ) return true;
+  bool hasProtectedBits = false;
+  for (uint i=0; i<device()->nbWords(Pic::MemoryRangeType::Config); i++)
+    if ( device()->config()._words[i].pmask!=0 ) hasProtectedBits = true;
+  if ( !hasProtectedBits ) return true;
+  Device::Array cdata;
+  if ( !specific()->read(Pic::MemoryRangeType::Config, cdata, 0) ) return false;
+  Device::Array data = _deviceMemory->arrayForWriting(Pic::MemoryRangeType::Config);
+  for (uint i=0; i<cdata.count(); i++) {
+    BitValue pmask = device()->config()._words[i].pmask;
+    if ( pmask==0 ) continue;
+    cdata[i] = cdata[i].clearMaskBits(pmask);
+    cdata[i] |= data[i].maskWith(pmask);
+  }
+  if ( !specific()->canWriteRange(Pic::MemoryRangeType::Config) ) {
+    log(Log::LineType::Warning, i18n("Could not restore band gap bits because programmer does not support writing config bits."));
+    return true;
+  }
+  log(Log::DebugLevel::Normal, QString("  Write config with band gap bits: %2").arg(toHexLabel(cdata[0], device()->nbCharsWord(Pic::MemoryRangeType::Config))));
+  if ( !programRange(Pic::MemoryRangeType::Config, cdata) ) return false;
+  if ( !specific()->read(Pic::MemoryRangeType::Config, data, 0) ) return false;
+  if ( data==cdata ) log(Log::LineType::Information, i18n("  Band gap bits have been preserved."));
+  return true;
+}
+
+bool Programmer::PicBase::eraseAll()
+{
+  if ( !specific()->canEraseAll() ) {
+    log(Log::LineType::SoftError, i18n("The selected programmer does not support erasing the whole device."));
+    return false;
+  }
+  if ( !specific()->erase(_hasProtectedCode || _hasProtectedEeprom) ) return false;
+  if ( !restoreCalibration() ) return false;
+  return true;
+}
+
+bool Programmer::PicBase::checkErase()
+{
+  if ( device()->memoryTechnology()==Device::MemoryTechnology::Rom || device()->memoryTechnology()==Device::MemoryTechnology::Romless
+       || device()->memoryTechnology()==Device::MemoryTechnology::Eprom ) {
+    log(Log::LineType::SoftError, i18n("Cannot erase ROM or EPROM device."));
+    return false;
+  }
+  return true;
+}
+
+bool Programmer::PicBase::internalErase(const Device::MemoryRange &range)
+{
+  if ( !initProgramming(Task::Erase) ) return false;
+  bool ok = true;
+  if ( range.all() ) ok = eraseAll();
+  else ok = eraseRange(static_cast<const Pic::MemoryRange &>(range)._type);
+  if ( !restoreBandGapBits() ) return false;
+  return ok;
+}
+
+bool Programmer::PicBase::eraseSingle(Pic::MemoryRangeType type)
+{
+  return erase(Pic::MemoryRange(type));
+}
+
+bool Programmer::PicBase::eraseRange(Pic::MemoryRangeType type)
+{
+  bool ok = internalEraseRange(type);
+  if ( !restoreCalibration() ) return false;
+  if ( ok && readConfigEntry(Config::BlankCheckAfterErase).toBool() ) {
+    Pic::Memory memory(*device());
+    VerifyData vdata(BlankCheckVerify, memory);
+    return readRange(type, 0, &vdata);
+  }
+  return ok;
+}
+
+bool Programmer::PicBase::internalEraseRange(Pic::MemoryRangeType type)
+{
+  if ( !specific()->canEraseRange(type) && !specific()->canEraseAll() ) {
+    log(Log::LineType::SoftError, i18n("The selected programmer does not support erasing neither the specified range nor the whole device."));
+    return false;
+  }
+  if ( type==Pic::MemoryRangeType::Code && _hasProtectedCode ) {
+    log(Log::LineType::SoftError, i18n("Cannot erase protected code memory. Consider erasing the whole chip."));
+    return false;
+  }
+  if ( type==Pic::MemoryRangeType::Eeprom && _hasProtectedEeprom ) {
+    log(Log::LineType::SoftError, i18n("Cannot erase protected data EEPROM. Consider erasing the whole chip."));
+    return false;
+  }
+  if ( specific()->canEraseRange(type) ) return specific()->eraseRange(type);
+  bool softErase = true;
+  if ( type!=Pic::MemoryRangeType::Code && (!specific()->canReadRange(Pic::MemoryRangeType::Code)
+       || !specific()->canWriteRange(Pic::MemoryRangeType::Code)) ) softErase = false;
+  if ( type!=Pic::MemoryRangeType::Eeprom && (!specific()->canReadRange(Pic::MemoryRangeType::Eeprom)
+       || !specific()->canWriteRange(Pic::MemoryRangeType::Eeprom)) ) softErase = false;
+  if ( type!=Pic::MemoryRangeType::Config && (!specific()->canReadRange(Pic::MemoryRangeType::Config)
+       || !specific()->canWriteRange(Pic::MemoryRangeType::Config)) ) softErase = false;
+  if ( type!=Pic::MemoryRangeType::UserId && (!specific()->canReadRange(Pic::MemoryRangeType::UserId)
+       || !specific()->canWriteRange(Pic::MemoryRangeType::UserId)) ) softErase = false;
+  if ( !softErase ) {
+    log(Log::LineType::SoftError, i18n("Cannot erase specified range because of programmer limitations."));
+    return false;
+  }
+  if ( !askContinue(i18n("%1: Erasing this range only is not supported with this programmer. This will erase the whole chip and restore the other memory ranges.").arg(type.label())) ) {
+    logUserAbort();
+    return false;
+  }
+  if ( type!=Pic::MemoryRangeType::Code && !preserveCode() ) return false;
+  if ( type!=Pic::MemoryRangeType::Eeprom && !preserveEeprom() ) return false;
+  if ( type!=Pic::MemoryRangeType::UserId && !readRange(Pic::MemoryRangeType::UserId, _deviceMemory, 0) ) return false;
+  specific()->erase(_hasProtectedCode || _hasProtectedEeprom);
+  if ( type!=Pic::MemoryRangeType::Code && !programAndVerifyRange(Pic::MemoryRangeType::Code, *_deviceMemory) ) return false;
+  if ( type!=Pic::MemoryRangeType::Eeprom && !programAndVerifyRange(Pic::MemoryRangeType::Eeprom, *_deviceMemory) ) return false;
+  if ( type!=Pic::MemoryRangeType::UserId && !programAndVerifyRange(Pic::MemoryRangeType::UserId, *_deviceMemory) ) return false;
+  if ( !programAndVerifyRange(Pic::MemoryRangeType::Config, *_deviceMemory) ) return false;
+  return true;
+}
+
+//-----------------------------------------------------------------------------
+bool Programmer::PicBase::readSingle(Pic::MemoryRangeType type, Pic::Memory &memory)
+{
+  if ( !specific()->canReadRange(type) ) {
+    log(Log::LineType::SoftError, i18n("The selected programmer cannot read the specified memory range."));
+    return false;
+  }
+  Pic::Memory tmp(*device());
+  if ( !read(tmp, Pic::MemoryRange(type)) ) return false;
+  memory.copyFrom(type, tmp);
+  if ( type==Pic::MemoryRangeType::Cal ) memory.copyFrom(Pic::MemoryRangeType::CalBackup, tmp);
+  return true;
+}
+
+bool Programmer::PicBase::readRange(Pic::MemoryRangeType type, Pic::Memory *memory, const VerifyData *vd)
+{
+  if ( !device()->isReadable(type) ) return true;
+  if ( !specific()->canReadRange(type) ) {
+    log(Log::LineType::Information, i18n("The selected programmer cannot read %1: operation skipped.").arg(type.label()));
+    return true;
+  }
+  VerifyData *vdata = (vd ? new VerifyData(vd->actions, vd->memory) : 0);
+  if (vdata) {
+    log(Log::LineType::Information, i18n("  Verify memory: %1").arg(type.label()));
+    if ( !(vdata->actions & IgnoreProtectedVerify) ) {
+      vdata->protectedRanges = static_cast<const Pic::Memory &>(vdata->memory).protectedRanges(Pic::Protection::ProgramProtected, type);
+      if ( !vdata->protectedRanges.isEmpty() ) log(Log::LineType::Warning, i18n("  Part of device memory is protected (in %1) and cannot be verified.")
+                                               .arg(type.label()));
+    } else vdata->protectedRanges.clear();
+  } else {
+    log(Log::LineType::Information, i18n("  Read memory: %1").arg(type.label()));
+    CRASH_ASSERT(memory);
+  }
+  Device::Array data;
+  bool ok = specific()->read(type, data, vdata);
+  delete vdata;
+  if (!ok) return false;
+  if (memory) memory->setArray(type, data);
+  return true;
+}
+
+bool Programmer::PicBase::checkRead()
+{
+  if ( device()->memoryTechnology()==Device::MemoryTechnology::Romless ) {
+    log(Log::LineType::SoftError, i18n("Cannot read ROMless device."));
+    return false;
+  }
+  return true;
+}
+
+bool Programmer::PicBase::internalRead(Device::Memory *memory, const Device::MemoryRange &range, const VerifyData *vdata)
+{
+  if ( !initProgramming(Task::Read) ) return false;
+  Pic::Memory *pmemory = static_cast<Pic::Memory *>(memory);
+  if ( !range.all() ) {
+    Pic::MemoryRangeType type = static_cast<const Pic::MemoryRange &>(range)._type;
+    if ( type==Pic::MemoryRangeType::Cal ) {
+      if ( !readRange(Pic::MemoryRangeType::Cal, pmemory, vdata) ) return false;
+      return readRange(Pic::MemoryRangeType::CalBackup, pmemory, vdata);
+    }
+    return readRange(type, pmemory, vdata);
+  }
+  if ( !readRange(Pic::MemoryRangeType::Config,    pmemory, vdata) ) return false;
+  if ( !readRange(Pic::MemoryRangeType::UserId,    pmemory, vdata) ) return false;
+  if ( vdata==0 ) if ( !readRange(Pic::MemoryRangeType::Cal,       pmemory, 0) ) return false;
+  if ( vdata==0 ) if ( !readRange(Pic::MemoryRangeType::CalBackup, pmemory, 0) ) return false;
+  if ( !readRange(Pic::MemoryRangeType::Code,      pmemory, vdata) ) return false;
+  if ( !readRange(Pic::MemoryRangeType::Eeprom,    pmemory, vdata) ) return false;
+  return true;
+}
+
+//-----------------------------------------------------------------------------
+bool Programmer::PicBase::programSingle(Pic::MemoryRangeType type, const Pic::Memory &memory)
+{
+  if ( !specific()->canWriteRange(type) ) {
+    log(Log::LineType::SoftError, i18n("The selected programmer cannot read the specified memory range."));
+    return false;
+  }
+  return program(memory, Pic::MemoryRange(type));
+}
+
+bool Programmer::PicBase::programRange(Pic::MemoryRangeType mtype, const Device::Array &data)
+{
+  log(Log::LineType::Information, i18n("  Write memory: %1").arg(mtype.label()));
+  bool only = ( readConfigEntry(Config::OnlyProgramNonMask).toBool()
+                && (mtype==Pic::MemoryRangeType::Code || mtype==Pic::MemoryRangeType::Eeprom) );
+  return specific()->write(mtype, data, !only);
+}
+
+bool Programmer::PicBase::programAndVerifyRange(Pic::MemoryRangeType type, const Pic::Memory &memory)
+{
+  if ( !device()->isWritable(type) || !specific()->canWriteRange(type) ) return true;
+  Device::Array data = memory.arrayForWriting(type);
+  if ( !programRange(type, data) ) return false;
+  if ( !readConfigEntry(Config::VerifyAfterProgram).toBool() ) return true;
+  if ( !specific()->canReadRange(type) ) return true;
+  VerifyActions actions = IgnoreProtectedVerify;
+  if ( type==Pic::MemoryRangeType::Code && readConfigEntry(Config::OnlyVerifyProgrammed).toBool() ) actions |= OnlyProgrammedVerify;
+  VerifyData vdata(actions, memory);
+  return readRange(type, 0, &vdata);
+}
+
+bool Programmer::PicBase::programAll(const Pic::Memory &memory)
+{
+  if ( !programAndVerifyRange(Pic::MemoryRangeType::Code, memory) ) return false;
+  if ( readConfigEntry(Config::ProgramEeprom).toBool() ) {
+    const Pic::Memory &tmp = (readConfigEntry(Config::PreserveEeprom).toBool() ? *_deviceMemory : memory);
+    if ( !programAndVerifyRange(Pic::MemoryRangeType::Eeprom, tmp) ) return false;
+  }
+  if ( !programAndVerifyRange(Pic::MemoryRangeType::UserId, memory) ) return false;
+  if ( memory.isProtected(Pic::Protection::WriteProtected, Pic::MemoryRangeType::Config) ) {
+    log(Log::DebugLevel::Normal, "  Config write protection is on: first program without it and then with it");
+    Pic::Memory tmp(memory.device());
+    tmp.copyFrom(Pic::MemoryRangeType::Config, memory);
+    tmp.setProtection(false, Pic::Protection::WriteProtected, Pic::MemoryRangeType::Config);
+    if ( !programAndVerifyRange(Pic::MemoryRangeType::Config, tmp) ) return false;
+  }
+  if ( !programAndVerifyRange(Pic::MemoryRangeType::Config, memory) ) return false;
+  return true;
+}
+
+bool Programmer::PicBase::checkProgram(const Device::Memory &memory)
+{
+  if ( device()->memoryTechnology()==Device::MemoryTechnology::Rom || device()->memoryTechnology()==Device::MemoryTechnology::Romless ) {
+    log(Log::LineType::SoftError, i18n("Cannot write ROM or ROMless device."));
+    return false;
+  }
+  if ( !group().isDebugger() && static_cast<const Pic::Memory &>(memory).hasDebugOn() ) {
+    if ( !askContinue(i18n("DEBUG configuration bit is on. Are you sure you want to continue programming the chip?")) ) {
+      logUserAbort();
+      return false;
+    }
+  }
+  return true;
+}
+
+bool Programmer::PicBase::internalProgram(const Device::Memory &memory, const Device::MemoryRange &range)
+{
+  if ( !initProgramming(Task::Erase) ) return false;
+  const Pic::Memory &pmemory = static_cast<const Pic::Memory &>(memory);
+
+  // blank check if OTP device
+  bool eprom = ( device()->memoryTechnology()==Device::MemoryTechnology::Eprom );
+  if (eprom) {
+    log(Log::LineType::Information, i18n("  EPROM device: blank checking first..."));
+    Pic::Memory memory(*device());
+    VerifyData vdata(BlankCheckVerify, memory);
+    if ( !internalRead(0, range, &vdata) ) return false;
+    log(Log::LineType::Information, i18n("  Blank check successful"));
+    // check if protecting device
+    bool protectedCode = pmemory.isProtected(Pic::Protection::ProgramProtected, Pic::MemoryRangeType::Code);
+    bool protectedEeprom = pmemory.isProtected(Pic::Protection::ProgramProtected, Pic::MemoryRangeType::Eeprom);
+    if ( protectedCode || protectedEeprom ) {
+      log(Log::LineType::SoftError, i18n("Protecting code memory or data EEPROM on OTP devices is disabled as a security..."));
+      return false;
+    }
+  }
+
+  // programming
+  bool ok = true;
+  if ( !range.all() ) {
+    Pic::MemoryRangeType type = static_cast<const Pic::MemoryRange &>(range)._type;
+    if ( (type==Pic::MemoryRangeType::Code && _hasProtectedCode) || (type==Pic::MemoryRangeType::Eeprom && _hasProtectedEeprom) ) {
+      log(Log::LineType::SoftError, i18n("This memory range is programming protected."));
+      return false;
+    }
+    if ( specific()->canEraseRange(type) ) {
+      if ( !specific()->emulatedErase() && !eraseRange(type) ) return false;
+    } else log(Log::LineType::Warning, i18n("The range cannot be erased first by the selected programmer so programming may fail..."));
+    ok = programRange(type, pmemory.arrayForWriting(type));
+    VerifyData vdata(NormalVerify, pmemory);
+    if (ok) ok = readRange(type, 0, &vdata);
+  } else {
+    if ( !eprom ) {
+      if ( specific()->canEraseAll() ) {
+        if ( !specific()->emulatedErase() ) {
+          log(Log::LineType::Information, i18n("  Erasing device"));
+          ok = ( !readConfigEntry(Config::PreserveEeprom).toBool() || preserveEeprom() );
+          if (ok) ok = eraseAll();
+        }
+      } else log(Log::LineType::Warning, i18n("The device cannot be erased first by the selected programmer so programming may fail..."));
+    }
+    if (ok) ok = programAll(pmemory);
+  }
+  if ( !restoreBandGapBits() ) return false;
+  return ok;
+}
+
+//-----------------------------------------------------------------------------
+bool Programmer::PicBase::checkProgramCalibration(const Device::Array &data)
+{
+  QString message, s = prettyCalibration(data);
+  if ( !device()->checkCalibration(data, &message) ) {
+    sorry(i18n("The calibration word %1 is not valid.").arg(s), message);
+    return false;
+  }
+  return askContinue(i18n("Do you want to overwrite the device calibration with %1?").arg(s));
+}
+
+bool Programmer::PicBase::tryProgramCalibration(const Device::Array &data, bool &success)
+{
+  log(Log::LineType::Information, i18n("  Write memory: %1").arg(Pic::MemoryRangeType(Pic::MemoryRangeType::Cal).label()));
+  success = true;
+  if ( !specific()->write(Pic::MemoryRangeType::Cal, data, true) ) return false;
+  Device::Array read;
+  if ( !specific()->read(Pic::MemoryRangeType::Cal, read, 0) ) return false;
+  for (uint i=0; i<data.count(); i++)
+    if ( data[i]!=read[i] ) success = false;
+  if ( !success ) return true;
+  if ( device()->isWritable(Pic::MemoryRangeType::CalBackup) ) {
+    if ( !specific()->read(Pic::MemoryRangeType::CalBackup, read, 0) ) return false;
+    if ( device()->checkCalibration(read) ) return true; // do not overwrite correct backup value
+    log(Log::LineType::Information, i18n("  Write memory: %1").arg(Pic::MemoryRangeType(Pic::MemoryRangeType::CalBackup).label()));
+    if ( !specific()->write(Pic::MemoryRangeType::CalBackup, data, true) ) return false;
+    if ( !specific()->read(Pic::MemoryRangeType::CalBackup, read, 0) ) return false;
+    for (uint i=0; i<data.count(); i++)
+      if ( data[i]!=read[i] ) success = false;
+  }
+  return true;
+}
+
+bool Programmer::PicBase::internalProgramCalibration(const Device::Array &data)
+{
+  if ( !initProgramming(Task::Write) ) return false;
+  // try without erase
+  bool success;
+  if ( !tryProgramCalibration(data, success) ) return false;
+  if (success) return true;
+  if ( !askContinue(i18n("Programming calibration data needs a chip erase. Continue anyway?")) ) {
+    logUserAbort();
+    return false;
+  }
+  log(Log::LineType::Information, i18n("  Erasing device"));
+  bool ok = specific()->erase(_hasProtectedCode || _hasProtectedEeprom);
+  if ( !restoreBandGapBits() ) return false;
+  if ( !ok ) return false;
+  // retry
+  if ( !tryProgramCalibration(data, success) ) return false;
+  return success;
+}
+
+bool Programmer::PicBase::programCalibration(const Device::Array &data)
+{
+  _progressMonitor.clear();
+  bool ok = doProgramCalibration(data);
+  endProgramming();
+  return ok;
+}
+
+bool Programmer::PicBase::doProgramCalibration(const Device::Array &data)
+{
+  if ( !checkProgramCalibration(data) ) return false;
+  if ( !doConnectDevice() ) return false;
+  log(Log::LineType::Information, i18n("Programming calibration..."));
+  emit actionMessage(i18n("Programming calibration..."));
+  if ( !internalProgramCalibration(data) ) return false;
+  log(Log::LineType::Information, i18n("Programming calibration successful"));
+  return true;
+}
+
+//-----------------------------------------------------------------------------
+bool Programmer::PicBase::verifySingle(Pic::MemoryRangeType type, const Pic::Memory &memory)
+{
+  return verify(memory, Pic::MemoryRange(type));
+}
+
+bool Programmer::PicBase::blankCheckSingle(Pic::MemoryRangeType type)
+{
+  return blankCheck(Pic::MemoryRange(type));
+}
diff --git a/src/devices/pic/prog/pic_prog.h b/src/devices/pic/prog/pic_prog.h
new file mode 100644
index 0000000..0fb37f7
--- /dev/null
+++ b/src/devices/pic/prog/pic_prog.h
@@ -0,0 +1,110 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_PROG_H
+#define PIC_PROG_H
+
+#include "pic_prog_specific.h"
+#include "progs/base/prog_group.h"
+#include "devices/base/device_group.h"
+
+namespace Pic
+{
+
+class MemoryRange : public Device::MemoryRange {
+public:
+  MemoryRange(MemoryRangeType type) : _type(type) {}
+  virtual bool all() const { return _type==MemoryRangeType::Nb_Types; }
+  MemoryRangeType _type;
+};
+
+} //namespace
+
+namespace Programmer
+{
+//-----------------------------------------------------------------------------
+class PicGroup : public Group
+{
+public:
+  virtual bool canReadVoltage(Pic::VoltageType) const { return false; }
+  virtual bool canReadVoltages() const;
+  virtual ::Debugger::DeviceSpecific *createDebuggerDeviceSpecific(::Debugger::Base &base) const;
+};
+
+//-----------------------------------------------------------------------------
+class PicBase : public Base
+{
+public:
+  PicBase(const Group &group, const Pic::Data *data, const char *name);
+  virtual ~PicBase();
+  PicDeviceSpecific *specific() { return static_cast<PicDeviceSpecific *>(_specific); }
+  const PicDeviceSpecific *specific() const { return static_cast<PicDeviceSpecific *>(_specific); }
+  const Pic::Data *device() const { return static_cast<const Pic::Data *>(_device); }
+  const Pic::Memory &deviceMemory() const { return *_deviceMemory; }
+  const PicGroup &group() const { return static_cast<const PicGroup &>(_group); }
+  double voltage(Pic::VoltageType type) const { return _voltages[type].value; }
+  virtual bool readVoltages();
+  bool getTargetMode(Pic::TargetMode &mode);
+
+  bool eraseSingle(Pic::MemoryRangeType type);
+  bool readSingle(Pic::MemoryRangeType type, Pic::Memory &memory);
+  bool programSingle(Pic::MemoryRangeType type, const Pic::Memory &memory);
+  bool verifySingle(Pic::MemoryRangeType type, const Pic::Memory &memory);
+  bool blankCheckSingle(Pic::MemoryRangeType type);
+  bool readCalibration();
+  bool programCalibration(const Device::Array &data);
+
+protected:
+  PicHardware *hardware() { return static_cast<PicHardware *>(_hardware); }
+  virtual bool internalSetupHardware();
+  virtual double vdd() const { return _voltages[Pic::TargetVdd].value; }
+  virtual double vpp() const { return _voltages[Pic::TargetVpp].value; }
+  virtual bool verifyDeviceId();
+  virtual uint nbSteps(Task task, const Device::MemoryRange *range) const;
+  bool initProgramming(Task task);
+  virtual bool initProgramming();
+  virtual bool internalRun();
+  virtual bool internalStop();
+  virtual void clear();
+
+  virtual bool checkErase();
+  virtual bool internalErase(const Device::MemoryRange &range);
+
+  virtual bool checkRead();
+  virtual bool internalRead(Device::Memory *memory, const Device::MemoryRange &range, const VerifyData *data);
+  bool readRange(Pic::MemoryRangeType type, Pic::Memory *memory, const VerifyData *data);
+
+  virtual bool checkProgram(const Device::Memory &memory);
+  virtual bool internalProgram(const Device::Memory &memory, const Device::MemoryRange &range);
+  virtual bool programAll(const Pic::Memory &memory);
+  bool programAndVerifyRange(Pic::MemoryRangeType type, const Pic::Memory &memory);
+  bool programRange(Pic::MemoryRangeType type, const Device::Array &array);
+
+private:
+  Pic::Memory *_deviceMemory;
+  bool _hasProtectedCode, _hasProtectedEeprom;
+  PicHardware::VoltagesData _voltages;
+
+  BitValue readDeviceId();
+  bool eraseAll();
+  bool eraseRange(Pic::MemoryRangeType type);
+  bool restoreCalibration();
+  bool restoreBandGapBits();
+  bool doProgramCalibration(const Device::Array &data);
+  bool checkProgramCalibration(const Device::Array &data);
+  bool internalProgramCalibration(const Device::Array &data);
+  QString prettyCalibration(const Device::Array &data) const;
+  bool tryProgramCalibration(const Device::Array &data, bool &success);
+  bool preserveCode();
+  bool preserveEeprom();
+  bool internalEraseRange(Pic::MemoryRangeType type);
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/pic/prog/pic_prog_specific.cpp b/src/devices/pic/prog/pic_prog_specific.cpp
new file mode 100644
index 0000000..bfcd2fa
--- /dev/null
+++ b/src/devices/pic/prog/pic_prog_specific.cpp
@@ -0,0 +1,121 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include "pic_prog_specific.h"
+
+#include "common/global/global.h"
+
+//-----------------------------------------------------------------------------
+const char * const Pic::VOLTAGE_TYPE_LABELS[Nb_VoltageTypes] = {
+  I18N_NOOP("Programmer Vpp"), I18N_NOOP("Target Vdd"), I18N_NOOP("Target Vpp")
+};
+
+const char * const Pic::TARGET_MODE_LABELS[Nb_TargetModes] = {
+  I18N_NOOP("Stopped"), I18N_NOOP("Running"), I18N_NOOP("In Programming")
+};
+
+const char * const Pic::RESET_MODE_LABELS[Nb_ResetModes] = {
+  I18N_NOOP("Reset Held"), I18N_NOOP("Reset Released")
+};
+
+//-----------------------------------------------------------------------------
+uint Programmer::PicDeviceSpecific::findNonMaskStart(Pic::MemoryRangeType type, const Device::Array &data) const
+{
+  uint start = 0;
+  for (; start<data.count(); start++)
+    if ( data[start]!=device().mask(type) ) break;
+  const_cast<PicDeviceSpecific *>(this)->log(Log::DebugLevel::Normal, QString("start before align: %1").arg(start));
+  uint align = device().nbWordsWriteAlignment(type);
+  start -= start % align;
+  const_cast<PicDeviceSpecific *>(this)->log(Log::DebugLevel::Normal, QString("start after align: %1 (align=%2)").arg(start).arg(align));
+  return start;
+}
+
+uint Programmer::PicDeviceSpecific::findNonMaskEnd(Pic::MemoryRangeType type, const Device::Array &data) const
+{
+  uint end = data.count()-1;
+  for (; end>0; end--)
+    if ( data[end]!=device().mask(type) ) break;
+  const_cast<PicDeviceSpecific *>(this)->log(Log::DebugLevel::Normal, QString("end before align: %1").arg(end));
+  uint align = device().nbWordsWriteAlignment(type);
+  if ( (end+1) % align ) end += align - (end+1) % align;
+  const_cast<PicDeviceSpecific *>(this)->log(Log::DebugLevel::Normal, QString("end after align: %1 (align=%2)").arg(end).arg(align));
+  Q_ASSERT(end<data.count());
+  return end;
+}
+
+bool Programmer::PicDeviceSpecific::read(Pic::MemoryRangeType type, Device::Array &data, const VerifyData *vdata)
+{
+  setPowerOn();
+  bool ok = doRead(type, data, vdata);
+  setPowerOff();
+  return ok;
+}
+
+bool Programmer::PicDeviceSpecific::write(Pic::MemoryRangeType mtype, const Device::Array &data, bool force)
+{
+  setPowerOn();
+  bool ok = doWrite(mtype, data, force);
+  setPowerOff();
+  return ok;
+}
+
+bool Programmer::PicDeviceSpecific::erase(bool isProtected)
+{
+  setPowerOn();
+  bool ok = doErase(isProtected);
+  setPowerOff();
+  return ok;
+}
+
+bool Programmer::PicDeviceSpecific::eraseRange(Pic::MemoryRangeType type)
+{
+  setPowerOn();
+  bool ok = doEraseRange(type);
+  setPowerOff();
+  return ok;
+}
+
+bool Programmer::PicDeviceSpecific::doEmulatedEraseRange(Pic::MemoryRangeType type)
+{
+  Pic::Memory memory(device());
+  if ( !doWrite(type, memory.arrayForWriting(type), true) ) return false;
+  if ( !canReadRange(type) ) return true;
+  VerifyData vdata(BlankCheckVerify, memory);
+  Device::Array data;
+  return doRead(type, data, &vdata);
+}
+
+//-----------------------------------------------------------------------------
+bool Programmer::PicHardware::compareWords(Pic::MemoryRangeType type, uint index, BitValue v, BitValue d, Programmer::VerifyActions actions)
+{
+  if ( v==d ) return true;
+  uint inc = device().addressIncrement(type);
+  Address address = device().range(type).start + inc * index;
+  if ( actions & ::Programmer::BlankCheckVerify )
+    log(Log::LineType::SoftError, i18n("Device memory is not blank (in %1 at address %2: reading %3 and expecting %4).")
+      .arg(type.label()).arg(toHexLabel(address, device().nbCharsAddress()))
+      .arg(toHexLabel(d, device().nbCharsWord(type))).arg(toHexLabel(v, device().nbCharsWord(type))));
+  else log(Log::LineType::SoftError, i18n("Device memory does not match hex file (in %1 at address %2: reading %3 and expecting %4).")
+      .arg(type.label()).arg(toHexLabel(address, device().nbCharsAddress()))
+      .arg(toHexLabel(d, device().nbCharsWord(type))).arg(toHexLabel(v, device().nbCharsWord(type))));
+  return false;
+}
+
+bool Programmer::PicHardware::verifyWord(uint i, BitValue word, Pic::MemoryRangeType type, const VerifyData &vdata)
+{
+  if ( !(vdata.actions & ::Programmer::IgnoreProtectedVerify) && vdata.protectedRanges.contains(i) ) return true; // protected
+  BitValue v = static_cast<const Pic::Memory &>(vdata.memory).normalizedWord(type, i);
+  BitValue d = static_cast<const Pic::Memory &>(vdata.memory).normalizeWord(type, i, word);
+  if ( type==Pic::MemoryRangeType::Config ) {
+    BitValue pmask = device().config()._words[i].pmask;
+    v = v.clearMaskBits(pmask);
+    d = d.clearMaskBits(pmask);
+  }
+  return compareWords(type, i, v, d, vdata.actions);
+}
diff --git a/src/devices/pic/prog/pic_prog_specific.h b/src/devices/pic/prog/pic_prog_specific.h
new file mode 100644
index 0000000..fef8a61
--- /dev/null
+++ b/src/devices/pic/prog/pic_prog_specific.h
@@ -0,0 +1,86 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2006 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#ifndef PIC_PROG_SPECIFIC_H
+#define PIC_PROG_SPECIFIC_H
+
+#include "progs/base/prog_specific.h"
+#include "progs/base/generic_prog.h"
+#include "devices/pic/pic/pic_memory.h"
+
+//----------------------------------------------------------------------------
+namespace Pic
+{
+  enum ResetMode { ResetHeld = 0, ResetReleased, Nb_ResetModes};
+  extern const char * const RESET_MODE_LABELS[Nb_ResetModes];
+
+  enum VoltageType { ProgrammerVpp = 0, TargetVdd, TargetVpp, Nb_VoltageTypes };
+  extern const char * const VOLTAGE_TYPE_LABELS[Nb_VoltageTypes];
+
+  enum TargetMode { TargetStopped = 0, TargetRunning, TargetInProgramming, Nb_TargetModes};
+  extern const char * const TARGET_MODE_LABELS[Nb_TargetModes];
+
+  enum WriteMode { WriteOnlyMode = 0, EraseWriteMode, Nb_WriteModes };
+} // namespace
+
+namespace Programmer
+{
+//-----------------------------------------------------------------------------
+class PicDeviceSpecific : public DeviceSpecific
+{
+public:
+  PicDeviceSpecific(::Programmer::Base &base) : DeviceSpecific(base) {}
+  const Pic::Data &device() const { return static_cast<const Pic::Data &>(*_base.device()); }
+  virtual bool canEraseAll() const = 0;
+  virtual bool canEraseRange(Pic::MemoryRangeType type) const = 0;
+  virtual bool emulatedErase() const { return false; }
+  virtual bool canReadRange(Pic::MemoryRangeType type) const = 0;
+  virtual bool canWriteRange(Pic::MemoryRangeType type) const = 0;
+  bool eraseRange(Pic::MemoryRangeType type);
+  bool erase(bool isProtected);
+  bool read(Pic::MemoryRangeType type, Device::Array &data, const VerifyData *vdata);
+  bool write(Pic::MemoryRangeType type, const Device::Array &data, bool force);
+  uint findNonMaskStart(Pic::MemoryRangeType type, const Device::Array &data) const;
+  uint findNonMaskEnd(Pic::MemoryRangeType type, const Device::Array &data) const;
+
+protected:
+  virtual bool doErase(bool isProtected) = 0;
+  virtual bool doEraseRange(Pic::MemoryRangeType type) = 0;
+  bool doEmulatedEraseRange(Pic::MemoryRangeType type);
+  virtual bool doRead(Pic::MemoryRangeType type, Device::Array &data, const VerifyData *vdata) = 0;
+  virtual bool doWrite(Pic::MemoryRangeType type, const Device::Array &data, bool force) = 0;
+};
+
+//-----------------------------------------------------------------------------
+class PicHardware : public Hardware
+{
+public:
+  class VoltageData {
+  public:
+    VoltageData() : value(UNKNOWN_VOLTAGE) {}
+    double value;
+    bool error;
+  };
+  class VoltagesData : public QValueVector<VoltageData> {
+  public:
+    VoltagesData() : QValueVector<VoltageData>(Pic::Nb_VoltageTypes) {}
+  };
+
+public:
+  PicHardware(::Programmer::Base &base, Port::Base *port, const QString &name) : Hardware(base, port, name) {}
+  const Pic::Data &device() const { return static_cast<const Pic::Data &>(*_base.device()); }
+  virtual bool readVoltages(VoltagesData &) { return true; }
+  virtual bool getTargetMode(Pic::TargetMode &mode) { mode = Pic::TargetInProgramming; return true; }
+  virtual bool setTargetReset(Pic::ResetMode) { return true; }
+  bool compareWords(Pic::MemoryRangeType type, uint index, BitValue v, BitValue d, VerifyActions actions);
+  bool verifyWord(uint index, BitValue word, Pic::MemoryRangeType type, const VerifyData &vdata);
+};
+
+} // namespace
+
+#endif
diff --git a/src/devices/pic/prog/prog.pro b/src/devices/pic/prog/prog.pro
new file mode 100644
index 0000000..c0caf87
--- /dev/null
+++ b/src/devices/pic/prog/prog.pro
@@ -0,0 +1,6 @@
+STOPDIR = ../../../..
+include($${STOPDIR}/lib.pro)
+
+TARGET   = picprog
+HEADERS += pic_prog.h pic_debug.h pic_prog_specific.h
+SOURCES += pic_prog.cpp pic_debug.cpp pic_prog_specific.cpp
diff --git a/src/devices/pic/xml/Makefile.am b/src/devices/pic/xml/Makefile.am
new file mode 100644
index 0000000..a941f8d
--- /dev/null
+++ b/src/devices/pic/xml/Makefile.am
@@ -0,0 +1,12 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+noinst_PROGRAMS = pic_xml_to_data
+
+pic_xml_to_data_SOURCES = pic_xml_to_data.cpp
+pic_xml_to_data_DEPENDENCIES = $(top_builddir)/src/devices/pic/base/libpicbase.la \
+	$(top_builddir)/src/xml_to_data/libxmltodata.la $(top_builddir)/src/devices/base/libdevicebase.la \
+	$(top_builddir)/src/common/common/libcommon.la
+pic_xml_to_data_LDADD = $(top_builddir)/src/devices/pic/base/libpicbase.la \
+	$(top_builddir)/src/xml_to_data/libxmltodata.la $(top_builddir)/src/devices/base/libdevicebase.la \
+	$(top_builddir)/src/common/common/libcommon.la $(LIB_KDECORE)
diff --git a/src/devices/pic/xml/pic_xml_to_data.cpp b/src/devices/pic/xml/pic_xml_to_data.cpp
new file mode 100644
index 0000000..f3675de
--- /dev/null
+++ b/src/devices/pic/xml/pic_xml_to_data.cpp
@@ -0,0 +1,718 @@
+/***************************************************************************
+ *   Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ ***************************************************************************/
+#include <qfile.h>
+#include <qregexp.h>
+
+#include "xml_to_data/device_xml_to_data.h"
+#include "common/common/misc.h"
+#include "devices/pic/base/pic_config.h"
+#include "devices/pic/base/pic_register.h"
+
+namespace Pic
+{
+class XmlToData : public Device::XmlToData<Data>
+{
+private:
+  virtual QString namespaceName() const { return "Pic"; }
+
+bool getVoltages(ProgVoltageType type, QDomElement element)
+{
+  QDomElement voltages = findUniqueElement(element, "voltages", "name", type.key());
+  if ( voltages.isNull() ) return false;
+  bool ok1, ok2, ok3;
+  data()->_voltages[type].min = voltages.attribute("min").toDouble(&ok1);
+  data()->_voltages[type].max = voltages.attribute("max").toDouble(&ok2);
+  data()->_voltages[type].nominal = voltages.attribute("nominal").toDouble(&ok3);
+  if ( !ok1 || !ok2 || !ok3 ) qFatal(QString("Cannot extract voltage value for \"%1\"").arg(type.key()));
+  if ( data()->_voltages[type].min>data()->_voltages[type].max
+       || data()->_voltages[type].nominal<data()->_voltages[type].min
+       || data()->_voltages[type].nominal>data()->_voltages[type].max )
+    qFatal("Inconsistent voltages order");
+  return true;
+}
+
+bool getMemoryRange(MemoryRangeType type, QDomElement element)
+{
+  QDomElement range = findUniqueElement(element, "memory", "name", type.key());
+  if ( range.isNull() ) return false;
+  data()->_ranges[type].properties = Present;
+  bool ok;
+  uint nbCharsAddress = data()->nbCharsAddress();
+  data()->_ranges[type].start = fromHexLabel(range.attribute("start"), nbCharsAddress, &ok);
+  if ( !ok ) qFatal("Cannot extract start address");
+  data()->_ranges[type].end = fromHexLabel(range.attribute("end"), nbCharsAddress, &ok);
+  if ( !ok ) qFatal("Cannot extract end address");
+  if ( data()->_ranges[type].end<data()->_ranges[type].start ) qFatal("Memory range end is before its start");
+  uint nbCharsWord = data()->nbCharsWord(type);
+  if ( data()->nbBitsWord(type)==0 ) qFatal(QString("Architecture doesn't contain memory range %1").arg(type.key()));
+  if ( type==MemoryRangeType::UserId ) {
+    data()->_userIdRecommendedMask = fromHexLabel(range.attribute("rmask"), nbCharsWord, &ok);
+    if ( !ok ) qFatal("Cannot extract rmask value for user id");
+    if ( !data()->_userIdRecommendedMask.isInside(data()->mask(type)) ) qFatal(QString("rmask is not inside mask %1 (%2)").arg(toHexLabel(data()->_userIdRecommendedMask, 8)).arg(toHexLabel(data()->mask(type), 8)));
+  }
+  if ( range.attribute("hexfile_offset")!="?" ) {
+    data()->_ranges[type].properties |= Programmable;
+    if ( !range.attribute("hexfile_offset").isEmpty() ) {
+      data()->_ranges[type].hexFileOffset = fromHexLabel(range.attribute("hexfile_offset"), nbCharsAddress, &ok);
+      if ( !ok ) qFatal("Cannot extract hexfile_offset");
+    }
+  }
+  if ( type==MemoryRangeType::Cal && !data()->is18Family() ) {
+    data()->_calibration.opcodeMask = fromHexLabel(range.attribute("cal_opmask"), nbCharsWord, &ok);
+    if ( !ok ) qFatal("Cannot extract calibration opcode mask");
+    data()->_calibration.opcode = fromHexLabel(range.attribute("cal_opcode"), nbCharsWord, &ok);
+    if ( !ok ) qFatal("Cannot extract calibration opcode");
+    if ( !data()->_calibration.opcode.isInside(data()->_calibration.opcodeMask) ) qFatal("Calibration opcode should be inside opcode mask");
+    if ( !data()->_calibration.opcodeMask.isInside(data()->mask(type)) ) qFatal("Calibration mask should be inside opcode mask");
+  }
+  QString wwa = range.attribute("word_write_align");
+  QString wea = range.attribute("word_erase_align");
+  if ( type==MemoryRangeType::Code ) {
+    if ( data()->_architecture==Architecture::P18F || data()->_architecture==Architecture::P18J ) {
+      data()->_nbWordsCodeWrite = wwa.toUInt(&ok);
+      if ( !ok || data()->_nbWordsCodeWrite==0 || (data()->_nbWordsCodeWrite%4)!=0 ) qFatal("Missing or malformed word write align");
+      data()->_nbWordsCodeRowErase = wea.toUInt(&ok);
+      if ( !ok || (data()->_nbWordsCodeRowErase%4)!=0 ) qFatal("Missing or malformed word erase align");
+    } else {
+      if ( !wwa.isEmpty() || !wea.isEmpty() ) qFatal("word align should not be defined for this device family/subfamily");
+      data()->_nbWordsCodeWrite = 0; // #### TODO
+      data()->_nbWordsCodeRowErase = 0; // #### TODO
+    }
+  } else if ( !wwa.isEmpty() || !wea.isEmpty() ) qFatal("word align should not be defined for this memory range");
+  return true;
+}
+
+bool hasValue(const Pic::Config::Mask &mask, BitValue value)
+{
+  for (uint i=0; i<uint(mask.values.count()); i++)
+    if ( mask.values[i].value==value ) return true;
+  return false;
+}
+
+void processName(const Pic::Config::Mask &cmask, BitValue pmask, Pic::Config::Value &cvalue)
+{
+  QStringList &cnames = cvalue.configNames[Pic::ConfigNameType::Default];
+  if ( cvalue.name=="invalid" ) {
+    cvalue.name = QString::null;
+    if ( !cnames.isEmpty() ) qFatal(QString("No cname should be defined for invalid value in mask %1").arg(cmask.name));
+    return;
+  }
+  if ( cvalue.name.isEmpty() ) qFatal(QString("Empty value name in mask %1").arg(cmask.name));
+  if ( cmask.value.isInside(pmask) ) { // protected bits
+    if ( !cnames.isEmpty() ) qFatal(QString("Config name should be null for protected config mask \"%1\"").arg(cmask.name));
+  } else {
+    if ( cnames.isEmpty() && cmask.name!="BSSEC" && cmask.name!="BSSIZ" && cmask.name!="SSSEC" && cmask.name!="SSSIZ" ) {
+      // ### FIXME: 18J 24H 30F1010/202X
+      if ( data()->architecture()!=Pic::Architecture::P18J && data()->architecture()!=Pic::Architecture::P24H
+           && data()->architecture()!=Pic::Architecture::P24F && data()->architecture()!=Pic::Architecture::P33F
+           && data()->name()!="30F1010" && data()->name()!="30F2020" && data()->name()!="30F2023" )
+        qFatal(QString("cname not defined for \"%1\" (%2)").arg(cvalue.name).arg(cmask.name));
+    }
+    if ( cnames.count()==1 && cnames[0]=="_" ) cnames.clear();
+    for (uint i=0; i<uint(cnames.count()); i++) {
+      if ( cnames[i].startsWith("0x") ) {
+        if ( cnames.count()!=1 ) qFatal("Hex cname cannot be combined");
+        bool ok;
+        BitValue v = fromHexLabel(cnames[i], &ok);
+        uint nbChars = data()->nbCharsWord(MemoryRangeType::Config);
+        BitValue mask = cmask.value.complementInMask(maxValue(NumberBase::Hex, nbChars));
+        if ( ok && v==(mask | cvalue.value) ) continue;
+      } else if ( XOR(cnames[i].startsWith("_"), data()->architecture()==Pic::Architecture::P30F) ) continue;
+      qFatal(QString("Invalid config name for \"%1\"/\"%2\"").arg(cmask.name).arg(cvalue.name));
+    }
+    QStringList &ecnames = cvalue.configNames[Pic::ConfigNameType::Extra];
+    for (uint i=0; i<uint(ecnames.count()); i++)
+      if ( ecnames[i][0]!='_'  ) qFatal(QString("Invalid extra config name for %1").arg(cvalue.name));
+  }
+}
+
+Pic::Config::Mask toConfigMask(QDomElement mask, BitValue pmask)
+{
+  uint nbChars = data()->nbCharsWord(MemoryRangeType::Config);
+  bool ok;
+  QString defName;
+  QMap<Pic::ConfigNameType, QStringList> defConfigNames;
+  Config::Mask cmask;
+  cmask.name = mask.attribute("name");
+  if ( !Config::hasMaskName(cmask.name) ) qFatal(QString("Unknown mask name %1").arg(cmask.name));
+  cmask.value = fromHexLabel(mask.attribute("value"), nbChars, &ok);
+  if ( !ok || cmask.value==0 || cmask.value>data()->mask(MemoryRangeType::Config) )
+    qFatal(QString("Malformed mask value in mask %1").arg(mask.attribute("name")));
+  //QStringList names;
+  QDomNode child = mask.firstChild();
+  while ( !child.isNull() ) {
+    QDomElement value = child.toElement();
+    child = child.nextSibling();
+    if ( value.isNull() ) continue;
+    if ( value.nodeName()!="value" ) qFatal(QString("Non value child in mask %1").arg(cmask.name));
+    if ( value.attribute("value")=="default" ) {
+      if ( !defName.isEmpty() ) qFatal(QString("Default value already defined for mask %1").arg(cmask.name));
+      defName = value.attribute("name");
+      //if ( names.contains(defName) ) qFatal(QString("Value name duplicated in mask %1").arg(cmask.name));
+      //names.append(defName);
+      FOR_EACH(Pic::ConfigNameType, type) defConfigNames[type] = QStringList::split(' ', value.attribute(type.data().key));
+      continue;
+    }
+    Config::Value cvalue;
+    cvalue.value = fromHexLabel(value.attribute("value"), nbChars, &ok);
+    if ( !ok || !cvalue.value.isInside(cmask.value) ) qFatal(QString("Malformed value in mask %1").arg(cmask.name));
+    cvalue.name = value.attribute("name");
+    //if ( names.contains(cvalue.name) ) qFatal(QString("Value name duplicated in mask %1").arg(cmask.name));
+    //names.append(cvalue.name);
+    FOR_EACH(Pic::ConfigNameType, type) cvalue.configNames[type] = QStringList::split(' ', value.attribute(type.data().key));
+    processName(cmask, pmask, cvalue);
+    cmask.values.append(cvalue);
+  }
+  // add default values
+  if ( !defName.isEmpty() ) {
+    uint nb = 0;
+    BitValue::const_iterator it;
+    for (it=cmask.value.begin(); it!=cmask.value.end(); ++it) {
+      if ( hasValue(cmask, *it) ) continue; // already set
+      nb++;
+      Config::Value cvalue;
+      cvalue.value = *it;
+      cvalue.name = defName;
+      cvalue.configNames = defConfigNames;
+      processName(cmask, pmask, cvalue);
+      cmask.values.append(cvalue);
+    }
+    if ( nb<=1 ) qFatal(QString("Default value used less than twice in mask %1").arg(cmask.name));
+  }
+  qHeapSort(cmask.values);
+  return cmask;
+}
+
+Pic::Config::Word toConfigWord(QDomElement config)
+{
+  uint nbChars = data()->nbCharsWord(MemoryRangeType::Config);
+  Config::Word cword;
+  cword.name = config.attribute("name");
+  if ( cword.name.isNull() ) qFatal("Config word name not specified.");
+  bool ok;
+  cword.wmask = fromHexLabel(config.attribute("wmask"), nbChars, &ok);
+  BitValue gmask = data()->mask(MemoryRangeType::Config);
+  if ( !ok || cword.wmask>gmask ) qFatal(QString("Missing or malformed config wmask \"%1\"").arg(config.attribute("wmask")));
+  cword.bvalue = fromHexLabel(config.attribute("bvalue"), nbChars, &ok);
+  if ( !ok ) qFatal(QString("Missing or malformed config bvalue \"%1\"").arg(config.attribute("bvalue")));
+  if ( config.attribute("pmask").isEmpty() ) cword.pmask = 0;
+  else {
+    bool ok;
+    cword.pmask = fromHexLabel(config.attribute("pmask"), nbChars, &ok);
+    if ( !ok || cword.pmask>gmask ) qFatal("Missing or malformed config pmask");
+  }
+  cword.ignoredCNames = QStringList::split(' ', config.attribute("icnames"));
+  for (uint i=0; i<uint(cword.ignoredCNames.count()); i++)
+    if ( cword.ignoredCNames[i][0]!='_'  ) qFatal(QString("Invalid ignored config name for %1").arg(cword.name));
+  QDomNode child = config.firstChild();
+  while ( !child.isNull() ) {
+    QDomElement mask = child.toElement();
+    child = child.nextSibling();
+    if ( mask.isNull() ) continue;
+    if ( mask.nodeName()!="mask" ) qFatal(QString("Non mask child in config %1").arg(cword.name));
+    if ( mask.attribute("name").isEmpty() ) qFatal(QString("Empty mask name in config %1").arg(cword.name));
+    Config::Mask cmask = toConfigMask(mask, cword.pmask);
+    if ( !cmask.value.isInside(gmask) ) qFatal(QString("Mask value not inside mask in config %1").arg(cword.name));
+    for (uint i=0; i<uint(cword.masks.count()); i++) {
+      if ( cword.masks[i].name==cmask.name ) qFatal(QString("Duplicated mask name %1 in config %2").arg(cmask.name).arg(cword.name));
+      if ( cmask.value.isOverlapping(cword.masks[i].value) ) qFatal(QString("Overlapping masks in config %1").arg(cword.name));
+    }
+    cword.masks.append(cmask);
+  }
+  qHeapSort(cword.masks);
+  BitValue mask = (cword.usedMask() | cword.bvalue).clearMaskBits(cword.pmask);
+  if ( config.attribute("cmask").isEmpty() ) {
+    if ( data()->_architecture==Pic::Architecture::P30F ) cword.cmask = cword.wmask;
+    else cword.cmask = mask;
+  } else {
+    bool ok;
+    cword.cmask = fromHexLabel(config.attribute("cmask"), nbChars, &ok);
+    if ( !ok || cword.cmask>gmask ) qFatal("Missing or malformed config cmask");
+    //if ( data()->_architecture==Pic::Architecture::P30X &&cword.cmask==cword.wmask ) qFatal(QString("Redundant cmask in %1").arg(cword.name));
+    if ( cword.cmask==mask ) qFatal(QString("Redundant cmask in %1").arg(cword.name));
+  }
+  if ( !cword.pmask.isInside(cword.usedMask()) ) qFatal("pmask should be inside or'ed mask values.");
+  return cword;
+}
+
+QValueVector<Pic::Config::Word> getConfigWords(QDomElement element)
+{
+  uint nbWords = data()->nbWords(MemoryRangeType::Config);
+  QValueVector<Config::Word> configWords(nbWords);
+  QDomNode child = element.firstChild();
+  while ( !child.isNull() ) {
+    QDomElement config = child.toElement();
+    child = child.nextSibling();
+    if ( config.isNull() || config.nodeName()!="config" ) continue;
+    bool ok;
+    uint offset = fromHexLabel(config.attribute("offset"), 1, &ok);
+    if ( !ok ) qFatal("Missing or malformed config offset");
+    if ( (offset % data()->addressIncrement(MemoryRangeType::Config))!=0 ) qFatal("Config offset not aligned");
+    offset /= data()->addressIncrement(MemoryRangeType::Config);
+    if ( offset>=nbWords ) qFatal(QString("Offset too big %1/%2").arg(offset).arg(nbWords));
+    if ( !configWords[offset].name.isNull() ) qFatal(QString("Config offset %1 is duplicated").arg(offset));
+    for (uint i=0; i<nbWords; i++) {
+      if ( !configWords[i].name.isNull() && configWords[i].name==config.attribute("name") )
+        qFatal(QString("Duplicated config name %1").arg(configWords[i].name));
+    }
+    configWords[offset] = toConfigWord(config);
+  }
+  return configWords;
+}
+
+QString getChecksumData(QDomElement checksum)
+{
+  Checksum::Data cdata;
+  cdata.blankChecksum = 0x0;
+  cdata.checkChecksum = 0x0;
+
+  const Protection &protection = data()->_config->protection();
+  QString valueName;
+  if ( protection.family()==Protection::BlockProtection ) {
+    valueName = checksum.attribute("protected_blocks");
+    bool ok;
+    uint nb = valueName.toUInt(&ok);
+    uint max = (protection.hasBootBlock() ? 1 : 0) + protection.nbBlocks();
+    if ( !ok || nb>max ) qFatal("Invalid number of protected blocks for checksum");
+    if ( nb>0 ) cdata.protectedMaskNames += "CPB";
+    for (uint i=1; i<nb; i++) cdata.protectedMaskNames += "CP_" + QString::number(i-1);
+    cdata.bbsize = checksum.attribute("bbsize");
+    const Config::Mask *mask = data()->_config->findMask(protection.bootSizeMaskName());
+    if ( mask==0 ) {
+      if ( !cdata.bbsize.isEmpty() ) qFatal("Device does not have a variable boot size (no \"bbsize\" allowed in checksum)");
+    } else if ( cdata.bbsize.isEmpty() ) {
+      if ( nb==1 ) qFatal("\"bbsize\" should be define in checksum for \"protected_blocks\"==1");
+    } else {
+      const Config::Value *value = data()->_config->findValue(protection.bootSizeMaskName(), cdata.bbsize);
+      if ( value==0 ) qFatal("Invalid \"bbsize\" in checksum");
+      valueName += "_" + cdata.bbsize;
+    }
+  } else {
+    valueName = checksum.attribute("protected");
+    if ( protection.family()==Protection::NoProtection && !valueName.isEmpty() )
+      qFatal("Checksum protected attribute for device with no code protection");
+  }
+  if ( data()->_checksums.contains(valueName) ) qFatal("Duplicate checksum protected range");
+
+  QString s = checksum.attribute("constant");
+  if ( s.isEmpty() ) cdata.constant = 0x0000;
+  else {
+    bool ok;
+    cdata.constant = fromHexLabel(s, 4, &ok);
+    if ( !ok ) qFatal("Malformed checksum constant");
+  }
+
+  s = checksum.attribute("type");
+  if ( s.isEmpty() ) cdata.algorithm = Checksum::Algorithm::Normal;
+  else {
+    cdata.algorithm = Checksum::Algorithm::fromKey(s);
+    if ( cdata.algorithm==Checksum::Algorithm::Nb_Types ) qFatal("Unrecognized checksum algorithm");
+  }
+
+  s = checksum.attribute("mprotected");
+  if ( !s.isEmpty() ) {
+    QStringList list = QStringList::split(" ", s);
+    for (uint i=0; i<uint(list.count()); i++) {
+      const Config::Mask *mask = data()->config().findMask(list[i]);
+      if ( mask==0 ) qFatal(QString("Not valid mask name for \"protected\" tag in checksum: %1").arg(list[i]));
+      if ( mask->values.count()==2 ) continue;
+      for (uint k=0; k<uint(mask->values.count()); k++) {
+        QString valueName = mask->values[k].name;
+        if ( valueName.isEmpty() ) continue;
+        if ( !protection.isNoneProtectedValueName(valueName) && !protection.isAllProtectedValueName(valueName) )
+          qFatal(QString("Not switch protection from mask name for \"protected\" tag in checksum: %1").arg(list[i]));
+      }
+    }
+    cdata.protectedMaskNames = list;
+  }
+
+  s = checksum.attribute("bchecksum");
+  if ( s.isEmpty() ) qFatal("No blank checksum");
+  else {
+    bool ok;
+    cdata.blankChecksum = fromHexLabel(s, 4, &ok);
+    if ( !ok ) qFatal("Malformed blank checksum");
+  }
+
+  s = checksum.attribute("cchecksum");
+  if ( s.isEmpty() ) qFatal("No check checksum");
+  else {
+    bool ok;
+    cdata.checkChecksum = fromHexLabel(s, 4, &ok);
+    if ( !ok ) qFatal("Malformed check checksum");
+  }
+
+  data()->_checksums[valueName] = cdata;
+  return valueName;
+}
+
+virtual void processDevice(QDomElement device)
+{
+  Device::XmlToDataBase::processDevice(device);
+
+  QString arch = device.attribute("architecture");
+  data()->_architecture = Architecture::fromKey(arch);
+  if ( data()->_architecture==Architecture::Nb_Types ) qFatal(QString("Unrecognized architecture \"%1\"").arg(arch));
+  if ( (data()->_architecture==Architecture::P18F && data()->_name.contains("C"))
+       || (data()->_architecture==Architecture::P18F && data()->_name.contains("J")) ) qFatal("Not matching family");
+
+  bool ok;
+  QString pc = device.attribute("pc");
+  data()->_nbBitsPC = data()->_architecture.data().nbBitsPC;
+  if ( data()->_nbBitsPC==0 ) {
+    data()->_nbBitsPC = pc.toUInt(&ok);
+    if ( !ok || data()->_nbBitsPC==0 ) qFatal("Malformed or missing PC");
+  } else if ( !pc.isEmpty() ) qFatal("No PC should be provided for this device architecture");
+
+  QString sw = device.attribute("self_write");
+  data()->_selfWrite = (data()->_memoryTechnology!=Device::MemoryTechnology::Flash ? SelfWrite::No : data()->_architecture.data().selfWrite);
+  if ( data()->_selfWrite==SelfWrite::Nb_Types ) {
+    data()->_selfWrite = SelfWrite::fromKey(sw);
+    if ( data()->_selfWrite==SelfWrite::Nb_Types ) qFatal("Malformed or missing self-write field");
+  } else if ( !sw.isEmpty() ) qFatal("Self-write is set for the whole family or non-flash device");
+
+  // device ids
+  FOR_EACH(Device::Special, special) {
+    QString key = "id" + (special==Device::Special::Normal ? QString::null : QString("_") + special.key());
+    QString id = device.attribute(key);
+    if ( id.isEmpty() ) {
+      if ( special==Device::Special::Normal ) data()->_ids[special] = 0x0000;
+    } else {
+      data()->_ids[special] = fromHexLabel(id, 4, &ok);
+      if ( !ok ) qFatal("Malformed id");
+    }
+  }
+
+  // voltages
+  QStringList names;
+  FOR_EACH(ProgVoltageType, vtype) {
+    names += vtype.key();
+    if ( !getVoltages(vtype, device) ) {
+      switch (vtype.type()) {
+        case ProgVoltageType::Vpp:
+        case ProgVoltageType::VddBulkErase: qFatal(QString("Voltage \"%1\" not defined").arg(vtype.key()));
+        case ProgVoltageType::VddWrite: data()->_voltages[ProgVoltageType::VddWrite] = data()->_voltages[ProgVoltageType::VddBulkErase]; break;
+        case ProgVoltageType::Nb_Types: Q_ASSERT(false); break;
+      }
+    }
+  }
+  //if ( data()->vddMin()>data()->_voltages[ProgVoltageType::VddWrite].min ) qFatal("Vdd min higher than VddWrite min");
+  //if ( data()->vddMax()<data()->_voltages[ProgVoltageType::VddWrite].max ) qFatal("Vdd max lower than VddWrite max");
+  if ( data()->_voltages[ProgVoltageType::VddWrite].min>data()->_voltages[ProgVoltageType::VddBulkErase].min ) qFatal("VddWrite min higher than VddBulkErase min");
+  if ( data()->_voltages[ProgVoltageType::VddWrite].max<data()->_voltages[ProgVoltageType::VddBulkErase].max ) qFatal("VddWrite max lower than VddBulkErase max");
+  checkTagNames(device, "voltages", names);
+
+  // memory ranges
+  names.clear();
+  FOR_EACH(MemoryRangeType, i) {
+    names += i.key();
+    if ( !getMemoryRange(i, device) ) continue;
+     if ( !(data()->_ranges[i].properties & Programmable) ) continue;
+    for(MemoryRangeType k; k<i; ++k) {
+      if ( !(data()->_ranges[k].properties & Present)
+           || !(data()->_ranges[k].properties & Programmable) ) continue;
+      if ( i==MemoryRangeType::DebugVector
+           && k==MemoryRangeType::ProgramExecutive ) continue;
+      if ( k==MemoryRangeType::DebugVector
+           && i==MemoryRangeType::ProgramExecutive ) continue;
+      Address start1 = data()->_ranges[k].start + data()->_ranges[k].hexFileOffset;
+      Address end1 = data()->_ranges[k].end + data()->_ranges[k].hexFileOffset;
+      Address start2 = data()->_ranges[i].start + data()->_ranges[i].hexFileOffset;
+      Address end2 = data()->_ranges[i].end + data()->_ranges[i].hexFileOffset;
+      if ( end1>=start2 && start1<=end2 )
+        qFatal(QString("Overlapping memory ranges (%1 and %2)").arg(k.key()).arg(i.key()));
+    }
+  }
+  checkTagNames(device, "memory", names);
+  if ( XOR(data()->_ids[Device::Special::Normal]!=0x0000, (data()->_ranges[MemoryRangeType::DeviceId].properties & Present)) )
+    qFatal("Id present and device id memory range absent or the opposite");
+
+  // config words
+  QValueVector<Config::Word> cwords = getConfigWords(device);
+  uint nbWords = data()->nbWords(MemoryRangeType::Config);
+  data()->_config->_words.resize(nbWords);
+  FOR_EACH(Pic::ConfigNameType, type) {
+    QMap<QString, QString> cnames; // cname -> mask name
+    for (uint i=0; i<nbWords; i++) {
+      if ( cwords[i].name.isNull() ) qFatal(QString("Config word #%1 not defined").arg(i));
+      data()->_config->_words[i] = cwords[i];
+      const Config::Word &word = data()->_config->_words[i];
+      for (uint j=0; j<uint(word.masks.count()); j++) {
+        const Config::Mask &mask = word.masks[j];
+        for (uint k=0; k<uint(mask.values.count()); k++) {
+          const QStringList &vcnames = mask.values[k].configNames[type];
+          for (uint l=0; l<uint(vcnames.count()); l++) {
+            if ( vcnames[l].startsWith("0x") ) continue;
+            if ( cnames.contains(vcnames[l]) && cnames[vcnames[l]]!=mask.name )
+              qFatal(QString("Duplicated config name for %1/%2").arg(mask.name).arg(mask.values[k].name));
+            cnames[vcnames[l]] = word.masks[j].name;
+          }
+        }
+      }
+    }
+  }
+  // check validity of value names
+  for (uint i=0; i<nbWords; i++) {
+    const Config::Word &word = data()->_config->_words[i];
+    for (uint j=0; j<uint(word.masks.count()); j++) {
+      const Config::Mask &mask = word.masks[j];
+      for (uint k=0; k<uint(mask.values.count()); k++) {
+        const Config::Value &value = mask.values[k];
+        if ( !value.isValid() ) continue;
+        if ( !data()->_config->checkValueName(mask.name, value.name) )
+          qFatal(QString("Malformed value name \"%1\" in mask %2").arg(value.name).arg(mask.name));
+      }
+    }
+  }
+  // check if all values are explicit
+  for (uint i=0; i<nbWords; i++) {
+    const Config::Word &word = data()->_config->_words[i];
+    for (uint j=0; j<uint(word.masks.count()); j++) {
+      const Config::Mask &mask = word.masks[j];
+      BitValue::const_iterator it;
+      for (it=mask.value.begin(); it!=mask.value.end(); ++it)
+        if ( !hasValue(mask, *it) ) qFatal(QString("Value %1 not defined in mask %2").arg(toHexLabel(*it, data()->nbCharsWord(MemoryRangeType::Config))).arg(mask.name));
+    }
+  }
+
+  // checksums (after config bits!)
+  QDomElement checksums = findUniqueElement(device, "checksums", QString::null, QString::null);
+  if ( checksums.isNull() ) {
+    // qFatal("No checksum defined"); // #### FIXME
+  } else {
+    QMap<QString, bool> valueNames;
+    const Pic::Protection &protection = data()->_config->protection();
+    if ( protection.family()==Protection::BasicProtection ) {
+      QString maskName = protection.maskName(Protection::ProgramProtected, MemoryRangeType::Code);
+      const Pic::Config::Mask *mask = data()->_config->findMask(maskName);
+      Q_ASSERT(mask);
+      for (uint i=0; i<uint(mask->values.count()); i++) valueNames[mask->values[i].name] = false;
+    }
+    QDomNode child = checksums.firstChild();
+    while ( !child.isNull() ) {
+      if ( !child.isElement() ) continue;
+      if ( child.nodeName()!="checksum" ) qFatal("Childs of \"checksums\" should \"checksum\"");
+      QString valueName = getChecksumData(child.toElement());
+      if ( protection.family()==Protection::BasicProtection ) {
+        if ( !valueNames.contains(valueName) ) qFatal("Unknown protected attribute");
+        valueNames[valueName] = true;
+      }
+      child = child.nextSibling();
+    }
+    QMap<QString, bool>::const_iterator it;
+    for (it=valueNames.begin(); it!=valueNames.end(); ++it)
+      if ( !it.key().isEmpty() && !it.data() ) qFatal(QString("Missing checksum \"%1\"").arg(it.key()));
+  }
+}
+
+void processMirrored(QDomElement element)
+{
+  QValueVector<RangeData> mirrored;
+  QDomNode child = element.firstChild();
+  while ( !child.isNull() ) {
+    if ( !child.isElement() ) qFatal("\"mirror\" child should be an element");
+    QDomElement e = child.toElement();
+    if ( e.nodeName()!="range" ) qFatal("\"mirror\" child should be \"range\"");
+    RangeData rd;
+    bool ok;
+    rd.start = fromHexLabel(e.attribute("start"), &ok);
+    Address end = fromHexLabel(e.attribute("end"), &ok);
+    rd.length = end-rd.start+1;
+    if ( !mirrored.isEmpty() && rd.length!=mirrored[0].length )
+      qFatal("Mirrored are not of the same length");
+    mirrored.append(rd);
+    child = child.nextSibling();
+  }
+  if ( !mirrored.isEmpty() ) static_cast<RegistersData *>(data()->_registersData)->mirrored.append(mirrored);
+}
+
+void processUnused(QDomElement e)
+{
+  RangeData rd;
+  bool ok;
+  rd.start = fromHexLabel(e.attribute("start"), &ok);
+  if (!ok) qFatal("Malformed start for unused register");
+  Address end = fromHexLabel(e.attribute("end"), &ok);
+  rd.length = end-rd.start+1;
+  if (!ok) qFatal("Malformed end for unused register");
+  static_cast<RegistersData *>(data()->_registersData)->unused.append(rd);
+}
+
+void processSfr(QDomElement e)
+{
+  QString name = e.attribute("name");
+  if ( name.isEmpty() ) qFatal("SFR cannot have empty name");
+  if ( data()->registersData().sfrs.contains(name) || data()->registersData().combined.contains(name) )
+    qFatal("SFR name is duplicated");
+  bool ok;
+  uint address = fromHexLabel(e.attribute("address"), &ok);
+  if ( !ok ) qFatal(QString("SFR %1 address %2 is malformed").arg(name).arg(e.attribute("address")));
+  uint rlength = data()->registersData().nbBanks * data()->architecture().data().registerBankLength;
+  if ( address>=rlength ) qFatal(QString("Address %1 outside register range").arg(toHexLabel(address, 3)));
+  RegisterData rdata;
+  rdata.address = address;
+  uint nb = data()->registersData().nbBits();
+  if ( nb>Device::MAX_NB_PORT_BITS ) qFatal(QString("Need higher MAX_NB_PORT_BITS: %1").arg(nb));
+  QString access = e.attribute("access");
+  if ( uint(access.length())!=nb ) qFatal("access is missing or malformed");
+  QString mclr = e.attribute("mclr");
+  if ( uint(mclr.length())!=nb ) qFatal("mclr is missing or malformed");
+  QString por = e.attribute("por");
+  if ( uint(por.length())!=nb ) qFatal("por is missing or malformed");
+  for (uint i=0; i<nb; i++) {
+    uint k = nb - i - 1;
+    bool ok;
+    rdata.bits[k].properties = RegisterBitProperties(fromHex(access[i].latin1(), &ok));
+    if ( !ok || rdata.bits[k].properties>MaxRegisterBitProperty ) qFatal(QString("Malformed access bit %1").arg(k));
+    rdata.bits[k].mclr = RegisterBitState(fromHex(mclr[i].latin1(), &ok));
+    if ( !ok || rdata.bits[k].mclr>Nb_RegisterBitStates ) qFatal(QString("Malformed mclr bit %1").arg(k));
+    rdata.bits[k].por = RegisterBitState(fromHex(por[i].latin1(), &ok));
+    if ( !ok || rdata.bits[k].por>Nb_RegisterBitStates ) qFatal(QString("Malformed por bit %1").arg(k));
+  }
+  static_cast<RegistersData *>(data()->_registersData)->sfrs[name] = rdata;
+}
+
+void processCombined(QDomElement e)
+{
+  QString name = e.attribute("name");
+  if ( name.isEmpty() ) qFatal("Combined register cannot have empty name");
+  if ( data()->registersData().sfrs.contains(name) || data()->registersData().combined.contains(name) )
+    qFatal("Combined register name is duplicated");
+  bool ok;
+  CombinedData rdata;
+  rdata.address = fromHexLabel(e.attribute("address"), &ok);
+  if ( !ok ) qFatal(QString("Combined %1 address %2 is malformed").arg(name).arg(e.attribute("address")));
+  uint rlength = data()->registersData().nbBanks * data()->architecture().data().registerBankLength;
+  if ( rdata.address>=rlength ) qFatal(QString("Address %1 outside register range").arg(toHexLabel(rdata.address, 3)));
+  rdata.nbChars = 2*e.attribute("size").toUInt(&ok);
+  if ( !ok || rdata.nbChars<2 ) qFatal(QString("Combined %1 size %2 is malformed").arg(name).arg(e.attribute("size")));
+  Address end = rdata.address + rdata.nbChars/2 - 1;
+  if ( end>=rlength ) qFatal(QString("Address %1 outside register range").arg(toHexLabel(end, 3)));
+  static_cast<RegistersData *>(data()->_registersData)->combined[name] = rdata;
+}
+
+void processDeviceRegisters(QDomElement element)
+{
+  QString s = element.attribute("same_as");
+  if ( !s.isEmpty() ) {
+    if ( !_map.contains(s) ) qFatal(QString("Registers same as unknown device %1").arg(s));
+    const Pic::Data *d = static_cast<const Pic::Data *>(_map[s]);
+    data()->_registersData = d->_registersData;
+    return;
+  }
+
+  RegistersData &rdata = *static_cast<RegistersData *>(data()->_registersData);
+  bool ok;
+  rdata.nbBanks = element.attribute("nb_banks").toUInt(&ok);
+  if ( !ok || data()->registersData().nbBanks==0 ) qFatal("Malformed number of banks");
+  if ( data()->is18Family() ) {
+    rdata.accessBankSplit = fromHexLabel(element.attribute("access_bank_split_offset"), &ok);
+    if ( !ok || rdata.accessBankSplit==0 || rdata.accessBankSplit>=0xFF ) qFatal("Malformed access bank split offset");
+    rdata.unusedBankMask = fromHexLabel(element.attribute("unused_bank_mask"), &ok);
+    if ( !ok || rdata.unusedBankMask>=maxValue(NumberBase::Hex, rdata.nbBanks) ) qFatal("Malformed access unused bank mask");
+  } else {
+    rdata.accessBankSplit = 0;
+    rdata.unusedBankMask = 0;
+  }
+
+  QDomNode child = element.firstChild();
+  while ( !child.isNull() ) {
+    if ( !child.isElement() ) qFatal("\"device\" child should be an element");
+    QDomElement e = child.toElement();
+    if ( e.nodeName()=="mirror" ) processMirrored(e);
+    else if ( e.nodeName()=="unused" ) processUnused(e);
+    else if ( e.nodeName()=="combined" ) processCombined(e);
+    else if ( e.nodeName()=="sfr" ) processSfr(e);
+    else qFatal(QString("Node name \"%1\" is not recognized").arg(e.nodeName()));
+    child = child.nextSibling();
+  }
+
+  for (uint i=0; i<Device::MAX_NB_PORTS; i++) {
+    QString portname = rdata.portName(i);
+    if ( portname.isEmpty() ) break;
+    bool hasPort = rdata.sfrs.contains(portname);
+    QString trisname = rdata.trisName(i);
+    if ( trisname.isEmpty() ) continue;
+    bool hasTris = rdata.sfrs.contains(trisname);
+    if ( !hasPort && hasTris ) qFatal(QString("%1 needs %2 to be present").arg(trisname).arg(portname));
+    QString latchname = rdata.latchName(i);
+    if ( latchname.isEmpty() ) continue;
+    bool hasLatch = rdata.sfrs.contains(latchname);
+    if ( !hasPort && hasLatch ) qFatal(QString("%1 needs %2 to be present").arg(latchname).arg(portname));
+  }
+}
+
+void processRegistersFile(const QString &filename, QStringList &devices)
+{
+  QDomDocument doc = parseFile(filename);
+  QDomElement root = doc.documentElement();
+  if ( root.nodeName()!="registers" ) qFatal("root node should be \"registers\"");
+  for (QDomNode child=root.firstChild(); !child.isNull(); child = child.nextSibling()) {
+    if ( child.isComment() ) qDebug("comment: %s", child.toComment().data().latin1());
+    else {
+      if ( !child.isElement() ) qFatal("\"registers\" child should be an element");
+      if ( child.nodeName()!="device" ) qFatal("Device node should be named \"device\"");
+      QDomElement device = child.toElement();
+      QString name = device.attribute("name");
+      if ( devices.contains(name) ) qFatal(QString("Registers already defined for %1").arg(name));
+      if ( _map.contains(name) ) {
+        _data = _map[name];
+        processDeviceRegisters(device);
+        devices.append(name);
+      }
+    }
+  }
+}
+
+void processRegisters()
+{
+  QStringList devices;
+  processRegistersFile("registers/registers.xml", devices);
+  processRegistersFile("registers/registers_missing.xml", devices);
+
+  // check if we miss any register description
+  QMap<QString, Device::Data *>::const_iterator it = _map.begin();
+  for (; it!=_map.end(); ++it) {
+    _data = it.data();
+    if ( !devices.contains(it.key()) ) qWarning("Register description not found for %s", it.key().latin1());
+  }
+}
+
+virtual void checkPins(const QMap<QString, uint> &pinLabels) const
+{
+  if ( !pinLabels.contains("VDD") ) qFatal("No VDD pin specified");
+  if ( !pinLabels.contains("VSS") ) qFatal("No VSS pin specified");
+  QMap<QString, uint>::const_iterator it;
+  for (it=pinLabels.begin(); it!=pinLabels.end(); ++it) {
+    if ( it.key()=="VDD" || it.key()=="VSS" || it.key().startsWith("CCP") ) continue;
+    if ( it.data()!=1 ) qFatal(QString("Duplicated pin \"%1\"").arg(it.key()));
+  }
+  const Pic::RegistersData &rdata = static_cast<const Pic::RegistersData &>(*_data->registersData());
+  for (uint i=0; i<Device::MAX_NB_PORTS; i++) {
+    if ( !rdata.hasPort(i) ) continue;
+    for (uint k=0; k<Device::MAX_NB_PORT_BITS; k++) {
+      if ( !rdata.hasPortBit(i, k) ) continue;
+      QString name = rdata.portBitName(i, k);
+      if ( !pinLabels.contains(name) ) qFatal(QString("Pin \"%1\" not present").arg(name));
+    }
+  }
+}
+
+virtual void parse()
+{
+  Device::XmlToDataBase::parse();
+  processRegisters();
+}
+
+}; // class Pic::XmlToData
+
+} // namespace
+
+//-----------------------------------------------------------------------------
+XML_MAIN(Pic::XmlToData)
diff --git a/src/devices/pic/xml/xml.pro b/src/devices/pic/xml/xml.pro
new file mode 100644
index 0000000..d63b0aa
--- /dev/null
+++ b/src/devices/pic/xml/xml.pro
@@ -0,0 +1,13 @@
+STOPDIR = ../../../..
+include($${STOPDIR}/app.pro)
+
+TARGET   = pic_xml_to_data
+SOURCES += pic_xml_to_data.cpp
+LIBS    += ../../../devices/pic/base/libpicbase.a ../../../xml_to_data/libxmltodata.a \
+           ../../../devices/base/libdevicebase.a ../../../common/global/libglobal.a \
+           ../../../common/nokde/libnokde.a ../../../common/common/libcommon.a
+
+unix:QMAKE_POST_LINK = cd ../xml_data && ../xml/pic_xml_to_data
+unix:QMAKE_CLEAN += ../xml_data/pic_data.cpp
+win32:QMAKE_POST_LINK = cd ..\xml_data && ..\xml\pic_xml_to_data.exe
+win32:QMAKE_CLEAN += ..\xml_data\pic_data.cpp
diff --git a/src/devices/pic/xml_data/10F200.xml b/src/devices/pic/xml_data/10F200.xml
new file mode 100644
index 0000000..11ce1ff
--- /dev/null
+++ b/src/devices/pic/xml_data/10F200.xml
@@ -0,0 +1,76 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="10F200" document="019863" status="IP" memory_technology="FLASH" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEF1D" cchecksum="0xDD65" />
+    <checksum protected="040:0FE" bchecksum="0xEEF1" cchecksum="0xD45D" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="4" end="4" vdd_min="2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"            start="0x000" end="0x0FE" />
+  <memory name="calibration"        start="0x0FF" end="0x0FF" cal_opmask="0xF00"     cal_opcode="0xC00" />
+  <memory name="user_ids"           start="0x100" end="0x103" rmask="0x00F"          />
+  <memory name="config"             start="0x1FF" end="0x1FF" hexfile_offset="0xFFF" />
+  <memory name="calibration_backup" start="0x104" end="0x104" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x01F" cmask="0x01C" >
+    <mask name="FOSC"  value="0x003" >
+      <value value="default" name="invalid" />
+      <value value="0x003"   name="INTRC" cname="_IntRC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x008" >
+      <value value="0x000" name="040:0FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"  nb_pins="8" >
+    <pin index="1" name="N/C"             />
+    <pin index="2" name="VDD"             />
+    <pin index="3" name="GP2/T0CKI/FOSC4" />
+    <pin index="4" name="GP1/ICSPCLK"     />
+    <pin index="5" name="GP3/MCLR/VPP"    />
+    <pin index="6" name="VSS"             />
+    <pin index="7" name="N/C"             />
+    <pin index="8" name="GP0/ISCPDAT"     />
+  </package>
+
+  <package types="sot23" nb_pins="6" >
+    <pin index="1" name="" />
+    <pin index="2" name="" />
+    <pin index="3" name="" />
+    <pin index="4" name="" />
+    <pin index="5" name="" />
+    <pin index="6" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/10F202.xml b/src/devices/pic/xml_data/10F202.xml
new file mode 100644
index 0000000..25ce72a
--- /dev/null
+++ b/src/devices/pic/xml_data/10F202.xml
@@ -0,0 +1,76 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="10F202" document="020030" status="IP" memory_technology="FLASH" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEE1D" cchecksum="0xDC65" />
+    <checksum protected="040:1FE" bchecksum="0xEDF1" cchecksum="0xD35D" />
+  </checksums>
+  
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="4" end="4" vdd_min="2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"            start="0x000" end="0x1FE" />
+  <memory name="calibration"        start="0x1FF" end="0x1FF" cal_opmask="0xF00"     cal_opcode="0xC00" />
+  <memory name="user_ids"           start="0x200" end="0x203" rmask="0x00F"          />
+  <memory name="config"             start="0x3FF" end="0x3FF" hexfile_offset="0xFFF" />
+  <memory name="calibration_backup" start="0x204" end="0x204" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x01F" cmask="0x01C" >
+    <mask name="FOSC"  value="0x003" >
+      <value value="default" name="invalid" />
+      <value value="0x003" name="INTRC" cname="_IntRC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x008" >
+      <value value="0x000" name="040:1FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"  nb_pins="8" >
+    <pin index="1" name="N/C"             />
+    <pin index="2" name="VDD"             />
+    <pin index="3" name="GP2/T0CKI/FOSC4" />
+    <pin index="4" name="GP1/ICSPCLK"     />
+    <pin index="5" name="GP3/MCLR/VPP"    />
+    <pin index="6" name="VSS"             />
+    <pin index="7" name="N/C"             />
+    <pin index="8" name="GP0/ISCPDAT"     />
+  </package>
+
+  <package types="sot23" nb_pins="6" >
+    <pin index="1" name="" />
+    <pin index="2" name="" />
+    <pin index="3" name="" />
+    <pin index="4" name="" />
+    <pin index="5" name="" />
+    <pin index="6" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/10F204.xml b/src/devices/pic/xml_data/10F204.xml
new file mode 100644
index 0000000..e2d2e6d
--- /dev/null
+++ b/src/devices/pic/xml_data/10F204.xml
@@ -0,0 +1,76 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="10F204" document="020031" status="IP" memory_technology="FLASH" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEF1D" cchecksum="0xDD65" />
+    <checksum protected="040:0FE" bchecksum="0xEEF1" cchecksum="0xD45D" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="4" end="4" vdd_min="2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"            start="0x000" end="0x0FE" />
+  <memory name="calibration"        start="0x0FF" end="0x0FF" cal_opmask="0xF00"     cal_opcode="0xC00" />
+  <memory name="user_ids"           start="0x100" end="0x103" rmask="0x00F"          />
+  <memory name="config"             start="0x1FF" end="0x1FF" hexfile_offset="0xFFF" />
+  <memory name="calibration_backup" start="0x104" end="0x104" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x01F" cmask="0x01C" >
+    <mask name="FOSC"  value="0x003" >
+      <value value="default" name="invalid" />
+      <value value="0x003" name="INTRC" cname="_IntRC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x008" >
+      <value value="0x000" name="040:0FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"  nb_pins="8" >
+    <pin index="1" name="N/C"                  />
+    <pin index="2" name="VDD"                  />
+    <pin index="3" name="GP2/T0CKI/FOSC4/COUT" />
+    <pin index="4" name="GP1/ISCPCLK/CIN-"     />
+    <pin index="5" name="GP3/MCLR/VPP"         />
+    <pin index="6" name="VSS"                  />
+    <pin index="7" name="N/C"                  />
+    <pin index="8" name="GP0/ISCPDAT/CIN+"     />
+  </package>
+
+  <package types="sot23" nb_pins="6" >
+    <pin index="1" name="" />
+    <pin index="2" name="" />
+    <pin index="3" name="" />
+    <pin index="4" name="" />
+    <pin index="5" name="" />
+    <pin index="6" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/10F206.xml b/src/devices/pic/xml_data/10F206.xml
new file mode 100644
index 0000000..4e66268
--- /dev/null
+++ b/src/devices/pic/xml_data/10F206.xml
@@ -0,0 +1,76 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="10F206" document="020032" status="IP" memory_technology="FLASH" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEE1D" cchecksum="0xDC65" />
+    <checksum protected="040:1FE" bchecksum="0xEDF1" cchecksum="0xD35D" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="4" end="4" vdd_min="2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"            start="0x000" end="0x1FE" />
+  <memory name="calibration"        start="0x1FF" end="0x1FF" cal_opmask="0xF00"     cal_opcode="0xC00" />
+  <memory name="user_ids"           start="0x200" end="0x203" rmask="0x00F"          />
+  <memory name="config"             start="0x3FF" end="0x3FF" hexfile_offset="0xFFF" />
+  <memory name="calibration_backup" start="0x204" end="0x204" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x01F" cmask="0x01C" >
+    <mask name="FOSC"  value="0x003" >
+      <value value="default" name="invalid" />
+      <value value="0x003" name="INTRC" cname="_IntRC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x008" >
+      <value value="0x000" name="040:1FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"  nb_pins="8" >
+    <pin index="1" name="N/C"                  />
+    <pin index="2" name="VDD"                  />
+    <pin index="3" name="GP2/T0CKI/FOSC4/COUT" />
+    <pin index="4" name="GP1/ISCPCLK/CIN-"     />
+    <pin index="5" name="GP3/MCLR/VPP"         />
+    <pin index="6" name="VSS"                  />
+    <pin index="7" name="N/C"                  />
+    <pin index="8" name="GP0/ISCPDAT/CIN+"     />
+  </package>
+
+  <package types="sot23" nb_pins="6" >
+    <pin index="1" name="" />
+    <pin index="2" name="" />
+    <pin index="3" name="" />
+    <pin index="4" name="" />
+    <pin index="5" name="" />
+    <pin index="6" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/10F220.xml b/src/devices/pic/xml_data/10F220.xml
new file mode 100644
index 0000000..694d161
--- /dev/null
+++ b/src/devices/pic/xml_data/10F220.xml
@@ -0,0 +1,81 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="10F220" document="023673" status="IP" memory_technology="FLASH" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEF20" cchecksum="0xDD68" />
+    <checksum protected="040:0FE" bchecksum="0xEEF7" cchecksum="0xD463" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="4" end="4" vdd_min="2" vdd_max="5.5" />
+    <frequency start="8" end="8" vdd_min="2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"            start="0x000" end="0x0FE" />
+  <memory name="calibration"        start="0x0FF" end="0x0FF" cal_opmask="0xF00"     cal_opcode="0xC00" />
+  <memory name="user_ids"           start="0x100" end="0x103" rmask="0x00F"          />
+  <memory name="config"             start="0x1FF" end="0x1FF" hexfile_offset="0xFFF" />
+  <memory name="calibration_backup" start="0x104" end="0x104" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x01F" >
+    <mask name="IOSCFS" value="0x001" >
+      <value value="0x000" name="4MHZ" cname="_IOFSCS_4MHZ" ecnames="_IOSCFS_4MHZ" />
+      <value value="0x001" name="8MHZ" cname="_IOFSCS_8MHZ" ecnames="_IOSCFS_8MHZ" />
+    </mask>
+    <mask name="MCPU"   value="0x002" >
+      <value value="0x000" name="On"  cname="_MCPU_ON"  />
+      <value value="0x002" name="Off" cname="_MCPU_OFF" />
+    </mask>
+    <mask name="WDT"    value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"     value="0x008" >
+      <value value="0x000" name="040:0FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE"  value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"  nb_pins="8" >
+    <pin index="1" name="N/C"             />
+    <pin index="2" name="VDD"             />
+    <pin index="3" name="GP2/T0CKI/FOSC4" />
+    <pin index="4" name="GP1/ISCPCLK/AN1" />
+    <pin index="5" name="GP3/MCLR/VPP"    />
+    <pin index="6" name="VSS"             />
+    <pin index="7" name="N/C"             />
+    <pin index="8" name="GP0/ISCPDAT/AN0" />
+  </package>
+
+  <package types="sot23" nb_pins="6" >
+    <pin index="1" name="" />
+    <pin index="2" name="" />
+    <pin index="3" name="" />
+    <pin index="4" name="" />
+    <pin index="5" name="" />
+    <pin index="6" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/10F222.xml b/src/devices/pic/xml_data/10F222.xml
new file mode 100644
index 0000000..4cba906
--- /dev/null
+++ b/src/devices/pic/xml_data/10F222.xml
@@ -0,0 +1,81 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="10F222" document="023672" status="IP" memory_technology="FLASH" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEE20" cchecksum="0xDC68" />
+    <checksum protected="040:1FE" bchecksum="0xEDF7" cchecksum="0xD363" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="4" end="4" vdd_min="2" vdd_max="5.5" />
+    <frequency start="8" end="8" vdd_min="2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"            start="0x000" end="0x1FE" />
+  <memory name="calibration"        start="0x1FF" end="0x1FF" cal_opmask="0xF00"     cal_opcode="0xC00" />
+  <memory name="user_ids"           start="0x200" end="0x203" rmask="0x00F"          />
+  <memory name="config"             start="0x3FF" end="0x3FF" hexfile_offset="0xFFF" />
+  <memory name="calibration_backup" start="0x204" end="0x204" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x01F" >
+    <mask name="IOSCFS" value="0x001" >
+      <value value="0x000" name="4MHZ" cname="_IOFSCS_4MHZ" ecnames="_IOSCFS_4MHZ" />
+      <value value="0x001" name="8MHZ" cname="_IOFSCS_8MHZ" ecnames="_IOSCFS_8MHZ" />
+    </mask>
+    <mask name="MCPU"   value="0x002" >
+      <value value="0x000" name="On"  cname="_MCPU_ON"  />
+      <value value="0x002" name="Off" cname="_MCPU_OFF" />
+    </mask>
+    <mask name="WDT"    value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"     value="0x008" >
+      <value value="0x000" name="040:1FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE"  value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"  nb_pins="8" >
+    <pin index="1" name="N/C"             />
+    <pin index="2" name="VDD"             />
+    <pin index="3" name="GP2/T0CKI/FOSC4" />
+    <pin index="4" name="GP1/ISCPCLK/AN1" />
+    <pin index="5" name="GP3/MCLR/VPP"    />
+    <pin index="6" name="VSS"             />
+    <pin index="7" name="N/C"             />
+    <pin index="8" name="GP0/ISCPDAT/AN0" />
+  </package>
+
+  <package types="sot23" nb_pins="6" >
+    <pin index="1" name="" />
+    <pin index="2" name="" />
+    <pin index="3" name="" />
+    <pin index="4" name="" />
+    <pin index="5" name="" />
+    <pin index="6" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12C508.xml b/src/devices/pic/xml_data/12C508.xml
new file mode 100644
index 0000000..cb39eae
--- /dev/null
+++ b/src/devices/pic/xml_data/12C508.xml
@@ -0,0 +1,71 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12C508" document="010102" status="NR" alternative="12F508" memory_technology="EPROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEE20" cchecksum="0xDC68" />
+    <checksum protected="040:1FE" bchecksum="0xEDF7" cchecksum="0xD363" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="13"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x000" end="0x1FE" />
+  <memory name="calibration" start="0x1FF" end="0x1FF" cal_opmask="0xF00" cal_opcode="0xC00" />
+  <memory name="user_ids"    start="0x200" end="0x203" rmask="0x00F"      />
+  <memory name="config"      start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x01F" bvalue="0x01F" >
+    <mask name="FOSC"  value="0x003" >
+      <value value="0x000" name="LP"    cname="_LP_OSC"    />
+      <value value="0x001" name="XT"    cname="_XT_OSC"    />
+      <value value="0x002" name="INTRC" cname="_IntRC_OSC" />
+      <value value="0x003" name="EXTRC" cname="_ExtRC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x008" >
+      <value value="0x000" name="040:1FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="VDD"            />
+    <pin index="2" name="GP5/OSC1/CLKIN" />
+    <pin index="3" name="GP4/OSC2"       />
+    <pin index="4" name="GP3/MCLR/VPP"   />
+    <pin index="5" name="GP2/T0CKI"      />
+    <pin index="6" name="GP1"            />
+    <pin index="7" name="GP0"            />
+    <pin index="8" name="VSS"            />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12C508A.xml b/src/devices/pic/xml_data/12C508A.xml
new file mode 100644
index 0000000..f1ffb3f
--- /dev/null
+++ b/src/devices/pic/xml_data/12C508A.xml
@@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12C508A" document="010103" status="NR" alternative="12F508" memory_technology="EPROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEE20" cchecksum="0xDC68" />
+    <checksum protected="040:1FE" bchecksum="0xEDF7" cchecksum="0xD363" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="13"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x000" end="0x1FE" />
+  <memory name="calibration" start="0x1FF" end="0x1FF" cal_opmask="0xF00" cal_opcode="0xC00" />
+  <memory name="user_ids"    start="0x200" end="0x203" rmask="0x00F"      />
+  <memory name="config"      start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x01F" bvalue="0x01F" >
+    <mask name="FOSC"  value="0x003" >
+      <value value="0x000" name="LP"    cname="_LP_OSC"    />
+      <value value="0x001" name="XT"    cname="_XT_OSC"    />
+      <value value="0x002" name="INTRC" cname="_IntRC_OSC" />
+      <value value="0x003" name="EXTRC" cname="_ExtRC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x008" >
+      <value value="0x000" name="040:1FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="VDD"            />
+    <pin index="2" name="GP5/OSC1/CLKIN" />
+    <pin index="3" name="GP4/OSC2"       />
+    <pin index="4" name="GP3/MCLR/VPP"   />
+    <pin index="5" name="GP2/T0CKI"      />
+    <pin index="6" name="GP1"            />
+    <pin index="7" name="GP0"            />
+    <pin index="8" name="VSS"            />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12C509.xml b/src/devices/pic/xml_data/12C509.xml
new file mode 100644
index 0000000..dbe885b
--- /dev/null
+++ b/src/devices/pic/xml_data/12C509.xml
@@ -0,0 +1,71 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12C509" document="010104" status="NR" alternative="12F509" memory_technology="EPROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEC20" cchecksum="0xDA68" />
+    <checksum protected="040:3FE" bchecksum="0xEBF7" cchecksum="0xD163" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="13"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x000" end="0x3FE" />
+  <memory name="calibration" start="0x3FF" end="0x3FF" cal_opmask="0xF00" cal_opcode="0xC00" />
+  <memory name="user_ids"    start="0x400" end="0x403" rmask="0x00F"      />
+  <memory name="config"      start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x01F" bvalue="0x01F" >
+    <mask name="FOSC"  value="0x003" >
+      <value value="0x000" name="LP"    cname="_LP_OSC"    />
+      <value value="0x001" name="XT"    cname="_XT_OSC"    />
+      <value value="0x002" name="INTRC" cname="_IntRC_OSC" />
+      <value value="0x003" name="EXTRC" cname="_ExtRC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x008" >
+      <value value="0x000" name="040:3FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="VDD"            />
+    <pin index="2" name="GP5/OSC1/CLKIN" />
+    <pin index="3" name="GP4/OSC2"       />
+    <pin index="4" name="GP3/MCLR/VPP"   />
+    <pin index="5" name="GP2/T0CKI"      />
+    <pin index="6" name="GP1"            />
+    <pin index="7" name="GP0"            />
+    <pin index="8" name="VSS"            />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12C509A.xml b/src/devices/pic/xml_data/12C509A.xml
new file mode 100644
index 0000000..240783f
--- /dev/null
+++ b/src/devices/pic/xml_data/12C509A.xml
@@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12C509A" document="010105" status="NR" alternative="12F509" memory_technology="EPROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEC20" cchecksum="0xDA68" />
+    <checksum protected="040:3FE" bchecksum="0xEBF7" cchecksum="0xD163" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="13"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x000" end="0x3FE" />
+  <memory name="calibration" start="0x3FF" end="0x3FF" cal_opmask="0xF00" cal_opcode="0xC00" />
+  <memory name="user_ids"    start="0x400" end="0x403" rmask="0x00F"      />
+  <memory name="config"      start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x01F" bvalue="0x01F" >
+    <mask name="FOSC"  value="0x003" >
+      <value value="0x000" name="LP"    cname="_LP_OSC"    />
+      <value value="0x001" name="XT"    cname="_XT_OSC"    />
+      <value value="0x002" name="INTRC" cname="_IntRC_OSC" />
+      <value value="0x003" name="EXTRC" cname="_ExtRC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x008" >
+      <value value="0x000" name="040:3FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="VDD"            />
+    <pin index="2" name="GP5/OSC1/CLKIN" />
+    <pin index="3" name="GP4/OSC2"       />
+    <pin index="4" name="GP3/MCLR/VPP"   />
+    <pin index="5" name="GP2/T0CKI"      />
+    <pin index="6" name="GP1"            />
+    <pin index="7" name="GP0"            />
+    <pin index="8" name="VSS"            />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12C671.xml b/src/devices/pic/xml_data/12C671.xml
new file mode 100644
index 0000000..f675723
--- /dev/null
+++ b/src/devices/pic/xml_data/12C671.xml
@@ -0,0 +1,85 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12C671" document="010106" status="NR" alternative="12F675" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xFC00" cchecksum="0xC7CE" />
+    <checksum protected="200:3FE" bchecksum="0x0FBF" cchecksum="0xC174" />
+    <checksum protected="All"     bchecksum="0xFC9F" cchecksum="0xC86D" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0" end="10" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x0000" end="0x03FE" />
+  <memory name="calibration" start="0x03FF" end="0x03FF" cal_opmask="0x3C00" cal_opcode="0x3400" />
+  <memory name="user_ids"    start="0x2000" end="0x2003" rmask="0x000F"      />
+  <memory name="config"      start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" icnames="_CP_50" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="invalid" />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTRC_OSC" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRC_OSC" />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0080" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0080" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F60" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1520" name="200:3FE" cname="_CP_75"  />
+      <value value="default" name="Off"     cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="VDD"                 />
+    <pin index="2" name="GP5/OSC1/CLKIN"      />
+    <pin index="3" name="GP4/OSC2/AN3/CLKOUT" />
+    <pin index="4" name="GP3/MCLR/VPP"        />
+    <pin index="5" name="GP2/T0CKI/AN2/INT"   />
+    <pin index="6" name="GP1/AN1/VREF"        />
+    <pin index="7" name="GP0/AN0"             />
+    <pin index="8" name="VSS"                 />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12C672.xml b/src/devices/pic/xml_data/12C672.xml
new file mode 100644
index 0000000..80511f1
--- /dev/null
+++ b/src/devices/pic/xml_data/12C672.xml
@@ -0,0 +1,87 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12C672" document="010107" status="NR" alternative="12F683" memory_technology="EPROM" architecture="16X" 
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xF800" cchecksum="0xC3CE" />
+    <checksum protected="400:7FE" bchecksum="0x1EDF" cchecksum="0xD094" />
+    <checksum protected="200:7FE" bchecksum="0x0BBF" cchecksum="0xBD74" />
+    <checksum protected="All"     bchecksum="0xF89F" cchecksum="0xC46D" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0" end="10" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x0000" end="0x07FE" />
+  <memory name="calibration" start="0x07FF" end="0x07FF" cal_opmask="0x3C00" cal_opcode="0x3400" />
+  <memory name="user_ids"    start="0x2000" end="0x2003" rmask="0x000F"      />
+  <memory name="config"      start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="invalid" />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTRC_OSC" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRC_OSC" />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0080" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0080" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F60" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1520" name="200:7FE" cname="_CP_75"  />
+      <value value="0x2A40" name="400:7FE" cname="_CP_50"  />
+      <value value="default" name="Off"     cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="VDD"                 />
+    <pin index="2" name="GP5/OSC1/CLKIN"      />
+    <pin index="3" name="GP4/OSC2/AN3/CLKOUT" />
+    <pin index="4" name="GP3/MCLR/VPP"        />
+    <pin index="5" name="GP2/T0CKI/AN2/INT"   />
+    <pin index="6" name="GP1/AN1/VREF"        />
+    <pin index="7" name="GP0/AN0"             />
+    <pin index="8" name="VSS"                 />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12CE518.xml b/src/devices/pic/xml_data/12CE518.xml
new file mode 100644
index 0000000..e27cbb3
--- /dev/null
+++ b/src/devices/pic/xml_data/12CE518.xml
@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12CE518" document="010108" status="NR" alternative="12F629" memory_technology="EPROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEE20" cchecksum="0xDC68" />
+    <checksum protected="040:1FE" bchecksum="0xEDF7" cchecksum="0xD363" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="13"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x000" end="0x1FE" />
+  <memory name="calibration" start="0x1FF" end="0x1FF" cal_opmask="0xF00" cal_opcode="0xC00" />
+  <memory name="user_ids"    start="0x200" end="0x203" rmask="0x00F"      />
+  <memory name="config"      start="0xFFF" end="0xFFF" />
+  <memory name="eeprom"      start="0x000" end="0x00F" rmask="0xFF" hexfile_offset="?" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x01F" bvalue="0x01F" >
+    <mask name="FOSC"  value="0x003" >
+      <value value="0x000" name="LP"    cname="_LP_OSC"    />
+      <value value="0x001" name="XT"    cname="_XT_OSC"    />
+      <value value="0x002" name="INTRC" cname="_IntRC_OSC" />
+      <value value="0x003" name="EXTRC" cname="_ExtRC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x008" >
+      <value value="0x000" name="040:1FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="VDD"            />
+    <pin index="2" name="GP5/OSC1/CLKIN" />
+    <pin index="3" name="GP4/OSC2"       />
+    <pin index="4" name="GP3/MCLR/VPP"   />
+    <pin index="5" name="GP2/T0CKI"      />
+    <pin index="6" name="GP1"            />
+    <pin index="7" name="GP0"            />
+    <pin index="8" name="VSS"            />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12CE519.xml b/src/devices/pic/xml_data/12CE519.xml
new file mode 100644
index 0000000..210e186
--- /dev/null
+++ b/src/devices/pic/xml_data/12CE519.xml
@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12CE519" document="010109" status="NR" alternative="12F629" memory_technology="EPROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEC20" cchecksum="0xDA68" />
+    <checksum protected="040:3FE" bchecksum="0xEBF7" cchecksum="0xD163" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="13"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x000" end="0x3FE" />
+  <memory name="calibration" start="0x3FF" end="0x3FF" cal_opmask="0xF00" cal_opcode="0xC00" />
+  <memory name="user_ids"    start="0x400" end="0x403" rmask="0x00F"      />
+  <memory name="config"      start="0xFFF" end="0xFFF" />
+  <memory name="eeprom"      start="0x000" end="0x00F" rmask="0xFF" hexfile_offset="?" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x01F" bvalue="0x01F" >
+    <mask name="FOSC"  value="0x003" >
+      <value value="0x000" name="LP"    cname="_LP_OSC"    />
+      <value value="0x001" name="XT"    cname="_XT_OSC"    />
+      <value value="0x002" name="INTRC" cname="_IntRC_OSC" />
+      <value value="0x003" name="EXTRC" cname="_ExtRC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x008" >
+      <value value="0x000" name="040:3FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="VDD"            />
+    <pin index="2" name="GP5/OSC1/CLKIN" />
+    <pin index="3" name="GP4/OSC2"       />
+    <pin index="4" name="GP3/MCLR/VPP"   />
+    <pin index="5" name="GP2/T0CKI"      />
+    <pin index="6" name="GP1"            />
+    <pin index="7" name="GP0"            />
+    <pin index="8" name="VSS"            />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12CE673.xml b/src/devices/pic/xml_data/12CE673.xml
new file mode 100644
index 0000000..3007c29
--- /dev/null
+++ b/src/devices/pic/xml_data/12CE673.xml
@@ -0,0 +1,86 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12CE673" document="010110" status="NR" alternative="12F675" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xFC00" cchecksum="0xC7CE" />
+    <checksum protected="200:3FE" bchecksum="0x0FBF" cchecksum="0xC174" />
+    <checksum protected="All"     bchecksum="0xFC9F" cchecksum="0xC86D" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0" end="10" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x0000" end="0x03FE" />
+  <memory name="calibration" start="0x03FF" end="0x03FF" cal_opmask="0x3C00" cal_opcode="0x3400" />
+  <memory name="user_ids"    start="0x2000" end="0x2003" rmask="0x000F"      />
+  <memory name="config"      start="0x2007" end="0x2007" />
+  <memory name="eeprom"      start="0x0000" end="0x000F" hexfile_offset="?" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" icnames="_CP_50" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="invalid" />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTRC_OSC" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRC_OSC" />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0080" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0080" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F60" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1520" name="200:3FE" cname="_CP_75"  />
+      <value value="default" name="Off"     cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="8" >
+    <pin index="1" name="VDD"                 />
+    <pin index="2" name="GP5/OSC1/CLKIN"      />
+    <pin index="3" name="GP4/OSC2/AN3/CLKOUT" />
+    <pin index="4" name="GP3/MCLR/VPP"        />
+    <pin index="5" name="GP2/T0CKI/AN2/INT"   />
+    <pin index="6" name="GP1/AN1/VREF"        />
+    <pin index="7" name="GP0/AN0"             />
+    <pin index="8" name="VSS"                 />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12CE674.xml b/src/devices/pic/xml_data/12CE674.xml
new file mode 100644
index 0000000..7670f3f
--- /dev/null
+++ b/src/devices/pic/xml_data/12CE674.xml
@@ -0,0 +1,88 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12CE674" document="010111" status="NR" alternative="12F683" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xF800" cchecksum="0xC3CE" />
+    <checksum protected="400:7FE" bchecksum="0x1EDF" cchecksum="0xD094" />
+    <checksum protected="200:7FE" bchecksum="0x0BBF" cchecksum="0xBD74" />
+    <checksum protected="All"     bchecksum="0xF89F" cchecksum="0xC46D" />
+  </checksums>
+
+  <!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0" end="10" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x0000" end="0x07FE" />
+  <memory name="calibration" start="0x07FF" end="0x07FF" cal_opmask="0x3C00" cal_opcode="0x3400" />
+  <memory name="user_ids"    start="0x2000" end="0x2003" rmask="0x000F"      />
+  <memory name="config"      start="0x2007" end="0x2007" />
+  <memory name="eeprom"      start="0x0000" end="0x000F" hexfile_offset="?" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="invalid" />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTRC_OSC" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRC_OSC" />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0080" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0080" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F60" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1520" name="200:7FE" cname="_CP_75"  />
+      <value value="0x2A40" name="400:7FE" cname="_CP_50"  />
+      <value value="default" name="Off"     cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="8" >
+    <pin index="1" name="VDD"                 />
+    <pin index="2" name="GP5/OSC1/CLKIN"      />
+    <pin index="3" name="GP4/OSC2/AN3/CLKOUT" />
+    <pin index="4" name="GP3/MCLR/VPP"        />
+    <pin index="5" name="GP2/T0CKI/AN2/INT"   />
+    <pin index="6" name="GP1/AN1/VREF"        />
+    <pin index="7" name="GP0/AN0"             />
+    <pin index="8" name="VSS"                 />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12CR509A.xml b/src/devices/pic/xml_data/12CR509A.xml
new file mode 100644
index 0000000..9a795da
--- /dev/null
+++ b/src/devices/pic/xml_data/12CR509A.xml
@@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12CR509A" document="010112" status="NR" alternative="12F509" memory_technology="ROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEC20" cchecksum="0xDA68" />
+    <checksum protected="040:3FE" bchecksum="0xEBF7" cchecksum="0xD163" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="13"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x000" end="0x3FE" />
+  <memory name="calibration" start="0x3FF" end="0x3FF" cal_opmask="0xF00" cal_opcode="0xC00" />
+  <memory name="user_ids"    start="0x400" end="0x403" rmask="0x00F"      />
+  <memory name="config"      start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x01F" bvalue="0x01F" >
+    <mask name="FOSC"  value="0x003" >
+      <value value="0x000" name="LP"    cname="_LP_OSC"    />
+      <value value="0x001" name="XT"    cname="_XT_OSC"    />
+      <value value="0x002" name="INTRC" cname="_IntRC_OSC" />
+      <value value="0x003" name="EXTRC" cname="_ExtRC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x008" >
+      <value value="0x000" name="040:3FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="8" >
+    <pin index="1" name="VDD"            />
+    <pin index="2" name="GP5/OSC1/CLKIN" />
+    <pin index="3" name="GP4/OSC2"       />
+    <pin index="4" name="GP3/MCLR/VPP"   />
+    <pin index="5" name="GP2/T0CKI"      />
+    <pin index="6" name="GP1"            />
+    <pin index="7" name="GP0"            />
+    <pin index="8" name="VSS"            />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12F508.xml b/src/devices/pic/xml_data/12F508.xml
new file mode 100644
index 0000000..19fd956
--- /dev/null
+++ b/src/devices/pic/xml_data/12F508.xml
@@ -0,0 +1,71 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12F508" document="020094" status="IP" memory_technology="FLASH" architecture="10X" pc="12"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEE20" cchecksum="0xDC68" />
+    <checksum protected="040:1FE" bchecksum="0xEDF7" cchecksum="0xD363" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"            start="0x000" end="0x1FE" />
+  <memory name="calibration"        start="0x1FF" end="0x1FF" cal_opmask="0xF00"     cal_opcode="0xC00" />
+  <memory name="user_ids"           start="0x200" end="0x203" rmask="0x00F"          />
+  <memory name="config"             start="0x3FF" end="0x3FF" hexfile_offset="0xFFF" />
+  <memory name="calibration_backup" start="0x204" end="0x204" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x01F" bvalue="0x01F" >
+    <mask name="FOSC"  value="0x003" >
+      <value value="0x000" name="LP"    cname="_LP_OSC"    />
+      <value value="0x001" name="XT"    cname="_XT_OSC"    />
+      <value value="0x002" name="INTRC" cname="_IntRC_OSC" />
+      <value value="0x003" name="EXTRC" cname="_ExtRC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x008" >
+      <value value="0x000" name="040:1FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic msop" nb_pins="8" >
+    <pin index="1" name="VDD"            />
+    <pin index="2" name="GP5/OSC1/CLKIN" />
+    <pin index="3" name="GP4/OSC2"       />
+    <pin index="4" name="GP3/MCLR/VPP"   />
+    <pin index="5" name="GP2/T0CKI"      />
+    <pin index="6" name="GP1/ICSPCLK"    />
+    <pin index="7" name="GP0/ICSPDAT"    />
+    <pin index="8" name="VSS"            />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12F509.xml b/src/devices/pic/xml_data/12F509.xml
new file mode 100644
index 0000000..8f3ae12
--- /dev/null
+++ b/src/devices/pic/xml_data/12F509.xml
@@ -0,0 +1,71 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12F509" document="020095" status="IP" memory_technology="FLASH" architecture="10X" pc="12"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEC20" cchecksum="0xDA68" />
+    <checksum protected="040:3FE" bchecksum="0xEBF7" cchecksum="0xD163" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"            start="0x000" end="0x3FE" />
+  <memory name="calibration"        start="0x3FF" end="0x3FF" cal_opmask="0xF00"     cal_opcode="0xC00" />
+  <memory name="user_ids"           start="0x400" end="0x403" rmask="0x00F"          />
+  <memory name="config"             start="0x7FF" end="0x7FF" hexfile_offset="0xFFF" />
+  <memory name="calibration_backup" start="0x404" end="0x404" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x01F" bvalue="0x01F" >
+    <mask name="FOSC"  value="0x003" >
+      <value value="0x000" name="LP"    cname="_LP_OSC"    />
+      <value value="0x001" name="XT"    cname="_XT_OSC"    />
+      <value value="0x002" name="INTRC" cname="_IntRC_OSC" />
+      <value value="0x003" name="EXTRC" cname="_ExtRC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x008" >
+      <value value="0x000" name="040:3FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic msop" nb_pins="8" >
+    <pin index="1" name="VDD"            />
+    <pin index="2" name="GP5/OSC1/CLKIN" />
+    <pin index="3" name="GP4/OSC2"       />
+    <pin index="4" name="GP3/MCLR/VPP"   />
+    <pin index="5" name="GP2/T0CKI"      />
+    <pin index="6" name="GP1/ICSPCLK"    />
+    <pin index="7" name="GP0/ICSPDAT"    />
+    <pin index="8" name="VSS"            />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12F510.xml b/src/devices/pic/xml_data/12F510.xml
new file mode 100644
index 0000000..15a2d81
--- /dev/null
+++ b/src/devices/pic/xml_data/12F510.xml
@@ -0,0 +1,74 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12F510" document="023670" status="IP" memory_technology="FLASH" architecture="10X" pc="10"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEC40" cchecksum="0xDA88" />
+    <checksum protected="040:3FE" bchecksum="0xEC37" cchecksum="0xD1A3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="4" vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="8" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"            start="0x000" end="0x3FE" />
+  <memory name="calibration"        start="0x3FF" end="0x3FF" cal_opmask="0xF00"     cal_opcode="0xC00" />
+  <memory name="user_ids"           start="0x400" end="0x403" rmask="0x00F"          />
+  <memory name="config"             start="0x7FF" end="0x7FF" hexfile_offset="0xFFF" />
+  <memory name="calibration_backup" start="0x404" end="0x404" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x03F" >
+    <mask name="FOSC"   value="0x003" >
+      <value value="0x000" name="LP"    cname="_LP_OSC"    />
+      <value value="0x001" name="XT"    cname="_XT_OSC"    />
+      <value value="0x002" name="INTRC" cname="_IntRC_OSC" />
+      <value value="0x003" name="EXTRC" cname="_ExtRC_OSC" />
+    </mask>
+    <mask name="WDT"    value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"     value="0x008" >
+      <value value="0x000" name="040:3FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE"  value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="IOSCFS" value="0x020" >
+      <value value="0x000" name="4MHZ" cname="_IOSCFS_OFF" />
+      <value value="0x020" name="8MHZ" cname="_IOSCFS_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic msop" nb_pins="8" >
+    <pin index="1" name="VDD"                   />
+    <pin index="2" name="GP5/OSC1/CLKIN"        />
+    <pin index="3" name="GP4/OSC2"              />
+    <pin index="4" name="GP3/MCLR/VPP"          />
+    <pin index="5" name="GP2/AN2/T0CKI/C1OUT"   />
+    <pin index="6" name="GP1/AN1/C1IN-/ICSPCLK" />
+    <pin index="7" name="GP0/AN0/C1IN+/ICSPDAT" />
+    <pin index="8" name="VSS"                   />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12F519.xml b/src/devices/pic/xml_data/12F519.xml
new file mode 100644
index 0000000..600618c
--- /dev/null
+++ b/src/devices/pic/xml_data/12F519.xml
@@ -0,0 +1,82 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12F519" status="IP" memory_technology="FLASH" architecture="10X" pc="11"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+  <!--* Documents ************************************************************-->
+  <documents webpage="530188" datasheet="41319" progsheet="41316" erratas="" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"                      bchecksum="0xEC80" cchecksum="0xDAC8" />
+    <checksum protected="040:3FE" mprotected="CPD" bchecksum="0xEC77" cchecksum="0xD1E3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="5.5" />
+    <frequency start="4" end="8" vdd_min="3.0" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"               start="0x000" end="0x3FE" />
+  <memory name="calibration"        start="0x3FF" end="0x3FF" cal_opmask="0xF00"     cal_opcode="0xC00" />
+  <memory name="eeprom"             start="0x400" end="0x43F" />
+  <memory name="user_ids"           start="0x440" end="0x443" rmask="0x00F"          />
+  <memory name="config"             start="0x7FF" end="0x7FF" hexfile_offset="0xFFF" />
+  <memory name="calibration_backup" start="0x444" end="0x444" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x07F" >
+    <mask name="FOSC"   value="0x003" >
+      <value value="0x000" name="LP"    cname="_LP_OSC"    />
+      <value value="0x001" name="XT"    cname="_XT_OSC"    />
+      <value value="0x002" name="INTRC" cname="_IntRC_OSC" />
+      <value value="0x003" name="EXTRC" cname="_ExtRC_OSC" />
+    </mask>
+    <mask name="WDT"    value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"     value="0x008" >
+      <value value="0x000" name="040:3FE" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE"  value="0x010" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x010" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="IOSCFS" value="0x020" >
+      <value value="0x000" name="4MHZ" cname="_IOSCFS_OFF" />
+      <value value="0x020" name="8MHZ" cname="_IOSCFS_ON"  />
+    </mask>
+    <mask name="CPD"    value="0x040" >
+      <value value="0x000" name="All" cname="_CPDF_ON"  />
+      <value value="0x040" name="Off" cname="_CPDF_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic msop dfn" nb_pins="8" >
+    <pin index="1" name="VDD"                   />
+    <pin index="2" name="GP5/OSC1/CLKIN"        />
+    <pin index="3" name="GP4/OSC2"              />
+    <pin index="4" name="GP3/MCLR/VPP"          />
+    <pin index="5" name="GP2/T0CKI"             />
+    <pin index="6" name="GP1/ICSPCLK"           />
+    <pin index="7" name="GP0/ICSPDAT"           />
+    <pin index="8" name="VSS"                   />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12F609.xml b/src/devices/pic/xml_data/12F609.xml
new file mode 100644
index 0000000..d3409ee
--- /dev/null
+++ b/src/devices/pic/xml_data/12F609.xml
@@ -0,0 +1,99 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12F609" status="IP" memory_technology="FLASH" self_write="no" self_write="no" architecture="16X" id="0x2240" id_high_voltage="0x2280"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="028259" datasheet="41302" progsheet="41284" erratas="80294" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xFFFF" cchecksum="0xCBCD" />
+    <checksum protected="All" bchecksum="0x03BE" cchecksum="0xCF8C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="8"  vdd_min="2.0" vdd_max="5.5" />
+    <frequency start="8"  end="10" vdd_min="3.0" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <frequency_range name="extended" special="high_voltage" >
+    <frequency start="0"  end="8"  vdd_min="2.0" vdd_max="5.0" />
+    <frequency start="8"  end="10" vdd_min="3.0" vdd_max="5.0" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.0" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x03FF" />
+  <memory name="calibration"  start="0x2008" end="0x2008" cal_opmask="0x0000" cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"      />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x03FF" >
+    <mask name="FOSC"   value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"    value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE"  value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE"  value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"     value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="IOSCFS" value="0x0080" >
+      <value value="0x0000" name="4MHZ" cname="_IOSCFS_4MHZ" />
+      <value value="0x0080" name="8MHZ" cname="_IOSCFS_8MHZ" />
+    </mask>
+    <mask name="BODEN"  value="0x0300" >
+      <value value="default" name="Off"    cname="_BOR_OFF"    />
+      <value value="0x0200"  name="On_run" cname="_BOR_NSLEEP" />
+      <value value="0x0300"  name="On"     cname="_BOR_ON"     />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic dfns tssop" nb_pins="8" >
+    <pin index="1" name="VDD" />
+    <pin index="2" name="GP5/OSC1/T1CKI/CLKIN" />
+    <pin index="3" name="GP4/OSC2/C1IN-/T1G/CLKOUT" />
+    <pin index="4" name="GP3/MCLR/VPP" />
+    <pin index="5" name="GP2/T0CKI/INT/COUT" />
+    <pin index="6" name="GP1/C0IN-/CLK" />
+    <pin index="7" name="GP0/CIN+/DAT" />
+    <pin index="8" name="VSS" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12F615.xml b/src/devices/pic/xml_data/12F615.xml
new file mode 100644
index 0000000..d59445e
--- /dev/null
+++ b/src/devices/pic/xml_data/12F615.xml
@@ -0,0 +1,99 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12F615" status="IP" memory_technology="FLASH" self_write="no" self_write="no" architecture="16X" id="0x2180" id_high_voltage="0x21A0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027148" datasheet="41302" progsheet="41284" erratas="80294" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xFFFF" cchecksum="0xCBCD" />
+    <checksum protected="All" bchecksum="0x03BE" cchecksum="0xCF8C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <frequency_range name="extended" special="high_voltage">
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.0" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.0" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.0" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x03FF" />
+  <memory name="calibration"  start="0x2008" end="0x2008" cal_opmask="0x0000" cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"      />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x03FF" >
+    <mask name="FOSC"   value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"    value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE"  value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE"  value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"     value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="IOSCFS" value="0x0080" >
+      <value value="0x0000" name="4MHZ" cname="_IOSCFS_4MHZ" />
+      <value value="0x0080" name="8MHZ" cname="_IOSCFS_8MHZ" />
+    </mask>
+    <mask name="BODEN"  value="0x0300" >
+      <value value="default" name="Off"    cname="_BOR_OFF"    />
+      <value value="0x0200" name="On_run" cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"     cname="_BOR_ON"     />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic dfns tssop" nb_pins="8" >
+    <pin index="1" name="VDD" />
+    <pin index="2" name="GP5/OSC1/T1CKI/CLKIN" />
+    <pin index="3" name="GP4/OSC2/AN3/C1IN-/T1G/CLKOUT" />
+    <pin index="4" name="GP3/MCLR/VPP" />
+    <pin index="5" name="GP2/AN2/T0CKI/INT/COUT/CCP1/P1A" />
+    <pin index="6" name="GP1/AN1/C0IN-/VREF/CLK" />
+    <pin index="7" name="GP0/AN0/CIN+/P1B/DAT" />
+    <pin index="8" name="VSS" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12F629.xml b/src/devices/pic/xml_data/12F629.xml
new file mode 100644
index 0000000..53c0cf4
--- /dev/null
+++ b/src/devices/pic/xml_data/12F629.xml
@@ -0,0 +1,102 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12F629" document="010113" status="IP" memory_technology="FLASH" self_write="no" self_write="no" architecture="16X" id="0x0F80"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xBE00" cchecksum="0x89CE" />
+    <checksum protected="All" bchecksum="0xBF7F" cchecksum="0x8B4D" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" special="AD off" />
+    <frequency start="0"  end="4"  vdd_min="2.2" vdd_max="5.5" special="AD on"  />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" special="AD off" />
+    <frequency start="0"  end="4"  vdd_min="2.5" vdd_max="5.5" special="AD on"  />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"   max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x03FE" />
+  <memory name="calibration"  start="0x03FF" end="0x03FF" cal_opmask="0x3C00"     cal_opcode="0x3400" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x31FF" bvalue="0x31FF" pmask="0x3000" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC"           cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0080" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0080" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BG"    value="0x3000">
+      <value value="0x0000" name="Lowest"   />
+      <value value="0x1000" name="Mid/Low"  />
+      <value value="0x2000" name="Mid/High" />
+      <value value="0x3000" name="Highest"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic dfns" nb_pins="8" >
+    <pin index="1" name="VDD"                  />
+    <pin index="2" name="GP5/T1CKI/OSC1/CLKIN" />
+    <pin index="3" name="GP4/T1G/OSC2/CLKOUT"  />
+    <pin index="4" name="GP3/MCLR/VPP"         />
+    <pin index="5" name="GP2/T0CKI/INT/COUT"   />
+    <pin index="6" name="GP1/CIN-/ICSPCLK"     />
+    <pin index="7" name="GP0/CIN+/ICSPDAT"     />
+    <pin index="8" name="VSS"                  />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12F635.xml b/src/devices/pic/xml_data/12F635.xml
new file mode 100644
index 0000000..f06c3b6
--- /dev/null
+++ b/src/devices/pic/xml_data/12F635.xml
@@ -0,0 +1,104 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12F635" document="019829" status="IP" memory_technology="FLASH" self_write="no" self_write="no" architecture="16X" id="0x0FA0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x1BFF" cchecksum="0xE7CD" />
+    <checksum protected="All" bchecksum="0x3BBE" cchecksum="0x078C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x03FF" />
+  <memory name="calibration"  start="0x2008" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x1FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOD_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOD_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOD_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOD_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="WUREN" value="0x1000" >
+      <value value="0x0000" name="On"  cname="_WUREN_ON"  />
+      <value value="0x1000" name="Off" cname="_WUREN_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic dfns" nb_pins="8" >
+    <pin index="1" name="VDD"                    />
+    <pin index="2" name="GP5/T1CKI/OSC1/CLKIN"   />
+    <pin index="3" name="GP4/T1G/OSC2/CLKOUT"    />
+    <pin index="4" name="GP3/MCLR/VPP"           />
+    <pin index="5" name="GP2/T0CKI/INT/COUT"     />
+    <pin index="6" name="GP1/CIN-/ICSPCLK"       />
+    <pin index="7" name="GP0/CIN+/ICSPDAT/ULPWU" />
+    <pin index="8" name="VSS"                    />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12F675.xml b/src/devices/pic/xml_data/12F675.xml
new file mode 100644
index 0000000..6e0f054
--- /dev/null
+++ b/src/devices/pic/xml_data/12F675.xml
@@ -0,0 +1,102 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12F675" document="010114" status="IP" memory_technology="FLASH" self_write="no" self_write="no" architecture="16X" id="0x0FC0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xBE00" cchecksum="0x89CE" />
+    <checksum protected="All" bchecksum="0xBF7F" cchecksum="0x8B4D" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" special="AD off" />
+    <frequency start="0"  end="4"  vdd_min="2.2" vdd_max="5.5" special="AD on"  />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" special="AD off" />
+    <frequency start="0"  end="4"  vdd_min="2.5" vdd_max="5.5" special="AD on"  />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"   max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x03FE" />
+  <memory name="calibration"  start="0x03FF" end="0x03FF" cal_opmask="0x3C00"     cal_opcode="0x3400" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x31FF" bvalue="0x31FF" pmask="0x3000" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC"           cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0080" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0080" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BG"    value="0x3000">
+      <value value="0x0000" name="Lowest"   />
+      <value value="0x1000" name="Mid/Low"  />
+      <value value="0x2000" name="Mid/High" />
+      <value value="0x3000" name="Highest"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic dfns" nb_pins="8" >
+    <pin index="1" name="VDD"                       />
+    <pin index="2" name="GP5/T1CKI/OSC1/CLKIN"      />
+    <pin index="3" name="GP4/AN3/T1G/OSC2/CLKOUT"   />
+    <pin index="4" name="GP3/MCLR/VPP"              />
+    <pin index="5" name="GP2/AN2/T0CKI/INT/COUT"    />
+    <pin index="6" name="GP1/AN1/CIN-/VREF/ICSPCLK" />
+    <pin index="7" name="GP0/AN0/CIN+/ICSPDAT"      />
+    <pin index="8" name="VSS"                       />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/12F683.xml b/src/devices/pic/xml_data/12F683.xml
new file mode 100644
index 0000000..1c23260
--- /dev/null
+++ b/src/devices/pic/xml_data/12F683.xml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="12F683" document="010115" status="IP" memory_technology="FLASH" self_write="no" self_write="no" architecture="16X" id="0x0460"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x07FF" cchecksum="0xD3CD" />
+    <checksum protected="All" bchecksum="0x17BE" cchecksum="0xE38C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="calibration"  start="0x2008" end="0x2008" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x0FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOD_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOD_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOD_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOD_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic dfn dfns" nb_pins="8" >
+    <pin index="1" name="VDD"                         />
+    <pin index="2" name="GP5/T1CKI/OSC1/CLKIN"        />
+    <pin index="3" name="GP4/AN3/T1G/OSC2/CLKOUT"     />
+    <pin index="4" name="GP3/MCLR/VPP"                />
+    <pin index="5" name="GP2/AN2/T0CKI/INT/COUT/CCP1" />
+    <pin index="6" name="GP1/AN1/C1IN-/VREF/ICSPCLK"  />
+    <pin index="7" name="GP0/AN0/C1IN+/ICSPDAT/ULPWU" />
+    <pin index="8" name="VSS"                         />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/14000.xml b/src/devices/pic/xml_data/14000.xml
new file mode 100644
index 0000000..8cf2db6
--- /dev/null
+++ b/src/devices/pic/xml_data/14000.xml
@@ -0,0 +1,99 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="14000" document="010116" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"                  bchecksum="0x2FFD" cchecksum="0xFBCB" />
+    <checksum protected="All" mprotected="CPC" bchecksum="0x300A" cchecksum="0xFBD8" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="2.7" vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x0000" end="0x0FBF" />
+  <memory name="calibration" start="0x0FC0" end="0x0FFF" cal_opmask="0x0000" cal_opcode="0x0000" />
+  <memory name="user_ids"    start="0x2000" end="0x2003" rmask="0x007F"      />
+  <memory name="config"      start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FBD" pmask="0x0042" >
+    <mask name="FOSC"  value="0x0001" >
+      <value value="0x0000" name="HS"    cname="_FOSC_HS" />
+      <value value="0x0001" name="INTRC" cname="_FOSC_RC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="TRIM" value="0x0042" >
+      <value value="0x0000" name="00" />
+      <value value="0x0002" name="01" />
+      <value value="0x0040" name="10" />
+      <value value="0x0042" name="11" />
+    </mask>
+    <mask name="CP"    value="0x1E30" >
+      <value value="0x0000"  name="All" cname="_CPP_ON _CPU_ON"   />
+      <value value="0x1E30"  name="Off" cname="_CPP_OFF _CPU_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+    <mask name="CPC"   value="0x2180" >
+      <value value="0x0000"  name="All" cname="_CPC_ON"  />
+      <value value="0x2180"  name="Off" cname="_CPC_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C432.xml b/src/devices/pic/xml_data/16C432.xml
new file mode 100644
index 0000000..e112d5c
--- /dev/null
+++ b/src/devices/pic/xml_data/16C432.xml
@@ -0,0 +1,88 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C432" document="010117" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="400:7FF" bchecksum="0x5DEE" cchecksum="0x0FA3" />
+    <checksum protected="200:7FF" bchecksum="0x4ADE" cchecksum="0xFC93" />
+    <checksum protected="All"     bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip ssop" nb_pins="20" >
+    <pin index="1"  name="LIN"          />
+    <pin index="2"  name="RA2/AN2/VREF" />
+    <pin index="3"  name="RA3/AN3"      />
+    <pin index="4"  name="RA4/T0CKI"    />
+    <pin index="5"  name="MCLR/VPP"     />
+    <pin index="6"  name="VSS"          />
+    <pin index="7"  name="RB0/INT"      />
+    <pin index="8"  name="RB1"          />
+    <pin index="9"  name="RB2"          />
+    <pin index="10" name="RB3"          />
+    <pin index="11" name="RB4"          />
+    <pin index="12" name="RB5"          />
+    <pin index="13" name="RB6"          />
+    <pin index="14" name="RB7"          />
+    <pin index="15" name="VDD"          />
+    <pin index="16" name="OSC2/CLKOUT"  />
+    <pin index="17" name="OSC1/CLKIN"   />
+    <pin index="18" name="RA0/AN0"      />
+    <pin index="19" name="BACT"         />
+    <pin index="20" name="VBAT"         />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C433.xml b/src/devices/pic/xml_data/16C433.xml
new file mode 100644
index 0000000..cf07aaa
--- /dev/null
+++ b/src/devices/pic/xml_data/16C433.xml
@@ -0,0 +1,91 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C433" document="010118" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xF800" cchecksum="0xC3CE" />
+    <checksum protected="400:7FE" bchecksum="0x1EDF" cchecksum="0xD094" />
+    <checksum protected="200:7FE" bchecksum="0x0BBF" cchecksum="0xBD74" />
+    <checksum protected="All"     bchecksum="0xF89F" cchecksum="0xC46D" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="10" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x0000" end="0x07FE" />
+  <memory name="calibration" start="0x07FF" end="0x07FF" cal_opmask="0x3C00" cal_opcode="0x3400" />
+  <memory name="user_ids"    start="0x2000" end="0x2003" rmask="0x007F"      />
+  <memory name="config"      start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="invalid" />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTRC_OSC" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRC_OSC" />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0080" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0080" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F60" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1520" name="200:7FE" cname="_CP_75"  />
+      <value value="0x2A40" name="400:7FE" cname="_CP_50"  />
+      <value value="0x3F60" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="LIN"                 />
+    <pin index="2"  name="N/C"                 />
+    <pin index="3"  name="VSS"                 />
+    <pin index="4"  name="VDD"                 />
+    <pin index="5"  name="AVDD"                />
+    <pin index="6"  name="GP5/OSC1/CLKIN"      />
+    <pin index="7"  name="GP4/OSC2/AN3/CLKOUT" />
+    <pin index="8"  name="GP3/MCLR/VPP"        />
+    <pin index="9"  name="N/C"                 />
+    <pin index="10" name="N/C"                 />
+    <pin index="11" name="GP2/T0CKI/AN2/INT"   />
+    <pin index="12" name="GP1/AN1/VREF"        />
+    <pin index="13" name="GP0/AN0"             />
+    <pin index="14" name="VSS"                 />
+    <pin index="15" name="AVSS"                />
+    <pin index="16" name="VSS"                 />
+    <pin index="17" name="BACT"                />
+    <pin index="18" name="VBAT"                />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C505.xml b/src/devices/pic/xml_data/16C505.xml
new file mode 100644
index 0000000..2cbe2c9
--- /dev/null
+++ b/src/devices/pic/xml_data/16C505.xml
@@ -0,0 +1,87 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C505" document="010119" status="NR" alternative="16F505" memory_technology="EPROM" architecture="10X" pc="12"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xFC00" cchecksum="0xEA48" />
+    <checksum protected="040:3FE" bchecksum="0xFBEF" cchecksum="0xE15B" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"     start="0x000" end="0x3FE" />
+  <memory name="calibration" start="0x3FF" end="0x3FF" cal_opmask="0xF00" cal_opcode="0xC00" />
+  <memory name="user_ids"    start="0x400" end="0x403" rmask="0x00F"      />
+  <memory name="config"      start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0xFFF" >
+    <mask name="FOSC"  value="0x007" >
+      <value value="0x000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x003" name="invalid" />
+      <value value="0x004" name="INTRC_IO"     cname="_IntRC_OSC_RB4EN"    />
+      <value value="0x005" name="INTRC_CLKOUT" cname="_IntRC_OSC_CLKOUTEN" />
+      <value value="0x006" name="EXTRC_IO"     cname="_ExtRC_OSC_RB4EN"    />
+      <value value="0x007" name="EXTRC_CLKOUT" cname="_ExtRC_OSC_CLKOUTEN" />
+    </mask>
+    <mask name="WDT"   value="0x008" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x020" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0xFD0" >
+      <value value="0x000" name="040:3FE" cname="_CP_ON"  />
+      <value value="0xFD0" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="14" >
+    <pin index="1"  name="VDD"             />
+    <pin index="2"  name="RB5/OSC1/CLKIN"  />
+    <pin index="3"  name="RB4/OSC2/CLKOUT" />
+    <pin index="4"  name="RB3/MCLR/VPP"    />
+    <pin index="5"  name="RC5/T0CKI"       />
+    <pin index="6"  name="RC4"             />
+    <pin index="7"  name="RC3"             />
+    <pin index="8"  name="RC2"             />
+    <pin index="9"  name="RC1"             />
+    <pin index="10" name="RC0"             />
+    <pin index="11" name="RB2"             />
+    <pin index="12" name="RB1/ICSPCLK"     />
+    <pin index="13" name="RB0/ICSPDAT"     />
+    <pin index="14" name="VSS"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C52.xml b/src/devices/pic/xml_data/16C52.xml
new file mode 100644
index 0000000..6ef7753
--- /dev/null
+++ b/src/devices/pic/xml_data/16C52.xml
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C52" document="010120" status="EOL" memory_technology="EPROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"             bchecksum="0xFE8B" cchecksum="0xECD3" />
+    <checksum protected="All" type="XOR4" bchecksum="0x1683" cchecksum="0x1671" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="6.25" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code" start="0x000" end="0x17F" />
+  <memory name="config"  start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x008" bvalue="0x00B" >
+    <mask name="FOSC" value="0x003" >
+      <value value="default" name="invalid" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="CP"   value="0x008" >
+      <value value="0x000" name="All" cname="_CP_ON"  />
+      <value value="0x008" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C54.xml b/src/devices/pic/xml_data/16C54.xml
new file mode 100644
index 0000000..06455ee
--- /dev/null
+++ b/src/devices/pic/xml_data/16C54.xml
@@ -0,0 +1,105 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C54" document="010121" status="NR" alternative="16F54" memory_technology="EPROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" constant="0x0FF0" bchecksum="0x0DFF" cchecksum="0xFC47" />
+    <checksum protected="All" type="XOR4"       bchecksum="0x1E07" cchecksum="0x1DF5" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"    vdd_min="3"   vdd_max="6.25" osc="RC" />
+    <frequency start="0" end="4"    vdd_min="3"   vdd_max="6.25" osc="XT" />
+    <frequency start="0" end="20"   vdd_min="4.5" vdd_max="5.5"  osc="HS" />
+    <frequency start="0" end="0.04" vdd_min="2.5" vdd_max="6.25" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"    vdd_min="3.25" vdd_max="6"   osc="RC" />
+    <frequency start="0" end="4"    vdd_min="3.25" vdd_max="6"   osc="XT" />
+    <frequency start="0" end="20"   vdd_min="4.5"  vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.04" vdd_min="2.5"  vdd_max="6"   osc="LP" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x1FF" />
+  <memory name="user_ids" start="0x200" end="0x203" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x00C" bvalue="0x00F" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0x008" >
+      <value value="0x000" name="All" cname="_CP_ON"  />
+      <value value="0x008" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKL"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="RA2" 		/>
+    <pin index="2"  name="RA3" 		/>
+    <pin index="3"  name="RTCC" 	/>
+    <pin index="4"  name="MCLR/VPP" 	/>
+    <pin index="5"  name="VSS" 		/>
+    <pin index="6"  name="VSS" 		/>
+    <pin index="7"  name="RB0" 		/>
+    <pin index="8"  name="RB1" 		/>
+    <pin index="9"  name="RB2" 		/>
+    <pin index="10" name="RB3" 		/>
+    <pin index="11" name="RB4" 		/>
+    <pin index="12" name="RB5" 		/>
+    <pin index="13" name="RB6" 		/>
+    <pin index="14" name="RB7" 		/>
+    <pin index="15" name="VDD" 		/>
+    <pin index="16" name="VDD" 		/>
+    <pin index="17" name="OSC2/CLKOUT" 	/>
+    <pin index="18" name="OSC1/CLKIN" 	/>
+    <pin index="19" name="RA0" 		/>
+    <pin index="20" name="RA1" 		/>
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C54A.xml b/src/devices/pic/xml_data/16C54A.xml
new file mode 100644
index 0000000..c264f10
--- /dev/null
+++ b/src/devices/pic/xml_data/16C54A.xml
@@ -0,0 +1,115 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C54A" document="010122" status="NR" alternative="16F54" memory_technology="EPROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"             bchecksum="0x0DFF" cchecksum="0xFC47" />
+    <checksum protected="All" type="XOR4" bchecksum="0x1E07" cchecksum="0x1DF5" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="6.25" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="6.25" osc="XT" />
+    <frequency start="0" end="20"  vdd_min="4.5" vdd_max="5.5"  osc="HS" />
+    <frequency start="0" end="0.2" vdd_min="3"   vdd_max="6.25" osc="LP" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_voltage" >
+    <frequency start="0" end="4"   vdd_min="2" vdd_max="3.8" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="2" vdd_max="3.8" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2" vdd_max="3.8" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3.5" vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3.5" vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" osc="HS" />
+  </frequency_range>
+  <frequency_range name="extended"   special="low_power"   >
+    <frequency start="0" end="4"   vdd_min="2.5" vdd_max="6.25" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="2.5" vdd_max="6.25" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="6.25" osc="LP" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x1FF" />
+  <memory name="user_ids" start="0x200" end="0x203" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="All" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C54B.xml b/src/devices/pic/xml_data/16C54B.xml
new file mode 100644
index 0000000..d20ae0e
--- /dev/null
+++ b/src/devices/pic/xml_data/16C54B.xml
@@ -0,0 +1,110 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C54B" document="010123" status="EOL" memory_technology="EPROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x0DFF" cchecksum="0xFC47" />
+    <checksum protected="040:1FF" bchecksum="0x0DC6" cchecksum="0xF332" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20"  vdd_min="4.5" vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.2" vdd_min="3"   vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x1FF" />
+  <memory name="user_ids" start="0x200" end="0x203" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="040:1FF" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C54C.xml b/src/devices/pic/xml_data/16C54C.xml
new file mode 100644
index 0000000..0d1907b
--- /dev/null
+++ b/src/devices/pic/xml_data/16C54C.xml
@@ -0,0 +1,110 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C54C" document="010124" status="NR" alternative="16F54" memory_technology="EPROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x0DFF" cchecksum="0xFC47" />
+    <checksum protected="040:1FF" bchecksum="0x0DC6" cchecksum="0xF332" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20"  vdd_min="4.5" vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.2" vdd_min="3"   vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x1FF" />
+  <memory name="user_ids" start="0x200" end="0x203" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="040:1FF" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C55.xml b/src/devices/pic/xml_data/16C55.xml
new file mode 100644
index 0000000..0d93443
--- /dev/null
+++ b/src/devices/pic/xml_data/16C55.xml
@@ -0,0 +1,123 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C55" document="010125" status="NR" alternative="16C55A" memory_technology="EPROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" constant="0x0FF0" bchecksum="0x0DFF" cchecksum="0xFC47" />
+    <checksum protected="All" type="XOR4"       bchecksum="0x1E07" cchecksum="0x1DF5" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"    vdd_min="3"   vdd_max="6.25" osc="RC" />
+    <frequency start="0" end="4"    vdd_min="3"   vdd_max="6.25" osc="XT" />
+    <frequency start="0" end="20"   vdd_min="4.5" vdd_max="5.5"  osc="HS" />
+    <frequency start="0" end="0.04" vdd_min="2.5" vdd_max="6.25" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"    vdd_min="3.25" vdd_max="6"   osc="RC" />
+    <frequency start="0" end="4"    vdd_min="3.25" vdd_max="6"   osc="XT" />
+    <frequency start="0" end="20"   vdd_min="4.5"  vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.04" vdd_min="2.5"  vdd_max="6"   osc="LP" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x1FF" />
+  <memory name="user_ids" start="0x200" end="0x203" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x00C" bvalue="0x00F" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0x008" >
+      <value value="0x000" name="All" cname="_CP_ON"  />
+      <value value="0x008" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="T0CKI"       />
+    <pin index="2"  name="VDD"         />
+    <pin index="3"  name="N/C"         />
+    <pin index="4"  name="VSS"         />
+    <pin index="5"  name="N/C"         />
+    <pin index="6"  name="RA0"         />
+    <pin index="7"  name="RA1"         />
+    <pin index="8"  name="RA2"         />
+    <pin index="9"  name="RA3"         />
+    <pin index="10" name="RB0"         />
+    <pin index="11" name="RB1"         />
+    <pin index="12" name="RB2"         />
+    <pin index="13" name="RB3"         />
+    <pin index="14" name="RB4"         />
+    <pin index="15" name="RB5"         />
+    <pin index="16" name="RB6"         />
+    <pin index="17" name="RB7"         />
+    <pin index="18" name="RC0"         />
+    <pin index="19" name="RC1"         />
+    <pin index="20" name="RC2"         />
+    <pin index="21" name="RC3"         />
+    <pin index="22" name="RC4"         />
+    <pin index="23" name="RC5"         />
+    <pin index="24" name="RC6"         />
+    <pin index="25" name="RC7"         />
+    <pin index="26" name="OSC2/CLKOUT" />
+    <pin index="27" name="OSC1/CLKIN"  />
+    <pin index="28" name="MCLR/VPP"    />
+  </package>
+
+  <package types="ssop"      nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C554.xml b/src/devices/pic/xml_data/16C554.xml
new file mode 100644
index 0000000..1723220
--- /dev/null
+++ b/src/devices/pic/xml_data/16C554.xml
@@ -0,0 +1,112 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C554" document="010126" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x3D3F" cchecksum="0x090D" />
+    <checksum protected="All" bchecksum="0x3D4E" cchecksum="0x091C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.7" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x01FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FBC" bvalue="0x3F3F"  >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x3F30" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="RA4/T0CKI"   />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0/INT"     />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C557.xml b/src/devices/pic/xml_data/16C557.xml
new file mode 100644
index 0000000..3a9ddab
--- /dev/null
+++ b/src/devices/pic/xml_data/16C557.xml
@@ -0,0 +1,137 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C557" status="?" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="?" datasheet="40143" progsheet="30261" erratas="40143e1" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x373F" cchecksum="0x030D" />
+    <checksum protected="400:7FF" bchecksum="0x5D6E" cchecksum="0x0F23" />
+    <checksum protected="200:7FF" bchecksum="0x4A5E" cchecksum="0xFC13" />
+    <checksum protected="All"     bchecksum="0x374E" cchecksum="0x031C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.7" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FBC" bvalue="0x3F3F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="RA4/T0CKI"   />
+    <pin index="2"  name="VDD"         />
+    <pin index="3"  name="N/C"         />
+    <pin index="4"  name="VSS"         />
+    <pin index="5"  name="RA5"         />
+    <pin index="6"  name="RA0"         />
+    <pin index="7"  name="RA1"         />
+    <pin index="8"  name="RA2"         />
+    <pin index="9"  name="RA3"         />
+    <pin index="10" name="RB0/INT"     />
+    <pin index="11" name="RB1"         />
+    <pin index="12" name="RB2"         />
+    <pin index="13" name="RB3"         />
+    <pin index="14" name="RB4"         />
+    <pin index="15" name="RB5"         />
+    <pin index="16" name="RB6"         />
+    <pin index="17" name="RB7"         />
+    <pin index="18" name="RC0"         />
+    <pin index="19" name="RC1"         />
+    <pin index="20" name="RC2"         />
+    <pin index="21" name="RC3"         />
+    <pin index="22" name="RC4"         />
+    <pin index="23" name="RC5"         />
+    <pin index="24" name="RC6"         />
+    <pin index="25" name="RC7"         />
+    <pin index="26" name="OSC2/CLKOUT" />
+    <pin index="27" name="OSC1/CLKIN"  />
+    <pin index="28" name="MCLR/VPP"    />
+  </package>
+
+  <package types="ssop"      nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C558.xml b/src/devices/pic/xml_data/16C558.xml
new file mode 100644
index 0000000..484efee
--- /dev/null
+++ b/src/devices/pic/xml_data/16C558.xml
@@ -0,0 +1,116 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C558" document="010127" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x373F" cchecksum="0x030D" />
+    <checksum protected="400:7FF" bchecksum="0x5D6E" cchecksum="0x0F23" />
+    <checksum protected="200:7FF" bchecksum="0x4A5E" cchecksum="0xFC13" />
+    <checksum protected="All"     bchecksum="0x374E" cchecksum="0x031C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.7" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FBC" bvalue="0x3F3F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="RA4/T0CKI"   />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0/INT"     />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C55A.xml b/src/devices/pic/xml_data/16C55A.xml
new file mode 100644
index 0000000..27b9eac
--- /dev/null
+++ b/src/devices/pic/xml_data/16C55A.xml
@@ -0,0 +1,128 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C55A" document="010128" status="IP" memory_technology="EPROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x0DFF" cchecksum="0xFC47" />
+    <checksum protected="040:1FF" bchecksum="0x0DC6" cchecksum="0xF332" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20"  vdd_min="4.5" vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.2" vdd_min="3"   vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x1FF" />
+  <memory name="user_ids" start="0x200" end="0x203" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="040:1FF" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="T0CKI"       />
+    <pin index="2"  name="VDD"         />
+    <pin index="3"  name="N/C"         />
+    <pin index="4"  name="VSS"         />
+    <pin index="5"  name="N/C"         />
+    <pin index="6"  name="RA0"         />
+    <pin index="7"  name="RA1"         />
+    <pin index="8"  name="RA2"         />
+    <pin index="9"  name="RA3"         />
+    <pin index="10" name="RB0"         />
+    <pin index="11" name="RB1"         />
+    <pin index="12" name="RB2"         />
+    <pin index="13" name="RB3"         />
+    <pin index="14" name="RB4"         />
+    <pin index="15" name="RB5"         />
+    <pin index="16" name="RB6"         />
+    <pin index="17" name="RB7"         />
+    <pin index="18" name="RC0"         />
+    <pin index="19" name="RC1"         />
+    <pin index="20" name="RC2"         />
+    <pin index="21" name="RC3"         />
+    <pin index="22" name="RC4"         />
+    <pin index="23" name="RC5"         />
+    <pin index="24" name="RC6"         />
+    <pin index="25" name="RC7"         />
+    <pin index="26" name="OSC2/CLKOUT" />
+    <pin index="27" name="OSC1/CLKIN"  />
+    <pin index="28" name="MCLR/VPP"    />
+  </package>
+
+  <package types="ssop"      nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C56.xml b/src/devices/pic/xml_data/16C56.xml
new file mode 100644
index 0000000..a8ec195
--- /dev/null
+++ b/src/devices/pic/xml_data/16C56.xml
@@ -0,0 +1,105 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C56" document="010129" status="NR" alternative="16C56A" memory_technology="EPROM" architecture="10X" pc="10"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" constant="0x0FF0" bchecksum="0x0BFF" cchecksum="0xFA47" />
+    <checksum protected="All" type="XOR4"       bchecksum="0x3C07" cchecksum="0x3BF5" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"    vdd_min="3"   vdd_max="6.25" osc="RC" />
+    <frequency start="0" end="4"    vdd_min="3"   vdd_max="6.25" osc="XT" />
+    <frequency start="0" end="20"   vdd_min="4.5" vdd_max="5.5"  osc="HS" />
+    <frequency start="0" end="0.04" vdd_min="2.5" vdd_max="6.25" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"    vdd_min="3.25" vdd_max="6"   osc="RC" />
+    <frequency start="0" end="4"    vdd_min="3.25" vdd_max="6"   osc="XT" />
+    <frequency start="0" end="20"   vdd_min="4.5"  vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.04" vdd_min="2.5"  vdd_max="6"   osc="LP" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x3FF" />
+  <memory name="user_ids" start="0x400" end="0x403" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x00C" bvalue="0x00F" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0x008" >
+      <value value="0x000" name="All" cname="_CP_ON"  />
+      <value value="0x008" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C56A.xml b/src/devices/pic/xml_data/16C56A.xml
new file mode 100644
index 0000000..0543765
--- /dev/null
+++ b/src/devices/pic/xml_data/16C56A.xml
@@ -0,0 +1,110 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C56A" document="010130" status="IP" memory_technology="EPROM" architecture="10X" pc="10"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x0BFF" cchecksum="0xFA47" />
+    <checksum protected="040:3FF" bchecksum="0x0BC6" cchecksum="0xF132" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20"  vdd_min="4.5" vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.2" vdd_min="3"   vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x3FF" />
+  <memory name="user_ids" start="0x400" end="0x403" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="040:3FF" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C57.xml b/src/devices/pic/xml_data/16C57.xml
new file mode 100644
index 0000000..4aef05a
--- /dev/null
+++ b/src/devices/pic/xml_data/16C57.xml
@@ -0,0 +1,123 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C57" document="010131" status="NR" alternative="16F57" memory_technology="EPROM" architecture="10X" pc="11"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" constant="0x0FF0" bchecksum="0x07FF" cchecksum="0xF647" />
+    <checksum protected="All" type="XOR4"       bchecksum="0x7807" cchecksum="0x77F5" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"    vdd_min="3"   vdd_max="6.25" osc="RC" />
+    <frequency start="0" end="4"    vdd_min="3"   vdd_max="6.25" osc="XT" />
+    <frequency start="0" end="20"   vdd_min="4.5" vdd_max="5.5"  osc="HS" />
+    <frequency start="0" end="0.04" vdd_min="2.5" vdd_max="6.25" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"    vdd_min="3.25" vdd_max="6"   osc="RC" />
+    <frequency start="0" end="4"    vdd_min="3.25" vdd_max="6"   osc="XT" />
+    <frequency start="0" end="20"   vdd_min="4.5"  vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.04" vdd_min="2.5"  vdd_max="6"   osc="LP" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x7FF" />
+  <memory name="user_ids" start="0x800" end="0x803" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x00C" bvalue="0x00F" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0x008" >
+      <value value="0x000" name="All" cname="_CP_ON"  />
+      <value value="0x008" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="T0CKI"       />
+    <pin index="2"  name="VDD"         />
+    <pin index="3"  name="N/C"         />
+    <pin index="4"  name="VSS"         />
+    <pin index="5"  name="N/C"         />
+    <pin index="6"  name="RA0"         />
+    <pin index="7"  name="RA1"         />
+    <pin index="8"  name="RA2"         />
+    <pin index="9"  name="RA3"         />
+    <pin index="10" name="RB0"         />
+    <pin index="11" name="RB1"         />
+    <pin index="12" name="RB2"         />
+    <pin index="13" name="RB3"         />
+    <pin index="14" name="RB4"         />
+    <pin index="15" name="RB5"         />
+    <pin index="16" name="RB6"         />
+    <pin index="17" name="RB7"         />
+    <pin index="18" name="RC0"         />
+    <pin index="19" name="RC1"         />
+    <pin index="20" name="RC2"         />
+    <pin index="21" name="RC3"         />
+    <pin index="22" name="RC4"         />
+    <pin index="23" name="RC5"         />
+    <pin index="24" name="RC6"         />
+    <pin index="25" name="RC7"         />
+    <pin index="26" name="OSC2/CLKOUT" />
+    <pin index="27" name="OSC1/CLKIN"  />
+    <pin index="28" name="MCLR/VPP"    />
+  </package>
+
+  <package types="ssop"      nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C57C.xml b/src/devices/pic/xml_data/16C57C.xml
new file mode 100644
index 0000000..4d5f180
--- /dev/null
+++ b/src/devices/pic/xml_data/16C57C.xml
@@ -0,0 +1,128 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C57C" document="010132" status="NR" alternative="16F57" memory_technology="EPROM" architecture="10X" pc="11"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x07FF" cchecksum="0xF647" />
+    <checksum protected="040:7FF" bchecksum="0x07C6" cchecksum="0xED32" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20"  vdd_min="4.5" vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.2" vdd_min="3"   vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x7FF" />
+  <memory name="user_ids" start="0x800" end="0x803" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="040:7FF" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="T0CKI"       />
+    <pin index="2"  name="VDD"         />
+    <pin index="3"  name="N/C"         />
+    <pin index="4"  name="VSS"         />
+    <pin index="5"  name="N/C"         />
+    <pin index="6"  name="RA0"         />
+    <pin index="7"  name="RA1"         />
+    <pin index="8"  name="RA2"         />
+    <pin index="9"  name="RA3"         />
+    <pin index="10" name="RB0"         />
+    <pin index="11" name="RB1"         />
+    <pin index="12" name="RB2"         />
+    <pin index="13" name="RB3"         />
+    <pin index="14" name="RB4"         />
+    <pin index="15" name="RB5"         />
+    <pin index="16" name="RB6"         />
+    <pin index="17" name="RB7"         />
+    <pin index="18" name="RC0"         />
+    <pin index="19" name="RC1"         />
+    <pin index="20" name="RC2"         />
+    <pin index="21" name="RC3"         />
+    <pin index="22" name="RC4"         />
+    <pin index="23" name="RC5"         />
+    <pin index="24" name="RC6"         />
+    <pin index="25" name="RC7"         />
+    <pin index="26" name="OSC2/CLKOUT" />
+    <pin index="27" name="OSC1/CLKIN"  />
+    <pin index="28" name="MCLR/VPP"    />
+  </package>
+
+  <package types="ssop"      nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C58A.xml b/src/devices/pic/xml_data/16C58A.xml
new file mode 100644
index 0000000..a12abb6
--- /dev/null
+++ b/src/devices/pic/xml_data/16C58A.xml
@@ -0,0 +1,114 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C58A" document="010133" status="EOL" memory_technology="EPROM" architecture="10X" pc="11"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" constant="0x0FF0" bchecksum="0x07FF" cchecksum="0xF647" />
+    <checksum protected="All" type="XOR4"       bchecksum="0x7807" cchecksum="0x77F5" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="6.25" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="6.25" osc="XT" />
+    <frequency start="0" end="20"  vdd_min="4.5" vdd_max="5.5"  osc="HS" />
+    <frequency start="0" end="0.2" vdd_min="3"   vdd_max="6.25" osc="LP" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_voltage" >
+    <frequency start="0" end="4"   vdd_min="2" vdd_max="3.8" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="2" vdd_max="3.8" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2" vdd_max="3.8" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3.5" vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3.5" vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" osc="HS" />
+  </frequency_range>
+  <frequency_range name="extended"   special="low_power"   >
+    <frequency start="0" end="4"   vdd_min="2.5" vdd_max="6.25" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="2.5" vdd_max="6.25" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="6.25" osc="LP" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x7FF" />
+  <memory name="user_ids" start="0x800" end="0x803" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x00C" bvalue="0x00F" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0x008" >
+      <value value="0x000" name="All" cname="_CP_ON"  />
+      <value value="0x008" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C58B.xml b/src/devices/pic/xml_data/16C58B.xml
new file mode 100644
index 0000000..04f56ce
--- /dev/null
+++ b/src/devices/pic/xml_data/16C58B.xml
@@ -0,0 +1,110 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C58B" document="010134" status="IP" memory_technology="EPROM" architecture="10X" pc="11"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x07FF" cchecksum="0xF647" />
+    <checksum protected="040:7FF" bchecksum="0x07C6" cchecksum="0xED32" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20"  vdd_min="4.5" vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.2" vdd_min="3"   vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x7FF" />
+  <memory name="user_ids" start="0x800" end="0x803" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="040:7FF" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C61.xml b/src/devices/pic/xml_data/16C61.xml
new file mode 100644
index 0000000..0b62c88
--- /dev/null
+++ b/src/devices/pic/xml_data/16C61.xml
@@ -0,0 +1,84 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C61" status="EOL" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="?" datasheet="30234" progsheet="30228" erratas="80132" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" constant="0x3FE0" bchecksum="0x3BFF" cchecksum="0x07CD" />
+    <checksum protected="All" type="XNOR7"      bchecksum="0xFC6F" cchecksum="0xFC15" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x03FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x001F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="Off" cname="_PWRTE_OFF" />
+      <value value="0x0008" name="On"  cname="_PWRTE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0010" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0010" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="RA4/T0CKI"   />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0/INT"     />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C62.xml b/src/devices/pic/xml_data/16C62.xml
new file mode 100644
index 0000000..8eebe47
--- /dev/null
+++ b/src/devices/pic/xml_data/16C62.xml
@@ -0,0 +1,95 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C62" document="010135" status="EOL" alternative="16C62B 16F72" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"                  constant="0x3F80" bchecksum="0x37BF" cchecksum="0x038D" />
+    <checksum protected="400:7FF" type="XNOR7" constant="0x3F80" bchecksum="0x37AF" cchecksum="0x1D69" />
+    <checksum protected="200:7FF" type="XNOR7" constant="0x3F80" bchecksum="0x379F" cchecksum="0x1D59" />
+    <checksum protected="All"     type="XNOR7" constant="0x3F80" bchecksum="0x378F" cchecksum="0x3735" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x003F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="Off" cname="_PWRTE_OFF" />
+      <value value="0x0008" name="On"  cname="_PWRTE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0030" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x0010" name="200:7FF" cname="_CP_75"  />
+      <value value="0x0020" name="400:7FF" cname="_CP_50"  />
+      <value value="0x0030" name="Off"     cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0"             />
+    <pin index="3"  name="RA1"             />
+    <pin index="4"  name="RA2"             />
+    <pin index="5"  name="RA3"             />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS"          />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSI/T1CKI" />
+    <pin index="12" name="RC1/T1OSO"       />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6"             />
+    <pin index="18" name="RC7"             />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C620.xml b/src/devices/pic/xml_data/16C620.xml
new file mode 100644
index 0000000..8a676af
--- /dev/null
+++ b/src/devices/pic/xml_data/16C620.xml
@@ -0,0 +1,113 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C620" document="010136" status="NR" alternative="16C620A" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x3D7F" cchecksum="0x094D" />
+    <checksum protected="All" bchecksum="0x3DCE" cchecksum="0x099C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3"   vdd_max="6" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="6" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x01FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x3F30" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C620A.xml b/src/devices/pic/xml_data/16C620A.xml
new file mode 100644
index 0000000..9770da4
--- /dev/null
+++ b/src/devices/pic/xml_data/16C620A.xml
@@ -0,0 +1,117 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C620A" document="010137" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x3D7F" cchecksum="0x094D" />
+    <checksum protected="All" bchecksum="0x3DCE" cchecksum="0x099C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" vdd_min_end="4.5" />
+    <frequency start="20" end="40" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.7" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x01FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x3F30" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C621.xml b/src/devices/pic/xml_data/16C621.xml
new file mode 100644
index 0000000..401ee06
--- /dev/null
+++ b/src/devices/pic/xml_data/16C621.xml
@@ -0,0 +1,115 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C621" document="010138" status="NR" alternative="16C621A" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x3B7F" cchecksum="0x074D" />
+    <checksum protected="200:3FF" bchecksum="0x4EDE" cchecksum="0x0093" />
+    <checksum protected="All"     bchecksum="0x3BCE" cchecksum="0x079C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="6" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="6" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="6" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x03FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:3FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C621A.xml b/src/devices/pic/xml_data/16C621A.xml
new file mode 100644
index 0000000..97e136e
--- /dev/null
+++ b/src/devices/pic/xml_data/16C621A.xml
@@ -0,0 +1,119 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C621A" document="010139" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x3B7F" cchecksum="0x074D" />
+    <checksum protected="200:3FF" bchecksum="0x4EDE" cchecksum="0x0093" />
+    <checksum protected="All"     bchecksum="0x3BCE" cchecksum="0x079C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" vdd_min_end="4.5" />
+    <frequency start="20" end="40" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.7" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x03FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:3FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C622.xml b/src/devices/pic/xml_data/16C622.xml
new file mode 100644
index 0000000..f1675bc
--- /dev/null
+++ b/src/devices/pic/xml_data/16C622.xml
@@ -0,0 +1,117 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C622" document="010140" status="NR" alternative="16C622A" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="400:7FF" bchecksum="0x5DEE" cchecksum="0x0FA3" />
+    <checksum protected="200:7FF" bchecksum="0x4ADE" cchecksum="0xFC93" />
+    <checksum protected="All"     bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="6" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="6" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="6" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C622A.xml b/src/devices/pic/xml_data/16C622A.xml
new file mode 100644
index 0000000..04e0d9b
--- /dev/null
+++ b/src/devices/pic/xml_data/16C622A.xml
@@ -0,0 +1,121 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C622A" document="010141" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="400:7FF" bchecksum="0x5DEE" cchecksum="0x0FA3" />
+    <checksum protected="200:7FF" bchecksum="0x4ADE" cchecksum="0xFC93" />
+    <checksum protected="All"     bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" vdd_min_end="4.5" />
+    <frequency start="20" end="40" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.7" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C62A.xml b/src/devices/pic/xml_data/16C62A.xml
new file mode 100644
index 0000000..71bf13f
--- /dev/null
+++ b/src/devices/pic/xml_data/16C62A.xml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C62A" document="010142" status="NR" alternative="16C62B 16F72" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="400:7FF" bchecksum="0x5DEE" cchecksum="0x0FA3" />
+    <checksum protected="200:7FF" bchecksum="0x4ADE" cchecksum="0xFC93" />
+    <checksum protected="All"     bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0"             />
+    <pin index="3"  name="RA1"             />
+    <pin index="4"  name="RA2"             />
+    <pin index="5"  name="RA3"             />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS"          />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSO/T1CKI" />
+    <pin index="12" name="RC1/T1OSI"       />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6"             />
+    <pin index="18" name="RC7"             />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C62B.xml b/src/devices/pic/xml_data/16C62B.xml
new file mode 100644
index 0000000..6550cbb
--- /dev/null
+++ b/src/devices/pic/xml_data/16C62B.xml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C62B" document="010143" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="400:7FF" bchecksum="0x5DEE" cchecksum="0x0FA3" />
+    <checksum protected="200:7FF" bchecksum="0x4ADE" cchecksum="0xFC93" />
+    <checksum protected="All"     bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0"             />
+    <pin index="3"  name="RA1"             />
+    <pin index="4"  name="RA2"             />
+    <pin index="5"  name="RA3"             />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS"          />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSO/T1CKI" />
+    <pin index="12" name="RC1/T1OSI"       />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6"             />
+    <pin index="18" name="RC7"             />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C63.xml b/src/devices/pic/xml_data/16C63.xml
new file mode 100644
index 0000000..7d21001
--- /dev/null
+++ b/src/devices/pic/xml_data/16C63.xml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C63" document="010144" status="NR" alternative="16C63A 16F73" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F7F" cchecksum="0xFB4D" />
+    <checksum protected="800:FFF" bchecksum="0x51EE" cchecksum="0x03A3" />
+    <checksum protected="400:FFF" bchecksum="0x40DE" cchecksum="0xF293" />
+    <checksum protected="All"     bchecksum="0x2FCE" cchecksum="0xFB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0"             />
+    <pin index="3"  name="RA1"             />
+    <pin index="4"  name="RA2"             />
+    <pin index="5"  name="RA3"             />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS"          />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSI/T1CKI" />
+    <pin index="12" name="RC1/T1OSO/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C63A.xml b/src/devices/pic/xml_data/16C63A.xml
new file mode 100644
index 0000000..2a3eac3
--- /dev/null
+++ b/src/devices/pic/xml_data/16C63A.xml
@@ -0,0 +1,101 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C63A" document="010145" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F7F" cchecksum="0xFB4D" />
+    <checksum protected="800:FFF" bchecksum="0x51EE" cchecksum="0x03A3" />
+    <checksum protected="400:FFF" bchecksum="0x40DE" cchecksum="0xF293" />
+    <checksum protected="All"     bchecksum="0x2FCE" cchecksum="0xFB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2"         />
+    <pin index="5"  name="RA3/AN3/VREF"    />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSI/T1CKI" />
+    <pin index="12" name="RC1/T1OSO/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C64.xml b/src/devices/pic/xml_data/16C64.xml
new file mode 100644
index 0000000..2bd6f77
--- /dev/null
+++ b/src/devices/pic/xml_data/16C64.xml
@@ -0,0 +1,201 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C64" document="010146" status="EOL" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+  
+  <!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"                  constant="0x3F80" bchecksum="0x37BF" cchecksum="0x038D" />
+    <checksum protected="400:7FF" type="XNOR7" constant="0x3F80" bchecksum="0x37AF" cchecksum="0x1D69" />
+    <checksum protected="200:7FF" type="XNOR7" constant="0x3F80" bchecksum="0x379F" cchecksum="0x1D59" />
+    <checksum protected="All"     type="XNOR7" constant="0x3F80" bchecksum="0x378F" cchecksum="0x3735" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x003F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="Off" cname="_PWRTE_OFF" />
+      <value value="0x0008" name="On"  cname="_PWRTE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0030" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x0010" name="200:7FF" cname="_CP_75"  />
+      <value value="0x0020" name="400:7FF" cname="_CP_50"  />
+      <value value="0x0030" name="Off"     cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="mqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C641.xml b/src/devices/pic/xml_data/16C641.xml
new file mode 100644
index 0000000..2a819ff
--- /dev/null
+++ b/src/devices/pic/xml_data/16C641.xml
@@ -0,0 +1,99 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C641" status="?" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="?" datasheet="30559" progsheet="?" erratas="er16c641" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="MPEEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="_MPEEN_OFF" />
+      <value value="0x0080" name="On"  cname="_MPEEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:7FF" cname="_CP_50"  />
+      <value value="0x2A20" name="200:7FF" cname="_CP_75"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"     />
+    <pin index="2"  name="RA0/AN0"      />
+    <pin index="3"  name="RA1/AN1"      />
+    <pin index="4"  name="RA2/AN2/VREF" />
+    <pin index="5"  name="RA3/AN3"      />
+    <pin index="6"  name="RA4/T0CKI"    />
+    <pin index="7"  name="RA5"          />
+    <pin index="8"  name="VSS"          />
+    <pin index="9"  name="OSC1/CLKIN"   />
+    <pin index="10" name="OSC2/CLKOUT"  />
+    <pin index="11" name="RC0"          />
+    <pin index="12" name="RC1"          />
+    <pin index="13" name="RC2"          />
+    <pin index="14" name="RC3"          />
+    <pin index="15" name="RC4"          />
+    <pin index="16" name="RC5"          />
+    <pin index="17" name="RC6"          />
+    <pin index="18" name="RC7"          />
+    <pin index="19" name="VSS"          />
+    <pin index="20" name="VDD"          />
+    <pin index="21" name="RB0/INT"      />
+    <pin index="22" name="RB1"          />
+    <pin index="23" name="RB2"          />
+    <pin index="24" name="RB3"          />
+    <pin index="25" name="RB4"          />
+    <pin index="26" name="RB5"          />
+    <pin index="27" name="RB6"          />
+    <pin index="28" name="RB7"          />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C642.xml b/src/devices/pic/xml_data/16C642.xml
new file mode 100644
index 0000000..c5847a9
--- /dev/null
+++ b/src/devices/pic/xml_data/16C642.xml
@@ -0,0 +1,104 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C642" document="010147" status="NR" alternative="16F72" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2FFF" cchecksum="0xFBCD" />
+    <checksum protected="800:FFF" bchecksum="0x52EE" cchecksum="0x04A3" />
+    <checksum protected="400:FFF" bchecksum="0x41DE" cchecksum="0xF393" />
+    <checksum protected="All"     bchecksum="0x30CE" cchecksum="0xFC9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="MPEEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="_MPEEN_OFF" />
+      <value value="0x0080" name="On"  cname="_MPEEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"     />
+    <pin index="2"  name="RA0/AN0"      />
+    <pin index="3"  name="RA1/AN1"      />
+    <pin index="4"  name="RA2/AN2/VREF" />
+    <pin index="5"  name="RA3/AN3"      />
+    <pin index="6"  name="RA4/T0CKI"    />
+    <pin index="7"  name="RA5"          />
+    <pin index="8"  name="VSS"          />
+    <pin index="9"  name="OSC1/CLKIN"   />
+    <pin index="10" name="OSC2/CLKOUT"  />
+    <pin index="11" name="RC0"          />
+    <pin index="12" name="RC1"          />
+    <pin index="13" name="RC2"          />
+    <pin index="14" name="RC3"          />
+    <pin index="15" name="RC4"          />
+    <pin index="16" name="RC5"          />
+    <pin index="17" name="RC6"          />
+    <pin index="18" name="RC7"          />
+    <pin index="19" name="VSS"          />
+    <pin index="20" name="VDD"          />
+    <pin index="21" name="RB0/INT"      />
+    <pin index="22" name="RB1"          />
+    <pin index="23" name="RB2"          />
+    <pin index="24" name="RB3"          />
+    <pin index="25" name="RB4"          />
+    <pin index="26" name="RB5"          />
+    <pin index="27" name="RB6"          />
+    <pin index="28" name="RB7"          />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C64A.xml b/src/devices/pic/xml_data/16C64A.xml
new file mode 100644
index 0000000..c5331e6
--- /dev/null
+++ b/src/devices/pic/xml_data/16C64A.xml
@@ -0,0 +1,253 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C64A" document="010148" status="NR" alternative="16F74" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="400:7FF" bchecksum="0x5DEE" cchecksum="0x0FA3" />
+    <checksum protected="200:7FF" bchecksum="0x4ADE" cchecksum="0xFC93" />
+    <checksum protected="All"     bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="mqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C65.xml b/src/devices/pic/xml_data/16C65.xml
new file mode 100644
index 0000000..1d5de06
--- /dev/null
+++ b/src/devices/pic/xml_data/16C65.xml
@@ -0,0 +1,201 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C65" document="010149" status="EOL" alternative="16C65B" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"                  constant="0x3F80" bchecksum="0x2FBF" cchecksum="0xFB8D" />
+    <checksum protected="800:FFF" type="XNOR7" constant="0x3F80" bchecksum="0x2FAF" cchecksum="0x1569" />
+    <checksum protected="400:FFF" type="XNOR7" constant="0x3F80" bchecksum="0x2F9F" cchecksum="0x1559" />
+    <checksum protected="All"     type="XNOR7" constant="0x3F80" bchecksum="0x2F8F" cchecksum="0x2F35" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x003F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="Off" cname="_PWRTE_OFF" />
+      <value value="0x0008" name="On"  cname="_PWRTE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0030" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x0010" name="400:FFF" cname="_CP_75"  />
+      <value value="0x0020" name="800:FFF" cname="_CP_50"  />
+      <value value="0x0030" name="Off"     cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="mqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C65A.xml b/src/devices/pic/xml_data/16C65A.xml
new file mode 100644
index 0000000..4220f2d
--- /dev/null
+++ b/src/devices/pic/xml_data/16C65A.xml
@@ -0,0 +1,253 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C65A" document="010150" status="NR" alternative="16C65B 16F74" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F7F" cchecksum="0xFB4D" />
+    <checksum protected="800:FFF" bchecksum="0x51EE" cchecksum="0x03A3" />
+    <checksum protected="400:FFF" bchecksum="0x40DE" cchecksum="0xF293" />
+    <checksum protected="All"     bchecksum="0x2FCE" cchecksum="0xFB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="mqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C65B.xml b/src/devices/pic/xml_data/16C65B.xml
new file mode 100644
index 0000000..c5eae8a
--- /dev/null
+++ b/src/devices/pic/xml_data/16C65B.xml
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C65B" document="010151" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F7F" cchecksum="0xFB4D" />
+    <checksum protected="800:FFF" bchecksum="0x51EE" cchecksum="0x03A3" />
+    <checksum protected="400:FFF" bchecksum="0x40DE" cchecksum="0xF293" />
+    <checksum protected="All"     bchecksum="0x2FCE" cchecksum="0xFB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"      nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc"      nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="mqfp tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C66.xml b/src/devices/pic/xml_data/16C66.xml
new file mode 100644
index 0000000..bfa3307
--- /dev/null
+++ b/src/devices/pic/xml_data/16C66.xml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C66" document="010152" status="NR" alternative="16F76" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"       bchecksum="0x1F7F" cchecksum="0xEB4D" />
+    <checksum protected="1000:1FFF" bchecksum="0x39EE" cchecksum="0xEBA3" />
+    <checksum protected="0800:1FFF" bchecksum="0x2CDE" cchecksum="0xDE93" />
+    <checksum protected="All"       bchecksum="0x1FCE" cchecksum="0xEB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x1FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"       cname="_CP_ALL" />
+      <value value="0x1510" name="0800:1FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="1000:1FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"       cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0"             />
+    <pin index="3"  name="RA1"             />
+    <pin index="4"  name="RA2"             />
+    <pin index="5"  name="RA3"             />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS"          />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSI/T1CKI" />
+    <pin index="12" name="RC1/T1OSO/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C661.xml b/src/devices/pic/xml_data/16C661.xml
new file mode 100644
index 0000000..612f636
--- /dev/null
+++ b/src/devices/pic/xml_data/16C661.xml
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C661" status="?" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="?" datasheet="30559" progsheet="?" erratas="er16c661" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="MPEEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="_MPEEN_OFF" />
+      <value value="0x0080" name="On"  cname="_MPEEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C662.xml b/src/devices/pic/xml_data/16C662.xml
new file mode 100644
index 0000000..a09c5c5
--- /dev/null
+++ b/src/devices/pic/xml_data/16C662.xml
@@ -0,0 +1,116 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C662" document="010153" status="NR" alternative="16F74" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2FFF" cchecksum="0xFBCD" />
+    <checksum protected="800:FFF" bchecksum="0x52EE" cchecksum="0x04A3" />
+    <checksum protected="400:FFF" bchecksum="0x41DE" cchecksum="0xF393" />
+    <checksum protected="All"     bchecksum="0x30CE" cchecksum="0xFC9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="MPEEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="_MPEEN_OFF" />
+      <value value="0x0080" name="On"  cname="_MPEEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C67.xml b/src/devices/pic/xml_data/16C67.xml
new file mode 100644
index 0000000..43c1aa1
--- /dev/null
+++ b/src/devices/pic/xml_data/16C67.xml
@@ -0,0 +1,253 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C67" document="010154" status="NR" alternative="16F77" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"       bchecksum="0x1F7F" cchecksum="0xEB4D" />
+    <checksum protected="1000:1FFF" bchecksum="0x39EE" cchecksum="0xEBA3" />
+    <checksum protected="0800:1FFF" bchecksum="0x2CDE" cchecksum="0xDE93" />
+    <checksum protected="All"       bchecksum="0x1FCE" cchecksum="0xEB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x1FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"       cname="_CP_ALL" />
+      <value value="0x1510" name="0800:1FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="1000:1FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"       cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="mqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C71.xml b/src/devices/pic/xml_data/16C71.xml
new file mode 100644
index 0000000..d23acc3
--- /dev/null
+++ b/src/devices/pic/xml_data/16C71.xml
@@ -0,0 +1,81 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C71" document="010155" status="NR" alternative="16F716" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" constant="0x3FE0" bchecksum="0x3BFF" cchecksum="0x07CD" />
+    <checksum protected="All" type="XNOR7"      bchecksum="0xFC6F" cchecksum="0xFC15" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="0.2" vdd_min="3" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x03FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x001F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="Off" cname="_PWRTE_OFF" />
+      <value value="0x0008" name="On"  cname="_PWRTE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0010" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0010" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2"      />
+    <pin index="2"  name="RA3/AN3/VREF" />
+    <pin index="3"  name="RA4/T0CKI"    />
+    <pin index="4"  name="MCLR/VPP"     />
+    <pin index="5"  name="VSS"          />
+    <pin index="6"  name="RB0/INT"      />
+    <pin index="7"  name="RB1"          />
+    <pin index="8"  name="RB2"          />
+    <pin index="9"  name="RB3"          />
+    <pin index="10" name="RB4"          />
+    <pin index="11" name="RB5"          />
+    <pin index="12" name="RB6"          />
+    <pin index="13" name="RB7"          />
+    <pin index="14" name="VDD"          />
+    <pin index="15" name="OSC2/CLKOUT"  />
+    <pin index="16" name="OSC1/CLKIN"   />
+    <pin index="17" name="RA0/AN0"      />
+    <pin index="18" name="RA1/AN1"      />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C710.xml b/src/devices/pic/xml_data/16C710.xml
new file mode 100644
index 0000000..d6a90c2
--- /dev/null
+++ b/src/devices/pic/xml_data/16C710.xml
@@ -0,0 +1,112 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C710" document="010156" status="NR" alternative="16F716" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x3DFF" cchecksum="0x09CD" />
+    <checksum protected="040:1FF" bchecksum="0x3E0E" cchecksum="0xEFC3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x01FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3FB0" >
+      <value value="0x0000" name="040:1FF" cname="_CP_ON"  />
+      <value value="0x3FB0" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2"      />
+    <pin index="2"  name="RA3/AN3/VREF" />
+    <pin index="3"  name="RA4/T0CKI"    />
+    <pin index="4"  name="MCLR/VPP"     />
+    <pin index="5"  name="VSS"          />
+    <pin index="6"  name="RB0/INT"      />
+    <pin index="7"  name="RB1"          />
+    <pin index="8"  name="RB2"          />
+    <pin index="9"  name="RB3"          />
+    <pin index="10" name="RB4"          />
+    <pin index="11" name="RB5"          />
+    <pin index="12" name="RB6"          />
+    <pin index="13" name="RB7"          />
+    <pin index="14" name="VDD"          />
+    <pin index="15" name="OSC2/CLKOUT"  />
+    <pin index="16" name="OSC1/CLKIN"   />
+    <pin index="17" name="RA0/AN0"      />
+    <pin index="18" name="RA1/AN1"      />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C711.xml b/src/devices/pic/xml_data/16C711.xml
new file mode 100644
index 0000000..29518e3
--- /dev/null
+++ b/src/devices/pic/xml_data/16C711.xml
@@ -0,0 +1,112 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C711" document="010157" status="NR" alternative="16F716" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x3BFF" cchecksum="0x07CD" />
+    <checksum protected="040:3FF" bchecksum="0x3C0E" cchecksum="0xEDC3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x03FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3FB0" >
+      <value value="0x0000" name="040:3FF" cname="_CP_ON"  />
+      <value value="0x3FB0" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2"      />
+    <pin index="2"  name="RA3/AN3/VREF" />
+    <pin index="3"  name="RA4/T0CKI"    />
+    <pin index="4"  name="MCLR/VPP"     />
+    <pin index="5"  name="VSS"          />
+    <pin index="6"  name="RB0/INT"      />
+    <pin index="7"  name="RB1"          />
+    <pin index="8"  name="RB2"          />
+    <pin index="9"  name="RB3"          />
+    <pin index="10" name="RB4"          />
+    <pin index="11" name="RB5"          />
+    <pin index="12" name="RB6"          />
+    <pin index="13" name="RB7"          />
+    <pin index="14" name="VDD"          />
+    <pin index="15" name="OSC2/CLKOUT"  />
+    <pin index="16" name="OSC1/CLKIN"   />
+    <pin index="17" name="RA0/AN0"      />
+    <pin index="18" name="RA1/AN1"      />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C712.xml b/src/devices/pic/xml_data/16C712.xml
new file mode 100644
index 0000000..6979deb
--- /dev/null
+++ b/src/devices/pic/xml_data/16C712.xml
@@ -0,0 +1,108 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C712" document="010158" status="NR" alternative="16F716" memory_technology="EPROM" architecture="16X" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x3B7F" cchecksum="0x074D" />
+    <checksum protected="200:3FF" bchecksum="0x63EE" cchecksum="0x15A3" />
+    <checksum protected="All"     bchecksum="0x3BCE" cchecksum="0x079C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x03FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x2A20" name="200:3FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C715.xml b/src/devices/pic/xml_data/16C715.xml
new file mode 100644
index 0000000..501018f
--- /dev/null
+++ b/src/devices/pic/xml_data/16C715.xml
@@ -0,0 +1,117 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C715" document="010159" status="NR" alternative="16F716" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x37FF" cchecksum="0x03CD" />
+    <checksum protected="400:7FF" bchecksum="0x5EEE" cchecksum="0x10A3" />
+    <checksum protected="200:7FF" bchecksum="0x4BDE" cchecksum="0xFD93" />
+    <checksum protected="All"     bchecksum="0x38CE" cchecksum="0x049C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="MPEEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="_MPEEN_OFF" />
+      <value value="0x0080" name="On"  cname="_MPEEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2"      />
+    <pin index="2"  name="RA3/AN3/VREF" />
+    <pin index="3"  name="RA4/T0CKI"    />
+    <pin index="4"  name="MCLR/VPP"     />
+    <pin index="5"  name="VSS"          />
+    <pin index="6"  name="RB0/INT"      />
+    <pin index="7"  name="RB1"          />
+    <pin index="8"  name="RB2"          />
+    <pin index="9"  name="RB3"          />
+    <pin index="10" name="RB4"          />
+    <pin index="11" name="RB5"          />
+    <pin index="12" name="RB6"          />
+    <pin index="13" name="RB7"          />
+    <pin index="14" name="VDD"          />
+    <pin index="15" name="OSC2/CLKOUT"  />
+    <pin index="16" name="OSC1/CLKIN"   />
+    <pin index="17" name="RA0/AN0"      />
+    <pin index="18" name="RA1/AN1"      />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C716.xml b/src/devices/pic/xml_data/16C716.xml
new file mode 100644
index 0000000..f34e760
--- /dev/null
+++ b/src/devices/pic/xml_data/16C716.xml
@@ -0,0 +1,112 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C716" document="010160" status="NR" alternative="16F716" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="400:7FF" bchecksum="0x5DEE" cchecksum="0x0FA3" />
+    <checksum protected="200:7FF" bchecksum="0x4ADE" cchecksum="0xFC93" />
+    <checksum protected="All"     bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C717.xml b/src/devices/pic/xml_data/16C717.xml
new file mode 100644
index 0000000..19c6f6a
--- /dev/null
+++ b/src/devices/pic/xml_data/16C717.xml
@@ -0,0 +1,129 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C717" document="010161" status="IP" memory_technology="EPROM" architecture="16X" id="0x0AC0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="All"     bchecksum="0x43FE" cchecksum="0x0FCC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" vdd_min_end="4" />
+  </frequency_range>
+  <frequency_range name="industrial" >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x07FF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK_OSC"         />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="ER_IO"        cname="_ER_OSC_NOCLKOUT"    />
+      <value value="0x0007" name="ER_CLKOUT"    cname="_ER_OSC_CLKOUT"      />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C00" >
+      <value value="0x0000" name="4.5" cname="_VBOR_45" />
+      <value value="0x0400" name="4.2" cname="_VBOR_42" />
+      <value value="0x0800" name="2.7" cname="_VBOR_27" />
+      <value value="0x0C00" name="2.5" cname="_VBOR_25" />
+    </mask>
+    <mask name="CP"    value="0x3300" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x3300" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C72.xml b/src/devices/pic/xml_data/16C72.xml
new file mode 100644
index 0000000..e6b88a2
--- /dev/null
+++ b/src/devices/pic/xml_data/16C72.xml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C72" document="010162" status="NR" alternative="16F72" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="400:7FF" bchecksum="0x5DEE" cchecksum="0x0FA3" />
+    <checksum protected="200:7FF" bchecksum="0x4ADE" cchecksum="0xFC93" />
+    <checksum protected="All"     bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2"         />
+    <pin index="5"  name="RA3/AN3/VREF"    />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSO/T1CKI" />
+    <pin index="12" name="RC1/T1OSI"       />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6"             />
+    <pin index="18" name="RC7"             />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C72A.xml b/src/devices/pic/xml_data/16C72A.xml
new file mode 100644
index 0000000..cabb079
--- /dev/null
+++ b/src/devices/pic/xml_data/16C72A.xml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C72A" document="010163" status="NR" alternative="16F72" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="400:7FF" bchecksum="0x5DEE" cchecksum="0x0FA3" />
+    <checksum protected="200:7FF" bchecksum="0x4ADE" cchecksum="0xFC93" />
+    <checksum protected="All"     bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2"         />
+    <pin index="5"  name="RA3/AN3/VREF"    />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSO/T1CKI" />
+    <pin index="12" name="RC1/T1OSI"       />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6"             />
+    <pin index="18" name="RC7"             />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C73.xml b/src/devices/pic/xml_data/16C73.xml
new file mode 100644
index 0000000..78b69fa
--- /dev/null
+++ b/src/devices/pic/xml_data/16C73.xml
@@ -0,0 +1,95 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C73" document="010164" status="EOL" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     constant="0x3F80"              bchecksum="0x2FBF" cchecksum="0xFB8D" />
+    <checksum protected="800:FFF" constant="0x3F80" type="XNOR7" bchecksum="0x2FAF" cchecksum="0x1569" />
+    <checksum protected="400:FFF" constant="0x3F80" type="XNOR7" bchecksum="0x2F9F" cchecksum="0x1559" />
+    <checksum protected="All"     constant="0x3F80" type="XNOR7" bchecksum="0x2F8F" cchecksum="0x2F35" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x003F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="Off" cname="_PWRTE_OFF" />
+      <value value="0x0008" name="On"  cname="_PWRTE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0030" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x0010" name="400:FFF" cname="_CP_75"  />
+      <value value="0x0020" name="800:FFF" cname="_CP_50"  />
+      <value value="0x0030" name="Off"     cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2"         />
+    <pin index="5"  name="RA3/AN3/VREF"    />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSI/T1CKI" />
+    <pin index="12" name="RC1/T1OSO/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C73A.xml b/src/devices/pic/xml_data/16C73A.xml
new file mode 100644
index 0000000..df9a672
--- /dev/null
+++ b/src/devices/pic/xml_data/16C73A.xml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C73A" document="010165" status="NR" alternative="16F73" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F7F" cchecksum="0xFB4D" />
+    <checksum protected="800:FFF" bchecksum="0x51EE" cchecksum="0x03A3" />
+    <checksum protected="400:FFF" bchecksum="0x40DE" cchecksum="0xF293" />
+    <checksum protected="All"     bchecksum="0x2FCE" cchecksum="0xFB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2"         />
+    <pin index="5"  name="RA3/AN3/VREF"    />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSI/T1CKI" />
+    <pin index="12" name="RC1/T1OSO/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C73B.xml b/src/devices/pic/xml_data/16C73B.xml
new file mode 100644
index 0000000..b2418f1
--- /dev/null
+++ b/src/devices/pic/xml_data/16C73B.xml
@@ -0,0 +1,101 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C73B" document="010166" status="NR" alternative="16F73" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F7F" cchecksum="0xFB4D" />
+    <checksum protected="800:FFF" bchecksum="0x51EE" cchecksum="0x03A3" />
+    <checksum protected="400:FFF" bchecksum="0x40DE" cchecksum="0xF293" />
+    <checksum protected="All"     bchecksum="0x2FCE" cchecksum="0xFB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2"         />
+    <pin index="5"  name="RA3/AN3/VREF"    />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSI/T1CKI" />
+    <pin index="12" name="RC1/T1OSO/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C74.xml b/src/devices/pic/xml_data/16C74.xml
new file mode 100644
index 0000000..091501d
--- /dev/null
+++ b/src/devices/pic/xml_data/16C74.xml
@@ -0,0 +1,201 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C74" document="010167" status="EOL" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     constant="0x3F80"              bchecksum="0x2FBF" cchecksum="0xFB8D" />
+    <checksum protected="800:FFF" constant="0x3F80" type="XNOR7" bchecksum="0x2FAF" cchecksum="0x1569" />
+    <checksum protected="400:FFF" constant="0x3F80" type="XNOR7" bchecksum="0x2F9F" cchecksum="0x1559" />
+    <checksum protected="All"     constant="0x3F80" type="XNOR7" bchecksum="0x2F8F" cchecksum="0x2F35" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x003F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="Off" cname="_PWRTE_OFF" />
+      <value value="0x0008" name="On"  cname="_PWRTE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0030" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x0010" name="400:FFF" cname="_CP_75"  />
+      <value value="0x0020" name="800:FFF" cname="_CP_50"  />
+      <value value="0x0030" name="Off"     cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="mqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C745.xml b/src/devices/pic/xml_data/16C745.xml
new file mode 100644
index 0000000..1a4ab42
--- /dev/null
+++ b/src/devices/pic/xml_data/16C745.xml
@@ -0,0 +1,92 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C745" document="010168" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"       bchecksum="0x1F3F" cchecksum="0xEB0D" />
+    <checksum protected="1000:1FFF" bchecksum="0x396E" cchecksum="0xEB23" />
+    <checksum protected="0800:1FFF" bchecksum="0x2C5E" cchecksum="0xDE13" />
+    <checksum protected="All"       bchecksum="0x1F4E" cchecksum="0xEB1C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="24" end="24" vdd_min="4.35" vdd_max="5.25" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x1FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F3F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="HS"        cname="_HS_OSC" />
+      <value value="0x0001" name="EC_CLKOUT" cname="_EC_OSC" />
+      <value value="0x0002" name="H4"        cname="_H4_OSC" />
+      <value value="0x0003" name="E4_CLKOUT" cname="_E4_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"       cname="_CP_ALL" />
+      <value value="0x1510" name="0800:1FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="1000:1FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"       cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C74A.xml b/src/devices/pic/xml_data/16C74A.xml
new file mode 100644
index 0000000..0d784c9
--- /dev/null
+++ b/src/devices/pic/xml_data/16C74A.xml
@@ -0,0 +1,206 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C74A" document="010169" status="NR" alternative="16F74" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F7F" cchecksum="0xFB4D" />
+    <checksum protected="800:FFF" bchecksum="0x51EE" cchecksum="0x03A3" />
+    <checksum protected="400:FFF" bchecksum="0x40DE" cchecksum="0xF293" />
+    <checksum protected="All"     bchecksum="0x2FCE" cchecksum="0xFB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"      nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc"      nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="mqfp tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C74B.xml b/src/devices/pic/xml_data/16C74B.xml
new file mode 100644
index 0000000..ce7274f
--- /dev/null
+++ b/src/devices/pic/xml_data/16C74B.xml
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C74B" document="010170" status="NR" alternative="16F74" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F7F" cchecksum="0xFB4D" />
+    <checksum protected="800:FFF" bchecksum="0x51EE" cchecksum="0x03A3" />
+    <checksum protected="400:FFF" bchecksum="0x40DE" cchecksum="0xF293" />
+    <checksum protected="All"     bchecksum="0x2FCE" cchecksum="0xFB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"      nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc"      nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="mqfp tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C76.xml b/src/devices/pic/xml_data/16C76.xml
new file mode 100644
index 0000000..c5819a2
--- /dev/null
+++ b/src/devices/pic/xml_data/16C76.xml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C76" document="010171" status="NR" alternative="16F76" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"       bchecksum="0x1F7F" cchecksum="0xEB4D" />
+    <checksum protected="1000:1FFF" bchecksum="0x39EE" cchecksum="0xEBA3" />
+    <checksum protected="0800:1FFF" bchecksum="0x2CDE" cchecksum="0xDE93" />
+    <checksum protected="All"       bchecksum="0x1FCE" cchecksum="0xEB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x1FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"       cname="_CP_ALL" />
+      <value value="0x1510" name="0800:1FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="1000:1FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"       cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2"         />
+    <pin index="5"  name="RA3/AN3/VREF"    />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSI/T1CKI" />
+    <pin index="12" name="RC1/T1OSO/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C765.xml b/src/devices/pic/xml_data/16C765.xml
new file mode 100644
index 0000000..c441e17
--- /dev/null
+++ b/src/devices/pic/xml_data/16C765.xml
@@ -0,0 +1,198 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C765" document="010172" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"       bchecksum="0x1F3F" cchecksum="0xEB0D" />
+    <checksum protected="1000:1FFF" bchecksum="0x396E" cchecksum="0xEB23" />
+    <checksum protected="0800:1FFF" bchecksum="0x2C5E" cchecksum="0xDE13" />
+    <checksum protected="All"       bchecksum="0x1F4E" cchecksum="0xEB1C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="24" end="24" vdd_min="4.35" vdd_max="5.25" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x1FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F3F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="HS"        cname="_HS_OSC" />
+      <value value="0x0001" name="EC_CLKOUT" cname="_EC_OSC" />
+      <value value="0x0002" name="H4"        cname="_H4_OSC" />
+      <value value="0x0003" name="E4_CLKOUT" cname="_E4_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"       cname="_CP_ALL" />
+      <value value="0x1510" name="0800:1FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="1000:1FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"       cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C77.xml b/src/devices/pic/xml_data/16C77.xml
new file mode 100644
index 0000000..f863d24
--- /dev/null
+++ b/src/devices/pic/xml_data/16C77.xml
@@ -0,0 +1,206 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C77" document="010173" status="NR" alternative="16F77" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"       bchecksum="0x1F7F" cchecksum="0xEB4D" />
+    <checksum protected="1000:1FFF" bchecksum="0x39EE" cchecksum="0xEBA3" />
+    <checksum protected="0800:1FFF" bchecksum="0x2CDE" cchecksum="0xDE93" />
+    <checksum protected="All"       bchecksum="0x1FCE" cchecksum="0xEB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x1FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"       cname="_CP_ALL" />
+      <value value="0x1510" name="0800:1FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="1000:1FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"       cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"      nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc"      nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="mqfp tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C770.xml b/src/devices/pic/xml_data/16C770.xml
new file mode 100644
index 0000000..de1d9e9
--- /dev/null
+++ b/src/devices/pic/xml_data/16C770.xml
@@ -0,0 +1,108 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C770" document="010174" status="IP" memory_technology="EPROM" architecture="16X" id="0x0AE0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="All"     bchecksum="0x43FE" cchecksum="0x0FCC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" vdd_min_end="4" />
+  </frequency_range>
+  <frequency_range name="industrial" >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x07FF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK_OSC"         />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="ER_IO"        cname="_ER_OSC_NOCLKOUT"    />
+      <value value="0x0007" name="ER_CLKOUT"    cname="_ER_OSC_CLKOUT"      />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C00" >
+      <value value="0x0000" name="4.5" cname="_VBOR_45" />
+      <value value="0x0400" name="4.2" cname="_VBOR_42" />
+      <value value="0x0800" name="2.7" cname="_VBOR_27" />
+      <value value="0x0C00" name="2.5" cname="_VBOR_25" />
+    </mask>
+    <mask name="CP"    value="0x3300" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x3300" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C771.xml b/src/devices/pic/xml_data/16C771.xml
new file mode 100644
index 0000000..4bf7fcd
--- /dev/null
+++ b/src/devices/pic/xml_data/16C771.xml
@@ -0,0 +1,108 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C771" document="010175" status="IP" memory_technology="EPROM" architecture="16X" id="0x0B00"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F7F" cchecksum="0xFB4D" />
+    <checksum protected="All"     bchecksum="0x3BFE" cchecksum="0x07CC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" vdd_min_end="4" />
+  </frequency_range>
+  <frequency_range name="industrial" >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK_OSC"         />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="ER_IO"        cname="_ER_OSC_NOCLKOUT"    />
+      <value value="0x0007" name="ER_CLKOUT"    cname="_ER_OSC_CLKOUT"      />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C00" >
+      <value value="0x0000" name="4.5" cname="_VBOR_45" />
+      <value value="0x0400" name="4.2" cname="_VBOR_42" />
+      <value value="0x0800" name="2.7" cname="_VBOR_27" />
+      <value value="0x0C00" name="2.5" cname="_VBOR_25" />
+    </mask>
+    <mask name="CP"    value="0x3300" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x3300" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C773.xml b/src/devices/pic/xml_data/16C773.xml
new file mode 100644
index 0000000..1b74ed5
--- /dev/null
+++ b/src/devices/pic/xml_data/16C773.xml
@@ -0,0 +1,106 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C773" document="010176" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F7F" cchecksum="0xFB4D" />
+    <checksum protected="800:FFF" bchecksum="0x55EE" cchecksum="0x07A3" />
+    <checksum protected="400:FFF" bchecksum="0x48DE" cchecksum="0xFA93" />
+    <checksum protected="All"     bchecksum="0x3BCE" cchecksum="0x079C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C00" >
+      <value value="0x0000" name="4.5" cname="_VBOR_45" />
+      <value value="0x0400" name="4.2" cname="_VBOR_42" />
+      <value value="0x0800" name="2.7" cname="_VBOR_27" />
+      <value value="0x0C00" name="2.5" cname="_VBOR_25" />
+    </mask>
+    <mask name="CP"    value="0x3330" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1110" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2220" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3330" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C774.xml b/src/devices/pic/xml_data/16C774.xml
new file mode 100644
index 0000000..1d577ee
--- /dev/null
+++ b/src/devices/pic/xml_data/16C774.xml
@@ -0,0 +1,259 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C774" document="010177" status="IP" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F7F" cchecksum="0xFB4D" />
+    <checksum protected="800:FFF" bchecksum="0x55EE" cchecksum="0x07A3" />
+    <checksum protected="400:FFF" bchecksum="0x48DE" cchecksum="0xFA93" />
+    <checksum protected="All"     bchecksum="0x3BCE" cchecksum="0x079C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C00" >
+      <value value="0x0000" name="4.5" cname="_VBOR_45" />
+      <value value="0x0400" name="4.2" cname="_VBOR_42" />
+      <value value="0x0800" name="2.7" cname="_VBOR_27" />
+      <value value="0x0C00" name="2.5" cname="_VBOR_25" />
+    </mask>
+    <mask name="CP"    value="0x3330" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1110" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2220" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3330" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="mqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C781.xml b/src/devices/pic/xml_data/16C781.xml
new file mode 100644
index 0000000..2861a67
--- /dev/null
+++ b/src/devices/pic/xml_data/16C781.xml
@@ -0,0 +1,104 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C781" document="010178" status="IP" memory_technology="EPROM" architecture="16X" id="0x0D40"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x3B7F" cchecksum="0x074D" />
+    <checksum protected="All"     bchecksum="0x47FE" cchecksum="0x13CC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2.7" vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x03FF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK_OSC"         />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="ER_IO"        cname="_ER_OSC_NOCLKOUT"    />
+      <value value="0x0007" name="ER_CLKOUT"    cname="_ER_OSC_CLKOUT"      />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C00" >
+      <value value="0x0000" name="4.5" cname="_VBOR_45" />
+      <value value="0x0400" name="4.2" cname="_VBOR_42" />
+      <value value="0x0800" name="2.7" cname="_VBOR_27" />
+      <value value="0x0C00" name="2.5" cname="_VBOR_25" />
+    </mask>
+    <mask name="CP"    value="0x3300" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x3300" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C782.xml b/src/devices/pic/xml_data/16C782.xml
new file mode 100644
index 0000000..6192a30
--- /dev/null
+++ b/src/devices/pic/xml_data/16C782.xml
@@ -0,0 +1,104 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C782" document="010179" status="IP" memory_technology="EPROM" architecture="16X" id="0x0D60"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="All"     bchecksum="0x43FE" cchecksum="0x0FCC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2.7" vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x07FF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK_OSC"         />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="ER_IO"        cname="_ER_OSC_NOCLKOUT"    />
+      <value value="0x0007" name="ER_CLKOUT"    cname="_ER_OSC_CLKOUT"      />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C00" >
+      <value value="0x0000" name="4.5" cname="_VBOR_45" />
+      <value value="0x0400" name="4.2" cname="_VBOR_42" />
+      <value value="0x0800" name="2.7" cname="_VBOR_27" />
+      <value value="0x0C00" name="2.5" cname="_VBOR_25" />
+    </mask>
+    <mask name="CP"    value="0x3300" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x3300" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C84.xml b/src/devices/pic/xml_data/16C84.xml
new file mode 100644
index 0000000..595bcd9
--- /dev/null
+++ b/src/devices/pic/xml_data/16C84.xml
@@ -0,0 +1,99 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C84" document="010180" status="EOL" alternative="16F84A 16F627A" memory_technology="ROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="10" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="2" vdd_min="2" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12"  max="14"  nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x03FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="config"   start="0x2007" end="0x2007" />
+  <memory name="eeprom"   start="0x0000" end="0x003F" hexfile_offset="0x2100" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x001F" cmask="0x0018" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="Off" cname="_PWRTE_OFF" />
+      <value value="0x0008" name="On"  cname="_PWRTE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0010" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0010" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="RA4/T0CKI"   />
+    <pin index="4"  name="MCLR"        />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0/INT"     />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C923.xml b/src/devices/pic/xml_data/16C923.xml
new file mode 100644
index 0000000..a670a59
--- /dev/null
+++ b/src/devices/pic/xml_data/16C923.xml
@@ -0,0 +1,270 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C923" document="010181" status="NR" alternative="16C925" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F3F" cchecksum="0xFB0D" />
+    <checksum protected="800:FFF" bchecksum="0x516E" cchecksum="0x0323" />
+    <checksum protected="400:FFF" bchecksum="0x405E" cchecksum="0xF213" />
+    <checksum protected="All"     bchecksum="0x2F4E" cchecksum="0xFB1C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="8" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F3F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="spdip" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+  <package types="plcc"  nb_pins="68" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+  </package>
+
+  <package types="tqfp"  nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C924.xml b/src/devices/pic/xml_data/16C924.xml
new file mode 100644
index 0000000..614ff48
--- /dev/null
+++ b/src/devices/pic/xml_data/16C924.xml
@@ -0,0 +1,270 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C924" document="010182" status="NR" alternative="16C925" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F3F" cchecksum="0xFB0D" />
+    <checksum protected="800:FFF" bchecksum="0x516E" cchecksum="0x0323" />
+    <checksum protected="400:FFF" bchecksum="0x405E" cchecksum="0xF213" />
+    <checksum protected="All"     bchecksum="0x2F4E" cchecksum="0xFB1C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="8" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F3F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="spdip" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+  <package types="plcc"  nb_pins="68" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+  </package>
+
+  <package types="tqfp"  nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C925.xml b/src/devices/pic/xml_data/16C925.xml
new file mode 100644
index 0000000..b9c703d
--- /dev/null
+++ b/src/devices/pic/xml_data/16C925.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C925" document="010183" status="IP" memory_technology="EPROM" architecture="16X" id="0x0140"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CP"    value="0x0030" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x0010" name="000:EFF" cname="_CP_75"  />
+      <value value="0x0020" name="000:7FF" cname="_CP_50"  />
+      <value value="0x0030" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="plcc" nb_pins="68" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16C926.xml b/src/devices/pic/xml_data/16C926.xml
new file mode 100644
index 0000000..4120d43
--- /dev/null
+++ b/src/devices/pic/xml_data/16C926.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16C926" document="010184" status="IP" memory_technology="EPROM" architecture="16X" id="0x0100"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x1FFF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x007F" cmask="0x3F3F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CP"    value="0x0030" >
+      <value value="0x0000" name="All"       cname="_CP_ALL" />
+      <value value="0x0010" name="0000:1EFF" cname="_CP_75"  />
+      <value value="0x0020" name="0000:0FFF" cname="_CP_50"  />
+      <value value="0x0030" name="Off"       cname="_CP_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="plcc" nb_pins="68" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CE623.xml b/src/devices/pic/xml_data/16CE623.xml
new file mode 100644
index 0000000..18e6848
--- /dev/null
+++ b/src/devices/pic/xml_data/16CE623.xml
@@ -0,0 +1,114 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CE623" document="010185" status="NR" alternative="16F627A" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x3D7F" cchecksum="0x094D" />
+    <checksum protected="All" bchecksum="0x3DCE" cchecksum="0x099C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x01FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+  <memory name="eeprom"   start="0x0000" end="0x007F" hexfile_offset="?" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x3F30" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CE624.xml b/src/devices/pic/xml_data/16CE624.xml
new file mode 100644
index 0000000..4f205a7
--- /dev/null
+++ b/src/devices/pic/xml_data/16CE624.xml
@@ -0,0 +1,116 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CE624" document="010186" status="NR" alternative="16F627A" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x3B7F" cchecksum="0x074D" />
+    <checksum protected="200:3FF" bchecksum="0x4EDE" cchecksum="0x0093" />
+    <checksum protected="All"     bchecksum="0x3BCE" cchecksum="0x079C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x03FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+  <memory name="eeprom"   start="0x0000" end="0x007F" hexfile_offset="?" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:3FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CE625.xml b/src/devices/pic/xml_data/16CE625.xml
new file mode 100644
index 0000000..d7aa576
--- /dev/null
+++ b/src/devices/pic/xml_data/16CE625.xml
@@ -0,0 +1,117 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CE625" document="010187" status="NR" alternative="16F628A" memory_technology="EPROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="400:7FF" bchecksum="0x5DEE" cchecksum="0x0FA3" />
+    <checksum protected="200:7FF" bchecksum="0x4ADE" cchecksum="0xFC93" />
+    <checksum protected="All"     bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR54.xml_broken b/src/devices/pic/xml_data/16CR54.xml_broken
new file mode 100644
index 0000000..cef44cb
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR54.xml_broken
@@ -0,0 +1,87 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR54" document="" status="?" memory_technology="ROM" architecture="10X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Operating characteristics ********************************************-->
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="program"  start="0x000" end="0x1FF" />
+  <memory name="user_ids" start="0x200" end="0x203" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0x00C" cmask="0x008" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0x008" >
+      <value value="0x000" name="All" cname="_CP_ON"  />
+      <value value="0x008" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR54A.xml b/src/devices/pic/xml_data/16CR54A.xml
new file mode 100644
index 0000000..c3a5d2a
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR54A.xml
@@ -0,0 +1,107 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR54A" document="010188" status="NR" alternative="16F54" memory_technology="ROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"             bchecksum="0x0DFF" cchecksum="0xFC47" />
+    <checksum protected="All" type="XOR4" bchecksum="0x1E07" cchecksum="0x1DF5" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="2.5" vdd_max="6.25" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="2.5" vdd_max="6.25" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5"  osc="HS" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="6.25" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3.25" vdd_max="6"   osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3.25" vdd_max="6"   osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5"  vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x1FF" />
+  <memory name="user_ids" start="0x200" end="0x203" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="All" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR54B.xml b/src/devices/pic/xml_data/16CR54B.xml
new file mode 100644
index 0000000..43456d8
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR54B.xml
@@ -0,0 +1,110 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR54B" document="010189" status="EOL" memory_technology="ROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x0DFF" cchecksum="0xFC47" />
+    <checksum protected="040:1FF" bchecksum="0x0DC6" cchecksum="0xF332" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20"  vdd_min="4.5" vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.2" vdd_min="3"   vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x1FF" />
+  <memory name="user_ids" start="0x200" end="0x203" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="040:1FF" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR54C.xml b/src/devices/pic/xml_data/16CR54C.xml
new file mode 100644
index 0000000..3667ce3
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR54C.xml
@@ -0,0 +1,110 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR54C" document="010190" status="NR" alternative="16F54" memory_technology="ROM" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x0DFF" cchecksum="0xFC47" />
+    <checksum protected="040:1FF" bchecksum="0x0DC6" cchecksum="0xF332" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20"  vdd_min="4.5" vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.2" vdd_min="3"   vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x1FF" />
+  <memory name="user_ids" start="0x200" end="0x203" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="040:1FF" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR56A.xml b/src/devices/pic/xml_data/16CR56A.xml
new file mode 100644
index 0000000..0b28931
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR56A.xml
@@ -0,0 +1,110 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR56A" document="010191" status="IP" memory_technology="ROM" architecture="10X" pc="10"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x0BFF" cchecksum="0xFA47" />
+    <checksum protected="040:3FF" bchecksum="0x0BC6" cchecksum="0xF132" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20"  vdd_min="4.5" vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.2" vdd_min="3"   vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x3FF" />
+  <memory name="user_ids" start="0x400" end="0x403" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="040:3FF" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR57B.xml b/src/devices/pic/xml_data/16CR57B.xml
new file mode 100644
index 0000000..caba4c3
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR57B.xml
@@ -0,0 +1,125 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR57B" document="010193" status="EOL" memory_technology="ROM" architecture="10X" pc="11"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x07FF" cchecksum="0xF647" />
+    <checksum protected="040:7FF" bchecksum="0x07C6" cchecksum="0xED32" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="6.25" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="6.25" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5"  osc="HS" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="6.25" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3.25" vdd_max="6"   osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3.25" vdd_max="6"   osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5"  vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x7FF" />
+  <memory name="user_ids" start="0x800" end="0x803" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="040:7FF" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="T0CKI"       />
+    <pin index="2"  name="VDD"         />
+    <pin index="3"  name="N/C"         />
+    <pin index="4"  name="VSS"         />
+    <pin index="5"  name="N/C"         />
+    <pin index="6"  name="RA0"         />
+    <pin index="7"  name="RA1"         />
+    <pin index="8"  name="RA2"         />
+    <pin index="9"  name="RA3"         />
+    <pin index="10" name="RB0"         />
+    <pin index="11" name="RB1"         />
+    <pin index="12" name="RB2"         />
+    <pin index="13" name="RB3"         />
+    <pin index="14" name="RB4"         />
+    <pin index="15" name="RB5"         />
+    <pin index="16" name="RB6"         />
+    <pin index="17" name="RB7"         />
+    <pin index="18" name="RC0"         />
+    <pin index="19" name="RC1"         />
+    <pin index="20" name="RC2"         />
+    <pin index="21" name="RC3"         />
+    <pin index="22" name="RC4"         />
+    <pin index="23" name="RC5"         />
+    <pin index="24" name="RC6"         />
+    <pin index="25" name="RC7"         />
+    <pin index="26" name="OSC2/CLKOUT" />
+    <pin index="27" name="OSC1/CLKIN"  />
+    <pin index="28" name="MCLR/VPP"    />
+  </package>
+
+  <package types="ssop"      nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR57C.xml b/src/devices/pic/xml_data/16CR57C.xml
new file mode 100644
index 0000000..379f1bc
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR57C.xml
@@ -0,0 +1,128 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR57C" document="010194" status="NR" alternative="16F57" memory_technology="ROM" architecture="10X" pc="11"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x07FF" cchecksum="0xF647" />
+    <checksum protected="040:7FF" bchecksum="0x07C6" cchecksum="0xED32" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20"  vdd_min="4.5" vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.2" vdd_min="3"   vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x7FF" />
+  <memory name="user_ids" start="0x800" end="0x803" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="040:7FF" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="T0CKI"       />
+    <pin index="2"  name="VDD"         />
+    <pin index="3"  name="N/C"         />
+    <pin index="4"  name="VSS"         />
+    <pin index="5"  name="N/C"         />
+    <pin index="6"  name="RA0"         />
+    <pin index="7"  name="RA1"         />
+    <pin index="8"  name="RA2"         />
+    <pin index="9"  name="RA3"         />
+    <pin index="10" name="RB0"         />
+    <pin index="11" name="RB1"         />
+    <pin index="12" name="RB2"         />
+    <pin index="13" name="RB3"         />
+    <pin index="14" name="RB4"         />
+    <pin index="15" name="RB5"         />
+    <pin index="16" name="RB6"         />
+    <pin index="17" name="RB7"         />
+    <pin index="18" name="RC0"         />
+    <pin index="19" name="RC1"         />
+    <pin index="20" name="RC2"         />
+    <pin index="21" name="RC3"         />
+    <pin index="22" name="RC4"         />
+    <pin index="23" name="RC5"         />
+    <pin index="24" name="RC6"         />
+    <pin index="25" name="RC7"         />
+    <pin index="26" name="OSC2/CLKOUT" />
+    <pin index="27" name="OSC1/CLKIN"  />
+    <pin index="28" name="MCLR/VPP"    />
+  </package>
+
+  <package types="ssop"      nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR58A.xml b/src/devices/pic/xml_data/16CR58A.xml
new file mode 100644
index 0000000..3841400
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR58A.xml
@@ -0,0 +1,107 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR58A" document="010195" status="EOL" memory_technology="ROM" architecture="10X" pc="11"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x07FF" cchecksum="0xF647" />
+    <checksum protected="040:7FF" bchecksum="0x07C6" cchecksum="0xED32" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="6.25" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="6.25" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5"  osc="HS" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="6.25" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3.25" vdd_max="6"   osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3.25" vdd_max="6"   osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5"  vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x7FF" />
+  <memory name="user_ids" start="0x800" end="0x803" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="040:7FF" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR58B.xml b/src/devices/pic/xml_data/16CR58B.xml
new file mode 100644
index 0000000..b450e31
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR58B.xml
@@ -0,0 +1,110 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR58B" document="010196" status="IP" memory_technology="ROM" architecture="10X" pc="11"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x07FF" cchecksum="0xF647" />
+    <checksum protected="040:7FF" bchecksum="0x07C6" cchecksum="0xED32" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20"  vdd_min="4.5" vdd_max="5.5" osc="HS" />
+    <frequency start="0" end="0.2" vdd_min="3"   vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"   vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="0.2" vdd_min="2.5" vdd_max="5.5" osc="LP" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="RC" />
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" osc="XT" />
+    <frequency start="0" end="20" vdd_min="4.5" vdd_max="5.5" osc="HS" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x7FF" />
+  <memory name="user_ids" start="0x800" end="0x803" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFC" bvalue="0xFFF" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0xFF8" >
+      <value value="0x000" name="040:7FF" cname="_CP_ON"  />
+      <value value="0xFF8" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR62.xml b/src/devices/pic/xml_data/16CR62.xml
new file mode 100644
index 0000000..0b27a3c
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR62.xml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR62" document="010197" status="EOL" memory_technology="ROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="400:7FF" bchecksum="0x5DEE" cchecksum="0x0FA3" />
+    <checksum protected="200:7FF" bchecksum="0x4ADE" cchecksum="0xFC93" />
+    <checksum protected="All"     bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0"             />
+    <pin index="3"  name="RA1"             />
+    <pin index="4"  name="RA2"             />
+    <pin index="5"  name="RA3"             />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS"          />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSO/T1CKI" />
+    <pin index="12" name="RC1/T1OSI"       />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6"             />
+    <pin index="18" name="RC7"             />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR620A.xml b/src/devices/pic/xml_data/16CR620A.xml
new file mode 100644
index 0000000..a2e6db3
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR620A.xml
@@ -0,0 +1,113 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR620A" document="010198" status="IP" memory_technology="ROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x3D7F" cchecksum="0x094D" />
+    <checksum protected="All" bchecksum="0x3DCE" cchecksum="0x099C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x01FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x3F30" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR63.xml b/src/devices/pic/xml_data/16CR63.xml
new file mode 100644
index 0000000..08d6f3f
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR63.xml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR63" document="010199" status="IP" memory_technology="ROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F7F" cchecksum="0xFB4D" />
+    <checksum protected="800:FFF" bchecksum="0x51EE" cchecksum="0x03A3" />
+    <checksum protected="400:FFF" bchecksum="0x40DE" cchecksum="0xF293" />
+    <checksum protected="All"     bchecksum="0x2FCE" cchecksum="0xFB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0"             />
+    <pin index="3"  name="RA1"             />
+    <pin index="4"  name="RA2"             />
+    <pin index="5"  name="RA3"             />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS"          />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSI/T1CKI" />
+    <pin index="12" name="RC1/T1OSO/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6"             />
+    <pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR64.xml b/src/devices/pic/xml_data/16CR64.xml
new file mode 100644
index 0000000..e155a97
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR64.xml
@@ -0,0 +1,206 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR64" document="010200" status="EOL" memory_technology="ROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="400:7FF" bchecksum="0x5DEE" cchecksum="0x0FA3" />
+    <checksum protected="200:7FF" bchecksum="0x4ADE" cchecksum="0xFC93" />
+    <checksum protected="All"     bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="mqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR65.xml b/src/devices/pic/xml_data/16CR65.xml
new file mode 100644
index 0000000..df4d3f4
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR65.xml
@@ -0,0 +1,253 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR65" document="010201" status="IP" memory_technology="ROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2F7F" cchecksum="0xFB4D" />
+    <checksum protected="800:FFF" bchecksum="0x51EE" cchecksum="0x03A3" />
+    <checksum protected="400:FFF" bchecksum="0x40DE" cchecksum="0xF293" />
+    <checksum protected="All"     bchecksum="0x2FCE" cchecksum="0xFB9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x0FFF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="400:FFF" cname="_CP_75"  />
+      <value value="0x2A20" name="800:FFF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="mqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR72.xml b/src/devices/pic/xml_data/16CR72.xml
new file mode 100644
index 0000000..efaa9f8
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR72.xml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR72" document="010202" status="IP" memory_technology="ROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x377F" cchecksum="0x034D" />
+    <checksum protected="400:7FF" bchecksum="0x5DEE" cchecksum="0x0FA3" />
+    <checksum protected="200:7FF" bchecksum="0x4ADE" cchecksum="0xFC93" />
+    <checksum protected="All"     bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5"   />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x07FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="config"   start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3F7F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="CP"    value="0x3F30" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1510" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2A20" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3F30" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+<package types="sdip soic ssop" nb_pins="28" >
+	<pin index="1"  name="MCLR/VPP"        />
+	<pin index="2"  name="RA0/AN0"         />
+	<pin index="3"  name="RA1/AN1"         />
+	<pin index="4"  name="RA2/AN2"         />
+	<pin index="5"  name="RA3/AN3/VREF"    />
+	<pin index="6"  name="RA4/T0CKI"       />
+	<pin index="7"  name="RA5/SS/AN4"      />
+	<pin index="8"  name="VSS"             />
+	<pin index="9"  name="OSC1/CLKIN"      />
+	<pin index="10" name="OSC2/CLKOUT"     />
+	<pin index="11" name="RC0/T1OSO/T1CKI" />
+	<pin index="12" name="RC1/T1OSI"       />
+	<pin index="13" name="RC2/CCP1"        />
+	<pin index="14" name="RC3/SCK/SCL"     />
+	<pin index="15" name="RC4/SDI/SDA"     />
+	<pin index="16" name="RC5/SDO"         />
+	<pin index="17" name="RC6"             />
+	<pin index="18" name="RC7"             />
+	<pin index="19" name="VSS"             />
+	<pin index="20" name="VDD"             />
+	<pin index="21" name="RB0/INT"         />
+	<pin index="22" name="RB1"             />
+	<pin index="23" name="RB2"             />
+	<pin index="24" name="RB3"             />
+	<pin index="25" name="RB4"             />
+	<pin index="26" name="RB5"             />
+	<pin index="27" name="RB6"             />
+	<pin index="28" name="RB7"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR73.xml b/src/devices/pic/xml_data/16CR73.xml
new file mode 100644
index 0000000..6513255
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR73.xml
@@ -0,0 +1,127 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR73" document="026371" status="IP" memory_technology="ROM" architecture="16X" id="0x0600"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected="Off" bchecksum="0xF05F" cchecksum="0x7C2D" />
+    <checksum protected="All" bchecksum="0x005E" cchecksum="0x005E" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"      min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x000F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x005F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" ecnames="_WDTEN_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  ecnames="_WDTEN_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  ecnames="_PWRTEN_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" ecnames="_PWRTEN_OFF" />
+    </mask>
+    <mask name="CP"    value="0x0010" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x0010" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" ecnames="_BOREN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  ecnames="_BOREN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2"         />
+    <pin index="5"  name="RA3/AN3/VREF"    />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSI/T1CKI" />
+    <pin index="12" name="RC1/T1OSO/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6/PGC"         />
+    <pin index="28" name="RB7/PGD"         />
+  </package>
+
+  <package types="mlf"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR74.xml b/src/devices/pic/xml_data/16CR74.xml
new file mode 100644
index 0000000..6fec92e
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR74.xml
@@ -0,0 +1,202 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR74" document="026370" status="IP" memory_technology="ROM" architecture="16X" id="0x0620"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected="Off" bchecksum="0xF05F" cchecksum="0x7C2D" />
+    <checksum protected="All" bchecksum="0x005E" cchecksum="0x005E" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"      min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x000F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x005F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" ecnames="_WDTEN_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  ecnames="_WDTEN_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  ecnames="_PWRTEN_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" ecnames="_PWRTEN_OFF" />
+    </mask>
+    <mask name="CP"    value="0x0010" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x0010" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" ecnames="_BOREN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  ecnames="_BOREN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR76.xml b/src/devices/pic/xml_data/16CR76.xml
new file mode 100644
index 0000000..dd9916a
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR76.xml
@@ -0,0 +1,127 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR76" document="025241" status="IP" memory_technology="ROM" architecture="16X" id="0x0640"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected="Off" bchecksum="0xE05F" cchecksum="0x8C2D" />
+    <checksum protected="All" bchecksum="0x005E" cchecksum="0x005E" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"      min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x1FFF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x000F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x005F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" ecnames="_WDTEN_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  ecnames="_WDTEN_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  ecnames="_PWRTEN_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" ecnames="_PWRTEN_OFF" />
+    </mask>
+    <mask name="CP"    value="0x0010" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x0010" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" ecnames="_BOREN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  ecnames="_BOREN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2"         />
+    <pin index="5"  name="RA3/AN3/VREF"    />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSI/T1CKI" />
+    <pin index="12" name="RC1/T1OSO/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6/PGC"         />
+    <pin index="28" name="RB7/PGD"         />
+  </package>
+
+  <package types="mlf"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR77.xml b/src/devices/pic/xml_data/16CR77.xml
new file mode 100644
index 0000000..661ebf0
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR77.xml
@@ -0,0 +1,202 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR77" document="025194" status="IP" memory_technology="ROM" architecture="16X" id="0x0660"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected="Off" bchecksum="0xE05F" cchecksum="0x8C2D" />
+    <checksum protected="All" bchecksum="0x005E" cchecksum="0x005E" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"      min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x1FFF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x000F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x005F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" ecnames="_WDTEN_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  ecnames="_WDTEN_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  ecnames="_PWRTEN_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" ecnames="_PWRTEN_OFF" />
+    </mask>
+    <mask name="CP"    value="0x0010" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x0010" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" ecnames="_BOREN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  ecnames="_BOREN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR83.xml b/src/devices/pic/xml_data/16CR83.xml
new file mode 100644
index 0000000..01c4166
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR83.xml
@@ -0,0 +1,110 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR83" document="010203" status="NR" alternative="16F84A" memory_technology="ROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"                  bchecksum="0x3DFF" cchecksum="0x09CD" />
+    <checksum protected="All" mprotected="CPD" bchecksum="0x3E0E" cchecksum="0x09DC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="10" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="2" vdd_min="2" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12"  max="14"  nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x01FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="config"   start="0x2007" end="0x2007" />
+  <memory name="eeprom"   start="0x0000" end="0x003F" hexfile_offset="0x2100" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_DP_ON"  />
+      <value value="0x0080" name="Off" cname="_DP_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3F70" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x3F70" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="RA4/T0CKI"   />
+    <pin index="4"  name="MCLR"        />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0/INT"     />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16CR84.xml b/src/devices/pic/xml_data/16CR84.xml
new file mode 100644
index 0000000..5d93205
--- /dev/null
+++ b/src/devices/pic/xml_data/16CR84.xml
@@ -0,0 +1,110 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16CR84" document="010204" status="NR" alternative="16F84A" memory_technology="ROM" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"                  bchecksum="0x3BFF" cchecksum="0x07CD" />
+    <checksum protected="All" mprotected="CPD" bchecksum="0x3C0E" cchecksum="0x07DC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="10" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="2" vdd_min="2" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12"  max="14"  nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x03FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="config"   start="0x2007" end="0x2007" />
+  <memory name="eeprom"   start="0x0000" end="0x003F" hexfile_offset="0x2100" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF"  >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_DP_ON"  />
+      <value value="0x0080" name="Off" cname="_DP_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3F70" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x3F70" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="RA4/T0CKI"   />
+    <pin index="4"  name="MCLR"        />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0/INT"     />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F505.xml b/src/devices/pic/xml_data/16F505.xml
new file mode 100644
index 0000000..bbc2607
--- /dev/null
+++ b/src/devices/pic/xml_data/16F505.xml
@@ -0,0 +1,81 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F505" document="020096" status="IP" memory_technology="FLASH" architecture="10X" pc="12"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEC40" cchecksum="0xDA88" />
+    <checksum protected="040:3FE" bchecksum="0xEC2F" cchecksum="0xD19B" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"            start="0x000" end="0x3FE" />
+  <memory name="calibration"        start="0x3FF" end="0x3FF" cal_opmask="0xF00"     cal_opcode="0xC00" />
+  <memory name="user_ids"           start="0x400" end="0x403" rmask="0x00F"          />
+  <memory name="config"             start="0x7FF" end="0x7FF" hexfile_offset="0xFFF" />
+  <memory name="calibration_backup" start="0x404" end="0x404" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x03F" >
+    <mask name="FOSC"  value="0x007" >
+      <value value="0x000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x003" name="EC_IO"        cname="_EC_RB4EN"           />
+      <value value="0x004" name="INTRC_IO"     cname="_IntRC_OSC_RB4EN"    />
+      <value value="0x005" name="INTRC_CLKOUT" cname="_IntRC_OSC_CLKOUTEN" />
+      <value value="0x006" name="EXTRC_IO"     cname="_ExtRC_OSC_RB4EN"    />
+      <value value="0x007" name="EXTRC_CLKOUT" cname="_ExtRC_OSC_CLKOUTEN" />
+    </mask>
+    <mask name="WDT"   value="0x008" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"    value="0x010" >
+      <value value="0x000" name="040:3FE" cname="_CP_ON"  />
+      <value value="0x010" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x020" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop" nb_pins="14" >
+    <pin index="1"  name="VDD"             />
+    <pin index="2"  name="RB5/OSC1/CLKIN"  />
+    <pin index="3"  name="RB4/OSC2/CLKOUT" />
+    <pin index="4"  name="RB3/MCLR/VPP"    />
+    <pin index="5"  name="RC5/T0CKI"       />
+    <pin index="6"  name="RC4"             />
+    <pin index="7"  name="RC3"             />
+    <pin index="8"  name="RC2"             />
+    <pin index="9"  name="RC1"             />
+    <pin index="10" name="RC0"             />
+    <pin index="11" name="RB2"             />
+    <pin index="12" name="RB1/ICSPCLK"     />
+    <pin index="13" name="RB0/ICSPDAT"     />
+    <pin index="14" name="VSS"             />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F506.xml b/src/devices/pic/xml_data/16F506.xml
new file mode 100644
index 0000000..4fa7a47
--- /dev/null
+++ b/src/devices/pic/xml_data/16F506.xml
@@ -0,0 +1,86 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F506" document="023671" status="IP" memory_technology="FLASH" architecture="10X" pc="10"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0xEC80" cchecksum="0xDAC8" />
+    <checksum protected="040:3FE" bchecksum="0xECAF" cchecksum="0xD21B" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="8"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="8"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"            start="0x000" end="0x3FE" />
+  <memory name="calibration"        start="0x3FF" end="0x3FF" cal_opmask="0xF00"     cal_opcode="0xC00" />
+  <memory name="user_ids"           start="0x400" end="0x403" rmask="0x00F"          />
+  <memory name="config"             start="0x7FF" end="0x7FF" hexfile_offset="0xFFF" />
+  <memory name="calibration_backup" start="0x404" end="0x404" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x07F" >
+    <mask name="FOSC"   value="0x007" >
+      <value value="0x000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x004" name="INTRC_IO"     cname="_IntRC_OSC_RB4EN"    />
+      <value value="0x005" name="INTRC_CLKOUT" cname="_IntRC_OSC_CLKOUTEN" />
+      <value value="0x006" name="EXTRC_IO"     cname="_ExtRC_OSC_RB4EN"    />
+      <value value="0x007" name="EXTRC_CLKOUT" cname="_ExtRC_OSC_CLKOUTEN" />
+    </mask>
+    <mask name="WDT"    value="0x008" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"     value="0x010" >
+      <value value="0x000" name="040:3FE" cname="_CP_ON"  />
+      <value value="0x010" name="Off"     cname="_CP_OFF" />
+    </mask>
+    <mask name="MCLRE"  value="0x020" >
+      <value value="0x000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="IOSCFS" value="0x040" >
+      <value value="0x000" name="4MHZ" cname="_IOSCFS_OFF" />
+      <value value="0x040" name="8MHZ" cname="_IOSCFS_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop" nb_pins="14" >
+    <pin index="1"  name="VDD"                   />
+    <pin index="2"  name="RB5/OSC1/CLKIN"        />
+    <pin index="3"  name="RB4/OSC2/CLKOUT"       />
+    <pin index="4"  name="RB3/MCLR/VPP"          />
+    <pin index="5"  name="RC5/T0CKI"             />
+    <pin index="6"  name="RC4/C2OUT"             />
+    <pin index="7"  name="RC3"                   />
+    <pin index="8"  name="RC2/CVREF"             />
+    <pin index="9"  name="RC1/C2IN-"             />
+    <pin index="10" name="RC0/C2IN+"             />
+    <pin index="11" name="RB2/AN2/C1OUT"         />
+    <pin index="12" name="RB1/AN1/C1IN-/ICSPCLK" />
+    <pin index="13" name="RB0/AN0/C1IN+/ICSPDAT" />
+    <pin index="14" name="VSS"                   />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F54.xml b/src/devices/pic/xml_data/16F54.xml
new file mode 100644
index 0000000..4b55624
--- /dev/null
+++ b/src/devices/pic/xml_data/16F54.xml
@@ -0,0 +1,98 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F54" document="010205" status="IP" memory_technology="FLASH" architecture="10X" pc="9"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     constant="0x0FF0" bchecksum="0x0DFF" cchecksum="0xFC47" />
+    <checksum protected="040:1FF" constant="0x0FF0" bchecksum="0x1DB6" cchecksum="0x0322" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x1FF" />
+  <memory name="user_ids" start="0x200" end="0x203" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x00F" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0x008" >
+      <value value="0x000" name="040:1FF" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6/ICSPCLK" />
+    <pin index="13" name="RB7/ICSPDAT" />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F57.xml b/src/devices/pic/xml_data/16F57.xml
new file mode 100644
index 0000000..e84e053
--- /dev/null
+++ b/src/devices/pic/xml_data/16F57.xml
@@ -0,0 +1,116 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F57" document="010206" status="IP" memory_technology="FLASH" architecture="10X" pc="11"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     constant="0x0FF0" bchecksum="0x07FF" cchecksum="0xF647" />
+    <checksum protected="040:7FF" constant="0x0FF0" bchecksum="0x17B6" cchecksum="0xFD22" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x7FF" />
+  <memory name="user_ids" start="0x800" end="0x803" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x00F" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0x008" >
+      <value value="0x000" name="040:7FF" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="T0CKI"       />
+    <pin index="2"  name="VDD"         />
+    <pin index="3"  name="N/C"         />
+    <pin index="4"  name="VSS"         />
+    <pin index="5"  name="N/C"         />
+    <pin index="6"  name="RA0"         />
+    <pin index="7"  name="RA1"         />
+    <pin index="8"  name="RA2"         />
+    <pin index="9"  name="RA3"         />
+    <pin index="10" name="RB0"         />
+    <pin index="11" name="RB1"         />
+    <pin index="12" name="RB2"         />
+    <pin index="13" name="RB3"         />
+    <pin index="14" name="RB4"         />
+    <pin index="15" name="RB5"         />
+    <pin index="16" name="RB6/ICSPCLK" />
+    <pin index="17" name="RB7/ICSPDAT" />
+    <pin index="18" name="RC0"         />
+    <pin index="19" name="RC1"         />
+    <pin index="20" name="RC2"         />
+    <pin index="21" name="RC3"         />
+    <pin index="22" name="RC4"         />
+    <pin index="23" name="RC5"         />
+    <pin index="24" name="RC6"         />
+    <pin index="25" name="RC7"         />
+    <pin index="26" name="OSC2/CLKOUT" />
+    <pin index="27" name="OSC1/CLKIN"  />
+    <pin index="28" name="MCLR/VPP"    />
+  </package>
+
+  <package types="ssop"      nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F59.xml b/src/devices/pic/xml_data/16F59.xml
new file mode 100644
index 0000000..b29659a
--- /dev/null
+++ b/src/devices/pic/xml_data/16F59.xml
@@ -0,0 +1,144 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F59" document="021222" status="IP" memory_technology="FLASH" architecture="10X" pc="11"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     constant="0x0FF0" bchecksum="0x07FF" cchecksum="0xF647" />
+    <checksum protected="040:7FF" constant="0x0FF0" bchecksum="0x17B6" cchecksum="0xFD22" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"  max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x7FF" />
+  <memory name="user_ids" start="0x800" end="0x803" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x00F" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0x008" >
+      <value value="0x000" name="040:7FF" cname="_CP_ON"  />
+      <value value="0x008" name="Off"     cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="RA0"         />
+    <pin index="2"  name="RA1"         />
+    <pin index="3"  name="RA2"         />
+    <pin index="4"  name="RA3"         />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6/ICSPCLK" />
+    <pin index="13" name="RB7/ICSPDAT" />
+    <pin index="14" name="MCLR/VPP"    />
+    <pin index="15" name="VDD"         />
+    <pin index="16" name="RC0"         />
+    <pin index="17" name="RC1"         />
+    <pin index="18" name="RC2"         />
+    <pin index="19" name="RC3"         />
+    <pin index="20" name="RC4"         />
+    <pin index="21" name="RC5"         />
+    <pin index="22" name="RC6"         />
+    <pin index="23" name="RC7"         />
+    <pin index="24" name="RD0"         />
+    <pin index="25" name="VAA"         />
+    <pin index="26" name="RD1"         />
+    <pin index="27" name="RD2"         />
+    <pin index="28" name="RD3"         />
+    <pin index="29" name="RD4"         />
+    <pin index="30" name="RD5"         />
+    <pin index="31" name="RD6"         />
+    <pin index="32" name="RD7"         />
+    <pin index="33" name="OSC2/CLKOUT" />
+    <pin index="34" name="OSC1/CLKIN"  />
+    <pin index="35" name="VDD"         />
+    <pin index="36" name="RE4"         />
+    <pin index="37" name="RE5"         />
+    <pin index="38" name="RE6"         />
+    <pin index="39" name="RE7"         />
+    <pin index="40" name="T0CKI"       />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F610.xml b/src/devices/pic/xml_data/16F610.xml
new file mode 100644
index 0000000..46795b1
--- /dev/null
+++ b/src/devices/pic/xml_data/16F610.xml
@@ -0,0 +1,123 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F610" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x2260" id_high_voltage="0x22A0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="028257" datasheet="41288" progsheet="41284" erratas="80296" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xFFFF" cchecksum="0xCBCD" />
+    <checksum protected="All" bchecksum="0x03BE" cchecksum="0xCF8C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="8"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="8"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended" special="high_voltage">
+    <frequency start="0"  end="8"  vdd_min="2"   vdd_max="5.0" />
+    <frequency start="8"  end="10" vdd_min="3"   vdd_max="5.0" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.0" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x03FF" />
+  <memory name="calibration"  start="0x2008" end="0x2008" cal_opmask="0x0000" cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"      />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x03FF" >
+    <mask name="FOSC"   value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"    value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE"  value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE"  value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"     value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="IOSCFS" value="0x0080" >
+      <value value="0x0000" name="4MHZ" cname="_IOSCFS_4MHZ" />
+      <value value="0x0080" name="8MHZ" cname="_IOSCFS_8MHZ" />
+    </mask>
+    <mask name="BODEN"  value="0x0300" >
+      <value value="default" name="Off"    cname="_BOR_OFF"    />
+      <value value="0x0200" name="On_run" cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"     cname="_BOR_ON"     />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop" nb_pins="14" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="16" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F616.xml b/src/devices/pic/xml_data/16F616.xml
new file mode 100644
index 0000000..9f8ca55
--- /dev/null
+++ b/src/devices/pic/xml_data/16F616.xml
@@ -0,0 +1,124 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F616" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1240" id_high_voltage="0x1260"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026028" datasheet="41288" progsheet="41284" erratas="80296" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xFBFF" cchecksum="0xC7CD" />
+    <checksum protected="All" bchecksum="0xFFBE" cchecksum="0xCB8C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <frequency_range name="extended" special="high_voltage">
+    <frequency start="0"  end="8"  vdd_min="2"   vdd_max="5.0" />
+    <frequency start="8"  end="10" vdd_min="3"   vdd_max="5.0" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.0" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="calibration"  start="0x2008" end="0x2008" cal_opmask="0x0000" cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"      />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x03FF" >
+    <mask name="FOSC"   value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"    value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE"  value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE"  value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"     value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="IOSCFS" value="0x0080" >
+      <value value="0x0000" name="4MHZ" cname="_IOSCFS_4MHZ" />
+      <value value="0x0080" name="8MHZ" cname="_IOSCFS_8MHZ" />
+    </mask>
+    <mask name="BODEN"  value="0x0300" >
+      <value value="default" name="Off"    cname="_BOR_OFF"    />
+      <value value="0x0200" name="On_run" cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"     cname="_BOR_ON"     />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop" nb_pins="14" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="16" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F627.xml b/src/devices/pic/xml_data/16F627.xml
new file mode 100644
index 0000000..7ce03a5
--- /dev/null
+++ b/src/devices/pic/xml_data/16F627.xml
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F627" status="NR" alternative="16F627A" memory_technology="FLASH" self_write="no" architecture="16X" id="0x07A0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010207" datasheet="40300" progsheet="30034" erratas="80073" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x39FF" cchecksum="0x05CD" />
+    <checksum protected="200:3FF" bchecksum="0x4DFE" cchecksum="0xFFB3" />
+    <checksum protected="All"     bchecksum="0x3BFE" cchecksum="0x07CC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x03FF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+  <memory name="eeprom"    start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3DFF" icnames="_CP_50" >
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="FOSC"  value="0x0013" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK_OSC"         />
+      <value value="0x0010" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0011" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0012" name="ER_IO"        cname="_ER_OSC_NOCLKOUT"    />
+      <value value="0x0013" name="ER_CLKOUT"    cname="_ER_OSC_CLKOUT"      />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_DATA_CP_ON"  />
+      <value value="0x0100" name="Off" cname="_DATA_CP_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3C00" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1400" name="200:3FF" cname="_CP_75"  />
+      <value value="0x3C00" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2/VREF"        />
+    <pin index="2"  name="RA3/AN3/CMP1"        />
+    <pin index="3"  name="RA4/T0CKI/CMP2"      />
+    <pin index="4"  name="RA5/MCLR/VPP"        />
+    <pin index="5"  name="VSS"                 />
+    <pin index="6"  name="RB0/INT"             />
+    <pin index="7"  name="RB1/RX/DT"           />
+    <pin index="8"  name="RB2/TX/CK"           />
+    <pin index="9"  name="RB3/CCP1"            />
+    <pin index="10" name="RB4/PGM"             />
+    <pin index="11" name="RB5"                 />
+    <pin index="12" name="RB6/T1OSI/PGC"       />
+    <pin index="13" name="RB7/T1OSO/T1CKI/PGD" />
+    <pin index="14" name="VDD"                 />
+    <pin index="15" name="RA6/OSC2/CLKOUT"     />
+    <pin index="16" name="RA7/OSC1/CLKIN"      />
+    <pin index="17" name="RA0/AN0"             />
+    <pin index="18" name="RA1/AN1"             />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F627A.xml b/src/devices/pic/xml_data/16F627A.xml
new file mode 100644
index 0000000..de43d7a
--- /dev/null
+++ b/src/devices/pic/xml_data/16F627A.xml
@@ -0,0 +1,164 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F627A" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1040"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010208" datasheet="40044" progsheet="41196" erratas="80151" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x1DFF" cchecksum="0xE9CD" />
+    <checksum protected="All"     bchecksum="0x1FFE" cchecksum="0xEBCC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x03FF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x21FF" >
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="FOSC"  value="0x0013" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"              />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"              />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"              />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK_OSC"          />
+      <value value="0x0010" name="INTRC_IO"     cname="_INTOSC_OSC_NOCLKOUT" ecnames="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0011" name="INTRC_CLKOUT" cname="_INTOSC_OSC_CLKOUT"   ecnames="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0012" name="ER_IO"        cname="_RC_OSC_NOCLKOUT"     ecnames="_ER_OSC_NOCLKOUT"    />
+      <value value="0x0013" name="ER_CLKOUT"    cname="_RC_OSC_CLKOUT"       ecnames="_ER_OSC_CLKOUT"      />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BOREN_OFF" ecnames="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BOREN_ON"  ecnames="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_DATA_CP_ON"  />
+      <value value="0x0100" name="Off" cname="_DATA_CP_OFF" />
+    </mask>
+    <mask name="CP"    value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2/VREF"        />
+    <pin index="2"  name="RA3/AN3/CMP1"        />
+    <pin index="3"  name="RA4/T0CKI/CMP2"      />
+    <pin index="4"  name="RA5/MCLR/VPP"        />
+    <pin index="5"  name="VSS"                 />
+    <pin index="6"  name="RB0/INT"             />
+    <pin index="7"  name="RB1/RX/DT"           />
+    <pin index="8"  name="RB2/TX/CK"           />
+    <pin index="9"  name="RB3/CCP1"            />
+    <pin index="10" name="RB4/PGM"             />
+    <pin index="11" name="RB5"                 />
+    <pin index="12" name="RB6/T1OSI/PGC"       />
+    <pin index="13" name="RB7/T1OSO/T1CKI/PGD" />
+    <pin index="14" name="VDD"                 />
+    <pin index="15" name="RA6/OSC2/CLKOUT"     />
+    <pin index="16" name="RA7/OSC1/CLKIN"      />
+    <pin index="17" name="RA0/AN0"             />
+    <pin index="18" name="RA1/AN1"             />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F628.xml b/src/devices/pic/xml_data/16F628.xml
new file mode 100644
index 0000000..fed16fa
--- /dev/null
+++ b/src/devices/pic/xml_data/16F628.xml
@@ -0,0 +1,145 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F628" status="NR" alternative="16F628A" memory_technology="FLASH" self_write="no" architecture="16X" id="0x07C0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010209" datasheet="40300" progsheet="30034" erratas="80073" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x35FF" cchecksum="0x01CD" />
+    <checksum protected="400:7FF" bchecksum="0x5BFE" cchecksum="0x0DB3" />
+    <checksum protected="200:7FF" bchecksum="0x49FE" cchecksum="0xFBB3" />
+    <checksum protected="All"     bchecksum="0x37FE" cchecksum="0x03CC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="commercial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="4"  vdd_min="3"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x07FF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+  <memory name="eeprom"    start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3DFF" >
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="FOSC"  value="0x0013" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK_OSC"         />
+      <value value="0x0010" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0011" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0012" name="ER_IO"        cname="_ER_OSC_NOCLKOUT"    />
+      <value value="0x0013" name="ER_CLKOUT"    cname="_ER_OSC_CLKOUT"      />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_DATA_CP_ON"  />
+      <value value="0x0100" name="Off" cname="_DATA_CP_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3C00" >
+      <value value="0x0000" name="All"     cname="_CP_ALL" />
+      <value value="0x1400" name="200:7FF" cname="_CP_75"  />
+      <value value="0x2800" name="400:7FF" cname="_CP_50"  />
+      <value value="0x3C00" name="Off"     cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2/VREF"        />
+    <pin index="2"  name="RA3/AN3/CMP1"        />
+    <pin index="3"  name="RA4/T0CKI/CMP2"      />
+    <pin index="4"  name="RA5/MCLR/VPP"        />
+    <pin index="5"  name="VSS"                 />
+    <pin index="6"  name="RB0/INT"             />
+    <pin index="7"  name="RB1/RX/DT"           />
+    <pin index="8"  name="RB2/TX/CK"           />
+    <pin index="9"  name="RB3/CCP1"            />
+    <pin index="10" name="RB4/PGM"             />
+    <pin index="11" name="RB5"                 />
+    <pin index="12" name="RB6/T1OSI/PGC"       />
+    <pin index="13" name="RB7/T1OSO/T1CKI/PGD" />
+    <pin index="14" name="VDD"                 />
+    <pin index="15" name="RA6/OSC2/CLKOUT"     />
+    <pin index="16" name="RA7/OSC1/CLKIN"      />
+    <pin index="17" name="RA0/AN0"             />
+    <pin index="18" name="RA1/AN1"             />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F628A.xml b/src/devices/pic/xml_data/16F628A.xml
new file mode 100644
index 0000000..8c5a4cc
--- /dev/null
+++ b/src/devices/pic/xml_data/16F628A.xml
@@ -0,0 +1,164 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F628A" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1060"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010210" datasheet="40044" progsheet="41196" erratas="80151" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x19FF" cchecksum="0xE5CD" />
+    <checksum protected="All"     bchecksum="0x1BFE" cchecksum="0xE7CC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x21FF" >
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="FOSC"  value="0x0013" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"              />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"              />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"              />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK_OSC"          />
+      <value value="0x0010" name="INTRC_IO"     cname="_INTOSC_OSC_NOCLKOUT" ecnames="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0011" name="INTRC_CLKOUT" cname="_INTOSC_OSC_CLKOUT"   ecnames="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0012" name="ER_IO"        cname="_RC_OSC_NOCLKOUT"     ecnames="_ER_OSC_NOCLKOUT"    />
+      <value value="0x0013" name="ER_CLKOUT"    cname="_RC_OSC_CLKOUT"       ecnames="_ER_OSC_CLKOUT"      />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BOREN_OFF" ecnames="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BOREN_ON"  ecnames="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_DATA_CP_ON"  />
+      <value value="0x0100" name="Off" cname="_DATA_CP_OFF" />
+    </mask>
+    <mask name="CP"    value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2/VREF"        />
+    <pin index="2"  name="RA3/AN3/CMP1"        />
+    <pin index="3"  name="RA4/T0CKI/CMP2"      />
+    <pin index="4"  name="RA5/MCLR/VPP"        />
+    <pin index="5"  name="VSS"                 />
+    <pin index="6"  name="RB0/INT"             />
+    <pin index="7"  name="RB1/RX/DT"           />
+    <pin index="8"  name="RB2/TX/CK"           />
+    <pin index="9"  name="RB3/CCP1"            />
+    <pin index="10" name="RB4/PGM"             />
+    <pin index="11" name="RB5"                 />
+    <pin index="12" name="RB6/T1OSI/PGC"       />
+    <pin index="13" name="RB7/T1OSO/T1CKI/PGD" />
+    <pin index="14" name="VDD"                 />
+    <pin index="15" name="RA6/OSC2/CLKOUT"     />
+    <pin index="16" name="RA7/OSC1/CLKIN"      />
+    <pin index="17" name="RA0/AN0"             />
+    <pin index="18" name="RA1/AN1"             />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F630.xml b/src/devices/pic/xml_data/16F630.xml
new file mode 100644
index 0000000..a82ffdb
--- /dev/null
+++ b/src/devices/pic/xml_data/16F630.xml
@@ -0,0 +1,108 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F630" document="010211" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x10C0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xBE00" cchecksum="0x89CE" />
+    <checksum protected="All" bchecksum="0xBF7F" cchecksum="0x8B4D" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" special="AD off" />
+    <frequency start="0"  end="4"  vdd_min="2.2" vdd_max="5.5" special="AD on"  />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" special="AD off" />
+    <frequency start="0"  end="4"  vdd_min="2.5" vdd_max="5.5" special="AD on"  />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"   max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x03FE" />
+  <memory name="calibration"  start="0x03FF" end="0x03FF" cal_opmask="0x3C00"     cal_opcode="0x3400" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x31FF" bvalue="0x31FF" pmask="0x3000" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC"           cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN"     />
+    </mask>
+    <mask name="CP"    value="0x0080" >
+      <value value="0x0000" name="All" cname="_CP"     />
+      <value value="0x0080" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD"     />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BG"    value="0x3000">
+      <value value="0x0000" name="Lowest"   />
+      <value value="0x1000" name="Mid/Low"  />
+      <value value="0x2000" name="Mid/High" />
+      <value value="0x3000" name="Highest"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop" nb_pins="14" >
+    <pin index="1"  name="VDD"                  />
+    <pin index="2"  name="RA5/T1CKI/OSC1/CLKIN" />
+    <pin index="3"  name="RA4/T1G/OSC2/CLKOUT"  />
+    <pin index="4"  name="RA3/MCLR/VPP"         />
+    <pin index="5"  name="RC5"                  />
+    <pin index="6"  name="RC4"                  />
+    <pin index="7"  name="RC3"                  />
+    <pin index="8"  name="RC2"                  />
+    <pin index="9"  name="RC1"                  />
+    <pin index="10" name="RC0"                  />
+    <pin index="11" name="RA2/COUT/T0CKI/INT"   />
+    <pin index="12" name="RA1/CIN-/ICSPCLK"     />
+    <pin index="13" name="RA0/CIN+/ICSPDAT"     />
+    <pin index="14" name="VSS"                  />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F631.xml b/src/devices/pic/xml_data/16F631.xml
new file mode 100644
index 0000000..e6a5274
--- /dev/null
+++ b/src/devices/pic/xml_data/16F631.xml
@@ -0,0 +1,135 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F631" document="026027" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1420"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x0BFF" cchecksum="0xD7CD" />
+    <checksum protected="All" bchecksum="0x1BBE" cchecksum="0xE78C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x03FF" />
+  <memory name="calibration"  start="0x2008" end="0x2008" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x0FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOR_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOR_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOR_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="20" >
+    <pin index="1"  name="VDD"                     />
+    <pin index="2"  name="RA5/T1CKI/OSC1/CLKIN"    />
+    <pin index="3"  name="RA4/T1G/OSC2/CLKOUT"     />
+    <pin index="4"  name="RA3/MCLR/VPP"            />
+    <pin index="5"  name="RC5"                     />
+    <pin index="6"  name="RC4/C2OUT"               />
+    <pin index="7"  name="RC3/C12IN3-"             />
+    <pin index="8"  name="RC6"                     />
+    <pin index="9"  name="RC7"                     />
+    <pin index="10" name="RB7"                     />
+    <pin index="11" name="RB6"                     />
+    <pin index="12" name="RB5"                     />
+    <pin index="13" name="RB4"                     />
+    <pin index="14" name="RC2/C12IN2-"             />
+    <pin index="15" name="RC1/C12IN1-"             />
+    <pin index="16" name="RC0/C12IN+"              />
+    <pin index="17" name="RA2/C1OUT/T0CKI/INT"     />
+    <pin index="18" name="RA1/C12IN0-/ICSPCLK"     />
+    <pin index="19" name="RA0/C1IN+/ICSPDAT/ULPWU" />
+    <pin index="20" name="VSS"                     />
+  </package>
+
+  <package types="qfn"            nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F636.xml b/src/devices/pic/xml_data/16F636.xml
new file mode 100644
index 0000000..e47314e
--- /dev/null
+++ b/src/devices/pic/xml_data/16F636.xml
@@ -0,0 +1,110 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F636" document="019833" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x10A0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x17FF" cchecksum="0xE3CD" />
+    <checksum protected="All" bchecksum="0x37BE" cchecksum="0x038C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="calibration"  start="0x2008" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x1FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOD_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOD_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOD_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOD_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="WUREN" value="0x1000" >
+      <value value="0x0000" name="On"  cname="_WUREN_ON"  />
+      <value value="0x1000" name="Off" cname="_WUREN_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop" nb_pins="14" >
+    <pin index="1"  name="VDD"                     />
+    <pin index="2"  name="RA5/T1CKI/OSC1/CLKIN"    />
+    <pin index="3"  name="RA4/T1G/OSC2/CLKOUT"     />
+    <pin index="4"  name="RA3/MCLR/VPP"            />
+    <pin index="5"  name="RC5"                     />
+    <pin index="6"  name="RC4/C2OUT"               />
+    <pin index="7"  name="RC3"                     />
+    <pin index="8"  name="RC2"                     />
+    <pin index="9"  name="RC1/C2IN-"               />
+    <pin index="10" name="RC0/C2IN+"               />
+    <pin index="11" name="RA2/C1OUT/T0CKI/INT"     />
+    <pin index="12" name="RA1/C1IN-/VREF/ICSPCLK"  />
+    <pin index="13" name="RA0/C1IN+/ICSPDAT/ULPWU" />
+    <pin index="14" name="VSS"                     />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F639.xml b/src/devices/pic/xml_data/16F639.xml
new file mode 100644
index 0000000..7affb7b
--- /dev/null
+++ b/src/devices/pic/xml_data/16F639.xml
@@ -0,0 +1,116 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F639" document="022266" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x10A0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x17FF" cchecksum="0xE3CD" />
+    <checksum protected="All" bchecksum="0x37BE" cchecksum="0x038C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="calibration"  start="0x2008" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x1FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOD_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOD_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOD_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOD_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="WUREN" value="0x1000" >
+      <value value="0x0000" name="On"  cname="_WUREN_ON"  />
+      <value value="0x1000" name="Off" cname="_WUREN_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="ssop" nb_pins="20" >
+    <pin index="1"  name="VDD"                       />
+    <pin index="2"  name="RA5/T1CKI/OSC1/CLKIN"      />
+    <pin index="3"  name="RA4/T1G/OSC2/CLKOUT"       />
+    <pin index="4"  name="RA3/MCLR/VPP"              />
+    <pin index="5"  name="RC5"                       />
+    <pin index="6"  name="RC4/C2OUT"                 />
+    <pin index="7"  name="RC3/LFDATA/RSSI/CCLK/SDIO" />
+    <pin index="8"  name="VDDT"                      />
+    <pin index="9"  name="LCZ"                       />
+    <pin index="10" name="LCY"                       />
+    <pin index="11" name="LCX"                       />
+    <pin index="12" name="LCCOM"                     />
+    <pin index="13" name="VSST"                      />
+    <pin index="14" name="RC2/SCLK/ALERT"            />
+    <pin index="15" name="RC1/C2IN1-/CS"             />
+    <pin index="16" name="RC0/C2IN+"                 />
+    <pin index="17" name="RA2/C1OUT/T0CKI/INT"       />
+    <pin index="18" name="RA1/C1IN-/VREF/ICSPCLK"    />
+    <pin index="19" name="RA0/C1IN+/ICSPDAT/ULPWU"   />
+    <pin index="20" name="VSS"                       />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F648A.xml b/src/devices/pic/xml_data/16F648A.xml
new file mode 100644
index 0000000..17b4f83
--- /dev/null
+++ b/src/devices/pic/xml_data/16F648A.xml
@@ -0,0 +1,164 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F648A" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1100"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010212" datasheet="40044" progsheet="41196" erratas="80151" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x11FF" cchecksum="0xDDCD" />
+    <checksum protected="All"     bchecksum="0x13FE" cchecksum="0xDFCC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x21FF" >
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="FOSC"  value="0x0013" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"              />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"              />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"              />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK_OSC"          />
+      <value value="0x0010" name="INTRC_IO"     cname="_INTOSC_OSC_NOCLKOUT" ecnames="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0011" name="INTRC_CLKOUT" cname="_INTOSC_OSC_CLKOUT"   ecnames="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0012" name="ER_IO"        cname="_RC_OSC_NOCLKOUT"     ecnames="_ER_OSC_NOCLKOUT"    />
+      <value value="0x0013" name="ER_CLKOUT"    cname="_RC_OSC_CLKOUT"       ecnames="_ER_OSC_CLKOUT"      />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BOREN_OFF" ecnames="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BOREN_ON"  ecnames="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_DATA_CP_ON"  />
+      <value value="0x0100" name="Off" cname="_DATA_CP_OFF" />
+    </mask>
+    <mask name="CP"    value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2/VREF"        />
+    <pin index="2"  name="RA3/AN3/CMP1"        />
+    <pin index="3"  name="RA4/T0CKI/CMP2"      />
+    <pin index="4"  name="RA5/MCLR/VPP"        />
+    <pin index="5"  name="VSS"                 />
+    <pin index="6"  name="RB0/INT"             />
+    <pin index="7"  name="RB1/RX/DT"           />
+    <pin index="8"  name="RB2/TX/CK"           />
+    <pin index="9"  name="RB3/CCP1"            />
+    <pin index="10" name="RB4/PGM"             />
+    <pin index="11" name="RB5"                 />
+    <pin index="12" name="RB6/T1OSI/PGC"       />
+    <pin index="13" name="RB7/T1OSO/T1CKI/PGD" />
+    <pin index="14" name="VDD"                 />
+    <pin index="15" name="RA6/OSC2/CLKOUT"     />
+    <pin index="16" name="RA7/OSC1/CLKIN"      />
+    <pin index="17" name="RA0/AN0"             />
+    <pin index="18" name="RA1/AN1"             />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F676.xml b/src/devices/pic/xml_data/16F676.xml
new file mode 100644
index 0000000..b608d48
--- /dev/null
+++ b/src/devices/pic/xml_data/16F676.xml
@@ -0,0 +1,108 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F676" document="010213" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x10E0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xBE00" cchecksum="0x89CE" />
+    <checksum protected="All" bchecksum="0xBF7F" cchecksum="0x8B4D" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="commercial" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" special="AD off" />
+    <frequency start="0"  end="4"  vdd_min="2.2" vdd_max="5.5" special="AD on"  />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" special="AD off" />
+    <frequency start="0"  end="4"  vdd_min="2.5" vdd_max="5.5" special="AD on"  />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5"   max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x03FE" />
+  <memory name="calibration"  start="0x03FF" end="0x03FF" cal_opmask="0x3C00"     cal_opcode="0x3400" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x31FF" bvalue="0x31FF" pmask="0x3000" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC"           cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN"     />
+    </mask>
+    <mask name="CP"    value="0x0080" >
+      <value value="0x0000" name="All" cname="_CP"     />
+      <value value="0x0080" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD"     />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BG"    value="0x3000">
+      <value value="0x0000" name="Lowest"   />
+      <value value="0x1000" name="Mid/Low"  />
+      <value value="0x2000" name="Mid/High" />
+      <value value="0x3000" name="Highest"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop" nb_pins="14" >
+    <pin index="1"  name="VDD"                     />
+    <pin index="2"  name="RA5/T1CKI/OSC1/CLKIN"    />
+    <pin index="3"  name="RA4/T1G/OSC2/AN3/CLKOUT" />
+    <pin index="4"  name="RA3/MCLR/VPP"            />
+    <pin index="5"  name="RC5"                     />
+    <pin index="6"  name="RC4"                     />
+    <pin index="7"  name="RC3/AN7"                 />
+    <pin index="8"  name="RC2/AN6"                 />
+    <pin index="9"  name="RC1/AN5"                 />
+    <pin index="10" name="RC0/AN4"                 />
+    <pin index="11" name="RA2/AN2/COUT/T0CKI/INT"  />
+    <pin index="12" name="RA1/AN1/CIN-/ICSPCLK"    />
+    <pin index="13" name="RA0/AN0/CIN+/ICSPDAT"    />
+    <pin index="14" name="VSS"                     />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F677.xml b/src/devices/pic/xml_data/16F677.xml
new file mode 100644
index 0000000..d27b2eb
--- /dev/null
+++ b/src/devices/pic/xml_data/16F677.xml
@@ -0,0 +1,135 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F677" document="026026" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1440"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x07FF" cchecksum="0xD3CD" />
+    <checksum protected="All" bchecksum="0x17BE" cchecksum="0xE38C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="calibration"  start="0x2008" end="0x2008" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x0FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOR_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOR_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOR_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="20" >
+    <pin index="1"  name="VDD"                          />
+    <pin index="2"  name="RA5/T1CKI/OSC1/CLKIN"         />
+    <pin index="3"  name="RA4/AN3/T1G/OSC2/CLKOUT"      />
+    <pin index="4"  name="RA3/MCLR/VPP"                 />
+    <pin index="5"  name="RC5"                          />
+    <pin index="6"  name="RC4/C2OUT"                    />
+    <pin index="7"  name="RC3/AN7/C12IN3-"              />
+    <pin index="8"  name="RC6/AN8/SS"                   />
+    <pin index="9"  name="RC7/AN9/SDO"                  />
+    <pin index="10" name="RB7"                          />
+    <pin index="11" name="RB6/SCK/SCL"                  />
+    <pin index="12" name="RB5/AN11"                     />
+    <pin index="13" name="RB4/AN10/SDI/SDA"             />
+    <pin index="14" name="RC2/AN6/C12IN2-"              />
+    <pin index="15" name="RC1/AN5/C12IN1-"              />
+    <pin index="16" name="RC0/AN4/C12IN+"               />
+    <pin index="17" name="RA2/AN2/C1OUT/T0CKI/INT"      />
+    <pin index="18" name="RA1/AN1/C12IN0-/VREF/ICSPCLK" />
+    <pin index="19" name="RA0/AN0/C1IN+/ICSPDAT/ULPWU"  />
+    <pin index="20" name="VSS"                          />
+  </package>
+
+  <package types="qfn"            nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F684.xml b/src/devices/pic/xml_data/16F684.xml
new file mode 100644
index 0000000..f330925
--- /dev/null
+++ b/src/devices/pic/xml_data/16F684.xml
@@ -0,0 +1,106 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F684" document="010214" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1080"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x07FF" cchecksum="0xD3CD" />
+    <checksum protected="All" bchecksum="0x17BE" cchecksum="0xE38C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="calibration"  start="0x2008" end="0x2008" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x0FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOD_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOD_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOD_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOD_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop" nb_pins="14" >
+    <pin index="1"  name="VDD"                         />
+    <pin index="2"  name="RA5/T1CKI/OSC1/CLKIN"        />
+    <pin index="3"  name="RA4/T1G/OSC2/AN3/CLKOUT"     />
+    <pin index="4"  name="RA3/MCLR/VPP"                />
+    <pin index="5"  name="RC5/CCP1/P1A"                />
+    <pin index="6"  name="RC4/C2OUT/P1B"               />
+    <pin index="7"  name="RC3/AN7/P1C"                 />
+    <pin index="8"  name="RC2/AN6/P1D"                 />
+    <pin index="9"  name="RC1/AN5/C2IN-"               />
+    <pin index="10" name="RC0/AN4/C2IN+"               />
+    <pin index="11" name="RA2/AN2/C1OUT/T0CKI/INT"     />
+    <pin index="12" name="RA1/AN1/C1IN-/VREF/ICSPCLK"  />
+    <pin index="13" name="RA0/AN0/C1IN+/ICSPDAT/ULPWU" />
+    <pin index="14" name="VSS"                         />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F685.xml b/src/devices/pic/xml_data/16F685.xml
new file mode 100644
index 0000000..aa35aa3
--- /dev/null
+++ b/src/devices/pic/xml_data/16F685.xml
@@ -0,0 +1,135 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F685" document="023115" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x04A0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xFFFF" cchecksum="0xCBCD" />
+    <checksum protected="All" bchecksum="0x0FBE" cchecksum="0xDB8C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="calibration"  start="0x2008" end="0x2008" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x0FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOR_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOR_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOR_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="20" >
+    <pin index="1"  name="VDD"                          />
+    <pin index="2"  name="RA5/T1CKI/OSC1/CLKIN"         />
+    <pin index="3"  name="RA4/AN3/T1G/OSC2/CLKOUT"      />
+    <pin index="4"  name="RA3/MCLR/VPP"                 />
+    <pin index="5"  name="RC5/CCP1/P1A"                 />
+    <pin index="6"  name="RC4/C2OUT/P1B"                />
+    <pin index="7"  name="RC3/AN7/C12IN3-/P1C"          />
+    <pin index="8"  name="RC6/AN8"                      />
+    <pin index="9"  name="RC7/AN9"                      />
+    <pin index="10" name="RB7"                          />
+    <pin index="11" name="RB6"                          />
+    <pin index="12" name="RB5/AN11"                     />
+    <pin index="13" name="RB4/AN10"                     />
+    <pin index="14" name="RC2/AN6/C12IN2-/P1D"          />
+    <pin index="15" name="RC1/AN5/C12IN1-"              />
+    <pin index="16" name="RC0/AN4/C12IN+"               />
+    <pin index="17" name="RA2/AN2/C1OUT/T0CKI/INT"      />
+    <pin index="18" name="RA1/AN1/C12IN0-/VREF/ICSPCLK" />
+    <pin index="19" name="RA0/AN0/C1IN+/ICSPDAT/ULPWU"  />
+    <pin index="20" name="VSS"                          />
+  </package>
+
+  <package types="qfn"            nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F687.xml b/src/devices/pic/xml_data/16F687.xml
new file mode 100644
index 0000000..2e58780
--- /dev/null
+++ b/src/devices/pic/xml_data/16F687.xml
@@ -0,0 +1,135 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F687" document="023114" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1320"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x07FF" cchecksum="0xD3CD" />
+    <checksum protected="All" bchecksum="0x17BE" cchecksum="0xE38C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="calibration"  start="0x2008" end="0x2008" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x0FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOR_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOR_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOR_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="20" >
+    <pin index="1"  name="VDD"                          />
+    <pin index="2"  name="RA5/T1CKI/OSC1/CLKIN"         />
+    <pin index="3"  name="RA4/AN3/T1G/OSC2/CLKOUT"      />
+    <pin index="4"  name="RA3/MCLR/VPP"                 />
+    <pin index="5"  name="RC5"                          />
+    <pin index="6"  name="RC4/C2OUT"                    />
+    <pin index="7"  name="RC3/AN7/C12IN3-"              />
+    <pin index="8"  name="RC6/AN8/SS"                   />
+    <pin index="9"  name="RC7/AN9/SDO"                  />
+    <pin index="10" name="RB7/TX/CK"                    />
+    <pin index="11" name="RB6/SCK/SCL"                  />
+    <pin index="12" name="RB5/AN11/RX/DT"               />
+    <pin index="13" name="RB4/AN10/SDI/SDA"             />
+    <pin index="14" name="RC2/AN6/C12IN2-"              />
+    <pin index="15" name="RC1/AN5/C12IN1-"              />
+    <pin index="16" name="RC0/AN4/C12IN+"               />
+    <pin index="17" name="RA2/AN2/C1OUT/T0CKI/INT"      />
+    <pin index="18" name="RA1/AN1/C12IN0-/VREF/ICSPCLK" />
+    <pin index="19" name="RA0/AN0/C1IN+/ICSPDAT/ULPWU"  />
+    <pin index="20" name="VSS"                          />
+  </package>
+
+  <package types="qfn"            nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F688.xml b/src/devices/pic/xml_data/16F688.xml
new file mode 100644
index 0000000..2692159
--- /dev/null
+++ b/src/devices/pic/xml_data/16F688.xml
@@ -0,0 +1,106 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F688" document="010215" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1180"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xFFFF" cchecksum="0xCBCD" />
+    <checksum protected="All" bchecksum="0x0FBE" cchecksum="0xDB8C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="calibration"  start="0x2008" end="0x2008" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x0FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOD_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOD_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOD_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOD_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic tssop" nb_pins="14" >
+    <pin index="1"  name="VDD"                         />
+    <pin index="2"  name="RA5/T1CKI/OSC1/CLKIN"        />
+    <pin index="3"  name="RA4/T1G/OSC2/AN3/CLKOUT"     />
+    <pin index="4"  name="RA3/MCLR/VPP"                />
+    <pin index="5"  name="RC5/RX/DT"                   />
+    <pin index="6"  name="RC4/TX/CK"                   />
+    <pin index="7"  name="RC3/AN7"                     />
+    <pin index="8"  name="RC2/AN6"                     />
+    <pin index="9"  name="RC1/AN5/C2IN-"               />
+    <pin index="10" name="RC0/AN4/C2IN+"               />
+    <pin index="11" name="RA2/AN2/C1OUT/T0CKI/INT"     />
+    <pin index="12" name="RA1/AN1/C1IN-/VREF/ICSPCLK"  />
+    <pin index="13" name="RA0/AN0/C1IN+/ICSPDAT/ULPWU" />
+    <pin index="14" name="VSS"                         />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F689.xml b/src/devices/pic/xml_data/16F689.xml
new file mode 100644
index 0000000..f22fdcd
--- /dev/null
+++ b/src/devices/pic/xml_data/16F689.xml
@@ -0,0 +1,135 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F689" document="023113" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1340"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xFFFF" cchecksum="0xCBCD" />
+    <checksum protected="All" bchecksum="0x0FBE" cchecksum="0xDB8C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="calibration"  start="0x2008" end="0x2008" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x0FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOR_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOR_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOR_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="20" >
+    <pin index="1"  name="VDD"                          />
+    <pin index="2"  name="RA5/T1CKI/OSC1/CLKIN"         />
+    <pin index="3"  name="RA4/AN3/T1G/OSC2/CLKOUT"      />
+    <pin index="4"  name="RA3/MCLR/VPP"                 />
+    <pin index="5"  name="RC5"                          />
+    <pin index="6"  name="RC4/C2OUT"                    />
+    <pin index="7"  name="RC3/AN7/C12IN3-"              />
+    <pin index="8"  name="RC6/AN8/SS"                   />
+    <pin index="9"  name="RC7/AN9/SDO"                  />
+    <pin index="10" name="RB7/TX/CK"                    />
+    <pin index="11" name="RB6/SCK/SCL"                  />
+    <pin index="12" name="RB5/AN11/RX/DT"               />
+    <pin index="13" name="RB4/AN10/SDI/SDA"             />
+    <pin index="14" name="RC2/AN6/C12IN2-"              />
+    <pin index="15" name="RC1/AN5/C12IN1-"              />
+    <pin index="16" name="RC0/AN4/C12IN+"               />
+    <pin index="17" name="RA2/AN2/C1OUT/T0CKI/INT"      />
+    <pin index="18" name="RA1/AN1/C12IN0-/VREF/ICSPCLK" />
+    <pin index="19" name="RA0/AN0/C1IN+/ICSPDAT/ULPWU"  />
+    <pin index="20" name="VSS"                          />
+  </package>
+
+  <package types="qfn"            nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F690.xml b/src/devices/pic/xml_data/16F690.xml
new file mode 100644
index 0000000..7a51bac
--- /dev/null
+++ b/src/devices/pic/xml_data/16F690.xml
@@ -0,0 +1,135 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F690" document="023112" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1400"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xFFFF" cchecksum="0xCBCD" />
+    <checksum protected="All" bchecksum="0x0FBE" cchecksum="0xDB8C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="calibration"  start="0x2008" end="0x2008" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x0FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOR_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOR_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOR_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="20" >
+    <pin index="1"  name="VDD"                          />
+    <pin index="2"  name="RA5/T1CKI/OSC1/CLKIN"         />
+    <pin index="3"  name="RA4/AN3/T1G/OSC2/CLKOUT"      />
+    <pin index="4"  name="RA3/MCLR/VPP"                 />
+    <pin index="5"  name="RC5/CPP1/P1A"                 />
+    <pin index="6"  name="RC4/C2OUT/P1B"                />
+    <pin index="7"  name="RC3/AN7/C12IN3-"              />
+    <pin index="8"  name="RC6/AN8/SS"                   />
+    <pin index="9"  name="RC7/AN9/SDO"                  />
+    <pin index="10" name="RB7/TX/CK"                    />
+    <pin index="11" name="RB6/SCK/SCL"                  />
+    <pin index="12" name="RB5/AN11/RX/DT"               />
+    <pin index="13" name="RB4/AN10/SDI/SDA"             />
+    <pin index="14" name="RC2/AN6/C12IN2-/P1D"          />
+    <pin index="15" name="RC1/AN5/C12IN1-"              />
+    <pin index="16" name="RC0/AN4/C12IN+"               />
+    <pin index="17" name="RA2/AN2/C1OUT/T0CKI/INT"      />
+    <pin index="18" name="RA1/AN1/C12IN0-/VREF/ICSPCLK" />
+    <pin index="19" name="RA0/AN0/C1IN+/ICSPDAT/ULPWU"  />
+    <pin index="20" name="VSS"                          />
+  </package>
+
+  <package types="qfn"            nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F716.xml b/src/devices/pic/xml_data/16F716.xml
new file mode 100644
index 0000000..8ebaa00
--- /dev/null
+++ b/src/devices/pic/xml_data/16F716.xml
@@ -0,0 +1,119 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F716" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1140"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010216" datasheet="41206" progsheet="40245" erratas="80184" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x18CF" cchecksum="0xE49D" />
+    <checksum protected="All"     bchecksum="0x199E" cchecksum="0xE56C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="10" vdd_min="3" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="11"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x20CF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BOREN_OFF" ecnames="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BOREN_ON"  ecnames="_BODEN_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0080" >
+      <value value="0x0000" name="2.5" cname="_VBOR_25" />
+      <value value="0x0080" name="4.0" cname="_VBOR_40" />
+    </mask>
+    <mask name="CP"    value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ON"  ecnames="_CP_ALL" />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2"         />
+    <pin index="2"  name="RA3/AN3/VREF"    />
+    <pin index="3"  name="RA4/T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"        />
+    <pin index="5"  name="VSS"             />
+    <pin index="6"  name="RB0/INT/ECCPAS2" />
+    <pin index="7"  name="RB1/T1OSO/T1CKI" />
+    <pin index="8"  name="RB2/T1OSI"       />
+    <pin index="9"  name="RB3/CCP1/P1A"    />
+    <pin index="10" name="RB4/ECCPAS0"     />
+    <pin index="11" name="RB5/P1B"         />
+    <pin index="12" name="RB6/P1C"         />
+    <pin index="13" name="RB7/P1D"         />
+    <pin index="14" name="VDD"             />
+    <pin index="15" name="OSC2/CLKOUT"     />
+    <pin index="16" name="OSC1/CLKIN"      />
+    <pin index="17" name="RA0/AN0"         />
+    <pin index="18" name="RA1/AN1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F72.xml b/src/devices/pic/xml_data/16F72.xml
new file mode 100644
index 0000000..d49b2cd
--- /dev/null
+++ b/src/devices/pic/xml_data/16F72.xml
@@ -0,0 +1,130 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F72" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x00A0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010217" datasheet="39597" progsheet="39588" erratas="80155" />
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected="Off" bchecksum="0xF85F" cchecksum="0x842D" />
+    <checksum protected="All" bchecksum="0x005E" cchecksum="0x005E" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"      min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x07FF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x000F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x005F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" ecnames="_WDTEN_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  ecnames="_WDTEN_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  ecnames="_PWRTEN_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" ecnames="_PWRTEN_OFF" />
+    </mask>
+    <mask name="CP"    value="0x0010" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x0010" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" ecnames="_BOREN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  ecnames="_BOREN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2"         />
+    <pin index="5"  name="RA3/AN3/VREF"    />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSO/T1CKI" />
+    <pin index="12" name="RC1/T1OSI"       />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6"             />
+    <pin index="18" name="RC7"             />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6/PGC"         />
+    <pin index="28" name="RB7/PGD"         />
+  </package>
+
+  <package types="qfn"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F73.xml b/src/devices/pic/xml_data/16F73.xml
new file mode 100644
index 0000000..157cb74
--- /dev/null
+++ b/src/devices/pic/xml_data/16F73.xml
@@ -0,0 +1,121 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F73" document="010218" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0600"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"      min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x000F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x005F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" ecnames="_WDTEN_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  ecnames="_WDTEN_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  ecnames="_PWRTEN_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" ecnames="_PWRTEN_OFF" />
+    </mask>
+    <mask name="CP"    value="0x0010" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x0010" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" ecnames="_BOREN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  ecnames="_BOREN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2"         />
+    <pin index="5"  name="RA3/AN3/VREF"    />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSI/T1CKI" />
+    <pin index="12" name="RC1/T1OSO/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6/PGC"         />
+    <pin index="28" name="RB7/PGD"         />
+  </package>
+
+  <package types="mlf"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F737.xml b/src/devices/pic/xml_data/16F737.xml
new file mode 100644
index 0000000..0184aa9
--- /dev/null
+++ b/src/devices/pic/xml_data/16F737.xml
@@ -0,0 +1,215 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F737" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0BA0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010219" datasheet="30498" progsheet="30492" erratas="80177" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2A42" cchecksum="0xF610" />
+    <checksum protected="All"     bchecksum="0x4484" cchecksum="0x1052" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"      min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2008" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0x3FFF" bvalue="0x39FF" >
+    <mask name="WDT"    value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE"  value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="FOSC"   value="0x0013" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"       />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"       />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"       />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK"       />
+      <value value="0x0010" name="INTRC_IO"     cname="_INTRC_IO"     />
+      <value value="0x0011" name="INTRC_CLKOUT" cname="_INTRC_CLKOUT" />
+      <value value="0x0012" name="EXTRC_IO"     cname="_EXTRC_IO"     />
+      <value value="0x0013" name="EXTRC_CLKOUT" cname="_EXTRC_CLKOUT" />
+    </mask>
+    <mask name="MCLRE"  value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLR_OFF" />
+      <value value="0x0020" name="External" cname="_MCLR_ON"  />
+    </mask>
+    <mask name="BODEN"  value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BOREN_0" />
+      <value value="0x0040" name="On"  cname="_BOREN_1" />
+    </mask>
+    <mask name="BORV"   value="0x0180" >
+      <value value="0x0000" name="4.5" cname="_VBOR_4_5" />
+      <value value="0x0080" name="4.2" cname="_VBOR_4_2" />
+      <value value="0x0100" name="2.7" cname="_VBOR_2_7" />
+      <value value="0x0180" name="2.0" cname="_VBOR_2_0" />
+    </mask>
+    <mask name="DEBUG"  value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CCP2MX" value="0x1000" >
+      <value value="0x0000" name="RB3" cname="_CCP2_RB3" />
+      <value value="0x1000" name="RC1" cname="_CCP2_RC1" />
+    </mask>
+    <mask name="CP"     value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG2" wmask="0x3FFF" bvalue="0x0043" >
+    <mask name="FCMEN"  value="0x0001" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0001" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"   value="0x0002" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0002" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="BORSEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BORSEN_0" />
+      <value value="0x0040" name="On"  cname="_BORSEN_1" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP/RE3"           />
+    <pin index="2"  name="RA0/AN0"                />
+    <pin index="3"  name="RA1/AN1"                />
+    <pin index="4"  name="RA2/AN2/VREF-/CVREF"    />
+    <pin index="5"  name="RA3/AN3/VREF+"          />
+    <pin index="6"  name="RA4/T0CKI/C1OUT"        />
+    <pin index="7"  name="RA5/SS/AN4/LVDIN/C2OUT" />
+    <pin index="8"  name="VSS"                    />
+    <pin index="9"  name="OSC1/CLKIN/RA7"         />
+    <pin index="10" name="OSC2/CLKOUT/RA6"        />
+    <pin index="11" name="RC0/T1OSI/T1CKI"        />
+    <pin index="12" name="RC1/T1OSO/CCP2"         />
+    <pin index="13" name="RC2/CCP1"               />
+    <pin index="14" name="RC3/SCK/SCL"            />
+    <pin index="15" name="RC4/SDI/SDA"            />
+    <pin index="16" name="RC5/SDO"                />
+    <pin index="17" name="RC6/TX/CK"              />
+    <pin index="18" name="RC7/RX/DT"              />
+    <pin index="19" name="VSS"                    />
+    <pin index="20" name="VDD"                    />
+    <pin index="21" name="RB0/INT/AN12"           />
+    <pin index="22" name="RB1/AN10"               />
+    <pin index="23" name="RB2/AN8"                />
+    <pin index="24" name="RB3/CCP2/AN9"           />
+    <pin index="25" name="RB4/AN11"               />
+    <pin index="26" name="RB5/AN13/CCP3"          />
+    <pin index="27" name="RB6/PGC"                />
+    <pin index="28" name="RB7/PGD"                />
+  </package>
+
+  <package types="qfn"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"            nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F74.xml b/src/devices/pic/xml_data/16F74.xml
new file mode 100644
index 0000000..fc2b312
--- /dev/null
+++ b/src/devices/pic/xml_data/16F74.xml
@@ -0,0 +1,196 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F74" document="010220" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0620"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"      min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x000F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x005F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" ecnames="_WDTEN_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  ecnames="_WDTEN_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  ecnames="_PWRTEN_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" ecnames="_PWRTEN_OFF" />
+    </mask>
+    <mask name="CP"    value="0x0010" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x0010" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" ecnames="_BOREN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  ecnames="_BOREN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F747.xml b/src/devices/pic/xml_data/16F747.xml
new file mode 100644
index 0000000..ec03640
--- /dev/null
+++ b/src/devices/pic/xml_data/16F747.xml
@@ -0,0 +1,196 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F747" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0BE0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010221" datasheet="30498" progsheet="30492" erratas="80177" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x2A42" cchecksum="0xF610" />
+    <checksum protected="All"     bchecksum="0x4484" cchecksum="0x1052" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"      min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2008" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0x3FFF" bvalue="0x39FF" >
+    <mask name="WDT"    value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE"  value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="FOSC"   value="0x0013" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"       />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"       />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"       />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK"       />
+      <value value="0x0010" name="INTRC_IO"     cname="_INTRC_IO"     />
+      <value value="0x0011" name="INTRC_CLKOUT" cname="_INTRC_CLKOUT" />
+      <value value="0x0012" name="EXTRC_IO"     cname="_EXTRC_IO"     />
+      <value value="0x0013" name="EXTRC_CLKOUT" cname="_EXTRC_CLKOUT" />
+    </mask>
+    <mask name="MCLRE"  value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLR_OFF" />
+      <value value="0x0020" name="External" cname="_MCLR_ON"  />
+    </mask>
+    <mask name="BODEN"  value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BOREN_0" />
+      <value value="0x0040" name="On"  cname="_BOREN_1" />
+    </mask>
+    <mask name="BORV"   value="0x0180" >
+      <value value="0x0000" name="4.5" cname="_VBOR_4_5" />
+      <value value="0x0080" name="4.2" cname="_VBOR_4_2" />
+      <value value="0x0100" name="2.7" cname="_VBOR_2_7" />
+      <value value="0x0180" name="2.0" cname="_VBOR_2_0" />
+    </mask>
+    <mask name="DEBUG"  value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CCP2MX" value="0x1000" >
+      <value value="0x0000" name="RB3" cname="_CCP2_RB3" />
+      <value value="0x1000" name="RC1" cname="_CCP2_RC1" />
+    </mask>
+    <mask name="CP"     value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG2" wmask="0x3FFF" bvalue="0x0043" >
+    <mask name="FCMEN"  value="0x0001" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0001" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"   value="0x0002" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0002" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="BORSEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BORSEN_0" />
+      <value value="0x0040" name="On"  cname="_BORSEN_1" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="MCLR/VPP/RE3"           />
+    <pin index="2"  name="RA0/AN0"                />
+    <pin index="3"  name="RA1/AN1"                />
+    <pin index="4"  name="RA2/AN2/VREF-/CVREF"    />
+    <pin index="5"  name="RA3/AN3/VREF+"          />
+    <pin index="6"  name="RA4/T0CKI/C1OUT"        />
+    <pin index="7"  name="RA5/SS/AN4/LVDIN/C2OUT" />
+    <pin index="8"  name="RE0/RD/AN5"             />
+    <pin index="9"  name="RE1/WR/AN6"             />
+    <pin index="10" name="RE2/CS/AN7"             />
+    <pin index="11" name="VDD"                    />
+    <pin index="12" name="VSS"                    />
+    <pin index="13" name="OSC1/CLKIN/RA7"         />
+    <pin index="14" name="OSC2/CLKOUT/RA6"        />
+    <pin index="15" name="RC0/T1OSO/T1CKI"        />
+    <pin index="16" name="RC1/T1OSI/CCP2"         />
+    <pin index="17" name="RC2/CCP1"               />
+    <pin index="18" name="RC3/SCK/SCL"            />
+    <pin index="19" name="RD0/PSP0"               />
+    <pin index="20" name="RD1/PSP1"               />
+    <pin index="21" name="RD2/PSP2"               />
+    <pin index="22" name="RD3/PSP3"               />
+    <pin index="23" name="RC4/SDI/SDA"            />
+    <pin index="24" name="RC5/SDO"                />
+    <pin index="25" name="RC6/TX/CK"              />
+    <pin index="26" name="RC7/RX/DT"              />
+    <pin index="27" name="RD4/PSP4"               />
+    <pin index="28" name="RD5/PSP5"               />
+    <pin index="29" name="RD6/PSP6"               />
+    <pin index="30" name="RD7/PSP7"               />
+    <pin index="31" name="VSS"                    />
+    <pin index="32" name="VDD"                    />
+    <pin index="33" name="RB0/INT/AN12"           />
+    <pin index="34" name="RB1/AN10"               />
+    <pin index="35" name="RB2/AN8"                />
+    <pin index="36" name="RB3/CCP2/AN9"           />
+    <pin index="37" name="RB4/AN11"               />
+    <pin index="38" name="RB5/AN13/CCP3"          />
+    <pin index="39" name="RB6/PGC"                />
+    <pin index="40" name="RB7/PGD"                />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F76.xml b/src/devices/pic/xml_data/16F76.xml
new file mode 100644
index 0000000..3b6fcf3
--- /dev/null
+++ b/src/devices/pic/xml_data/16F76.xml
@@ -0,0 +1,121 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F76" document="010222" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0640"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"      min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x1FFF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x000F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x005F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" ecnames="_WDTEN_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  ecnames="_WDTEN_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  ecnames="_PWRTEN_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" ecnames="_PWRTEN_OFF" />
+    </mask>
+    <mask name="CP"    value="0x0010" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x0010" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" ecnames="_BOREN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  ecnames="_BOREN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2"         />
+    <pin index="5"  name="RA3/AN3/VREF"    />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSI/T1CKI" />
+    <pin index="12" name="RC1/T1OSO/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3"             />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6/PGC"         />
+    <pin index="28" name="RB7/PGD"         />
+  </package>
+
+  <package types="mlf"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F767.xml b/src/devices/pic/xml_data/16F767.xml
new file mode 100644
index 0000000..77ed134
--- /dev/null
+++ b/src/devices/pic/xml_data/16F767.xml
@@ -0,0 +1,215 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F767" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0EA0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010223" datasheet="30498" progsheet="30492" erratas="80177" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x1A42" cchecksum="0xE610" />
+    <checksum protected="All"     bchecksum="0x3484" cchecksum="0x0052" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"      min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x1FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2008" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0x3FFF" bvalue="0x39FF" >
+    <mask name="WDT"    value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE"  value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="FOSC"   value="0x0013" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"       />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"       />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"       />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK"       />
+      <value value="0x0010" name="INTRC_IO"     cname="_INTRC_IO"     />
+      <value value="0x0011" name="INTRC_CLKOUT" cname="_INTRC_CLKOUT" />
+      <value value="0x0012" name="EXTRC_IO"     cname="_EXTRC_IO"     />
+      <value value="0x0013" name="EXTRC_CLKOUT" cname="_EXTRC_CLKOUT" />
+    </mask>
+    <mask name="MCLRE"  value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLR_OFF" />
+      <value value="0x0020" name="External" cname="_MCLR_ON"  />
+    </mask>
+    <mask name="BODEN"  value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BOREN_0" />
+      <value value="0x0040" name="On"  cname="_BOREN_1" />
+    </mask>
+    <mask name="BORV"   value="0x0180" >
+      <value value="0x0000" name="4.5" cname="_VBOR_4_5" />
+      <value value="0x0080" name="4.2" cname="_VBOR_4_2" />
+      <value value="0x0100" name="2.7" cname="_VBOR_2_7" />
+      <value value="0x0180" name="2.0" cname="_VBOR_2_0" />
+    </mask>
+    <mask name="DEBUG"  value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CCP2MX" value="0x1000" >
+      <value value="0x0000" name="RB3" cname="_CCP2_RB3" />
+      <value value="0x1000" name="RC1" cname="_CCP2_RC1" />
+    </mask>
+    <mask name="CP"     value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG2" wmask="0x3FFF" bvalue="0x0043" >
+    <mask name="FCMEN"  value="0x0001" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0001" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"   value="0x0002" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0002" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="BORSEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BORSEN_0" />
+      <value value="0x0040" name="On"  cname="_BORSEN_1" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP/RE3"           />
+    <pin index="2"  name="RA0/AN0"                />
+    <pin index="3"  name="RA1/AN1"                />
+    <pin index="4"  name="RA2/AN2/VREF-/CVREF"    />
+    <pin index="5"  name="RA3/AN3/VREF+"          />
+    <pin index="6"  name="RA4/T0CKI/C1OUT"        />
+    <pin index="7"  name="RA5/SS/AN4/LVDIN/C2OUT" />
+    <pin index="8"  name="VSS"                    />
+    <pin index="9"  name="OSC1/CLKIN/RA7"         />
+    <pin index="10" name="OSC2/CLKOUT/RA6"        />
+    <pin index="11" name="RC0/T1OSI/T1CKI"        />
+    <pin index="12" name="RC1/T1OSO/CCP2"         />
+    <pin index="13" name="RC2/CCP1"               />
+    <pin index="14" name="RC3/SCK/SCL"            />
+    <pin index="15" name="RC4/SDI/SDA"            />
+    <pin index="16" name="RC5/SDO"                />
+    <pin index="17" name="RC6/TX/CK"              />
+    <pin index="18" name="RC7/RX/DT"              />
+    <pin index="19" name="VSS"                    />
+    <pin index="20" name="VDD"                    />
+    <pin index="21" name="RB0/INT/AN12"           />
+    <pin index="22" name="RB1/AN10"               />
+    <pin index="23" name="RB2/AN8"                />
+    <pin index="24" name="RB3/CCP2/AN9"           />
+    <pin index="25" name="RB4/AN11"               />
+    <pin index="26" name="RB5/AN13/CCP3"          />
+    <pin index="27" name="RB6/PGC"                />
+    <pin index="28" name="RB7/PGD"                />
+  </package>
+
+  <package types="qfn"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"            nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F77.xml b/src/devices/pic/xml_data/16F77.xml
new file mode 100644
index 0000000..e02e2cb
--- /dev/null
+++ b/src/devices/pic/xml_data/16F77.xml
@@ -0,0 +1,196 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F77" document="010224" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0660"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"      min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x1FFF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x000F" />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x005F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" ecnames="_WDTEN_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  ecnames="_WDTEN_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  ecnames="_PWRTEN_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" ecnames="_PWRTEN_OFF" />
+    </mask>
+    <mask name="CP"    value="0x0010" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x0010" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" ecnames="_BOREN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  ecnames="_BOREN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F777.xml b/src/devices/pic/xml_data/16F777.xml
new file mode 100644
index 0000000..71899b2
--- /dev/null
+++ b/src/devices/pic/xml_data/16F777.xml
@@ -0,0 +1,196 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F777" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0DE0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010225" datasheet="30498" progsheet="30492" erratas="80177" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"     bchecksum="0x1A42" cchecksum="0xE610" />
+    <checksum protected="All"     bchecksum="0x3484" cchecksum="0x0052" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"      min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x1FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2008" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0x3FFF" bvalue="0x39FF" >
+    <mask name="WDT"    value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE"  value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="FOSC"   value="0x0013" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"       />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"       />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"       />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK"       />
+      <value value="0x0010" name="INTRC_IO"     cname="_INTRC_IO"     />
+      <value value="0x0011" name="INTRC_CLKOUT" cname="_INTRC_CLKOUT" />
+      <value value="0x0012" name="EXTRC_IO"     cname="_EXTRC_IO"     />
+      <value value="0x0013" name="EXTRC_CLKOUT" cname="_EXTRC_CLKOUT" />
+    </mask>
+    <mask name="MCLRE"  value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLR_OFF" />
+      <value value="0x0020" name="External" cname="_MCLR_ON"  />
+    </mask>
+    <mask name="BODEN"  value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BOREN_0" />
+      <value value="0x0040" name="On"  cname="_BOREN_1" />
+    </mask>
+    <mask name="BORV"   value="0x0180" >
+      <value value="0x0000" name="4.5" cname="_VBOR_4_5" />
+      <value value="0x0080" name="4.2" cname="_VBOR_4_2" />
+      <value value="0x0100" name="2.7" cname="_VBOR_2_7" />
+      <value value="0x0180" name="2.0" cname="_VBOR_2_0" />
+    </mask>
+    <mask name="DEBUG"  value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CCP2MX" value="0x1000" >
+      <value value="0x0000" name="RB3" cname="_CCP2_RB3" />
+      <value value="0x1000" name="RC1" cname="_CCP2_RC1" />
+    </mask>
+    <mask name="CP"     value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG2" wmask="0x3FFF" bvalue="0x0043" >
+    <mask name="FCMEN"  value="0x0001" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0001" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"   value="0x0002" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0002" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="BORSEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BORSEN_0" />
+      <value value="0x0040" name="On"  cname="_BORSEN_1" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="MCLR/VPP/RE3"           />
+    <pin index="2"  name="RA0/AN0"                />
+    <pin index="3"  name="RA1/AN1"                />
+    <pin index="4"  name="RA2/AN2/VREF-/CVREF"    />
+    <pin index="5"  name="RA3/AN3/VREF+"          />
+    <pin index="6"  name="RA4/T0CKI/C1OUT"        />
+    <pin index="7"  name="RA5/SS/AN4/LVDIN/C2OUT" />
+    <pin index="8"  name="RE0/RD/AN5"             />
+    <pin index="9"  name="RE1/WR/AN6"             />
+    <pin index="10" name="RE2/CS/AN7"             />
+    <pin index="11" name="VDD"                    />
+    <pin index="12" name="VSS"                    />
+    <pin index="13" name="OSC1/CLKIN/RA7"         />
+    <pin index="14" name="OSC2/CLKOUT/RA6"        />
+    <pin index="15" name="RC0/T1OSO/T1CKI"        />
+    <pin index="16" name="RC1/T1OSI/CCP2"         />
+    <pin index="17" name="RC2/CCP1"               />
+    <pin index="18" name="RC3/SCK/SCL"            />
+    <pin index="19" name="RD0/PSP0"               />
+    <pin index="20" name="RD1/PSP1"               />
+    <pin index="21" name="RD2/PSP2"               />
+    <pin index="22" name="RD3/PSP3"               />
+    <pin index="23" name="RC4/SDI/SDA"            />
+    <pin index="24" name="RC5/SDO"                />
+    <pin index="25" name="RC6/TX/CK"              />
+    <pin index="26" name="RC7/RX/DT"              />
+    <pin index="27" name="RD4/PSP4"               />
+    <pin index="28" name="RD5/PSP5"               />
+    <pin index="29" name="RD6/PSP6"               />
+    <pin index="30" name="RD7/PSP7"               />
+    <pin index="31" name="VSS"                    />
+    <pin index="32" name="VDD"                    />
+    <pin index="33" name="RB0/INT/AN12"           />
+    <pin index="34" name="RB1/AN10"               />
+    <pin index="35" name="RB2/AN8"                />
+    <pin index="36" name="RB3/CCP2/AN9"           />
+    <pin index="37" name="RB4/AN11"               />
+    <pin index="38" name="RB5/AN13/CCP3"          />
+    <pin index="39" name="RB6/PGC"                />
+    <pin index="40" name="RB7/PGD"                />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F785.xml b/src/devices/pic/xml_data/16F785.xml
new file mode 100644
index 0000000..80c9091
--- /dev/null
+++ b/src/devices/pic/xml_data/16F785.xml
@@ -0,0 +1,120 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F785" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1200" id_high_voltage="0x1220"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="020257" datasheet="41249" progsheet="41237" erratas="80234" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"                  bchecksum="0x07FF" cchecksum="0xD3CD" />
+    <checksum protected="All" mprotected="CPD" bchecksum="0x173E" cchecksum="0xE30C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended" special="high_voltage">
+    <frequency start="0"  end="8"  vdd_min="2"   vdd_max="5.0" />
+    <frequency start="8"  end="10" vdd_min="3"   vdd_max="5.0" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.0" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="12"  nominal="11" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="calibration"  start="0x2008" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x0FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOR_OFF"    ecnames="_BOD_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOR_SBOREN" ecnames="_BOD_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOR_NSLEEP" ecnames="_BOD_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOR_ON"     ecnames="_BOD_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="20" >
+    <pin index="1"  name="VDD"                          />
+    <pin index="2"  name="RA5/T1CKI/OSC1/CLKIN"         />
+    <pin index="3"  name="RA4/AN3/T1G/OSC2/CLKOUT"      />
+    <pin index="4"  name="RA3/MCLR/VPP"                 />
+    <pin index="5"  name="RC5/CPP1"                     />
+    <pin index="6"  name="RC4/C2OUT/PH2"                />
+    <pin index="7"  name="RC3/AN7/C12IN3-/OP1"          />
+    <pin index="8"  name="RC6/AN8/OP1-"                 />
+    <pin index="9"  name="RC7/AN9/OP1+"                 />
+    <pin index="10" name="RB7/SYNC"                     />
+    <pin index="11" name="RB6"                          />
+    <pin index="12" name="RB5/AN11/OP2+"                />
+    <pin index="13" name="RB4/AN10/OP2-"                />
+    <pin index="14" name="RC2/AN6/C12IN2-/OP2"          />
+    <pin index="15" name="RC1/AN5/C12IN1-/PH1"          />
+    <pin index="16" name="RC0/AN4/C12IN+"               />
+    <pin index="17" name="RA2/AN2/C1OUT/T0CKI/INT"      />
+    <pin index="18" name="RA1/AN1/C12IN0-/VREF/ICSPCLK" />
+    <pin index="19" name="RA0/AN0/C1IN+/ICSPDAT"        />
+    <pin index="20" name="VSS"                          />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F818.xml b/src/devices/pic/xml_data/16F818.xml
new file mode 100644
index 0000000..0ff73b5
--- /dev/null
+++ b/src/devices/pic/xml_data/16F818.xml
@@ -0,0 +1,176 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F818" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x04C0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010226" datasheet="39598" progsheet="39603" erratas="80159 80212" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x3BFF" cchecksum="0x07CD" />
+    <checksum protected="All" bchecksum="0x5BFE" cchecksum="0x27CC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x03FF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="WDT"    value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE"  value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="FOSC"   value="0x0013" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"       />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"       />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"       />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK"       />
+      <value value="0x0010" name="INTRC_IO"     cname="_INTRC_IO"     />
+      <value value="0x0011" name="INTRC_CLKOUT" cname="_INTRC_CLKOUT" />
+      <value value="0x0012" name="EXTRC_IO"     cname="_EXTRC_IO"     />
+      <value value="0x0013" name="EXTRC_CLKOUT" cname="_EXTRC_CLKOUT" />
+    </mask>
+    <mask name="MCLRE"  value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLR_OFF" />
+      <value value="0x0020" name="External" cname="_MCLR_ON"  />
+    </mask>
+    <mask name="BODEN"  value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"    value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"    value="0x0600" >
+      <value value="0x0000" name="invalid" />
+      <value value="0x0200" name="000:3FF" cname="_WRT_ENABLE_1024" />
+      <value value="0x0400" name="000:1FF" cname="_WRT_ENABLE_512"  />
+      <value value="0x0600" name="Off"     cname="_WRT_ENABLE_OFF"  />
+    </mask>
+    <mask name="DEBUG"  value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CCP1MX" value="0x1000" >
+      <value value="0x0000" name="RB3" cname="_CCP1_RB3" />
+      <value value="0x1000" name="RB2" cname="_CCP1_RB2" />
+    </mask>
+    <mask name="CP"     value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2/VREF-"       />
+    <pin index="2"  name="RA3/AN3/VREF+"       />
+    <pin index="3"  name="RA4/AN4/T0CKI"       />
+    <pin index="4"  name="RA5/MCLR/VPP"        />
+    <pin index="5"  name="VSS"                 />
+    <pin index="6"  name="RB0/INT"             />
+    <pin index="7"  name="RB1/SDI/SDA"         />
+    <pin index="8"  name="RB2/SDO/CCP1"        />
+    <pin index="9"  name="RB3/CCP1/PGM"        />
+    <pin index="10" name="RB4/SCK/SCL"         />
+    <pin index="11" name="RB5/SS"              />
+    <pin index="12" name="RB6/T1OSO/T1CKI/PGC" />
+    <pin index="13" name="RB7/T1OSI/PGD"       />
+    <pin index="14" name="VDD"                 />
+    <pin index="15" name="RA6/OSC2/CLKOUT"     />
+    <pin index="16" name="RA7/OSC1/CLKIN"      />
+    <pin index="17" name="RA0/AN0"             />
+    <pin index="18" name="RA1/AN1"             />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F819.xml b/src/devices/pic/xml_data/16F819.xml
new file mode 100644
index 0000000..e7ee0a6
--- /dev/null
+++ b/src/devices/pic/xml_data/16F819.xml
@@ -0,0 +1,176 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F819" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x04E0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010227" datasheet="39598" progsheet="39603" erratas="80159 80212" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x37FF" cchecksum="0x03CD" />
+    <checksum protected="All" bchecksum="0x57FE" cchecksum="0x23CC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="WDT"    value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE"  value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="FOSC"   value="0x0013" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"       />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"       />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"       />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK"       />
+      <value value="0x0010" name="INTRC_IO"     cname="_INTRC_IO"     />
+      <value value="0x0011" name="INTRC_CLKOUT" cname="_INTRC_CLKOUT" />
+      <value value="0x0012" name="EXTRC_IO"     cname="_EXTRC_IO"     />
+      <value value="0x0013" name="EXTRC_CLKOUT" cname="_EXTRC_CLKOUT" />
+    </mask>
+    <mask name="MCLRE"  value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLR_OFF" />
+      <value value="0x0020" name="External" cname="_MCLR_ON"  />
+    </mask>
+    <mask name="BODEN"  value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"    value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"    value="0x0600" >
+      <value value="0x0000" name="000:5FF" cname="_WRT_ENABLE_1536" />
+      <value value="0x0200" name="000:3FF" cname="_WRT_ENABLE_1024" />
+      <value value="0x0400" name="000:1FF" cname="_WRT_ENABLE_512"  />
+      <value value="0x0600" name="Off"     cname="_WRT_ENABLE_OFF"  />
+    </mask>
+    <mask name="DEBUG"  value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CCP1MX" value="0x1000" >
+      <value value="0x0000" name="RB3" cname="_CCP1_RB3" />
+      <value value="0x1000" name="RB2" cname="_CCP1_RB2" />
+    </mask>
+    <mask name="CP"     value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2/VREF-"       />
+    <pin index="2"  name="RA3/AN3/VREF+"       />
+    <pin index="3"  name="RA4/AN4/T0CKI"       />
+    <pin index="4"  name="RA5/MCLR/VPP"        />
+    <pin index="5"  name="VSS"                 />
+    <pin index="6"  name="RB0/INT"             />
+    <pin index="7"  name="RB1/SDI/SDA"         />
+    <pin index="8"  name="RB2/SDO/CCP1"        />
+    <pin index="9"  name="RB3/CCP1/PGM"        />
+    <pin index="10" name="RB4/SCK/SCL"         />
+    <pin index="11" name="RB5/SS"              />
+    <pin index="12" name="RB6/T1OSO/T1CKI/PGC" />
+    <pin index="13" name="RB7/T1OSI/PGD"       />
+    <pin index="14" name="VDD"                 />
+    <pin index="15" name="RA6/OSC2/CLKOUT"     />
+    <pin index="16" name="RA7/OSC1/CLKIN"      />
+    <pin index="17" name="RA0/AN0"             />
+    <pin index="18" name="RA1/AN1"             />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F83.xml b/src/devices/pic/xml_data/16F83.xml
new file mode 100644
index 0000000..25b80a3
--- /dev/null
+++ b/src/devices/pic/xml_data/16F83.xml
@@ -0,0 +1,106 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F83" document="010228" status="NR" alternative="16F84A" memory_technology="FLASH" self_write="no" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x3DFF" cchecksum="0x09CD" />
+    <checksum protected="All" bchecksum="0x3E0E" cchecksum="0x09DC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="10" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="2" vdd_min="2" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12"  max="14"  nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x01FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="config"   start="0x2007" end="0x2007" />
+  <memory name="eeprom"   start="0x0000" end="0x003F" hexfile_offset="0x2100" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3FF0" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x3FF0" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="RA4/T0CKI"   />
+    <pin index="4"  name="MCLR"        />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0/INT"     />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F84.xml b/src/devices/pic/xml_data/16F84.xml
new file mode 100644
index 0000000..62c1f8d
--- /dev/null
+++ b/src/devices/pic/xml_data/16F84.xml
@@ -0,0 +1,106 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F84" document="010229" status="NR" alternative="16F84A" memory_technology="FLASH" self_write="no" architecture="16X"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x3BFF" cchecksum="0x07CD" />
+    <checksum protected="All" bchecksum="0x3C0E" cchecksum="0x07DC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="6"   />
+    <frequency start="4" end="10" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="2" vdd_min="2" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12"  max="14"  nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x0000" end="0x03FF" />
+  <memory name="user_ids" start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="config"   start="0x2007" end="0x2007" />
+  <memory name="eeprom"   start="0x0000" end="0x003F" hexfile_offset="0x2100" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3FF0" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x3FF0" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="RA4/T0CKI"   />
+    <pin index="4"  name="MCLR"        />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0/INT"     />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F84A.xml b/src/devices/pic/xml_data/16F84A.xml
new file mode 100644
index 0000000..ffffba1
--- /dev/null
+++ b/src/devices/pic/xml_data/16F84A.xml
@@ -0,0 +1,108 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F84A" document="010230" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0560"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x3BFF" cchecksum="0x07CD" />
+    <checksum protected="All" bchecksum="0x3C0E" cchecksum="0x07DC" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0" end="4"  vdd_min="4"   vdd_max="5.5" />
+    <frequency start="4" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12"  max="14"  nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x0000" end="0x03FF" />
+  <memory name="user_ids"  start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id" start="0x2006" end="0x2006" />
+  <memory name="config"    start="0x2007" end="0x2007" />
+  <memory name="eeprom"    start="0x0000" end="0x003F" hexfile_offset="0x2100" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3FF0" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x3FF0" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="RA4/T0CKI"   />
+    <pin index="4"  name="MCLR"        />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0/INT"     />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F87.xml b/src/devices/pic/xml_data/16F87.xml
new file mode 100644
index 0000000..835b481
--- /dev/null
+++ b/src/devices/pic/xml_data/16F87.xml
@@ -0,0 +1,186 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F87" status="IP" memory_technology="FLASH" self_write="yes" architecture="16X" id="0x0720"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010231" datasheet="30488" progsheet="39607" erratas="80171 80301" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x3002" cchecksum="0xFBD0" />
+    <checksum protected="All" bchecksum="0x5004" cchecksum="0x1BD2" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"      min="4.5" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2008" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="WDT"    value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE"  value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="FOSC"   value="0x0013" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"       />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"       />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"       />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK"       />
+      <value value="0x0010" name="INTRC_IO"     cname="_INTRC_IO"     />
+      <value value="0x0011" name="INTRC_CLKOUT" cname="_INTRC_CLKOUT" />
+      <value value="0x0012" name="EXTRC_IO"     cname="_EXTRC_IO"     />
+      <value value="0x0013" name="EXTRC_CLKOUT" cname="_EXTRC_CLKOUT" />
+    </mask>
+    <mask name="MCLRE"  value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLR_OFF" />
+      <value value="0x0020" name="External" cname="_MCLR_ON"  />
+    </mask>
+    <mask name="BODEN"  value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"    value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"    value="0x0600" >
+      <value value="0x0000" name="All"     cname="_WRT_PROTECT_ALL"  />
+      <value value="0x0200" name="000:7FF" cname="_WRT_PROTECT_2048" />
+      <value value="0x0400" name="000:0FF" cname="_WRT_PROTECT_256"  />
+      <value value="0x0600" name="Off"     cname="_WRT_PROTECT_OFF"  />
+    </mask>
+    <mask name="DEBUG"  value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CCP1MX" value="0x1000" >
+      <value value="0x0000" name="RB3" cname="_CCP1_RB3" />
+      <value value="0x1000" name="RB0" cname="_CCP1_RB0" />
+    </mask>
+    <mask name="CP"     value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG2" wmask="0x3FFF" bvalue="0x0003" >
+    <mask name="FCMEN" value="0x0001" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0001" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x0002" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0002" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2/VREF-/CVREF"     />
+    <pin index="2"  name="RA3/AN3/VREF+/C1OUT"     />
+    <pin index="3"  name="RA4/AN4/T0CKI/C2OUT"     />
+    <pin index="4"  name="RA5/MCLR/VPP"            />
+    <pin index="5"  name="VSS"                     />
+    <pin index="6"  name="RB0/INT/CCP1"            />
+    <pin index="7"  name="RB1/SDI/SDA"             />
+    <pin index="8"  name="RB2/SDO/CCP1"            />
+    <pin index="9"  name="RB3/CCP1/PGM"            />
+    <pin index="10" name="RB4/SCK/SCL"             />
+    <pin index="11" name="RB5/SS/TX/CK"            />
+    <pin index="12" name="RB6/AN5/T1OSO/T1CKI/PGC" />
+    <pin index="13" name="RB7/AN6/T1OSI/PGD"       />
+    <pin index="14" name="VDD"                     />
+    <pin index="15" name="RA6/OSC2/CLKOUT"         />
+    <pin index="16" name="RA7/OSC1/CLKIN"          />
+    <pin index="17" name="RA0/AN0"                 />
+    <pin index="18" name="RA1/AN1"                 />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F870.xml b/src/devices/pic/xml_data/16F870.xml
new file mode 100644
index 0000000..ec66b54
--- /dev/null
+++ b/src/devices/pic/xml_data/16F870.xml
@@ -0,0 +1,120 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F870" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0D00"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010232" datasheet="30569" progsheet="39025" erratas="80077" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x33FF" cchecksum="0xFFCD" />
+    <checksum protected="All" bchecksum="0x3FCE" cchecksum="0x0B9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="2" vdd_max="5.5" vdd_min_end="3" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.2" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x003F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3BFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"   value="0x0200" >
+      <value value="0x0000" name="Off" cname="_WRT_ENABLE_OFF" />
+      <value value="0x0200" name="All" cname="_WRT_ENABLE_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3030" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x3030" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP/THV"    />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2/VREF-"   />
+    <pin index="5"  name="RA3/AN3/VREF+"   />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/AN4"         />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSO/T1CKI" />
+    <pin index="12" name="RC1/T1OSI"       />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3"             />
+    <pin index="15" name="RC4"             />
+    <pin index="16" name="RC5"             />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3/PGM"         />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6/PGC"         />
+    <pin index="28" name="RB7/PGD"         />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F871.xml b/src/devices/pic/xml_data/16F871.xml
new file mode 100644
index 0000000..8b918ca
--- /dev/null
+++ b/src/devices/pic/xml_data/16F871.xml
@@ -0,0 +1,226 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F871" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0D20"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010233" datasheet="30569" progsheet="39025" erratas="80077" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x33FF" cchecksum="0xFFCD" />
+    <checksum protected="All" bchecksum="0x3FCE" cchecksum="0x0B9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="2" vdd_max="5.5" vdd_min_end="3" />
+    <frequency start="10" end="20" vdd_min="3" vdd_max="5.5" vdd_min_end="4" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.2" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x003F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3BFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"   value="0x0200" >
+      <value value="0x0000" name="Off" cname="_WRT_ENABLE_OFF" />
+      <value value="0x0200" name="All" cname="_WRT_ENABLE_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3030" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x3030" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F872.xml b/src/devices/pic/xml_data/16F872.xml
new file mode 100644
index 0000000..7702922
--- /dev/null
+++ b/src/devices/pic/xml_data/16F872.xml
@@ -0,0 +1,120 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F872" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x08E0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010234" datasheet="30221" progsheet="39025" erratas="80070 80076" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x33FF" cchecksum="0xFFCD" />
+    <checksum protected="All" bchecksum="0x3FCE" cchecksum="0x0B9C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2.2" vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="2.2" vdd_max="5.5" vdd_min_end="3" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" vdd_min_end="4" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.2" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x003F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3BFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"   value="0x0200" >
+      <value value="0x0000" name="Off" cname="_WRT_ENABLE_OFF" />
+      <value value="0x0200" name="All" cname="_WRT_ENABLE_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3030" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x3030" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2/VREF-"   />
+    <pin index="5"  name="RA3/AN3/VREF+"   />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSO/T1CKI" />
+    <pin index="12" name="RC1/T1OSI/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3/PGM"         />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6/PGC"         />
+    <pin index="28" name="RB7/PGD"         />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F873.xml b/src/devices/pic/xml_data/16F873.xml
new file mode 100644
index 0000000..4bbb1cb
--- /dev/null
+++ b/src/devices/pic/xml_data/16F873.xml
@@ -0,0 +1,127 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F873" status="NR" alternative="16F873A" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0960"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010235" datasheet="30292" progsheet="39025" erratas="80053 80052 80051" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"       bchecksum="0x2BFF" cchecksum="0xF7CD" />
+    <checksum protected="0F00:0FFF" bchecksum="0x48EE" cchecksum="0xFAA3" />
+    <checksum protected="0800:0FFF" bchecksum="0x3FDE" cchecksum="0xF193" />
+    <checksum protected="All"       bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="16" vdd_min="4"   vdd_max="5.5" />
+    <frequency start="16" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="10" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.2" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3BFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"   value="0x0200" >
+      <value value="0x0000" name="Off" cname="_WRT_ENABLE_OFF" />
+      <value value="0x0200" name="All" cname="_WRT_ENABLE_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3030" >
+      <value value="0x0000" name="All"       cname="_CP_ALL"       />
+      <value value="0x1010" name="0800:0FFF" cname="_CP_HALF"      />
+      <value value="0x2020" name="0F00:0FFF" cname="_CP_UPPER_256" />
+      <value value="0x3030" name="Off"       cname="_CP_OFF"       />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2/VREF-"   />
+    <pin index="5"  name="RA3/AN3/VREF+"   />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSO/T1CKI" />
+    <pin index="12" name="RC1/T1OSI/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3/PGM"         />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6/PGC"         />
+    <pin index="28" name="RB7/PGD"         />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F873A.xml b/src/devices/pic/xml_data/16F873A.xml
new file mode 100644
index 0000000..ee26828
--- /dev/null
+++ b/src/devices/pic/xml_data/16F873A.xml
@@ -0,0 +1,151 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F873A" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0E40"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010236" datasheet="39582" progsheet="39589" erratas="80128 80133 80240 80276" />
+
+<!--* Checksums ************************************************************-->
+<!-- <checksums>
+    <checksum protected="Off" bchecksum="0x1FCF" cchecksum="0xEB9D" />
+    <checksum protected="All" bchecksum="0x4F9E" cchecksum="0x1B6C" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.2" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F" />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x2FCF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"   value="0x0600" >
+      <value value="0x0000" name="0000:07FF" cname="_WRT_HALF"    />
+      <value value="0x0200" name="0000:03FF" cname="_WRT_1FOURTH" />
+      <value value="0x0400" name="0000:00FF" cname="_WRT_256"     />
+      <value value="0x0600" name="Off"       cname="_WRT_OFF"     />
+    </mask>
+    <mask name="DEBUG" value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CP"    value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"            />
+    <pin index="2"  name="RA0/AN0"             />
+    <pin index="3"  name="RA1/AN1"             />
+    <pin index="4"  name="RA2/AN2/VREF-/CVREF" />
+    <pin index="5"  name="RA3/AN3/VREF+"       />
+    <pin index="6"  name="RA4/T0CKI/C1OUT"     />
+    <pin index="7"  name="RA5/SS/AN4/C2OUT"    />
+    <pin index="8"  name="VSS"                 />
+    <pin index="9"  name="OSC1/CLKIN"          />
+    <pin index="10" name="OSC2/CLKOUT"         />
+    <pin index="11" name="RC0/T1OSO/T1CKI"     />
+    <pin index="12" name="RC1/T1OSI/CCP2"      />
+    <pin index="13" name="RC2/CCP1"            />
+    <pin index="14" name="RC3/SCK/SCL"         />
+    <pin index="15" name="RC4/SDI/SDA"         />
+    <pin index="16" name="RC5/SDO"             />
+    <pin index="17" name="RC6/TX/CK"           />
+    <pin index="18" name="RC7/RX/DT"           />
+    <pin index="19" name="VSS"                 />
+    <pin index="20" name="VDD"                 />
+    <pin index="21" name="RB0/INT"             />
+    <pin index="22" name="RB1"                 />
+    <pin index="23" name="RB2"                 />
+    <pin index="24" name="RB3/PGM"             />
+    <pin index="25" name="RB4"                 />
+    <pin index="26" name="RB5"                 />
+    <pin index="27" name="RB6/PGC"             />
+    <pin index="28" name="RB7/PGD"             />
+  </package>
+
+  <package types="qfn"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F874.xml b/src/devices/pic/xml_data/16F874.xml
new file mode 100644
index 0000000..fe20128
--- /dev/null
+++ b/src/devices/pic/xml_data/16F874.xml
@@ -0,0 +1,233 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F874" status="NR" alternative="16F874A" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0920"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010237" datasheet="30292" progsheet="39025" erratas="80053 80052 80051" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"       bchecksum="0x2BFF" cchecksum="0xF7CD" />
+    <checksum protected="0F00:0FFF" bchecksum="0x48EE" cchecksum="0xFAA3" />
+    <checksum protected="0800:0FFF" bchecksum="0x3FDE" cchecksum="0xF193" />
+    <checksum protected="All"       bchecksum="0x37CE" cchecksum="0x039C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="16" vdd_min="4"   vdd_max="5.5" />
+    <frequency start="16" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="10" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.2" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3BFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"   value="0x0200" >
+      <value value="0x0000" name="Off" cname="_WRT_ENABLE_OFF" />
+      <value value="0x0200" name="All" cname="_WRT_ENABLE_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3030" >
+      <value value="0x0000" name="All"       cname="_CP_ALL"       />
+      <value value="0x1010" name="0800:0FFF" cname="_CP_HALF"      />
+      <value value="0x2020" name="0F00:0FFF" cname="_CP_UPPER_256" />
+      <value value="0x3030" name="Off"       cname="_CP_OFF"       />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+<package types="pdip"      nb_pins="40" >
+	<pin index="1"  name="MCLR/VPP"			/>
+	<pin index="2"  name="RA0/AN0"			/>
+	<pin index="3"  name="RA1/AN1"			/>
+	<pin index="4"  name="RA2/AN2/VREF-"		/>
+	<pin index="5"  name="RA3/AN3/VREF+"		/>
+	<pin index="6"  name="RA4/T0CKL"		/>
+	<pin index="7"  name="RA5/AN4/SS"		/>
+	<pin index="8"  name="RE0/RD/AN5"		/>
+	<pin index="9"  name="RE1/WR/AN6"		/>
+	<pin index="10" name="RE2/CS/AN7"		/>
+	<pin index="11" name="VDD"			/>
+	<pin index="12" name="VSS"			/>
+	<pin index="13" name="OSC1/CLKIN"		/>
+	<pin index="14" name="OSC2/CLKOUT"		/>
+	<pin index="15" name="RC0/T1OSO/T1CKL"		/>
+	<pin index="16" name="RC1/T1OSI/CCP2"		/>
+	<pin index="17" name="RC2/CCP1"			/>
+	<pin index="18" name="RC3/SCK/SCL"		/>
+	<pin index="19" name="RD0/PSP0"			/>
+	<pin index="20" name="RD1/PSP1"			/>
+	<pin index="21" name="RD2/PSP2"			/>
+	<pin index="22" name="RD3/PSP3"			/>
+	<pin index="23" name="RC4/SDI/SDA"		/>
+	<pin index="24" name="RC5/SDO"			/>
+	<pin index="25" name="RC6/TX/CK"		/>
+	<pin index="26" name="RC7/RX/DT"		/>
+	<pin index="27" name="RD4/PSP4"			/>
+	<pin index="28" name="RD5/PSP5"			/>
+	<pin index="29" name="RD6/PSP6"			/>
+	<pin index="30" name="RD7/PSP7"			/>
+	<pin index="31" name="VSS"			/>
+	<pin index="32" name="VDD"			/>
+	<pin index="33" name="RB0/INT"			/>
+	<pin index="34" name="RB1"			/>
+	<pin index="35" name="RB2"			/>
+	<pin index="36" name="RB3/PGM"			/>
+	<pin index="37" name="RB4"			/>
+	<pin index="38" name="RB5"			/>
+	<pin index="39" name="RB6/PGC"			/>
+	<pin index="40" name="RB7/PGD"			/>
+</package>
+
+<package types="plcc"      nb_pins="44" >
+	<pin index="1"  name=""				/>
+	<pin index="2"  name="MCLR/VPP"			/>
+	<pin index="3"  name="RA0/AN0"			/>
+	<pin index="4"  name="RA1/AN1"			/>
+	<pin index="5"  name="RA2/AN2/VREF-"		/>
+	<pin index="6"  name="RA3/AN3/VREF+"		/>
+	<pin index="7"  name="RA4/T0CKL"		/>
+	<pin index="8"  name="RA5/AN4/SS"		/>
+	<pin index="9"  name="RE0/RD/AN5"		/>
+	<pin index="10" name="RE1/WR/AN6"		/>
+	<pin index="11" name="RE2/CS/AN7"		/>
+	<pin index="12" name="VDD"			/>
+	<pin index="13" name="VSS"			/>
+	<pin index="14" name="OSC1/CLKIN"		/>
+	<pin index="15" name="OSC2/CLKOUT"		/>
+	<pin index="16" name="RC0/T1OSO/T1CK1"		/>
+	<pin index="17" name=""				/>
+	<pin index="18" name="RC1/T1OSI/CCP2"		/>
+	<pin index="19" name="RC2/CCP1"			/>
+	<pin index="20" name="RC3/SCK/SCL"		/>
+	<pin index="21" name="RD0/PSP0"			/>
+	<pin index="22" name="RD1/PSP1"			/>
+	<pin index="23" name="RD2/PSP2"			/>
+	<pin index="24" name="RD3/PSP3"			/>
+	<pin index="25" name="RC4/SDI/SDA"		/>
+	<pin index="26" name="RC5/SDO"			/>
+	<pin index="27" name="RC6/TX/CK"		/>
+	<pin index="28" name=""				/>
+	<pin index="29" name="RC7/RX/DT"		/>
+	<pin index="30" name="RD4/PSP4"			/>
+	<pin index="31" name="RD5/PSP5"			/>
+	<pin index="32" name="RD6/PSP6"			/>
+	<pin index="33" name="RD7/PSP7"			/>
+	<pin index="34" name="VSS"			/>
+	<pin index="35" name="VDD"			/>
+	<pin index="36" name="RB0/INT"			/>
+	<pin index="37" name="RB1"			/>
+	<pin index="38" name="RB2"			/>
+	<pin index="39" name="RB3/PGM"			/>
+	<pin index="40" name=""				/>
+	<pin index="41" name="RB4"			/>
+	<pin index="42" name="RB5"			/>
+	<pin index="43" name="RB6/PGC"			/>
+	<pin index="44" name="RB7/PGD"			/>
+</package>
+
+<package types="mqfp tqfp" nb_pins="44" >
+	<pin index="1"  name="RC7/RX/DT"		/>
+	<pin index="2"  name="RD4/PSP4"			/>
+	<pin index="3"  name="RD5/PSP5"			/>
+	<pin index="4"  name="RD6/PSP6"			/>
+	<pin index="5"  name="RD7/PSP7"			/>
+	<pin index="6"  name="VSS"			/>
+	<pin index="7"  name="VDD"			/>
+	<pin index="8"  name="RB0/INT"			/>
+	<pin index="9"  name="RB1"			/>
+	<pin index="10" name="RB2"			/>
+	<pin index="11" name="RB3/PGM"			/>
+	<pin index="12" name=""				/>
+	<pin index="13" name=""				/>
+	<pin index="14" name="RB4"			/>
+	<pin index="15" name="RB5"			/>
+	<pin index="16" name="RB6/PGC"			/>
+	<pin index="17" name="RB7/PGD"			/>
+	<pin index="18" name="MCLR/VPP"			/>
+	<pin index="19" name="RA0/AN0"			/>
+	<pin index="20" name="RA1/AN1"			/>
+	<pin index="21" name="RA2/AN2/VREF-"		/>
+	<pin index="22" name="RA3/AN3/VREF+"		/>
+	<pin index="23" name="RA4/T0CKL"		/>
+	<pin index="24" name="RA5/AN4/SS"		/>
+	<pin index="25" name="RE0/AN5/RD"		/>
+	<pin index="26" name="RE1/AN6/WR"		/>
+	<pin index="27" name="RE2/AN7/CS"		/>
+	<pin index="28" name="VDD"			/>
+	<pin index="29" name="VSS"			/>
+	<pin index="30" name="OSC1/CLKIN"		/>
+	<pin index="31" name="OSC2/CLKOUT"		/>
+	<pin index="32" name="RC0/T1OSO/T1CKL"		/>
+	<pin index="33" name=""				/>
+	<pin index="34" name=""				/>
+	<pin index="35" name="RC1/T1OSI/CCP2"		/>
+	<pin index="36" name="RC2/CCP1"			/>
+	<pin index="37" name="RC3/SCK/SCL"		/>
+	<pin index="38" name="RD0/PSP0"			/>
+	<pin index="39" name="RD1/PSP1"			/>
+	<pin index="40" name="RD2/PSP2"			/>
+	<pin index="41" name="RD3/PSP3"			/>
+	<pin index="42" name="RC4/SDI/SDA"		/>
+	<pin index="43" name="RC5/SDO"			/>
+	<pin index="44" name="RC6/TX/CK"		/>
+</package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F874A.xml b/src/devices/pic/xml_data/16F874A.xml
new file mode 100644
index 0000000..c89b407
--- /dev/null
+++ b/src/devices/pic/xml_data/16F874A.xml
@@ -0,0 +1,273 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F874A" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0E60"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010238" datasheet="39582" progsheet="39589" erratas="80128 80133 80240 80276" />
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected="Off" bchecksum="0x1FCF" cchecksum="0xEB9D" />
+    <checksum protected="All" bchecksum="0x4F9E" cchecksum="0x1B6C" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.2" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x2FCF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"   value="0x0600" >
+      <value value="0x0000" name="0000:07FF" cname="_WRT_HALF"    />
+      <value value="0x0200" name="0000:03FF" cname="_WRT_1FOURTH" />
+      <value value="0x0400" name="0000:00FF" cname="_WRT_256"     />
+      <value value="0x0600" name="Off"       cname="_WRT_OFF"     />
+    </mask>
+    <mask name="DEBUG" value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CP"    value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F876.xml b/src/devices/pic/xml_data/16F876.xml
new file mode 100644
index 0000000..19264e8
--- /dev/null
+++ b/src/devices/pic/xml_data/16F876.xml
@@ -0,0 +1,127 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F876" status="NR" alternative="16F876A" memory_technology="FLASH" self_write="no" architecture="16X" id="0x09E0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010239" datasheet="30292" progsheet="39025" erratas="80053 80052 80051" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"       bchecksum="0x1BFF" cchecksum="0xE7CD" />
+    <checksum protected="1F00:1FFF" bchecksum="0x28EE" cchecksum="0xDAA3" />
+    <checksum protected="1000:1FFF" bchecksum="0x27DE" cchecksum="0xD993" />
+    <checksum protected="All"       bchecksum="0x27CE" cchecksum="0xF39C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="16" vdd_min="4"   vdd_max="5.5" />
+    <frequency start="16" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="10" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.2" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x1FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3BFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"   value="0x0200" >
+      <value value="0x0000" name="Off" cname="_WRT_ENABLE_OFF" />
+      <value value="0x0200" name="All" cname="_WRT_ENABLE_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3030" >
+      <value value="0x0000" name="All"       cname="_CP_ALL"       />
+      <value value="0x1010" name="1000:1FFF" cname="_CP_HALF"      />
+      <value value="0x2020" name="1F00:1FFF" cname="_CP_UPPER_256" />
+      <value value="0x3030" name="Off"       cname="_CP_OFF"       />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"        />
+    <pin index="2"  name="RA0/AN0"         />
+    <pin index="3"  name="RA1/AN1"         />
+    <pin index="4"  name="RA2/AN2/VREF-"   />
+    <pin index="5"  name="RA3/AN3/VREF+"   />
+    <pin index="6"  name="RA4/T0CKI"       />
+    <pin index="7"  name="RA5/SS/AN4"      />
+    <pin index="8"  name="VSS"             />
+    <pin index="9"  name="OSC1/CLKIN"      />
+    <pin index="10" name="OSC2/CLKOUT"     />
+    <pin index="11" name="RC0/T1OSO/T1CKI" />
+    <pin index="12" name="RC1/T1OSI/CCP2"  />
+    <pin index="13" name="RC2/CCP1"        />
+    <pin index="14" name="RC3/SCK/SCL"     />
+    <pin index="15" name="RC4/SDI/SDA"     />
+    <pin index="16" name="RC5/SDO"         />
+    <pin index="17" name="RC6/TX/CK"       />
+    <pin index="18" name="RC7/RX/DT"       />
+    <pin index="19" name="VSS"             />
+    <pin index="20" name="VDD"             />
+    <pin index="21" name="RB0/INT"         />
+    <pin index="22" name="RB1"             />
+    <pin index="23" name="RB2"             />
+    <pin index="24" name="RB3/PGM"         />
+    <pin index="25" name="RB4"             />
+    <pin index="26" name="RB5"             />
+    <pin index="27" name="RB6/PGC"         />
+    <pin index="28" name="RB7/PGD"         />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F876A.xml b/src/devices/pic/xml_data/16F876A.xml
new file mode 100644
index 0000000..f1c23ce
--- /dev/null
+++ b/src/devices/pic/xml_data/16F876A.xml
@@ -0,0 +1,151 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F876A" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0E00"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010240" datasheet="39582" progsheet="39589" erratas="80128 80133 80240 80276" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x0FCF" cchecksum="0xDB9D" />
+    <checksum protected="All" bchecksum="0x1F9E" cchecksum="0xEB6C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.2" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x1FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x2FCF">
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"   value="0x0600" >
+      <value value="0x0000" name="0000:0FFF" cname="_WRT_HALF"    />
+      <value value="0x0200" name="0000:07FF" cname="_WRT_1FOURTH" />
+      <value value="0x0400" name="0000:00FF" cname="_WRT_256"     />
+      <value value="0x0600" name="Off"       cname="_WRT_OFF"     />
+    </mask>
+    <mask name="DEBUG" value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CP"    value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="MCLR/VPP"            />
+    <pin index="2"  name="RA0/AN0"             />
+    <pin index="3"  name="RA1/AN1"             />
+    <pin index="4"  name="RA2/AN2/VREF-/CVREF" />
+    <pin index="5"  name="RA3/AN3/VREF+"       />
+    <pin index="6"  name="RA4/T0CKI/C1OUT"     />
+    <pin index="7"  name="RA5/SS/AN4/C2OUT"    />
+    <pin index="8"  name="VSS"                 />
+    <pin index="9"  name="OSC1/CLKIN"          />
+    <pin index="10" name="OSC2/CLKOUT"         />
+    <pin index="11" name="RC0/T1OSO/T1CKI"     />
+    <pin index="12" name="RC1/T1OSI/CCP2"      />
+    <pin index="13" name="RC2/CCP1"            />
+    <pin index="14" name="RC3/SCK/SCL"         />
+    <pin index="15" name="RC4/SDI/SDA"         />
+    <pin index="16" name="RC5/SDO"             />
+    <pin index="17" name="RC6/TX/CK"           />
+    <pin index="18" name="RC7/RX/DT"           />
+    <pin index="19" name="VSS"                 />
+    <pin index="20" name="VDD"                 />
+    <pin index="21" name="RB0/INT"             />
+    <pin index="22" name="RB1"                 />
+    <pin index="23" name="RB2"                 />
+    <pin index="24" name="RB3/PGM"             />
+    <pin index="25" name="RB4"                 />
+    <pin index="26" name="RB5"                 />
+    <pin index="27" name="RB6/PGC"             />
+    <pin index="28" name="RB7/PGD"             />
+  </package>
+
+  <package types="qfn"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F877.xml b/src/devices/pic/xml_data/16F877.xml
new file mode 100644
index 0000000..f83da05
--- /dev/null
+++ b/src/devices/pic/xml_data/16F877.xml
@@ -0,0 +1,233 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F877" status="NR" alternative="16F877A" memory_technology="FLASH" self_write="no" architecture="16X" id="0x09A0"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010241" datasheet="30292" progsheet="39025" erratas="80053 80052 80051" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off"       bchecksum="0x1BFF" cchecksum="0xE7CD" />
+    <checksum protected="1F00:1FFF" bchecksum="0x28EE" cchecksum="0xDAA3" />
+    <checksum protected="1000:1FFF" bchecksum="0x27DE" cchecksum="0xD993" />
+    <checksum protected="All"       bchecksum="0x27CE" cchecksum="0xF39C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="16" vdd_min="4"   vdd_max="5.5" />
+    <frequency start="16" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="10" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.2" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x1FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x3BFF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"   value="0x0200" >
+      <value value="0x0000" name="Off" cname="_WRT_ENABLE_OFF" />
+      <value value="0x0200" name="All" cname="_WRT_ENABLE_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CP"    value="0x3030" >
+      <value value="0x0000" name="All"       cname="_CP_ALL"       />
+      <value value="0x1010" name="1000:1FFF" cname="_CP_HALF"      />
+      <value value="0x2020" name="1F00:1FFF" cname="_CP_UPPER_256" />
+      <value value="0x3030" name="Off"       cname="_CP_OFF"       />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"      nb_pins="40" >
+    <pin index="1"  name="MCLR/VPP"		/>
+    <pin index="2"  name="RA0/AN0"		/>
+    <pin index="3"  name="RA1/AN1"		/>
+    <pin index="4"  name="RA2/AN2/VREF-"	/>
+    <pin index="5"  name="RA3/AN3/VREF+"	/>
+    <pin index="6"  name="RA4/T0CKL"		/>
+    <pin index="7"  name="RA5/AN4/SS"		/>
+    <pin index="8"  name="RE0/RD/AN5"		/>
+    <pin index="9"  name="RE1/WR/AN6"		/>
+    <pin index="10" name="RE2/CS/AN7"		/>
+    <pin index="11" name="VDD"			/>
+    <pin index="12" name="VSS"			/>
+    <pin index="13" name="OSC1/CLKIN"		/>
+    <pin index="14" name="OSC2/CLKOUT"		/>
+    <pin index="15" name="RC0/T1OSO/T1CKL"	/>
+    <pin index="16" name="RC1/T1OSI/CCP2"	/>
+    <pin index="17" name="RC2/CCP1"		/>
+    <pin index="18" name="RC3/SCK/SCL"		/>
+    <pin index="19" name="RD0/PSP0"		/>
+    <pin index="20" name="RD1/PSP1"		/>
+    <pin index="21" name="RD2/PSP2"		/>
+    <pin index="22" name="RD3/PSP3"		/>
+    <pin index="23" name="RC4/SDI/SDA"		/>
+    <pin index="24" name="RC5/SDO"		/>
+    <pin index="25" name="RC6/TX/CK"		/>
+    <pin index="26" name="RC7/RX/DT"		/>
+    <pin index="27" name="RD4/PSP4"		/>
+    <pin index="28" name="RD5/PSP5"		/>
+    <pin index="29" name="RD6/PSP6"		/>
+    <pin index="30" name="RD7/PSP7"		/>
+    <pin index="31" name="VSS"			/>
+    <pin index="32" name="VDD"			/>
+    <pin index="33" name="RB0/INT"		/>
+    <pin index="34" name="RB1"			/>
+    <pin index="35" name="RB2"			/>
+    <pin index="36" name="RB3/PGM"		/>
+    <pin index="37" name="RB4"			/>
+    <pin index="38" name="RB5"			/>
+    <pin index="39" name="RB6/PGC"		/>
+    <pin index="40" name="RB7/PGD"		/>
+  </package>
+
+  <package types="plcc"      nb_pins="44" >
+    <pin index="1"  name=""			/>
+    <pin index="2"  name="MCLR/VPP"		/>
+    <pin index="3"  name="RA0/AN0"		/>
+    <pin index="4"  name="RA1/AN1"		/>
+    <pin index="5"  name="RA2/AN2/VREF-"	/>
+    <pin index="6"  name="RA3/AN3/VREF+"	/>
+    <pin index="7"  name="RA4/T0CKL"		/>
+    <pin index="8"  name="RA5/AN4/SS"		/>
+    <pin index="9"  name="RE0/RD/AN5"		/>
+    <pin index="10" name="RE1/WR/AN6"		/>
+    <pin index="11" name="RE2/CS/AN7"		/>
+    <pin index="12" name="VDD"			/>
+    <pin index="13" name="VSS"			/>
+    <pin index="14" name="OSC1/CLKIN"		/>
+    <pin index="15" name="OSC2/CLKOUT"		/>
+    <pin index="16" name="RC0/T1OSO/T1CK1"	/>
+    <pin index="17" name=""			/>
+    <pin index="18" name="RC1/T1OSI/CCP2"	/>
+    <pin index="19" name="RC2/CCP1"		/>
+    <pin index="20" name="RC3/SCK/SCL"		/>
+    <pin index="21" name="RD0/PSP0"		/>
+    <pin index="22" name="RD1/PSP1"		/>
+    <pin index="23" name="RD2/PSP2"		/>
+    <pin index="24" name="RD3/PSP3"		/>
+    <pin index="25" name="RC4/SDI/SDA"		/>
+    <pin index="26" name="RC5/SDO"		/>
+    <pin index="27" name="RC6/TX/CK"		/>
+    <pin index="28" name=""			/>
+    <pin index="29" name="RC7/RX/DT"		/>
+    <pin index="30" name="RD4/PSP4"		/>
+    <pin index="31" name="RD5/PSP5"		/>
+    <pin index="32" name="RD6/PSP6"		/>
+    <pin index="33" name="RD7/PSP7"		/>
+    <pin index="34" name="VSS"			/>
+    <pin index="35" name="VDD"			/>
+    <pin index="36" name="RB0/INT"		/>
+    <pin index="37" name="RB1"			/>
+    <pin index="38" name="RB2"			/>
+    <pin index="39" name="RB3/PGM"		/>
+    <pin index="40" name=""			/>
+    <pin index="41" name="RB4"			/>
+    <pin index="42" name="RB5"			/>
+    <pin index="43" name="RB6/PGC"		/>
+    <pin index="44" name="RB7/PGD"		/>
+  </package>
+
+  <package types="mqfp tqfp" nb_pins="44" >
+    <pin index="1"  name="RC7/RX/DT"		/>
+    <pin index="2"  name="RD4/PSP4"		/>
+    <pin index="3"  name="RD5/PSP5"		/>
+    <pin index="4"  name="RD6/PSP6"		/>
+    <pin index="5"  name="RD7/PSP7"		/>
+    <pin index="6"  name="VSS"			/>
+    <pin index="7"  name="VDD"			/>
+    <pin index="8"  name="RB0/INT"		/>
+    <pin index="9"  name="RB1"			/>
+    <pin index="10" name="RB2"			/>
+    <pin index="11" name="RB3/PGM"		/>
+    <pin index="12" name=""			/>
+    <pin index="13" name=""			/>
+    <pin index="14" name="RB4"			/>
+    <pin index="15" name="RB5"			/>
+    <pin index="16" name="RB6/PGC"		/>
+    <pin index="17" name="RB7/PGD"		/>
+    <pin index="18" name="MCLR/VPP"		/>
+    <pin index="19" name="RA0/AN0"		/>
+    <pin index="20" name="RA1/AN1"		/>
+    <pin index="21" name="RA2/AN2/VREF-"	/>
+    <pin index="22" name="RA3/AN3/VREF+"	/>
+    <pin index="23" name="RA4/T0CKL"		/>
+    <pin index="24" name="RA5/AN4/SS"		/>
+    <pin index="25" name="RE0/AN5/RD"		/>
+    <pin index="26" name="RE1/AN6/WR"		/>
+    <pin index="27" name="RE2/AN7/CS"		/>
+    <pin index="28" name="VDD"			/>
+    <pin index="29" name="VSS"			/>
+    <pin index="30" name="OSC1/CLKIN"		/>
+    <pin index="31" name="OSC2/CLKOUT"		/>
+    <pin index="32" name="RC0/T1OSO/T1CKL"	/>
+    <pin index="33" name=""			/>
+    <pin index="34" name=""			/>
+    <pin index="35" name="RC1/T1OSI/CCP2"	/>
+    <pin index="36" name="RC2/CCP1"		/>
+    <pin index="37" name="RC3/SCK/SCL"		/>
+    <pin index="38" name="RD0/PSP0"		/>
+    <pin index="39" name="RD1/PSP1"		/>
+    <pin index="40" name="RD2/PSP2"		/>
+    <pin index="41" name="RD3/PSP3"		/>
+    <pin index="42" name="RC4/SDI/SDA"		/>
+    <pin index="43" name="RC5/SDO"		/>
+    <pin index="44" name="RC6/TX/CK"		/>
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F877A.xml b/src/devices/pic/xml_data/16F877A.xml
new file mode 100644
index 0000000..3a16d77
--- /dev/null
+++ b/src/devices/pic/xml_data/16F877A.xml
@@ -0,0 +1,273 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F877A" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x0E20"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010242" datasheet="39582" progsheet="39589" erratas="80128 80133 80240 80276" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x0FCF" cchecksum="0xDB9D" />
+    <checksum protected="All" bchecksum="0x1F9E" cchecksum="0xEB6C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.2" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x1FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0x3FFF" bvalue="0x2FCF" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC" />
+      <value value="0x0001" name="XT"           cname="_XT_OSC" />
+      <value value="0x0002" name="HS"           cname="_HS_OSC" />
+      <value value="0x0003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"   value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"   value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"   value="0x0600" >
+      <value value="0x0000" name="0000:0FFF" cname="_WRT_HALF"    />
+      <value value="0x0200" name="0000:07FF" cname="_WRT_1FOURTH" />
+      <value value="0x0400" name="0000:00FF" cname="_WRT_256"     />
+      <value value="0x0600" name="Off"       cname="_WRT_OFF"     />
+    </mask>
+    <mask name="DEBUG" value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CP"    value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F88.xml b/src/devices/pic/xml_data/16F88.xml
new file mode 100644
index 0000000..b2325c3
--- /dev/null
+++ b/src/devices/pic/xml_data/16F88.xml
@@ -0,0 +1,184 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F88" status="IP" memory_technology="FLASH" self_write="yes" architecture="16X" id="0x0760" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010243" datasheet="30488" progsheet="39607" erratas="80171 80301" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x3002" cchecksum="0xFBD0" />
+    <checksum protected="All" bchecksum="0x5004" cchecksum="0x1BD2" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4" end="10" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="20" vdd_min="4" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"           min="10"  max="13.5" nominal="13" />
+  <voltages name="vdd_prog"      min="4.5" max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2008" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="WDT"    value="0x0004" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE"  value="0x0008" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0008" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="FOSC"   value="0x0013" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"       />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"       />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"       />
+      <value value="0x0003" name="EC_IO"        cname="_EXTCLK"       />
+      <value value="0x0010" name="INTRC_IO"     cname="_INTRC_IO"     />
+      <value value="0x0011" name="INTRC_CLKOUT" cname="_INTRC_CLKOUT" />
+      <value value="0x0012" name="EXTRC_IO"     cname="_EXTRC_IO"     />
+      <value value="0x0013" name="EXTRC_CLKOUT" cname="_EXTRC_CLKOUT" />
+    </mask>
+    <mask name="MCLRE"  value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLR_OFF" />
+      <value value="0x0020" name="External" cname="_MCLR_ON"  />
+    </mask>
+    <mask name="BODEN"  value="0x0040" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x0040" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x0080" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x0080" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="CPD"    value="0x0100" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0100" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="WRT"    value="0x0600" >
+      <value value="0x0000" name="All"     cname="_WRT_PROTECT_ALL"  />
+      <value value="0x0200" name="000:7FF" cname="_WRT_PROTECT_2048" />
+      <value value="0x0400" name="000:0FF" cname="_WRT_PROTECT_256"  />
+      <value value="0x0600" name="Off"     cname="_WRT_PROTECT_OFF"  />
+    </mask>
+    <mask name="DEBUG"  value="0x0800" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x0800" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+    <mask name="CCP1MX" value="0x1000" >
+      <value value="0x0000" name="RB3" cname="_CCP1_RB3" />
+      <value value="0x1000" name="RB0" cname="_CCP1_RB0" />
+    </mask>
+    <mask name="CP"     value="0x2000" >
+      <value value="0x0000" name="All" cname="_CP_ALL" />
+      <value value="0x2000" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG2" wmask="0x3FFF" bvalue="0x0003" >
+    <mask name="FCMEN" value="0x0001" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0001" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x0002" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0002" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2/AN2/VREF-/CVREF"     />
+    <pin index="2"  name="RA3/AN3/VREF+/C1OUT"     />
+    <pin index="3"  name="RA4/AN4/T0CKI/C2OUT"     />
+    <pin index="4"  name="RA5/MCLR/VPP"            />
+    <pin index="5"  name="VSS"                     />
+    <pin index="6"  name="RB0/INT/CCP1"            />
+    <pin index="7"  name="RB1/SDI/SDA"             />
+    <pin index="8"  name="RB2/SDO/CCP1"            />
+    <pin index="9"  name="RB3/CCP1/PGM"            />
+    <pin index="10" name="RB4/SCK/SCL"             />
+    <pin index="11" name="RB5/SS/TX/CK"            />
+    <pin index="12" name="RB6/AN5/T1OSO/T1CKI/PGC" />
+    <pin index="13" name="RB7/AN6/T1OSI/PGD"       />
+    <pin index="14" name="VDD"                     />
+    <pin index="15" name="RA6/OSC2/CLKOUT"         />
+    <pin index="16" name="RA7/OSC1/CLKIN"          />
+    <pin index="17" name="RA0/AN0"                 />
+    <pin index="18" name="RA1/AN1"                 />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F882.xml b/src/devices/pic/xml_data/16F882.xml
new file mode 100644
index 0000000..db2c723
--- /dev/null
+++ b/src/devices/pic/xml_data/16F882.xml
@@ -0,0 +1,175 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F882" status="IP" memory_technology="FLASH" self_write="yes" architecture="16X" id="0x2000"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="530146" datasheet="41291" progsheet="41287" erratas="80302" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x3EFF" cchecksum="0x0ACD" />
+    <checksum protected="All" bchecksum="0x85BE" cchecksum="0x518C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="8"  vdd_min="2.0"   vdd_max="5.5" />
+    <frequency start="8"  end="10" vdd_min="3.0" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="12"  nominal="12" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x07FF" />
+  <memory name="calibration"  start="0x2009" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2008" />
+  <memory name="eeprom"       start="0x0000" end="0x007F" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOR_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOR_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOR_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x1000" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x1000" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x2000" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x2000" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG2" wmask="0x3FFF" bvalue="0x0700" >
+    <mask name="BORV" value="0x0100" >
+      <value value="0x0100" name="4.0" cname="_BOR40V" />
+      <value value="0x0000" name="2.1" cname="_BOR21V" />
+    </mask>
+    <mask name="WRT"  value="0x0600" >
+      <value value="0x0000" name="0000:03FF" cname="_WRT_HALF"    />
+      <value value="0x0200" name="0000:00FF" cname="_WRT_1FOURTH" />
+      <value value="0x0400" name="invalid" />
+      <value value="0x0600" name="Off"       cname="_WRT_OFF"     />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F883.xml b/src/devices/pic/xml_data/16F883.xml
new file mode 100644
index 0000000..1140b72
--- /dev/null
+++ b/src/devices/pic/xml_data/16F883.xml
@@ -0,0 +1,175 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F883" status="IP" memory_technology="FLASH" self_write="yes" architecture="16X" id="0x2020"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026563" datasheet="41291" progsheet="41287" erratas="80302" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x36FF" cchecksum="0x02CD" />
+    <checksum protected="All" bchecksum="0x7DBE" cchecksum="0x498C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="8"  vdd_min="2.0"   vdd_max="5.5" />
+    <frequency start="8"  end="10" vdd_min="3.0" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="12"  nominal="12" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="calibration"  start="0x2009" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2008" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOR_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOR_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOR_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x1000" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x1000" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x2000" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x2000" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG2" wmask="0x3FFF" bvalue="0x0700" >
+    <mask name="BORV" value="0x0100" >
+      <value value="0x0100" name="4.0" cname="_BOR40V" />
+      <value value="0x0000" name="2.1" cname="_BOR21V" />
+    </mask>
+    <mask name="WRT"  value="0x0600" >
+      <value value="0x0000" name="0000:07FF" cname="_WRT_HALF"    />
+      <value value="0x0200" name="0000:03FF" cname="_WRT_1FOURTH" />
+      <value value="0x0400" name="0000:00FF" cname="_WRT_256"     />
+      <value value="0x0600" name="Off"       cname="_WRT_OFF"     />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F884.xml b/src/devices/pic/xml_data/16F884.xml
new file mode 100644
index 0000000..fbe9423
--- /dev/null
+++ b/src/devices/pic/xml_data/16F884.xml
@@ -0,0 +1,250 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F884" status="IP" memory_technology="FLASH" self_write="yes" architecture="16X" id="0x2040"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026564" datasheet="41291" progsheet="41287" erratas="80302" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x36FF" cchecksum="0x02CD" />
+    <checksum protected="All" bchecksum="0x7DBE" cchecksum="0x498C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="8"  vdd_min="2.0"   vdd_max="5.5" />
+    <frequency start="8"  end="10" vdd_min="3.0" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="12"  nominal="12" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="calibration"  start="0x2009" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2008" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOR_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOR_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOR_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x1000" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x1000" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x2000" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x2000" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG2" wmask="0x3FFF" bvalue="0x0700" >
+    <mask name="BORV" value="0x0100" >
+      <value value="0x0100" name="4.0" cname="_BOR40V" />
+      <value value="0x0000" name="2.1" cname="_BOR21V" />
+    </mask>
+    <mask name="WRT"  value="0x0600" >
+      <value value="0x0000" name="0000:07FF" cname="_WRT_HALF"    />
+      <value value="0x0200" name="0000:03FF" cname="_WRT_1FOURTH" />
+      <value value="0x0400" name="0000:00FF" cname="_WRT_256"     />
+      <value value="0x0600" name="Off"       cname="_WRT_OFF"     />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F886.xml b/src/devices/pic/xml_data/16F886.xml
new file mode 100644
index 0000000..3205cd7
--- /dev/null
+++ b/src/devices/pic/xml_data/16F886.xml
@@ -0,0 +1,175 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F886" status="IP" memory_technology="FLASH" self_write="yes" architecture="16X" id="0x2060"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026562" datasheet="41291" progsheet="41287" erratas="80302" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x26FF" cchecksum="0xF2CD" />
+    <checksum protected="All" bchecksum="0x6DBE" cchecksum="0x398C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="8"  vdd_min="2.0"   vdd_max="5.5" />
+    <frequency start="8"  end="10" vdd_min="3.0" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="12"  nominal="12" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x1FFF" />
+  <memory name="calibration"  start="0x2009" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2008" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOR_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOR_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOR_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x1000" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x1000" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x2000" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x2000" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG2" wmask="0x3FFF" bvalue="0x0700" >
+    <mask name="BORV" value="0x0100" >
+      <value value="0x0100" name="4.0" cname="_BOR40V" />
+      <value value="0x0000" name="2.1" cname="_BOR21V" />
+    </mask>
+    <mask name="WRT"  value="0x0600" >
+      <value value="0x0000" name="0000:0FFF" cname="_WRT_HALF"    />
+      <value value="0x0200" name="0000:07FF" cname="_WRT_1FOURTH" />
+      <value value="0x0400" name="0000:00FF" cname="_WRT_256"     />
+      <value value="0x0600" name="Off"       cname="_WRT_OFF"     />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F887.xml b/src/devices/pic/xml_data/16F887.xml
new file mode 100644
index 0000000..78be11e
--- /dev/null
+++ b/src/devices/pic/xml_data/16F887.xml
@@ -0,0 +1,250 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F887" status="IP" memory_technology="FLASH" self_write="yes" architecture="16X" id="0x2080"
+        xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'
+        xsi:noNamespaceSchemaLocation='pic.xsd'>
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026561" datasheet="41291" progsheet="41287" erratas="80302" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x26FF" cchecksum="0xF2CD" />
+    <checksum protected="All" bchecksum="0x6DBE" cchecksum="0x398C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="8"  vdd_min="2.0"   vdd_max="5.5" />
+    <frequency start="8"  end="10" vdd_min="3.0" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="12"  nominal="12" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x1FFF" />
+  <memory name="calibration"  start="0x2009" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2008" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0x3FFF" bvalue="0x3FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOR_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOR_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOR_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOR_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="LVP"   value="0x1000" >
+      <value value="0x0000" name="Off" cname="_LVP_OFF" />
+      <value value="0x1000" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x2000" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x2000" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG2" wmask="0x3FFF" bvalue="0x0700" >
+    <mask name="BORV" value="0x0100" >
+      <value value="0x0100" name="4.0" cname="_BOR40V" />
+      <value value="0x0000" name="2.1" cname="_BOR21V" />
+    </mask>
+    <mask name="WRT"  value="0x0600" >
+      <value value="0x0000" name="0000:0FFF" cname="_WRT_HALF"    />
+      <value value="0x0200" name="0000:07FF" cname="_WRT_1FOURTH" />
+      <value value="0x0400" name="0000:00FF" cname="_WRT_256"     />
+      <value value="0x0600" name="Off"       cname="_WRT_OFF"     />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F913.xml b/src/devices/pic/xml_data/16F913.xml
new file mode 100644
index 0000000..c904d5d
--- /dev/null
+++ b/src/devices/pic/xml_data/16F913.xml
@@ -0,0 +1,156 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F913" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x13E0" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="020199" datasheet="41250" progsheet="41244" erratas="80238" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x0FFF" cchecksum="0xDBCD" />
+    <checksum protected="All" bchecksum="0x2FBE" cchecksum="0xFB8C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="calibration"  start="0x2008" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG" wmask="0x3FFF" bvalue="0x1FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOD_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOD_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOD_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOD_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x1000" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x1000" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F914.xml b/src/devices/pic/xml_data/16F914.xml
new file mode 100644
index 0000000..d74a0d5
--- /dev/null
+++ b/src/devices/pic/xml_data/16F914.xml
@@ -0,0 +1,188 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F914" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x13C0" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="020200" datasheet="41250" progsheet="41244" erratas="80238" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x0FFF" cchecksum="0xDBCD" />
+    <checksum protected="All" bchecksum="0x2FBE" cchecksum="0xFB8C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x0FFF" />
+  <memory name="calibration"  start="0x2008" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG" wmask="0x3FFF" bvalue="0x1FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOD_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOD_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOD_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOD_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x1000" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x1000" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F916.xml b/src/devices/pic/xml_data/16F916.xml
new file mode 100644
index 0000000..b066f93
--- /dev/null
+++ b/src/devices/pic/xml_data/16F916.xml
@@ -0,0 +1,156 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F916" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x13A0" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="020201" datasheet="41250" progsheet="41244" erratas="80238" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xFFFF" cchecksum="0xCBCD" />
+    <checksum protected="All" bchecksum="0x1FBE" cchecksum="0xEB8C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x1FFF" />
+  <memory name="calibration"  start="0x2008" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG" wmask="0x3FFF" bvalue="0x1FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOD_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOD_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOD_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOD_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x1000" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x1000" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F917.xml b/src/devices/pic/xml_data/16F917.xml
new file mode 100644
index 0000000..9e17dcc
--- /dev/null
+++ b/src/devices/pic/xml_data/16F917.xml
@@ -0,0 +1,188 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F917" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1380" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="020202" datasheet="41250" progsheet="41244" erratas="80238" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xFFFF" cchecksum="0xCBCD" />
+    <checksum protected="All" bchecksum="0x1FBE" cchecksum="0xEB8C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x1FFF" />
+  <memory name="calibration"  start="0x2008" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG" wmask="0x3FFF" bvalue="0x1FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOD_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOD_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOD_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOD_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x1000" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x1000" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16F946.xml b/src/devices/pic/xml_data/16F946.xml
new file mode 100644
index 0000000..53df522
--- /dev/null
+++ b/src/devices/pic/xml_data/16F946.xml
@@ -0,0 +1,161 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16F946" status="IP" memory_technology="FLASH" self_write="no" architecture="16X" id="0x1460" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="023674" datasheet="41250" progsheet="41244" erratas="80238" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xFFFF" cchecksum="0xCBCD" />
+    <checksum protected="All" bchecksum="0x1FBE" cchecksum="0xEB8C" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="extended" >
+    <frequency start="0"  end="4"  vdd_min="2"   vdd_max="5.5" />
+    <frequency start="4"  end="10" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"  max="13"  nominal="11.5" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5" nominal="5"    />
+  <voltages name="vdd_prog_write" min="2"   max="5.5" nominal="5"    />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x0000" end="0x1FFF" />
+  <memory name="calibration"  start="0x2008" end="0x2009" cal_opmask="0x0000"     cal_opcode="0x0000" />
+  <memory name="user_ids"     start="0x2000" end="0x2003" rmask="0x007F"          />
+  <memory name="device_id"    start="0x2006" end="0x2006" />
+  <memory name="config"       start="0x2007" end="0x2007" />
+  <memory name="eeprom"       start="0x0000" end="0x00FF" hexfile_offset="0x2100" />
+  <memory name="debug_vector" start="0x2004" end="0x2004" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG" wmask="0x3FFF" bvalue="0x1FFF" >
+    <mask name="FOSC"  value="0x0007" >
+      <value value="0x0000" name="LP"           cname="_LP_OSC"             />
+      <value value="0x0001" name="XT"           cname="_XT_OSC"             />
+      <value value="0x0002" name="HS"           cname="_HS_OSC"             />
+      <value value="0x0003" name="EC_IO"        cname="_EC_OSC"             />
+      <value value="0x0004" name="INTRC_IO"     cname="_INTRC_OSC_NOCLKOUT" ecnames="_INTOSCIO" />
+      <value value="0x0005" name="INTRC_CLKOUT" cname="_INTRC_OSC_CLKOUT"   ecnames="_INTOSC"   />
+      <value value="0x0006" name="EXTRC_IO"     cname="_EXTRC_OSC_NOCLKOUT" ecnames="_EXTRCIO"  />
+      <value value="0x0007" name="EXTRC_CLKOUT" cname="_EXTRC_OSC_CLKOUT"   ecnames="_EXTRC"    />
+    </mask>
+    <mask name="WDT"   value="0x0008" >
+      <value value="0x0000" name="Off" cname="_WDT_OFF" />
+      <value value="0x0008" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="PWRTE" value="0x0010" >
+      <value value="0x0000" name="On"  cname="_PWRTE_ON"  />
+      <value value="0x0010" name="Off" cname="_PWRTE_OFF" />
+    </mask>
+    <mask name="MCLRE" value="0x0020" >
+      <value value="0x0000" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x0020" name="External" cname="_MCLRE_ON"  />
+    </mask>
+    <mask name="CP"    value="0x0040" >
+      <value value="0x0000" name="All" cname="_CP_ON"  />
+      <value value="0x0040" name="Off" cname="_CP_OFF" />
+    </mask>
+    <mask name="CPD"   value="0x0080" >
+      <value value="0x0000" name="All" cname="_CPD_ON"  />
+      <value value="0x0080" name="Off" cname="_CPD_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x0300" >
+      <value value="0x0000" name="Off"      cname="_BOD_OFF"    />
+      <value value="0x0100" name="Software" cname="_BOD_SBODEN" />
+      <value value="0x0200" name="On_run"   cname="_BOD_NSLEEP" />
+      <value value="0x0300" name="On"       cname="_BOD_ON"     />
+    </mask>
+    <mask name="IESO"  value="0x0400" >
+      <value value="0x0000" name="Off" cname="_IESO_OFF" />
+      <value value="0x0400" name="On"  cname="_IESO_ON"  />
+    </mask>
+    <mask name="FCMEN" value="0x0800" >
+      <value value="0x0000" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x0800" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="DEBUG" value="0x1000" >
+      <value value="0x0000" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x1000" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/16HV540.xml b/src/devices/pic/xml_data/16HV540.xml
new file mode 100644
index 0000000..439aa82
--- /dev/null
+++ b/src/devices/pic/xml_data/16HV540.xml
@@ -0,0 +1,97 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="16HV540" document="010244" status="IP" memory_technology="EPROM" architecture="10X" pc="9">
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" constant="0x0FF0" bchecksum="0x0DFF" cchecksum="0xFC47" />
+    <checksum protected="All" type="XOR4"       bchecksum="0x1E07" cchecksum="0x1DF5" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4"     vdd_min="3.5" vdd_max="15" osc="RC" />
+    <frequency start="0" end="4"     vdd_min="3.5" vdd_max="15" osc="XT" />
+    <frequency start="0" end="20"    vdd_min="4.5" vdd_max="15" osc="HS" />
+    <frequency start="0" end="0.032" vdd_min="3.5" vdd_max="15" osc="LP" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.5" max="13.5" nominal="13" />
+  <voltages name="vdd_prog" min="4.75" max="5.25" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"  start="0x000" end="0x1FF" />
+  <memory name="user_ids" start="0x200" end="0x203" rmask="0x00F" />
+  <memory name="config"   start="0xFFF" end="0xFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFF" bvalue="0x00F" >
+    <mask name="FOSC" value="0x003" >
+      <value value="0x000" name="LP"           cname="_LP_OSC" />
+      <value value="0x001" name="XT"           cname="_XT_OSC" />
+      <value value="0x002" name="HS"           cname="_HS_OSC" />
+      <value value="0x003" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+    <mask name="WDT"  value="0x004" >
+      <value value="0x000" name="Off" cname="_WDT_OFF" />
+      <value value="0x004" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="CP"   value="0x008" >
+      <value value="0x000" name="All" cname="_CP_ON"  />
+      <value value="0x008" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="RA2"         />
+    <pin index="2"  name="RA3"         />
+    <pin index="3"  name="T0CKI"       />
+    <pin index="4"  name="MCLR/VPP"    />
+    <pin index="5"  name="VSS"         />
+    <pin index="6"  name="RB0"         />
+    <pin index="7"  name="RB1"         />
+    <pin index="8"  name="RB2"         />
+    <pin index="9"  name="RB3"         />
+    <pin index="10" name="RB4"         />
+    <pin index="11" name="RB5"         />
+    <pin index="12" name="RB6"         />
+    <pin index="13" name="RB7"         />
+    <pin index="14" name="VDD"         />
+    <pin index="15" name="OSC2/CLKOUT" />
+    <pin index="16" name="OSC1/CLKIN"  />
+    <pin index="17" name="RA0"         />
+    <pin index="18" name="RA1"         />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/17C42.xml b/src/devices/pic/xml_data/17C42.xml
new file mode 100644
index 0000000..e072c94
--- /dev/null
+++ b/src/devices/pic/xml_data/17C42.xml
@@ -0,0 +1,192 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="17C42" document="010245" status="EOL" alternatives="17C42A" memory_technology="EPROM" architecture="17C" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Microprocessor"                              constant="0xFFA0" bchecksum="0xF7FF" cchecksum="0x79BD" />
+    <checksum protected="Microcontroller"                             constant="0xFFA0" bchecksum="0xF7EF" cchecksum="0x79AD" />
+    <checksum protected="Extended microcontroller"                    constant="0xFFA0" bchecksum="0xF7BF" cchecksum="0x797D" />
+    <checksum protected="Code-protected microcontroller" type="XNOR8" constant="0xFFA0" bchecksum="0xF7AF" cchecksum="0xBB73" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="25" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code" start="0x0000" end="0x07FF" />
+  <memory name="config"  start="0xFE00" end="0xFE00" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFFF" bvalue="0x005F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LF_OSC" />
+      <value value="0x0001" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+      <value value="0x0002" name="XT"           cname="_XT_OSC" />
+      <value value="0x0003" name="EC"           cname="_EC_OSC" />
+    </mask>
+    <mask name="WDTPS" value="0x000C" >
+      <value value="0x0000" name="Disabled" cname="_WDT_OFF" ecnames="_WDT_NORM" />
+      <value value="0x0004" name="1:128"    cname="_WDT_64"  />
+      <value value="0x0008" name="1:512"    cname="_WDT_256" />
+      <value value="0x000C" name="1:1"      cname="_WDT_1"   />
+    </mask>
+    <mask name="PM"    value="0x0050" >
+      <value value="0x0000" name="Code-protected microcontroller" cname="_PMC_MODE" />
+      <value value="0x0010" name="Extended microcontroller"       cname="_XMC_MODE" />
+      <value value="0x0040" name="Microcontroller"                cname="_MC_MODE"  />
+      <value value="0x0050" name="Microprocessor"                 cname="_MP_MODE"  />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"      nb_pins="40" >
+    <pin index="1"  name="VDD"			/>
+    <pin index="2"  name="RC0/AD0"		/>
+    <pin index="3"  name="RC1/AD1"		/>
+    <pin index="4"  name="RC2/AD2"		/>
+    <pin index="5"  name="RC3/AD3"		/>
+    <pin index="6"  name="RC4/AD4"		/>
+    <pin index="7"  name="RC5/AD5"		/>
+    <pin index="8"  name="RC6/AD6"		/>
+    <pin index="9"  name="RC7/AD7"		/>
+    <pin index="10" name="VSS"			/>
+    <pin index="11" name="RB0/CAP1"		/>
+    <pin index="12" name="RB1/CAP2"		/>
+    <pin index="13" name="RB2/PWM1"		/>
+    <pin index="14" name="RB3/PWM2"		/>
+    <pin index="15" name="RB4/TCLK2"		/>
+    <pin index="16" name="RB5/TCLK3"		/>
+    <pin index="17" name="RB6"			/>
+    <pin index="18" name="RB7"			/>
+    <pin index="19" name="OSC1/CLKIN"		/>
+    <pin index="20" name="OSC2/CLKOUT"		/>
+    <pin index="21" name="RA5/TX/CK"		/>
+    <pin index="22" name="RA4/RX/DT"		/>
+    <pin index="23" name="RA3"			/>
+    <pin index="24" name="RA2"			/>
+    <pin index="25" name="RA1/T0CKL"		/>
+    <pin index="26" name="RA0/INT"		/>
+    <pin index="27" name="TEST"			/>
+    <pin index="28" name="RE2/WR"		/>
+    <pin index="29" name="RE1/OE"		/>
+    <pin index="30" name="RE0/ALE"		/>
+    <pin index="31" name="VSS"			/>
+    <pin index="32" name="MCLR/VPP"		/>
+    <pin index="33" name="RD7/AD15"		/>
+    <pin index="34" name="RD6/AD14"		/>
+    <pin index="35" name="RD5/AD13"		/>
+    <pin index="36" name="RD4/AD12"		/>
+    <pin index="37" name="RD3/AD11"		/>
+    <pin index="38" name="RD2/AD10"		/>
+    <pin index="39" name="RD1/AD9"		/>
+    <pin index="40" name="RD0/AD8"		/>
+  </package>
+
+  <package types="plcc"      nb_pins="44" >
+    <pin index="1"  name="VDD"			/>
+    <pin index="2"  name="NC"			/>
+    <pin index="3"  name="RC0/AD0"		/>
+    <pin index="4"  name="RC1/AD1"		/>
+    <pin index="5"  name="RC2/AD2"		/>
+    <pin index="6"  name="RC3/AD3"		/>
+    <pin index="7"  name="RC4/AD4"		/>
+    <pin index="8"  name="RC5/AD5"		/>
+    <pin index="9"  name="RC6/AD6"		/>
+    <pin index="10" name="RC7/AD7"		/>
+    <pin index="11" name="VSS"			/>
+    <pin index="12" name="VSS"			/>
+    <pin index="13" name="RB0/CAP1"		/>
+    <pin index="14" name="RB1/CAP2"		/>
+    <pin index="15" name="RB2/PWM1"		/>
+    <pin index="16" name="RB3/PWM2"		/>
+    <pin index="17" name="RB4/TCLK2"		/>
+    <pin index="18" name="RB5/TCLK3"		/>
+    <pin index="19" name="RB6"			/>
+    <pin index="20" name="RB7"			/>
+    <pin index="21" name="OSC1/CLKIN"		/>
+    <pin index="22" name="OSC2/CLKOUT"		/>
+    <pin index="23" name="RA5/TX/CK"		/>
+    <pin index="24" name="RA4/RX/DT"		/>
+    <pin index="25" name="RA3"			/>
+    <pin index="26" name="RA2"			/>
+    <pin index="27" name="RA1/T0CKL"		/>
+    <pin index="28" name="RA0/INT"		/>
+    <pin index="29" name="TEST"			/>
+    <pin index="30" name="RE2/WR"		/>
+    <pin index="31" name="RE1/OE"		/>
+    <pin index="32" name="RE0/ALE"		/>
+    <pin index="33" name="VSS"			/>
+    <pin index="34" name="VSS"			/>
+    <pin index="35" name="MCLR/VPP"		/>
+    <pin index="36" name="RD7/AD15"		/>
+    <pin index="37" name="RD6/AD14"		/>
+    <pin index="38" name="RD5/AD13"		/>
+    <pin index="39" name="RD4/AD12"		/>
+    <pin index="40" name="RD3/AD11"		/>
+    <pin index="41" name="RD2/AD10"		/>
+    <pin index="42" name="RD1/AD9"		/>
+    <pin index="43" name="RD0/AD8"		/>
+    <pin index="44" name="VDD"			/>
+  </package>
+
+  <package types="mqfp tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/17C42A.xml b/src/devices/pic/xml_data/17C42A.xml
new file mode 100644
index 0000000..58c59b3
--- /dev/null
+++ b/src/devices/pic/xml_data/17C42A.xml
@@ -0,0 +1,196 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="17C42A" document="010246" status="NR" alternative="18F4220" memory_technology="EPROM" architecture="17C" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Microprocessor"                              bchecksum="0xF95F" cchecksum="0x7B1D" />
+    <checksum protected="Microcontroller"                             bchecksum="0xF94F" cchecksum="0x7B0D" />
+    <checksum protected="Extended microcontroller"                    bchecksum="0xF91F" cchecksum="0x7ADD" />
+    <checksum protected="Code-protected microcontroller" type="XNOR8" bchecksum="0xF80F" cchecksum="0xBBD3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="33" vdd_min="4.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="8" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code" start="0x0000" end="0x07FF" />
+  <memory name="config"  start="0xFE00" end="0xFE00" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFFF" bvalue="0x015F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LF_OSC" />
+      <value value="0x0001" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+      <value value="0x0002" name="XT"           cname="_XT_OSC" />
+      <value value="0x0003" name="EC"           cname="_EC_OSC" />
+    </mask>
+    <mask name="WDTPS" value="0x000C" >
+      <value value="0x0000" name="Disabled" cname="_WDT_OFF" ecnames="_WDT_NORM" />
+      <value value="0x0004" name="1:128"    cname="_WDT_64"  />
+      <value value="0x0008" name="1:512"    cname="_WDT_256" />
+      <value value="0x000C" name="1:1"      cname="_WDT_1"   />
+    </mask>
+    <mask name="PM"    value="0x0150" >
+      <value value="0x0000" name="Code-protected microcontroller" cname="_PMC_MODE" />
+      <value value="0x0110" name="Extended microcontroller"       cname="_XMC_MODE" />
+      <value value="0x0140" name="Microcontroller"                cname="_MC_MODE"  />
+      <value value="0x0150" name="Microprocessor"                 cname="_MP_MODE"  />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"      nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc"      nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="mqfp tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/17C43.xml b/src/devices/pic/xml_data/17C43.xml
new file mode 100644
index 0000000..4c91f40
--- /dev/null
+++ b/src/devices/pic/xml_data/17C43.xml
@@ -0,0 +1,196 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="17C43" document="010247" status="NR" alternative="18F4320" memory_technology="EPROM" architecture="17C" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Microprocessor"                              bchecksum="0xF15F" cchecksum="0x731D" />
+    <checksum protected="Microcontroller"                             bchecksum="0xF14F" cchecksum="0x730D" />
+    <checksum protected="Extended microcontroller"                    bchecksum="0xF11F" cchecksum="0x72DD" />
+    <checksum protected="Code-protected microcontroller" type="XNOR8" bchecksum="0xF00F" cchecksum="0xB3D3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="33" vdd_min="4.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="8" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code" start="0x0000" end="0x0FFF" />
+  <memory name="config"  start="0xFE00" end="0xFE00" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFFF" bvalue="0x015F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LF_OSC" />
+      <value value="0x0001" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+      <value value="0x0002" name="XT"           cname="_XT_OSC" />
+      <value value="0x0003" name="EC"           cname="_EC_OSC" />
+    </mask>
+    <mask name="WDTPS" value="0x000C" >
+      <value value="0x0000" name="Disabled" cname="_WDT_OFF" ecnames="_WDT_NORM" />
+      <value value="0x0004" name="1:128"    cname="_WDT_64"  />
+      <value value="0x0008" name="1:512"    cname="_WDT_256" />
+      <value value="0x000C" name="1:1"      cname="_WDT_1"   />
+    </mask>
+    <mask name="PM"    value="0x0150" >
+      <value value="0x0000" name="Code-protected microcontroller" cname="_PMC_MODE" />
+      <value value="0x0110" name="Extended microcontroller"       cname="_XMC_MODE" />
+      <value value="0x0140" name="Microcontroller"                cname="_MC_MODE"  />
+      <value value="0x0150" name="Microprocessor"                 cname="_MP_MODE"  />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"      nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc"      nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="mqfp tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/17C44.xml b/src/devices/pic/xml_data/17C44.xml
new file mode 100644
index 0000000..da4be7b
--- /dev/null
+++ b/src/devices/pic/xml_data/17C44.xml
@@ -0,0 +1,196 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="17C44" document="010248" status="NR" alternative="18F4420" memory_technology="EPROM" architecture="17C" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Microprocessor"                              bchecksum="0xE15F" cchecksum="0x631D" />
+    <checksum protected="Microcontroller"                             bchecksum="0xE14F" cchecksum="0x630D" />
+    <checksum protected="Extended microcontroller"                    bchecksum="0xE11F" cchecksum="0x62DD" />
+    <checksum protected="Code-protected microcontroller" type="XNOR8" bchecksum="0xE00F" cchecksum="0xA3D3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="33" vdd_min="4.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="8" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code" start="0x0000" end="0x1FFF" />
+  <memory name="config"  start="0xFE00" end="0xFE00" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFFF" bvalue="0x015F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LF_OSC" />
+      <value value="0x0001" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+      <value value="0x0002" name="XT"           cname="_XT_OSC" />
+      <value value="0x0003" name="EC"           cname="_EC_OSC" />
+    </mask>
+    <mask name="WDTPS" value="0x000C" >
+      <value value="0x0000" name="Disabled" cname="_WDT_OFF" ecnames="_WDT_NORM" />
+      <value value="0x0004" name="1:128"    cname="_WDT_64"  />
+      <value value="0x0008" name="1:512"    cname="_WDT_256" />
+      <value value="0x000C" name="1:1"      cname="_WDT_1"   />
+    </mask>
+    <mask name="PM"    value="0x0150" >
+      <value value="0x0000" name="Code-protected microcontroller" cname="_PMC_MODE" />
+      <value value="0x0110" name="Extended microcontroller"       cname="_XMC_MODE" />
+      <value value="0x0140" name="Microcontroller"                cname="_MC_MODE"  />
+      <value value="0x0150" name="Microprocessor"                 cname="_MP_MODE"  />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"      nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc"      nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="mqfp tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/17C752.xml b/src/devices/pic/xml_data/17C752.xml
new file mode 100644
index 0000000..20f798f
--- /dev/null
+++ b/src/devices/pic/xml_data/17C752.xml
@@ -0,0 +1,201 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="17C752" document="010249" status="NR" alternative="18F6520" memory_technology="EPROM" architecture="17C" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Microprocessor"                              bchecksum="0xA05F" cchecksum="0x221D" />
+    <checksum protected="Microcontroller"                             bchecksum="0xA04F" cchecksum="0x220D" />
+    <checksum protected="Extended microcontroller"                    bchecksum="0xA01F" cchecksum="0x21DD" />
+    <checksum protected="Code-protected microcontroller" type="XNOR8" bchecksum="0x200F" cchecksum="0xE3D3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="8" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="33" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code" start="0x0000" end="0x1FFF" />
+  <memory name="config"  start="0xFE00" end="0xFE00" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFFF" bvalue="0xC05F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LF_OSC" />
+      <value value="0x0001" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+      <value value="0x0002" name="XT"           cname="_XT_OSC" />
+      <value value="0x0003" name="EC"           cname="_EC_OSC" />
+    </mask>
+    <mask name="WDTPS" value="0x000C" >
+      <value value="0x0000" name="Disabled" cname="_WDT_OFF" ecnames="_WDT_NORM" />
+      <value value="0x0004" name="1:64"     cname="_WDT_64"  />
+      <value value="0x0008" name="1:256"    cname="_WDT_256" />
+      <value value="0x000C" name="1:1"      cname="_WDT_1"   ecnames="_WDT_0"    />
+    </mask>
+    <mask name="BODEN" value="0x4000" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x4000" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="PM"    value="0x8050" >
+      <value value="0x0000" name="Code-protected microcontroller" cname="_PMC_MODE" />
+      <value value="0x8010" name="Extended microcontroller"       cname="_XMC_MODE" />
+      <value value="0x8040" name="Microcontroller"                cname="_MC_MODE"  />
+      <value value="0x8050" name="Microprocessor"                 cname="_MP_MODE"  />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="plcc" nb_pins="68" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/17C756.xml b/src/devices/pic/xml_data/17C756.xml
new file mode 100644
index 0000000..a5df4c4
--- /dev/null
+++ b/src/devices/pic/xml_data/17C756.xml
@@ -0,0 +1,201 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="17C756" document="010250" status="EOL" alternatives="17C756A" memory_technology="EPROM" architecture="17C" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Microprocessor"                              bchecksum="0x805F" cchecksum="0x021D" />
+    <checksum protected="Microcontroller"                             bchecksum="0x804F" cchecksum="0x020D" />
+    <checksum protected="Extended microcontroller"                    bchecksum="0x801F" cchecksum="0x01DD" />
+    <checksum protected="Code-protected microcontroller" type="XNOR8" bchecksum="0x000F" cchecksum="0xC3D3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="8" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="33" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code" start="0x0000" end="0x3FFF" />
+  <memory name="config"  start="0xFE00" end="0xFE00" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFFF" bvalue="0xC05F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LF_OSC" />
+      <value value="0x0001" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+      <value value="0x0002" name="XT"           cname="_XT_OSC" />
+      <value value="0x0003" name="EC"           cname="_EC_OSC" />
+    </mask>
+    <mask name="WDTPS" value="0x000C" >
+      <value value="0x0000" name="Disabled" cname="_WDT_OFF" ecnames="_WDT_NORM" />
+      <value value="0x0004" name="1:64"     cname="_WDT_64"  />
+      <value value="0x0008" name="1:256"    cname="_WDT_256" />
+      <value value="0x000C" name="1:1"      cname="_WDT_1"   ecnames="_WDT_0"    />
+    </mask>
+    <mask name="BODEN" value="0x4000" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x4000" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="PM"    value="0x8050" >
+      <value value="0x0000" name="Code-protected microcontroller" cname="_PMC_MODE" />
+      <value value="0x8010" name="Extended microcontroller"       cname="_XMC_MODE" />
+      <value value="0x8040" name="Microcontroller"                cname="_MC_MODE"  />
+      <value value="0x8050" name="Microprocessor"                 cname="_MP_MODE"  />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="plcc" nb_pins="68" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/17C756A.xml b/src/devices/pic/xml_data/17C756A.xml
new file mode 100644
index 0000000..f20ee31
--- /dev/null
+++ b/src/devices/pic/xml_data/17C756A.xml
@@ -0,0 +1,201 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="17C756A" document="010251" status="NR" alternative="18F6520" memory_technology="EPROM" architecture="17C" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Microprocessor"                              bchecksum="0x805F" cchecksum="0x021D" />
+    <checksum protected="Microcontroller"                             bchecksum="0x804F" cchecksum="0x020D" />
+    <checksum protected="Extended microcontroller"                    bchecksum="0x801F" cchecksum="0x01DD" />
+    <checksum protected="Code-protected microcontroller" type="XNOR8" bchecksum="0x000F" cchecksum="0xC3D3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="8" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="33" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code" start="0x0000" end="0x3FFF" />
+  <memory name="config"  start="0xFE00" end="0xFE00" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFFF" bvalue="0xC05F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LF_OSC" />
+      <value value="0x0001" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+      <value value="0x0002" name="XT"           cname="_XT_OSC" />
+      <value value="0x0003" name="EC"           cname="_EC_OSC" />
+    </mask>
+    <mask name="WDTPS" value="0x000C" >
+      <value value="0x0000" name="Disabled" cname="_WDT_OFF" ecnames="_WDT_NORM" />
+      <value value="0x0004" name="1:64"     cname="_WDT_64"  />
+      <value value="0x0008" name="1:256"    cname="_WDT_256" />
+      <value value="0x000C" name="1:1"      cname="_WDT_1"   ecnames="_WDT_0"    />
+    </mask>
+    <mask name="BODEN" value="0x4000" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x4000" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="PM"    value="0x8050" >
+      <value value="0x0000" name="Code-protected microcontroller" cname="_PMC_MODE" />
+      <value value="0x8010" name="Extended microcontroller"       cname="_XMC_MODE" />
+      <value value="0x8040" name="Microcontroller"                cname="_MC_MODE"  />
+      <value value="0x8050" name="Microprocessor"                 cname="_MP_MODE"  />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="plcc" nb_pins="68" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/17C762.xml b/src/devices/pic/xml_data/17C762.xml
new file mode 100644
index 0000000..10e3a86
--- /dev/null
+++ b/src/devices/pic/xml_data/17C762.xml
@@ -0,0 +1,233 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="17C762" document="010252" status="NR" alternative="18F8520" memory_technology="EPROM" architecture="17C" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Microprocessor"                              bchecksum="0xA05F" cchecksum="0x221D" />
+    <checksum protected="Microcontroller"                             bchecksum="0xA04F" cchecksum="0x220D" />
+    <checksum protected="Extended microcontroller"                    bchecksum="0xA01F" cchecksum="0x21DD" />
+    <checksum protected="Code-protected microcontroller" type="XNOR8" bchecksum="0x200F" cchecksum="0xE3D3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="8" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="33" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code" start="0x0000" end="0x1FFF" />
+  <memory name="config"  start="0xFE00" end="0xFE00" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFFF" bvalue="0xC05F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LF_OSC" />
+      <value value="0x0001" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+      <value value="0x0002" name="XT"           cname="_XT_OSC" />
+      <value value="0x0003" name="EC"           cname="_EC_OSC" />
+    </mask>
+    <mask name="WDTPS" value="0x000C" >
+      <value value="0x0000" name="Disabled" cname="_WDT_OFF" ecnames="_WDT_NORM" />
+      <value value="0x0004" name="1:64"     cname="_WDT_64"  />
+      <value value="0x0008" name="1:256"    cname="_WDT_256" />
+      <value value="0x000C" name="1:1"      cname="_WDT_1"   ecnames="_WDT_0"    />
+    </mask>
+    <mask name="BODEN" value="0x4000" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x4000" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="PM"    value="0x8050" >
+      <value value="0x0000" name="Code-protected microcontroller" cname="_PMC_MODE" />
+      <value value="0x8010" name="Extended microcontroller"       cname="_XMC_MODE" />
+      <value value="0x8040" name="Microcontroller"                cname="_MC_MODE"  />
+      <value value="0x8050" name="Microprocessor"                 cname="_MP_MODE"  />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="84" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+    <pin index="81" name="" />
+    <pin index="82" name="" />
+    <pin index="83" name="" />
+    <pin index="84" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/17C766.xml b/src/devices/pic/xml_data/17C766.xml
new file mode 100644
index 0000000..0d2559d
--- /dev/null
+++ b/src/devices/pic/xml_data/17C766.xml
@@ -0,0 +1,233 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="17C766" document="010253" status="NR" alternative="18F8520" memory_technology="EPROM" architecture="17C" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Microprocessor"                              bchecksum="0x805F" cchecksum="0x021D" />
+    <checksum protected="Microcontroller"                             bchecksum="0x804F" cchecksum="0x020D" />
+    <checksum protected="Extended microcontroller"                    bchecksum="0x801F" cchecksum="0x01DD" />
+    <checksum protected="Code-protected microcontroller" type="XNOR8" bchecksum="0x000F" cchecksum="0xC3D3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="8" vdd_min="3" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="33" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code" start="0x0000" end="0x3FFF" />
+  <memory name="config"  start="0xFE00" end="0xFE00" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFFF" bvalue="0xC05F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LF_OSC" />
+      <value value="0x0001" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+      <value value="0x0002" name="XT"           cname="_XT_OSC" />
+      <value value="0x0003" name="EC"           cname="_EC_OSC" />
+    </mask>
+    <mask name="WDTPS" value="0x000C" >
+      <value value="0x0000" name="Disabled" cname="_WDT_OFF" ecnames="_WDT_NORM" />
+      <value value="0x0004" name="1:64"     cname="_WDT_64"  />
+      <value value="0x0008" name="1:256"    cname="_WDT_256" />
+      <value value="0x000C" name="1:1"      cname="_WDT_1"   ecnames="_WDT_0"    />
+    </mask>
+    <mask name="BODEN" value="0x4000" >
+      <value value="0x0000" name="Off" cname="_BODEN_OFF" />
+      <value value="0x4000" name="On"  cname="_BODEN_ON"  />
+    </mask>
+    <mask name="PM"    value="0x8050" >
+      <value value="0x0000" name="Code-protected microcontroller" cname="_PMC_MODE" />
+      <value value="0x8010" name="Extended microcontroller"       cname="_XMC_MODE" />
+      <value value="0x8040" name="Microcontroller"                cname="_MC_MODE"  />
+      <value value="0x8050" name="Microprocessor"                 cname="_MP_MODE"  />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="84" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+    <pin index="81" name="" />
+    <pin index="82" name="" />
+    <pin index="83" name="" />
+    <pin index="84" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/17CR42.xml b/src/devices/pic/xml_data/17CR42.xml
new file mode 100644
index 0000000..b691cd8
--- /dev/null
+++ b/src/devices/pic/xml_data/17CR42.xml
@@ -0,0 +1,196 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="17CR42" document="010254" status="EOL" memory_technology="ROM" architecture="17C" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Microprocessor"                              bchecksum="0xF95F" cchecksum="0x7B1D" />
+    <checksum protected="Microcontroller"                             bchecksum="0xF94F" cchecksum="0x7B0D" />
+    <checksum protected="Extended microcontroller"                    bchecksum="0xF91F" cchecksum="0x7ADD" />
+    <checksum protected="Code-protected microcontroller" type="XNOR8" bchecksum="0xF80F" cchecksum="0xBBD3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="33" vdd_min="4.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="8" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code" start="0x0000" end="0x07FF" />
+  <memory name="config"  start="0xFE00" end="0xFE00" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFFF" bvalue="0x015F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LF_OSC" />
+      <value value="0x0001" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+      <value value="0x0002" name="XT"           cname="_XT_OSC" />
+      <value value="0x0003" name="EC"           cname="_EC_OSC" />
+    </mask>
+    <mask name="WDTPS" value="0x000C" >
+      <value value="0x0000" name="Disabled" cname="_WDT_OFF" ecnames="_WDT_NORM" />
+      <value value="0x0004" name="1:128"    cname="_WDT_64"  />
+      <value value="0x0008" name="1:512"    cname="_WDT_256" />
+      <value value="0x000C" name="1:1"      cname="_WDT_1"   />
+    </mask>
+    <mask name="PM"    value="0x0150" >
+      <value value="0x0000" name="Code-protected microcontroller" cname="_PMC_MODE" />
+      <value value="0x0110" name="Extended microcontroller"       cname="_XMC_MODE" />
+      <value value="0x0140" name="Microcontroller"                cname="_MC_MODE"  />
+      <value value="0x0150" name="Microprocessor"                 cname="_MP_MODE"  />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"      nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc"      nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="mqfp tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/17CR43.xml b/src/devices/pic/xml_data/17CR43.xml
new file mode 100644
index 0000000..13c1f2c
--- /dev/null
+++ b/src/devices/pic/xml_data/17CR43.xml
@@ -0,0 +1,196 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="17CR43" document="010255" status="EOL" memory_technology="ROM" architecture="17C" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Microprocessor"                              bchecksum="0xF15F" cchecksum="0x731D" />
+    <checksum protected="Microcontroller"                             bchecksum="0xF14F" cchecksum="0x730D" />
+    <checksum protected="Extended microcontroller"                    bchecksum="0xF11F" cchecksum="0x72DD" />
+    <checksum protected="Code-protected microcontroller" type="XNOR8" bchecksum="0xF00F" cchecksum="0xB3D3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="33" vdd_min="4.5" vdd_max="6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="8" vdd_min="2.5" vdd_max="6" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code" start="0x0000" end="0x0FFF" />
+  <memory name="config"  start="0xFE00" end="0xFE00" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="" wmask="0xFFFF" bvalue="0x015F" >
+    <mask name="FOSC"  value="0x0003" >
+      <value value="0x0000" name="LP"           cname="_LF_OSC" />
+      <value value="0x0001" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+      <value value="0x0002" name="XT"           cname="_XT_OSC" />
+      <value value="0x0003" name="EC"           cname="_EC_OSC" />
+    </mask>
+    <mask name="WDTPS" value="0x000C" >
+      <value value="0x0000" name="Disabled" cname="_WDT_OFF" ecnames="_WDT_NORM" />
+      <value value="0x0004" name="1:128"    cname="_WDT_64"  />
+      <value value="0x0008" name="1:512"    cname="_WDT_256" />
+      <value value="0x000C" name="1:1"      cname="_WDT_1"   />
+    </mask>
+    <mask name="PM"    value="0x0150" >
+      <value value="0x0000" name="Code-protected microcontroller" cname="_PMC_MODE" />
+      <value value="0x0110" name="Extended microcontroller"       cname="_XMC_MODE" />
+      <value value="0x0140" name="Microcontroller"                cname="_MC_MODE"  />
+      <value value="0x0150" name="Microprocessor"                 cname="_MP_MODE"  />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip"      nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc"      nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="mqfp tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18C242.xml b/src/devices/pic/xml_data/18C242.xml
new file mode 100644
index 0000000..798c478
--- /dev/null
+++ b/src/devices/pic/xml_data/18C242.xml
@@ -0,0 +1,146 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18C242" document="010256" status="NR" alternative="18F2420" memory_technology="EPROM" architecture="18C" id="0x0320" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xC146" cchecksum="0xC09C" />
+    <checksum protected="All" bchecksum="0x005E" cchecksum="0x0068" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="6"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="6" end="40" vdd_min="2.5" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x000000" end="0x003FFF" />
+  <memory name="user_ids"  start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id" start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"    start="0x300000" end="0x300007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG0" wmask="0xFF" bvalue="0xFF" >
+    <mask name="CP" value="0xFF" >
+      <value value="0x00" name="All" cname="_CP_ON"  />
+      <value value="0xFF" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.5" cname="_BORV_25" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG3" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG4" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG5" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_OFF" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG6" wmask="0xFF" bvalue="0x01" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG7" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18C252.xml b/src/devices/pic/xml_data/18C252.xml
new file mode 100644
index 0000000..81f370b
--- /dev/null
+++ b/src/devices/pic/xml_data/18C252.xml
@@ -0,0 +1,146 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18C252" document="010257" status="NR" alternative="18F2520" memory_technology="EPROM" architecture="18C" id="0x0220" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x8146" cchecksum="0x809C" />
+    <checksum protected="All" bchecksum="0x005A" cchecksum="0x0064" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="6"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="6" end="40" vdd_min="2.5" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x000000" end="0x007FFF" />
+  <memory name="user_ids"  start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id" start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"    start="0x300000" end="0x300007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG0" wmask="0xFF" bvalue="0xFF" >
+    <mask name="CP" value="0xFF" >
+      <value value="0x00" name="All" cname="_CP_ON"  />
+      <value value="0xFF" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.5" cname="_BORV_25" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG3" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG4" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG5" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_OFF" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG6" wmask="0xFF" bvalue="0x01" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG7" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18C442.xml b/src/devices/pic/xml_data/18C442.xml
new file mode 100644
index 0000000..419ee29
--- /dev/null
+++ b/src/devices/pic/xml_data/18C442.xml
@@ -0,0 +1,252 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18C442" document="010258" status="NR" alternative="18F4420" memory_technology="EPROM" architecture="18C" id="0x0300" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xC146" cchecksum="0xC09C" />
+    <checksum protected="All" bchecksum="0x005E" cchecksum="0x0068" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="6"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="6" end="40" vdd_min="2.5" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x000000" end="0x003FFF" />
+  <memory name="user_ids"  start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id" start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"    start="0x300000" end="0x300007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG0" wmask="0xFF" bvalue="0xFF" >
+    <mask name="CP" value="0xFF" >
+      <value value="0x00" name="All" cname="_CP_ON"  />
+      <value value="0xFF" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.5" cname="_BORV_25" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG3" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG4" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG5" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_OFF" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG6" wmask="0xFF" bvalue="0x01" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG7" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18C452.xml b/src/devices/pic/xml_data/18C452.xml
new file mode 100644
index 0000000..73e3610
--- /dev/null
+++ b/src/devices/pic/xml_data/18C452.xml
@@ -0,0 +1,252 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18C452" document="010259" status="NR" alternative="18F4520" memory_technology="EPROM" architecture="18C" id="0x0200" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x8146" cchecksum="0x809C" />
+    <checksum protected="All" bchecksum="0x005A" cchecksum="0x0064" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="6"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="6" end="40" vdd_min="2.5" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x000000" end="0x007FFF" />
+  <memory name="user_ids"  start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id" start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"    start="0x300000" end="0x300007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG0" wmask="0xFF" bvalue="0xFF" >
+    <mask name="CP" value="0xFF" >
+      <value value="0x00" name="All" cname="_CP_ON"  />
+      <value value="0xFF" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.5" cname="_BORV_25" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG3" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG4" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG5" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_OFF" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG6" wmask="0xFF" bvalue="0x01" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG7" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18C601.xml b/src/devices/pic/xml_data/18C601.xml
new file mode 100644
index 0000000..6d41b1c
--- /dev/null
+++ b/src/devices/pic/xml_data/18C601.xml
@@ -0,0 +1,225 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18C601" document="010260" status="IP" memory_technology="ROMLESS" architecture="18C" id="0x0120" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="4"  end="16" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3"   />
+    <frequency start="16" end="25" vdd_min="3"   vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="device_id" start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"    start="0x300000" end="0x300007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x02" >
+    <mask name="FOSC" value="0x03" >
+      <value value="0x00" name="LP"           cname="_LP_OSC" />
+      <value value="0x01" name="EC_CLKOUT"    cname="_EC_OSC" />
+      <value value="0x02" name="HS"           cname="_HS_OSC" />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x41" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BW"    value="0x40" >
+      <value value="0x00" name="8"  cname="_BW_8_BIT"  />
+      <value value="0x40" name="16" cname="_BW_16_BIT" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="0x7F"  />
+      <value value="0x80" name="Off" cname="0xFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="68" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18C658.xml b/src/devices/pic/xml_data/18C658.xml
new file mode 100644
index 0000000..9ca140c
--- /dev/null
+++ b/src/devices/pic/xml_data/18C658.xml
@@ -0,0 +1,248 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18C658" document="010261" status="NR" alternative="18F6585" memory_technology="EPROM" architecture="18C" id="0x00A0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x8145" cchecksum="0x809B" />
+    <checksum protected="All" bchecksum="0x0058" cchecksum="0x0062" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="6"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="6" end="40" vdd_min="2.5" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x000000" end="0x007FFF" />
+  <memory name="user_ids"  start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id" start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"    start="0x300000" end="0x300007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG0" wmask="0xFF" bvalue="0xFF" >
+    <mask name="CP" value="0xFF" >
+      <value value="0x00" name="All" cname="_CP_ON"  />
+      <value value="0xFF" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.5" cname="_BORV_25" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG3" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG4" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG5" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x6" name="CONFIG6" wmask="0xFF" bvalue="0x01" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG7" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="68" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18C801.xml b/src/devices/pic/xml_data/18C801.xml
new file mode 100644
index 0000000..3e067ad
--- /dev/null
+++ b/src/devices/pic/xml_data/18C801.xml
@@ -0,0 +1,257 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18C801" document="010262" status="IP" memory_technology="ROMLESS" architecture="18C" id="0x0100" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="4"  end="16" vdd_min="2.5" vdd_max="5.5" vdd_min_end="3"   />
+    <frequency start="16" end="25" vdd_min="3"   vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="device_id" start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"    start="0x300000" end="0x300007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x02" >
+    <mask name="FOSC" value="0x03" >
+      <value value="0x00" name="LP"           cname="_LP_OSC" />
+      <value value="0x01" name="EC_CLKOUT"    cname="_EC_OSC" />
+      <value value="0x02" name="HS"           cname="_HS_OSC" />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x41" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BW"    value="0x40" >
+      <value value="0x00" name="8"  cname="_BW_8_BIT"  />
+      <value value="0x40" name="16" cname="_BW_16_BIT" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="0x7F"  />
+      <value value="0x80" name="Off" cname="0xFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="84" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+    <pin index="81" name="" />
+    <pin index="82" name="" />
+    <pin index="83" name="" />
+    <pin index="84" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18C858.xml b/src/devices/pic/xml_data/18C858.xml
new file mode 100644
index 0000000..7ce8087
--- /dev/null
+++ b/src/devices/pic/xml_data/18C858.xml
@@ -0,0 +1,280 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18C858" document="010263" status="NR" alternative="18F8585" memory_technology="EPROM" architecture="18C" id="0x00E0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0x8145" cchecksum="0x809B" />
+    <checksum protected="All" bchecksum="0x0058" cchecksum="0x0062" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="6"  vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="6" end="40" vdd_min="2.5" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="12.75" max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.75"  max="5.25"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"   start="0x000000" end="0x007FFF" />
+  <memory name="user_ids"  start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id" start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"    start="0x300000" end="0x300007" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG0" wmask="0xFF" bvalue="0xFF" >
+    <mask name="CP" value="0xFF" >
+      <value value="0x00" name="All" cname="_CP_ON"  />
+      <value value="0xFF" name="Off" cname="_CP_OFF" />
+      <value value="default" name="invalid" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.5" cname="_BORV_25" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG3" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG4" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG5" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x6" name="CONFIG6" wmask="0xFF" bvalue="0x01" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG7" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="84" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+    <pin index="81" name="" />
+    <pin index="82" name="" />
+    <pin index="83" name="" />
+    <pin index="84" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F1220.xml b/src/devices/pic/xml_data/18F1220.xml
new file mode 100644
index 0000000..e46f7f0
--- /dev/null
+++ b/src/devices/pic/xml_data/18F1220.xml
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F1220" document="010264" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x07E0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xF3EB" cchecksum="0xF341" />
+    <checksum protected_blocks="1" bchecksum="0xF5D6" cchecksum="0xF56D" />
+    <checksum protected_blocks="3" bchecksum="0x03D3" cchecksum="0x03BF" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x000FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0xCF" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"     sdcc_cname="_OSC_LP" />
+      <value value="0x01" name="XT"           cname="_XT_OSC"     sdcc_cname="_OSC_XT" />
+      <value value="0x02" name="HS"           cname="_HS_OSC"     sdcc_cname="_OSC_HS" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_RC_OSC"  sdcc_cname="_OSC_EXT_CLKOUT_on_RA6" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"     sdcc_cname="_OSC_EC_CLKOUT" />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"   sdcc_cname="_OSC_EC_PORT" />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC"  sdcc_cname="_OSC_HS_PLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"   sdcc_cname="_OSC_EXT_Port_on_RA6" />
+      <value value="0x08" name="INTRC_IO"     cname="_INTIO2_OSC" sdcc_cname="_OSC_INT_Port_on_RA6_Port_on_RA7" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_INTIO1_OSC" sdcc_cname="_OSC_INT_CLKOUT_on_RA6_Port_on_RA7" />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FSCM_OFF" sdcc_cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FSCM_ON"  sdcc_cname="_FCMEN_ON" />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" sdcc_cname="_WDT_DISABLED_CONTROLLED" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  sdcc_cname="_WDT_ON" />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" sdcc_cname="_WDTPS_1_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" sdcc_cname="_WDTPS_1_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1K"  sdcc_cname="_WDTPS_1_1024" />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2K"  sdcc_cname="_WDTPS_1_2048" />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4K"  sdcc_cname="_WDTPS_1_4096" />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8K"  sdcc_cname="_WDTPS_1_8192" />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16K" sdcc_cname="_WDTPS_1_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32K" sdcc_cname="_WDTPS_1_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x80" >
+    <mask name="MCLRE" value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" sdcc_cname="_MCLRE_MCLR_disabled_RA5_input_en" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  sdcc_cname="_MCLRE_MCLR_enabled_RA5_input_dis" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F1230.xml b/src/devices/pic/xml_data/18F1230.xml
new file mode 100644
index 0000000..043687a
--- /dev/null
+++ b/src/devices/pic/xml_data/18F1230.xml
@@ -0,0 +1,311 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F1230" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1E00" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="022956" datasheet="39758" progsheet="39752" erratas="80308" />
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected_blocks="0"              bchecksum="0xF33E" cchecksum="0xF294" />
+    <checksum protected_blocks="1" bbsize="256" bchecksum="0xF2FE" cchecksum="0xF254" />
+    <checksum protected_blocks="1" bbsize="512" bchecksum="0xF30E" cchecksum="0xF264" />
+    <checksum protected_blocks="2"              bchecksum="0xF30D" cchecksum="0xF263" />
+    <checksum protected_blocks="3"              bchecksum="0xF31B" cchecksum="0xF271" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9.5" max="12.5" nominal="12" />
+  <voltages name="vdd_prog"       min="3"   max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x000FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x00007F" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO2" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO1" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOR_OFF"        />
+      <value value="0x02" name="Software" cname="_BOR_SBORENCTRL" />
+      <value value="0x04" name="On_run"   cname="_BOR_BOACTIVE"   />
+      <value value="0x06" name="On"       cname="_BOR_BOHW"       />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x0E" >
+    <mask name="PWMPIN" value="0x02" >
+      <value value="0x00" name="On"  cname="_PWMPIN_ON"  />
+      <value value="0x02" name="Off" cname="_PWMPIN_OFF" />
+    </mask>
+    <mask name="LPOL"   value="0x04" >
+      <value value="0x00" name="low"  cname="_LPOL_LOW"  />
+      <value value="0x04" name="high" cname="_LPOL_HIGH" />
+    </mask>
+    <mask name="HPOL"   value="0x08" >
+      <value value="0x00" name="low"  cname="_HPOL_LOW"  />
+      <value value="0x08" name="high" cname="_HPOL_HIGH" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="FLTAMX"  value="0x01" >
+      <value value="0x00" name="RA7" cname="_FLTAMX_RA7" />
+      <value value="0x01" name="RA5" cname="_FLTAMX_RA5" />
+    </mask>
+    <mask name="T1OSCMX" value="0x08" >
+      <value value="0x00" name="RB2" cname="_T1OSCMX_HIGH" />
+      <value value="0x08" name="RA6" cname="_T1OSCMX_LOW"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00"    name="256" cname="_BBSIZ_BB256" />
+      <value value="default" name="512" cname="_BBSIZ_BB512" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200/0400:07FF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"            cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200/0400:07FF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"            cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200/0400:07FF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"            cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F1320.xml b/src/devices/pic/xml_data/18F1320.xml
new file mode 100644
index 0000000..d4dd214
--- /dev/null
+++ b/src/devices/pic/xml_data/18F1320.xml
@@ -0,0 +1,280 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F1320" document="010265" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x07C0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xE3EB" cchecksum="0xE341" />
+    <checksum protected_blocks="1" bchecksum="0xE5D5" cchecksum="0xE56C" />
+    <checksum protected_blocks="3" bchecksum="0x03D2" cchecksum="0x03BE" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x001FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0xCF" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"     />
+      <value value="0x01" name="XT"           cname="_XT_OSC"     />
+      <value value="0x02" name="HS"           cname="_HS_OSC"     />
+      <value value="0x03" name="invalid" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"     />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"   />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"   />
+      <value value="0x08" name="INTRC_IO"     cname="_INTIO2_OSC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_INTIO1_OSC" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FSCM_OFF" />
+      <value value="0x40" name="On"  cname="_FSCM_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1K"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2K"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4K"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8K"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16K" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32K" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x80" >
+    <mask name="MCLRE" value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F1330.xml b/src/devices/pic/xml_data/18F1330.xml
new file mode 100644
index 0000000..14130ce
--- /dev/null
+++ b/src/devices/pic/xml_data/18F1330.xml
@@ -0,0 +1,313 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F1330" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1E20" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="022957" datasheet="39758" progsheet="39752" erratas="80308" />
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected_blocks="0"               bchecksum="0xE33E" cchecksum="0xE294" />
+    <checksum protected_blocks="1" bbsize="256"  bchecksum="0xE2FE" cchecksum="0xE254" />
+    <checksum protected_blocks="1" bbsize="512"  bchecksum="0xE30E" cchecksum="0xE264" />
+    <checksum protected_blocks="1" bbsize="1024" bchecksum="0xE31E" cchecksum="0xE274" />
+    <checksum protected_blocks="2"               bchecksum="0xE31D" cchecksum="0xE273" />
+    <checksum protected_blocks="3"               bchecksum="0xF31B" cchecksum="0xE271" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9.5" max="12.5" nominal="12" />
+  <voltages name="vdd_prog"       min="3"   max="5.5"  nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"  nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x001FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x00007F" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO2" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO1" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOR_OFF"        />
+      <value value="0x02" name="Software" cname="_BOR_SBORENCTRL" />
+      <value value="0x04" name="On_run"   cname="_BOR_BOACTIVE"   />
+      <value value="0x06" name="On"       cname="_BOR_BOHW"       />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x0E" >
+    <mask name="PWMPIN" value="0x02" >
+      <value value="0x00" name="On"  cname="_PWMPIN_ON"  />
+      <value value="0x02" name="Off" cname="_PWMPIN_OFF" />
+    </mask>
+    <mask name="LPOL"   value="0x04" >
+      <value value="0x00" name="low"  cname="_LPOL_LOW"  />
+      <value value="0x04" name="high" cname="_LPOL_HIGH" />
+    </mask>
+    <mask name="HPOL"   value="0x08" >
+      <value value="0x00" name="low"  cname="_HPOL_LOW"  />
+      <value value="0x08" name="high" cname="_HPOL_HIGH" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="FLTAMX"  value="0x01" >
+      <value value="0x00" name="RA7" cname="_FLTAMX_RA7" />
+      <value value="0x01" name="RA5" cname="_FLTAMX_RA5" />
+    </mask>
+    <mask name="T1OSCMX" value="0x08" >
+      <value value="0x00" name="RB2" cname="_T1OSCMX_HIGH" />
+      <value value="0x08" name="RA6" cname="_T1OSCMX_LOW"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="256"  cname="_BBSIZ_BB256" />
+      <value value="0x10" name="512"  cname="_BBSIZ_BB512" />
+      <value value="default" name="1024" cname="_BBSIZ_BB1K"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200/0400/0800:0FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200/0400/0800:0FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200/0400/0800:0FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2220.xml b/src/devices/pic/xml_data/18F2220.xml
new file mode 100644
index 0000000..43f6fbc
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2220.xml
@@ -0,0 +1,244 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2220" document="010266" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0580" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xF412" cchecksum="0xF368" />
+    <checksum protected_blocks="1" bchecksum="0xF5E8" cchecksum="0xF59D" />
+    <checksum protected_blocks="2" bchecksum="0xFBE7" cchecksum="0xFB9C" />
+    <checksum protected_blocks="3" bchecksum="0x03E5" cchecksum="0x03EF" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x000FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0xCF" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"     sdcc_cname="_OSC_LP" />
+      <value value="0x01" name="XT"           cname="_XT_OSC"     sdcc_cname="_OSC_XT" />
+      <value value="0x02" name="HS"           cname="_HS_OSC"     sdcc_cname="_OSC_HS" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_RC_OSC"  sdcc_cname="_OSC_EXT_CLKOUT_on_RA6" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"     sdcc_cname="_OSC_EC_CLKOUT" />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"   sdcc_cname="_OSC_EC_PORT" />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC"  sdcc_cname="_OSC_HS_PLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"   sdcc_cname="_OSC_EXT_Port_on_RA6" />
+      <value value="0x08" name="INTRC_IO"     cname="_INTIO2_OSC" sdcc_cname="_OSC_INT_Port_on_RA6_Port_on_RA7" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_INTIO1_OSC" sdcc_cname="_OSC_INT_CLKOUT_on_RA6_Port_on_RA7" />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FSCM_OFF" sdcc_cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FSCM_ON"  sdcc_cname="_FCMEN_ON" />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" sdcc_cname="_WDT_DISABLED_CONTROLLED" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  sdcc_cname="_WDT_ON" />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" sdcc_cname="_WDTPS_1_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" sdcc_cname="_WDTPS_1_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1K"  sdcc_cname="_WDTPS_1_1024" />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2K"  sdcc_cname="_WDTPS_1_2048" />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4K"  sdcc_cname="_WDTPS_1_4096" />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8K"  sdcc_cname="_WDTPS_1_8192" />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16K" sdcc_cname="_WDTPS_1_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32K" sdcc_cname="_WDTPS_1_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_B3" ecnames="_CCP2MX_OFF" sdcc_cname="_CCP2MUX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_C1" ecnames="_CCP2MX_ON"  sdcc_cname="_CCP2MUX_RC1" />
+    </mask>
+    <mask name="PBADEN" value="0x02" >
+      <value value="0x00" name="digital" cname="_PBAD_DIG" sdcc_cname="_PBADEN_PORTB_4_0__digital_I_O_on_REST" />
+      <value value="0x02" name="analog"  cname="_PBAD_ANA" sdcc_cname="_PBADEN_PORTB_4_0__analog_inputs_on_RSET" />
+    </mask>
+    <mask name="MCLRE"  value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" sdcc_cname="_MCLRE_MCLR_Disabled_RE3_Enabled" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  sdcc_cname="_MCLRE_MCLR_Enabled_RE3_Disabled" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2221.xml b/src/devices/pic/xml_data/18F2221.xml
new file mode 100644
index 0000000..f2a58d6
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2221.xml
@@ -0,0 +1,281 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2221" document="024612" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x2160" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x000FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO2" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO1" />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOR_OFF"   />
+      <value value="0x02" name="Software" cname="_BOR_SOFT"  />
+      <value value="0x04" name="On_run"   cname="_BOR_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOR_ON"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x87" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_RC1" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_DIG" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ANA" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x30" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="256" cname="_BBSIZ_BB256" />
+      <value value="default" name="512" cname="_BBSIZ_BB512" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="200/400:7FF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"         cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200/0400:07FF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"            cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200/0400:07FF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"            cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2320.xml b/src/devices/pic/xml_data/18F2320.xml
new file mode 100644
index 0000000..80e8250
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2320.xml
@@ -0,0 +1,271 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2320" document="010267" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0500" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xE412" cchecksum="0xE368" />
+    <checksum protected_blocks="1" bchecksum="0xE5E7" cchecksum="0xE59C" />
+    <checksum protected_blocks="2" bchecksum="0xEBE6" cchecksum="0xEB9B" />
+    <checksum protected_blocks="3" bchecksum="0xF3E4" cchecksum="0xF399" />
+    <checksum protected_blocks="4" bchecksum="0xFBE0" cchecksum="0xFB95" />
+    <checksum protected_blocks="5" bchecksum="0x03D8" cchecksum="0x03E2" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x001FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0xCF" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"     />
+      <value value="0x01" name="XT"           cname="_XT_OSC"     />
+      <value value="0x02" name="HS"           cname="_HS_OSC"     />
+      <value value="0x03" name="invalid" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"     />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"   />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"   />
+      <value value="0x08" name="INTRC_IO"     cname="_INTIO2_OSC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_INTIO1_OSC" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FSCM_OFF" />
+      <value value="0x40" name="On"  cname="_FSCM_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1K"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2K"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4K"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8K"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16K" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32K" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_B3" ecnames="_CCP2MX_OFF" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_C1" ecnames="_CCP2MX_ON"  />
+    </mask>
+    <mask name="PBADEN" value="0x02" >
+      <value value="0x00" name="digital" cname="_PBAD_DIG" />
+      <value value="0x02" name="analog"  cname="_PBAD_ANA" />
+    </mask>
+    <mask name="MCLRE"  value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="1000:17FF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="1800:1FFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="1000:17FF" cname="_WRT2_ON"  />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="1800:1FFF" cname="_WRT3_ON"  />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="1000:17FF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="1800:1FFF" cname="_EBTR3_ON"  />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2321.xml b/src/devices/pic/xml_data/18F2321.xml
new file mode 100644
index 0000000..a016fc7
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2321.xml
@@ -0,0 +1,282 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2321" document="024609" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x2120" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x001FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO2" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO1" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOR_OFF"   />
+      <value value="0x02" name="Software" cname="_BOR_SOFT"  />
+      <value value="0x04" name="On_run"   cname="_BOR_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOR_ON"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x87" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_RC1" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_DIG" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ANA" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x30" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="256"  cname="_BBSIZ_BB256" />
+      <value value="0x10" name="512"  cname="_BBSIZ_BB512" />
+      <value value="default" name="1024" cname="_BBSIZ_BB1K"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200/0400/0800:0FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200/0400/0800:0FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200/0400/0800:0FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"            nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2331.xml b/src/devices/pic/xml_data/18F2331.xml
new file mode 100644
index 0000000..46a8872
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2331.xml
@@ -0,0 +1,256 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2331" document="010268" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x08E0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xE464" cchecksum="0xE3BA" />
+    <checksum protected_blocks="1" bchecksum="0xE640" cchecksum="0xE5F5" />
+    <checksum protected_blocks="3" bchecksum="0x043D" cchecksum="0x0447" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x001FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0xCF" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRC"   />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRTEN_ON"  />
+      <value value="0x01" name="Off" cname="_PWRTEN_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOREN_OFF" />
+      <value value="0x02" name="On"  cname="_BOREN_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x3F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDTEN_OFF" />
+      <value value="0x01" name="On"  cname="_WDTEN_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDPS_32768" />
+    </mask>
+    <mask name="WINEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_WINEN_ON"  />
+      <value value="0x20" name="Off" cname="_WINEN_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x3C" >
+    <mask name="PWMPIN"  value="0x04" >
+      <value value="0x00" name="On"  cname="_PWMPIN_ON"  />
+      <value value="0x04" name="Off" cname="_PWMPIN_OFF" />
+    </mask>
+    <mask name="LPOL"    value="0x08" >
+      <value value="0x00" name="low"  cname="_LPOL_LOW"  />
+      <value value="0x08" name="high" cname="_LPOL_HIGH" />
+    </mask>
+    <mask name="HPOL"    value="0x10" >
+      <value value="0x00" name="low"  cname="_HPOL_LOW"  />
+      <value value="0x10" name="high" cname="_HPOL_HIGH" />
+    </mask>
+    <mask name="T1OSCMX" value="0x20" >
+      <value value="0x00" name="Legacy"    cname="_T1OSCMX_OFF" />
+      <value value="0x20" name="Low Power" cname="_T1OSCMX_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x9D" >
+    <mask name="MCLRE" value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2410.xml b/src/devices/pic/xml_data/18F2410.xml
new file mode 100644
index 0000000..15d6179
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2410.xml
@@ -0,0 +1,268 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2410" document="020415" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x1160" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC"  />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F242.xml b/src/devices/pic/xml_data/18F242.xml
new file mode 100644
index 0000000..d09dd83
--- /dev/null
+++ b/src/devices/pic/xml_data/18F242.xml
@@ -0,0 +1,221 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F242" document="010269" status="NR" alternative="18F2420" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0480" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xC2B4" cchecksum="0xC20A" />
+    <checksum protected_blocks="1" bchecksum="0xC491" cchecksum="0xC437" />
+    <checksum protected_blocks="3" bchecksum="0x028E" cchecksum="0x0289" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    sdcc_cname="_OSC_LP" />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    sdcc_cname="_OSC_XT" />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    sdcc_cname="_OSC_HS" />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    sdcc_cname="_OSC_RC" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    sdcc_cname="_OSC_EC_OSC2_Clock_Out" />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  sdcc_cname="_OSC_EC_OSC2_RA6" />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" sdcc_cname="_OSC_HS_PLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  sdcc_cname="_OSC_RC_OSC2" />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_OFF" sdcc_cname="_CCP2MUX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  sdcc_cname="_CCP2MUX_RC1" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" icnames="_CP2_OFF _CP2_ON _CP3_OFF _CP3_ON"         >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" icnames="_WRT2_OFF _WRT2_ON _WRT3_OFF _WRT3_ON"     >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" icnames="_EBTR2_OFF _EBTR2_ON _EBTR3_OFF _EBTR3_ON" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2420.xml b/src/devices/pic/xml_data/18F2420.xml
new file mode 100644
index 0000000..aba9ace
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2420.xml
@@ -0,0 +1,277 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2420" document="010270" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1140" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC"  />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" cmask="0x80" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" cmask="0x80" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2423.xml b/src/devices/pic/xml_data/18F2423.xml
new file mode 100644
index 0000000..0905f18
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2423.xml
@@ -0,0 +1,274 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2423" document="026428" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1150" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="12.5"  nominal="9" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC"  />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" cmask="0x80" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" cmask="0x80" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2431.xml b/src/devices/pic/xml_data/18F2431.xml
new file mode 100644
index 0000000..f898f99
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2431.xml
@@ -0,0 +1,257 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2431" document="010271" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x08C0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xC488" cchecksum="0xC3DE" />
+    <checksum protected_blocks="1" bchecksum="0xC668" cchecksum="0xC61D" />
+    <checksum protected_blocks="2" bchecksum="0xE465" cchecksum="0xE41A" />
+    <checksum protected_blocks="3" bchecksum="0x0459" cchecksum="0x0463" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0xCF" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRC"   />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRTEN_ON"  />
+      <value value="0x01" name="Off" cname="_PWRTEN_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOREN_OFF" />
+      <value value="0x02" name="On"  cname="_BOREN_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x3F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDTEN_OFF" />
+      <value value="0x01" name="On"  cname="_WDTEN_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDPS_32768" />
+    </mask>
+    <mask name="WINEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_WINEN_ON"  />
+      <value value="0x20" name="Off" cname="_WINEN_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x3C" >
+    <mask name="PWMPIN"  value="0x04" >
+      <value value="0x00" name="On"  cname="_PWMPIN_ON"  />
+      <value value="0x04" name="Off" cname="_PWMPIN_OFF" />
+    </mask>
+    <mask name="LPOL"    value="0x08" >
+      <value value="0x00" name="low"  cname="_LPOL_LOW"  />
+      <value value="0x08" name="high" cname="_LPOL_HIGH" />
+    </mask>
+    <mask name="HPOL"    value="0x10" >
+      <value value="0x00" name="low"  cname="_HPOL_LOW"  />
+      <value value="0x10" name="high" cname="_HPOL_HIGH" />
+    </mask>
+    <mask name="T1OSCMX" value="0x20" >
+      <value value="0x00" name="Legacy"    cname="_T1OSCMX_OFF" />
+      <value value="0x20" name="Low Power" cname="_T1OSCMX_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x9D" >
+    <mask name="MCLRE" value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2439.xml b/src/devices/pic/xml_data/18F2439.xml
new file mode 100644
index 0000000..ad389e3
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2439.xml
@@ -0,0 +1,210 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2439" document="010272" status="NR" alternative="18F2431" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0480" >
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xC2BF" cchecksum="0xC215" />
+    <checksum protected_blocks="1" bchecksum="0xC4A5" cchecksum="0xC43C" />
+    <checksum protected_blocks="2" bchecksum="0xE2A2" cchecksum="0xE239" />
+    <checksum protected_blocks="3" bchecksum="0x029E" cchecksum="0x028A" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC" value="0x07" >
+      <value value="default" name="invalid" />
+      <value value="0x02" name="HS"        cname="_OSC_HS"    />
+      <value value="0x04" name="EC_CLKOUT" cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"     cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"        cname="_OSC_HSPLL" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.5" cname="_BORV_25" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2450.xml b/src/devices/pic/xml_data/18F2450.xml
new file mode 100644
index 0000000..2388a92
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2450.xml
@@ -0,0 +1,299 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2450" document="023497" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x2420" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="8" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x07" cmask="0x00" >
+    <mask name="PLLDIV" value="0x07" >
+      <value value="0x00" name="1"  cname="_PLLDIV_1"  />
+      <value value="0x01" name="2"  cname="_PLLDIV_2"  />
+      <value value="0x02" name="3"  cname="_PLLDIV_3"  />
+      <value value="0x03" name="4"  cname="_PLLDIV_4"  />
+      <value value="0x04" name="5"  cname="_PLLDIV_5"  />
+      <value value="0x05" name="6"  cname="_PLLDIV_6"  />
+      <value value="0x06" name="10" cname="_PLLDIV_10" />
+      <value value="0x07" name="12" cname="_PLLDIV_12" />
+    </mask>
+    <mask name="CPUDIV" value="0x18" >
+      <value value="0x00" name="1" cname="_CPUDIV_OSC1_PLL2" />
+      <value value="0x08" name="2" cname="_CPUDIV_OSC2_PLL3" />
+      <value value="0x10" name="3" cname="_CPUDIV_OSC3_PLL4" />
+      <value value="0x18" name="4" cname="_CPUDIV_OSC4_PLL6" />
+    </mask>
+    <mask name="USBDIV" value="0x20" >
+      <value value="0x00" name="1" cname="_USBDIV_1" />
+      <value value="0x20" name="2" cname="_USBDIV_2" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" cmask="0x00" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="XT"           cname="_FOSC_XT_XT"       />
+      <value value="0x01" name="XT"           cname="_FOSC_XT_XT"       />
+      <value value="0x02" name="XTPLL"        cname="_FOSC_XTPLL"       />
+      <value value="0x03" name="XTPLL"        cname="_FOSC_XTPLL_XT"    />
+      <value value="0x04" name="EC_IO"        cname="_FOSC_ECIO_EC"     />
+      <value value="0x05" name="EC_CLKOUT"    cname="_FOSC_EC_EC"       />
+      <value value="0x06" name="ECPLL_IO"     cname="_FOSC_ECPLLIO_EC"  />
+      <value value="0x07" name="ECPLL_CLKOUT" cname="_FOSC_ECPLL_EC"    />
+      <value value="0x08" name="INTRC_IO"     cname="_FOSC_INTOSCIO_EC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_FOSC_INTOSC_EC"   />
+      <value value="0x0A" name="INTXT"        cname="_FOSC_INTOSC_XT"   />
+      <value value="0x0B" name="INTHS"        cname="_FOSC_INTOSC_HS"   />
+      <value value="0x0C" name="HS"           cname="_FOSC_HS"          />
+      <value value="0x0D" name="HS"           cname="_FOSC_HS"          />
+      <value value="0x0E" name="HSPLL"        cname="_FOSC_HSPLL_HS"    />
+      <value value="0x0F" name="HSPLL"        cname="_FOSC_HSPLL_HS"    />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE"  value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN"  value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOR_OFF"       />
+      <value value="0x02" name="Software" cname="_BOR_SOFT"      />
+      <value value="0x04" name="On_run"   cname="_BOR_ON_ACTIVE" />
+      <value value="0x06" name="On"       cname="_BOR_ON"        />
+    </mask>
+    <mask name="BORV"   value="0x18" >
+      <value value="0x00" name="4.6" cname="_BORV_46" />
+      <value value="0x08" name="4.3" cname="_BORV_43" />
+      <value value="0x10" name="2.8" cname="_BORV_28" />
+      <value value="0x18" name="2.1" cname="_BORV_21" />
+    </mask>
+    <mask name="VREGEN" value="0x20" >
+      <value value="0x00" name="Off" cname="_VREGEN_OFF" />
+      <value value="0x20" name="On"  cname="_VREGEN_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" cmask="0x00" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x08" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x08" >
+      <value value="0x00" name="1024" cname="_BBSIZ_BB1K" />
+      <value value="0x08" name="2048" cname="_BBSIZ_BB2K" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"            cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"            cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"            cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2455.xml b/src/devices/pic/xml_data/18F2455.xml
new file mode 100644
index 0000000..7097218
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2455.xml
@@ -0,0 +1,288 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2455" document="010273" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1260" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="48" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4"  end="16" vdd_min="3" vdd_max="5.5" />
+    <frequency start="16" end="25"  vdd_min="4" vdd_max="5.5" />
+    <frequency start="25"  end="48" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x005FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" >
+    <mask name="PLLDIV" value="0x07" >
+      <value value="0x00" name="1"  cname="_PLLDIV_1"  sdcc_cname="_PLLDIV_NO_DIVIDE__4MHZ_INPUT_" />
+      <value value="0x01" name="2"  cname="_PLLDIV_2"  sdcc_cname="_PLLDIV_DIVIDE_BY_2__8MHZ_INPUT_" />
+      <value value="0x02" name="3"  cname="_PLLDIV_3"  sdcc_cname="_PLLDIV_DIVIDE_BY_3__12MHZ_INPUT_" />
+      <value value="0x03" name="4"  cname="_PLLDIV_4"  sdcc_cname="_PLLDIV_DIVIDE_BY_4__16MHZ_INPUT_" />
+      <value value="0x04" name="5"  cname="_PLLDIV_5"  sdcc_cname="_PLLDIV_DIVIDE_BY_5__20MHZ_INPUT_" />
+      <value value="0x05" name="6"  cname="_PLLDIV_6"  sdcc_cname="_PLLDIV_DIVIDE_BY_6__24MHZ_INPUT_" />
+      <value value="0x06" name="10" cname="_PLLDIV_10" sdcc_cname="_PLLDIV_DIVIDE_BY_10__40MHZ_INPUT_" />
+      <value value="0x07" name="12" cname="_PLLDIV_12" sdcc_cname="_PLLDIV_DIVIDE_BY_12__48MHZ_INPUT_" />
+    </mask>
+    <mask name="CPUDIV" value="0x18" >
+      <value value="0x00" name="1" cname="_CPUDIV_OSC1_PLL2" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2_" />
+      <value value="0x08" name="2" cname="_CPUDIV_OSC2_PLL3" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___2__96MHZ_PLL_SRC___3_" />
+      <value value="0x10" name="3" cname="_CPUDIV_OSC3_PLL4" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___3__96MHZ_PLL_SRC___4_" />
+      <value value="0x18" name="4" cname="_CPUDIV_OSC4_PLL6" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___4__96MHZ_PLL_SRC___6_" />
+    </mask>
+    <mask name="USBDIV" value="0x20" >
+      <value value="0x00" name="1" cname="_USBDIV_1" sdcc_cname="_USBPLL_CLOCK_SRC_FROM_OSC1_OSC2" />
+      <value value="0x20" name="2" cname="_USBDIV_2" sdcc_cname="_USBPLL_CLOCK_SRC_FROM_96MHZ_PLL_2" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x05" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="XT"           cname="_FOSC_XT_XT"       sdcc_cname="_OSC_XT__USB_XT" />
+      <value value="0x01" name="XT"           cname="_FOSC_XT_XT"       sdcc_cname="_OSC_XT__USB_XT" />
+      <value value="0x02" name="XTPLL"        cname="_FOSC_XTPLL"       sdcc_cname="_OSC_XT__XT_PLL__USB_XT" />
+      <value value="0x03" name="XTPLL"        cname="_FOSC_XTPLL_XT"    sdcc_cname="_OSC_XT__XT_PLL__USB_XT" />
+      <value value="0x04" name="EC_IO"        cname="_FOSC_ECIO_EC"     sdcc_cname="_OSC_EC__EC_RA6__USB_EC" />
+      <value value="0x05" name="EC_CLKOUT"    cname="_FOSC_EC_EC"       sdcc_cname="_OSC_EC__EC_CLKO_RA6___USB_EC" />
+      <value value="0x06" name="ECPLL_IO"     cname="_FOSC_ECPLLIO_EC"  sdcc_cname="_OSC_EC__EC_PLL__EC_PLL_RA6__USB_EC" />
+      <value value="0x07" name="ECPLL_CLKOUT" cname="_FOSC_ECPLL_EC"    sdcc_cname="_OSC_EC__EC_PLL__EC_PLL_CLKO_RA6___USB_EC" />
+      <value value="0x08" name="INTRC_IO"     cname="_FOSC_INTOSCIO_EC" sdcc_cname="_OSC_INTOSC__INTOSC_RA6__USB_EC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_FOSC_INTOSC_EC"   sdcc_cname="_OSC_INTOSC__INTOSC_CLK0_RA6___USB_EC" />
+      <value value="0x0A" name="INTXT"        cname="_FOSC_INTOSC_XT"   sdcc_cname="_OSC_INTOSC__USB_XT" />
+      <value value="0x0B" name="INTHS"        cname="_FOSC_INTOSC_HS"   sdcc_cname="_OSC_INTOSC__USB_HS" />
+      <value value="0x0C" name="HS"           cname="_FOSC_HS"          sdcc_cname="_OSC_HS__USB_HS" />
+      <value value="0x0D" name="HS"           cname="_FOSC_HS"          sdcc_cname="_OSC_HS__USB_HS" />
+      <value value="0x0E" name="HSPLL"        cname="_FOSC_HSPLL_HS"    sdcc_cname="_OSC_HS__HS_PLL__USB_HS" />
+      <value value="0x0F" name="HSPLL"        cname="_FOSC_HSPLL_HS"    sdcc_cname="_OSC_HS__HS_PLL__USB_HS" />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEM_OFF" sdcc_cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEM_ON"  sdcc_cname="_FCMEN_ON" />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" cmask="0x18" >
+    <mask name="PWRTE"  value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN"  value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOR_OFF"       sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="Software" cname="_BOR_SOFT"      sdcc_cname="_BODEN_CONTROLLED_WITH_SBOREN_BIT" />
+      <value value="0x04" name="On_run"   cname="_BOR_ON_ACTIVE" sdcc_cname="_BODEN_ON_WHILE_ACTIVE" />
+      <value value="0x06" name="On"       cname="_BOR_ON"        sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"   value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x08" name="4.2" cname="_BORV_1" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x10" name="2.7" cname="_BORV_2" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x18" name="2.0" cname="_BORV_3" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+    <mask name="VREGEN" value="0x20" >
+      <value value="0x00" name="Off" cname="_VREGEN_OFF" />
+      <value value="0x20" name="On"  cname="_VREGEN_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" sdcc_cname="_WDT_DISABLED_CONTROLLED" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  sdcc_cname="_WDT_ON" />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   sdcc_cname="_WDTPS_1_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   sdcc_cname="_WDTPS_1_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   sdcc_cname="_WDTPS_1_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  sdcc_cname="_WDTPS_1_1024" />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  sdcc_cname="_WDTPS_1_2048" />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  sdcc_cname="_WDTPS_1_4096" />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  sdcc_cname="_WDTPS_1_8192" />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" sdcc_cname="_WDTPS_1_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" sdcc_cname="_WDTPS_1_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_OFF" sdcc_cname="_CCP2MUX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  sdcc_cname="_CCP2MUX_RC1" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" sdcc_cname="_MCLRE_MCLR_OFF_RE3_ON" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  sdcc_cname="_MCLRE_MCLR_ON_RE3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xDF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" sdcc_cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  sdcc_cname="_STVR_ON" />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" sdcc_cname="_ENHCPU_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  sdcc_cname="_ENHCPU_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  sdcc_cname="_CP_2_ON" />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" sdcc_cname="_CP_2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON"  sdcc_cname="_WRT_2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" sdcc_cname="_WRT_2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" cmask="0xC0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  sdcc_cname="_EBTR_2_ON" />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" sdcc_cname="_EBTR_2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F248.xml b/src/devices/pic/xml_data/18F248.xml
new file mode 100644
index 0000000..973ba90
--- /dev/null
+++ b/src/devices/pic/xml_data/18F248.xml
@@ -0,0 +1,216 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F248" document="010274" status="NR" alternative="18F2480" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0800" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xC2B3" cchecksum="0xC209" />
+    <checksum protected_blocks="1" bchecksum="0xC48F" cchecksum="0xC435" />
+    <checksum protected_blocks="3" bchecksum="0x028C" cchecksum="0x0287" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    sdcc_cname="_OSC_LP" />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    sdcc_cname="_OSC_XT" />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    sdcc_cname="_OSC_HS" />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    sdcc_cname="_OSC_RC" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    sdcc_cname="_OSC_EC_OSC2_Clock_Out" />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  sdcc_cname="_OSC_EC_OSC2_RA6" />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" sdcc_cname="_OSC_HS_PLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  sdcc_cname="_OSC_RC_OSC2" />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x0C" name="2.0" cname="_BORV_25" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2480.xml b/src/devices/pic/xml_data/18F2480.xml
new file mode 100644
index 0000000..7f8929b
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2480.xml
@@ -0,0 +1,283 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2480" document="010612" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1AE0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" cmask="0x0F" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"    />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"    />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO67"  />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRCIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" cmask="0x06" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"        />
+      <value value="0x02" name="Software" cname="_BOREN_SBORENCTRL" />
+      <value value="0x04" name="On_run"   cname="_BOREN_BOACTIVE"   />
+      <value value="0x06" name="On"       cname="_BOREN_BOHW"       />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" cmask="0x02" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x10" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x10" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x10" name="2048" cname="_BBSIZ_2048" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"            cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"            cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"            cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F24J10.xml b/src/devices/pic/xml_data/18F24J10.xml
new file mode 100644
index 0000000..c4ae257
--- /dev/null
+++ b/src/devices/pic/xml_data/18F24J10.xml
@@ -0,0 +1,182 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F24J10" status="IP" memory_technology="FLASH" architecture="18J" id="0x1D00" id_low_power="0x1D40">
+
+<!--* Documents ************************************************************-->
+  <documents webpage="024621" datasheet="39682" progsheet="39687" erratas="80265 80269" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="2.7" vdd_max="3.6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="2.7" />
+    <frequency start="4" end="40" vdd_min="2.35" vdd_max="2.7" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="2.7"   max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="2.7"   max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="2.7"   max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FF7" word_write_align="32" word_erase_align="512" />
+  <memory name="config"    start="0x003FF8" end="0x003FFF" />
+  <memory name="device_id" start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0x7F" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x07" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0xFF" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0xF8" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F2510.xml b/src/devices/pic/xml_data/18F2510.xml
new file mode 100644
index 0000000..1950de1
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2510.xml
@@ -0,0 +1,298 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2510" document="010416" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x1120" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC"  />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON"  />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON"  />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON"  />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2515.xml b/src/devices/pic/xml_data/18F2515.xml
new file mode 100644
index 0000000..89960ae
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2515.xml
@@ -0,0 +1,255 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2515" document="010275" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x0CE0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00BFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC"  />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON"  />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F252.xml b/src/devices/pic/xml_data/18F252.xml
new file mode 100644
index 0000000..b1d4153
--- /dev/null
+++ b/src/devices/pic/xml_data/18F252.xml
@@ -0,0 +1,246 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F252" document="010276" status="NR" alternative="18F2520" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0400" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0x82D8" cchecksum="0x822E" />
+    <checksum protected_blocks="1" bchecksum="0x84B7" cchecksum="0x845D" />
+    <checksum protected_blocks="3" bchecksum="0xC2B4" cchecksum="0xC25A" />
+    <checksum protected_blocks="5" bchecksum="0x02A8" cchecksum="0x02A3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    sdcc_cname="_OSC_LP" />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    sdcc_cname="_OSC_XT" />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    sdcc_cname="_OSC_HS" />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    sdcc_cname="_OSC_RC" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    sdcc_cname="_OSC_EC_OSC2_Clock_Out" />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  sdcc_cname="_OSC_EC_OSC2_RA6" />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" sdcc_cname="_OSC_HS_PLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  sdcc_cname="_OSC_RC_OSC2" />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_OFF" sdcc_cname="_CCP2MUX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  sdcc_cname="_CCP2MUX_RC1" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  sdcc_cname="_CP_2_ON" />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" sdcc_cname="_CP_2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON"  sdcc_cname="_CP_3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" sdcc_cname="_CP_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON"  sdcc_cname="_WRT_2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" sdcc_cname="_WRT_2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON"  sdcc_cname="_WRT_3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" sdcc_cname="_WRT_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  sdcc_cname="_EBTR_2_ON" />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" sdcc_cname="_EBTR_2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON"  sdcc_cname="_EBTR_3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" sdcc_cname="_EBTR_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2520.xml b/src/devices/pic/xml_data/18F2520.xml
new file mode 100644
index 0000000..3c77df0
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2520.xml
@@ -0,0 +1,307 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2520" document="010277" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1100" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC"  />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" cmask="0x80" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON"  />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON"  />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" cmask="0x80" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON"  />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2523.xml b/src/devices/pic/xml_data/18F2523.xml
new file mode 100644
index 0000000..6a92c8d
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2523.xml
@@ -0,0 +1,298 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2523" document="026427" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1110" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="12.5" nominal="9" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"   />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC"  />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" cmask="0x80" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON"  />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON"  />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" cmask="0x80" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON"  />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2525.xml b/src/devices/pic/xml_data/18F2525.xml
new file mode 100644
index 0000000..2ff5bc7
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2525.xml
@@ -0,0 +1,264 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2525" document="010278" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0CC0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00BFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC"  />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" cmask="0x80" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON"  />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" cmask="0x80" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2539.xml b/src/devices/pic/xml_data/18F2539.xml
new file mode 100644
index 0000000..0f4a17a
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2539.xml
@@ -0,0 +1,222 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2539" document="010279" status="NR" alternative="18F2431" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0400" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xA2BF" cchecksum="0xA215" />
+    <checksum protected_blocks="1" bchecksum="0xA4A5" cchecksum="0xA43C" />
+    <checksum protected_blocks="3" bchecksum="0xE2A2" cchecksum="0xE239" />
+    <checksum protected_blocks="4" bchecksum="0x029E" cchecksum="0x028A" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x005FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC" value="0x07" >
+      <value value="default" name="invalid" />
+      <value value="0x02" name="HS"        cname="_OSC_HS"    />
+      <value value="0x04" name="EC_CLKOUT" cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"     cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"        cname="_OSC_HSPLL" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.5" cname="_BORV_25" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2550.xml b/src/devices/pic/xml_data/18F2550.xml
new file mode 100644
index 0000000..21ab9ae
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2550.xml
@@ -0,0 +1,292 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2550" document="010280" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1240" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="48" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4"  end="16" vdd_min="3" vdd_max="5.5" />
+    <frequency start="16" end="25"  vdd_min="4" vdd_max="5.5" />
+    <frequency start="25"  end="48" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" >
+    <mask name="PLLDIV" value="0x07" >
+      <value value="0x00" name="1"  cname="_PLLDIV_1"  sdcc_cname="_PLLDIV_NO_DIVIDE__4MHZ_INPUT_" />
+      <value value="0x01" name="2"  cname="_PLLDIV_2"  sdcc_cname="_PLLDIV_DIVIDE_BY_2__8MHZ_INPUT_" />
+      <value value="0x02" name="3"  cname="_PLLDIV_3"  sdcc_cname="_PLLDIV_DIVIDE_BY_3__12MHZ_INPUT_" />
+      <value value="0x03" name="4"  cname="_PLLDIV_4"  sdcc_cname="_PLLDIV_DIVIDE_BY_4__16MHZ_INPUT_" />
+      <value value="0x04" name="5"  cname="_PLLDIV_5"  sdcc_cname="_PLLDIV_DIVIDE_BY_5__20MHZ_INPUT_" />
+      <value value="0x05" name="6"  cname="_PLLDIV_6"  sdcc_cname="_PLLDIV_DIVIDE_BY_6__24MHZ_INPUT_" />
+      <value value="0x06" name="10" cname="_PLLDIV_10" sdcc_cname="_PLLDIV_DIVIDE_BY_10__40MHZ_INPUT_" />
+      <value value="0x07" name="12" cname="_PLLDIV_12" sdcc_cname="_PLLDIV_DIVIDE_BY_12__48MHZ_INPUT_" />
+    </mask>
+    <mask name="CPUDIV" value="0x18" >
+      <value value="0x00" name="1" cname="_CPUDIV_OSC1_PLL2" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2_" />
+      <value value="0x08" name="2" cname="_CPUDIV_OSC2_PLL3" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___2__96MHZ_PLL_SRC___3_" />
+      <value value="0x10" name="3" cname="_CPUDIV_OSC3_PLL4" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___3__96MHZ_PLL_SRC___4_" />
+      <value value="0x18" name="4" cname="_CPUDIV_OSC4_PLL6" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___4__96MHZ_PLL_SRC___6_" />
+    </mask>
+    <mask name="USBDIV" value="0x20" >
+      <value value="0x00" name="1" cname="_USBDIV_1" sdcc_cname="_USBPLL_CLOCK_SRC_FROM_OSC1_OSC2" />
+      <value value="0x20" name="2" cname="_USBDIV_2" sdcc_cname="_USBPLL_CLOCK_SRC_FROM_96MHZ_PLL_2" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x05" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="XT"           cname="_FOSC_XT_XT"       sdcc_cname="_OSC_XT__USB_XT" />
+      <value value="0x01" name="XT"           cname="_FOSC_XT_XT"       sdcc_cname="_OSC_XT__USB_XT" />
+      <value value="0x02" name="XTPLL"        cname="_FOSC_XTPLL"       sdcc_cname="_OSC_XT__XT_PLL__USB_XT" />
+      <value value="0x03" name="XTPLL"        cname="_FOSC_XTPLL_XT"    sdcc_cname="_OSC_XT__XT_PLL__USB_XT" />
+      <value value="0x04" name="EC_IO"        cname="_FOSC_ECIO_EC"     sdcc_cname="_OSC_EC__EC_RA6__USB_EC" />
+      <value value="0x05" name="EC_CLKOUT"    cname="_FOSC_EC_EC"       sdcc_cname="_OSC_EC__EC_CLKO_RA6___USB_EC" />
+      <value value="0x06" name="ECPLL_IO"     cname="_FOSC_ECPLLIO_EC"  sdcc_cname="_OSC_EC__EC_PLL__EC_PLL_RA6__USB_EC" />
+      <value value="0x07" name="ECPLL_CLKOUT" cname="_FOSC_ECPLL_EC"    sdcc_cname="_OSC_EC__EC_PLL__EC_PLL_CLKO_RA6___USB_EC" />
+      <value value="0x08" name="INTRC_IO"     cname="_FOSC_INTOSCIO_EC" sdcc_cname="_OSC_INTOSC__INTOSC_RA6__USB_EC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_FOSC_INTOSC_EC"   sdcc_cname="_OSC_INTOSC__INTOSC_CLK0_RA6___USB_EC" />
+      <value value="0x0A" name="INTXT"        cname="_FOSC_INTOSC_XT"   sdcc_cname="_OSC_INTOSC__USB_XT" />
+      <value value="0x0B" name="INTHS"        cname="_FOSC_INTOSC_HS"   sdcc_cname="_OSC_INTOSC__USB_HS" />
+      <value value="0x0C" name="HS"           cname="_FOSC_HS"          sdcc_cname="_OSC_HS__USB_HS" />
+      <value value="0x0D" name="HS"           cname="_FOSC_HS"          sdcc_cname="_OSC_HS__USB_HS" />
+      <value value="0x0E" name="HSPLL"        cname="_FOSC_HSPLL_HS"    sdcc_cname="_OSC_HS__HS_PLL__USB_HS" />
+      <value value="0x0F" name="HSPLL"        cname="_FOSC_HSPLL_HS"    sdcc_cname="_OSC_HS__HS_PLL__USB_HS" />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEM_OFF" sdcc_cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEM_ON"  sdcc_cname="_FCMEN_ON" />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE"  value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN"  value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOR_OFF"       sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="Software" cname="_BOR_SOFT"      sdcc_cname="_BODEN_CONTROLLED_WITH_SBOREN_BIT" />
+      <value value="0x04" name="On_run"   cname="_BOR_ON_ACTIVE" sdcc_cname="_BODEN_ON_WHILE_ACTIVE" />
+      <value value="0x06" name="On"       cname="_BOR_ON"        sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"   value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x08" name="4.2" cname="_BORV_1" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x10" name="2.7" cname="_BORV_2" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x18" name="2.0" cname="_BORV_3" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+    <mask name="VREGEN" value="0x20" >
+      <value value="0x00" name="Off" cname="_VREGEN_OFF" />
+      <value value="0x20" name="On"  cname="_VREGEN_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" sdcc_cname="_WDT_DISABLED_CONTROLLED" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  sdcc_cname="_WDT_ON" />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   sdcc_cname="_WDTPS_1_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   sdcc_cname="_WDTPS_1_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   sdcc_cname="_WDTPS_1_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  sdcc_cname="_WDTPS_1_1024" />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  sdcc_cname="_WDTPS_1_2048" />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  sdcc_cname="_WDTPS_1_4096" />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  sdcc_cname="_WDTPS_1_8192" />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" sdcc_cname="_WDTPS_1_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" sdcc_cname="_WDTPS_1_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_OFF" sdcc_cname="_CCP2MUX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  sdcc_cname="_CCP2MUX_RC1" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" sdcc_cname="_MCLRE_MCLR_OFF_RE3_ON" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  sdcc_cname="_MCLRE_MCLR_ON_RE3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xDF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" sdcc_cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  sdcc_cname="_STVR_ON" />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" sdcc_cname="_ENHCPU_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  sdcc_cname="_ENHCPU_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  sdcc_cname="_CP_2_ON" />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" sdcc_cname="_CP_2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON"  sdcc_cname="_CP_3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" sdcc_cname="_CP_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON"  sdcc_cname="_WRT_2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" sdcc_cname="_WRT_2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON"  sdcc_cname="_WRT_3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" sdcc_cname="_WRT_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" cmask="0x40" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  sdcc_cname="_EBTR_2_ON" />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" sdcc_cname="_EBTR_2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON"  sdcc_cname="_EBTR_3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" sdcc_cname="_EBTR_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F258.xml b/src/devices/pic/xml_data/18F258.xml
new file mode 100644
index 0000000..bb27ca5
--- /dev/null
+++ b/src/devices/pic/xml_data/18F258.xml
@@ -0,0 +1,241 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F258" document="010281" status="NR" alternative="18F2580" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0840" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0x82D7" cchecksum="0x822D" />
+    <checksum protected_blocks="1" bchecksum="0x84B5" cchecksum="0x845B" />
+    <checksum protected_blocks="3" bchecksum="0xC2B2" cchecksum="0xC258" />
+    <checksum protected_blocks="5" bchecksum="0x02A6" cchecksum="0x02A1" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    sdcc_cname="_OSC_LP" />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    sdcc_cname="_OSC_XT" />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    sdcc_cname="_OSC_HS" />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    sdcc_cname="_OSC_RC" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    sdcc_cname="_OSC_EC_OSC2_Clock_Out" />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  sdcc_cname="_OSC_EC_OSC2_RA6" />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" sdcc_cname="_OSC_HS_PLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  sdcc_cname="_OSC_RC_OSC2" />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  sdcc_cname="_CP_2_ON" />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" sdcc_cname="_CP_2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON"  sdcc_cname="_CP_3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" sdcc_cname="_CP_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON"  sdcc_cname="_WRT_2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" sdcc_cname="_WRT_2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON"  sdcc_cname="_WRT_3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" sdcc_cname="_WRT_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  sdcc_cname="_EBTR_2_ON" />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" sdcc_cname="_EBTR_2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON"  sdcc_cname="_EBTR_3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" sdcc_cname="_EBTR_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2580.xml b/src/devices/pic/xml_data/18F2580.xml
new file mode 100644
index 0000000..6721af5
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2580.xml
@@ -0,0 +1,307 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2580" document="010613" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1AC0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRCIO7" />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"        />
+      <value value="0x02" name="Software" cname="_BOREN_SBORENCTRL" />
+      <value value="0x04" name="On_run"   cname="_BOREN_BOACTIVE"   />
+      <value value="0x06" name="On"       cname="_BOREN_BOHW"       />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x10" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x10" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x10" name="2048" cname="_BBSIZ_2048" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"            cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"            cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"            cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2585.xml b/src/devices/pic/xml_data/18F2585.xml
new file mode 100644
index 0000000..12b38f1
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2585.xml
@@ -0,0 +1,266 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2585" document="010282" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0EE0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00BFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRCIO7" />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"   />
+      <value value="0x02" name="Software" cname="_BOREN_SBORENCTRL"  />
+      <value value="0x04" name="On_run"   cname="_BOREN_BOACTIVE" />
+      <value value="0x06" name="On"       cname="_BOREN_BOHW"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x30" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x10" name="2048" cname="_BBSIZ_2048" />
+      <value value="0x20" name="4096" cname="_BBSIZ_4096" />
+      <value value="0x30" name="4096" cname="_BBSIZ_4096" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F25J10.xml b/src/devices/pic/xml_data/18F25J10.xml
new file mode 100644
index 0000000..57f37d4
--- /dev/null
+++ b/src/devices/pic/xml_data/18F25J10.xml
@@ -0,0 +1,182 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F25J10" status="IP" memory_technology="FLASH" architecture="18J" id="0x1C00" id_low_power="0x1C40">
+
+<!--* Documents ************************************************************-->
+  <documents webpage="024622" datasheet="39682" progsheet="39687" erratas="80265 80269" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="2.7" vdd_max="3.6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="2.7" />
+    <frequency start="4" end="40" vdd_min="2.35" vdd_max="2.7" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="2.7"   max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="2.7"   max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="2.7"   max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x007FF7" word_write_align="32" word_erase_align="512" />
+  <memory name="config"       start="0x007FF8" end="0x007FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0x7F" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x07" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0xFF" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0xF8" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic ssop" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F2610.xml b/src/devices/pic/xml_data/18F2610.xml
new file mode 100644
index 0000000..e38c6d2
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2610.xml
@@ -0,0 +1,267 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2610" document="010283" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x0CA0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2620.xml b/src/devices/pic/xml_data/18F2620.xml
new file mode 100644
index 0000000..7c25f21
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2620.xml
@@ -0,0 +1,265 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2620" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0C80" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010284" datasheet="39626" progsheet="39622" erratas="80222 80200 80224 80282" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.6" cname="_BORV_0" sdcc_cname="_BORV_46" />
+      <value value="0x08" name="4.3" cname="_BORV_1" sdcc_cname="_BORV_43" />
+      <value value="0x10" name="2.8" cname="_BORV_2" sdcc_cname="_BORV_28" />
+      <value value="0x18" name="2.1" cname="_BORV_3" sdcc_cname="_BORV_21" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" sdcc_cname="_WDT_DISABLED_CONTROLLED" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   sdcc_cname="_WDTPS_1_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   sdcc_cname="_WDTPS_1_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   sdcc_cname="_WDTPS_1_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  sdcc_cname="_WDTPS_1_1024" />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  sdcc_cname="_WDTPS_1_2048" />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  sdcc_cname="_WDTPS_1_4096" />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  sdcc_cname="_WDTPS_1_8192" />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" sdcc_cname="_WDTPS_1_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" sdcc_cname="_WDTPS_1_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" sdcc_cname="_CCP2MUX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC"  sdcc_cname="_CCP2MUX_RC1" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" sdcc_cname="_MCLRE_MCLR_OFF_RE3_ON" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  sdcc_cname="_MCLRE_MCLR_ON_RE3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" sdcc_cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  sdcc_cname="_STVR_ON" />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  sdcc_cname="_CP_2_ON" />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" sdcc_cname="_CP_2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  sdcc_cname="_CP_3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" sdcc_cname="_CP_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON"  sdcc_cname="_WRT_2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" sdcc_cname="_WRT_2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON"  sdcc_cname="_WRT_3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" sdcc_cname="_WRT_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  sdcc_cname="_EBTR_2_ON" />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" sdcc_cname="_EBTR_2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON"  sdcc_cname="_EBTR_3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" sdcc_cname="_EBTR_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2680.xml b/src/devices/pic/xml_data/18F2680.xml
new file mode 100644
index 0000000..2dcd013
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2680.xml
@@ -0,0 +1,278 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2680" document="010285" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0EC0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRCIO7" />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"   />
+      <value value="0x02" name="Software" cname="_BOREN_SBORENCTRL"  />
+      <value value="0x04" name="On_run"   cname="_BOREN_BOACTIVE" />
+      <value value="0x06" name="On"       cname="_BOREN_BOHW"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x30" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x10" name="2048" cname="_BBSIZ_2048" />
+      <value value="0x20" name="4096" cname="_BBSIZ_4096" />
+      <value value="0x30" name="4096" cname="_BBSIZ_4096" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2682.xml b/src/devices/pic/xml_data/18F2682.xml
new file mode 100644
index 0000000..8c13b2d
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2682.xml
@@ -0,0 +1,284 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2682" document="026329" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x2700" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x013FFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRCIO7" />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"   />
+      <value value="0x02" name="Software" cname="_BOREN_SBORENCTRL"  />
+      <value value="0x04" name="On_run"   cname="_BOREN_BOACTIVE" />
+      <value value="0x06" name="On"       cname="_BOREN_BOHW"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x30" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x10" name="2048" cname="_BBSIZ_2048" />
+      <value value="0x20" name="4096" cname="_BBSIZ_4096" />
+      <value value="0x30" name="4096" cname="_BBSIZ_4096" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+    <mask name="CP_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_CP4_ON" />
+      <value value="0x10" name="Off"         cname="_CP4_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+    <mask name="WRT_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_WRT4_ON" />
+      <value value="0x10" name="Off"         cname="_WRT4_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+    <mask name="EBTR_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_EBTR4_ON" />
+      <value value="0x10" name="Off"         cname="_EBTR4_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F2685.xml b/src/devices/pic/xml_data/18F2685.xml
new file mode 100644
index 0000000..bca6818
--- /dev/null
+++ b/src/devices/pic/xml_data/18F2685.xml
@@ -0,0 +1,296 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F2685" document="026328" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x2720" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x017FFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRCIO7" />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"   />
+      <value value="0x02" name="Software" cname="_BOREN_SBORENCTRL"  />
+      <value value="0x04" name="On_run"   cname="_BOREN_BOACTIVE" />
+      <value value="0x06" name="On"       cname="_BOREN_BOHW"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x30" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x10" name="2048" cname="_BBSIZ_2048" />
+      <value value="0x20" name="4096" cname="_BBSIZ_4096" />
+      <value value="0x30" name="4096" cname="_BBSIZ_4096" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x3F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+    <mask name="CP_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_CP4_ON" />
+      <value value="0x10" name="Off"         cname="_CP4_OFF" />
+    </mask>
+    <mask name="CP_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_CP5_ON" />
+      <value value="0x20" name="Off"         cname="_CP5_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x3F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+    <mask name="WRT_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_WRT4_ON" />
+      <value value="0x10" name="Off"         cname="_WRT4_OFF" />
+    </mask>
+    <mask name="WRT_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_WRT5_ON" />
+      <value value="0x20" name="Off"         cname="_WRT5_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x3F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+    <mask name="EBTR_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_EBTR4_ON" />
+      <value value="0x10" name="Off"         cname="_EBTR4_OFF" />
+    </mask>
+    <mask name="EBTR_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_EBTR5_ON" />
+      <value value="0x20" name="Off"         cname="_EBTR5_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4220.xml b/src/devices/pic/xml_data/18F4220.xml
new file mode 100644
index 0000000..f1c19c7
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4220.xml
@@ -0,0 +1,351 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4220" document="010286" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x05A0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xF412" cchecksum="0xF368" />
+    <checksum protected_blocks="1" bchecksum="0xF5E8" cchecksum="0xF59D" />
+    <checksum protected_blocks="2" bchecksum="0xFBE7" cchecksum="0xFB9C" />
+    <checksum protected_blocks="3" bchecksum="0x03E5" cchecksum="0x03EF" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x000FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0xCF" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"     />
+      <value value="0x01" name="XT"           cname="_XT_OSC"     />
+      <value value="0x02" name="HS"           cname="_HS_OSC"     />
+      <value value="0x03" name="invalid" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"     />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"   />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"   />
+      <value value="0x08" name="INTRC_IO"     cname="_INTIO2_OSC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_INTIO1_OSC" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FSCM_OFF" />
+      <value value="0x40" name="On"  cname="_FSCM_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1K"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2K"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4K"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8K"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16K" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32K" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_B3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_C1" />
+    </mask>
+    <mask name="PBADEN" value="0x02" >
+      <value value="0x00" name="digital" cname="_PBAD_DIG" />
+      <value value="0x02" name="analog"  cname="_PBAD_ANA" />
+    </mask>
+    <mask name="MCLRE"  value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4221.xml b/src/devices/pic/xml_data/18F4221.xml
new file mode 100644
index 0000000..d4a7e11
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4221.xml
@@ -0,0 +1,368 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4221" document="024611" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x2140" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x000FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO2" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO1" />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOR_OFF"   />
+      <value value="0x02" name="Software" cname="_BOR_SOFT"  />
+      <value value="0x04" name="On_run"   cname="_BOR_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOR_ON"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x87" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_RC1" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_DIG" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ANA" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x38" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="ICPORT" value="0x08" >
+      <value value="0x00" name="Off" cname="_ICPORT_OFF" />
+      <value value="0x08" name="On"  cname="_ICPORT_ON" />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="256" cname="_BBSIZ_BB256" />
+      <value value="0x10" name="512" cname="_BBSIZ_BB512" />
+      <value value="0x20" name="512" cname="_BBSIZ_BB512" />
+      <value value="0x30" name="512" cname="_BBSIZ_BB512" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200/0400:07FF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"            cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200/0400:07FF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"            cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200/0400:07FF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"            cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4320.xml b/src/devices/pic/xml_data/18F4320.xml
new file mode 100644
index 0000000..734bb11
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4320.xml
@@ -0,0 +1,377 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4320" document="010287" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0520" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xE412" cchecksum="0xE368" />
+    <checksum protected_blocks="1" bchecksum="0xE5E7" cchecksum="0xE59C" />
+    <checksum protected_blocks="2" bchecksum="0xEBE6" cchecksum="0xEB9B" />
+    <checksum protected_blocks="3" bchecksum="0xF3E4" cchecksum="0xF399" />
+    <checksum protected_blocks="4" bchecksum="0xFBE0" cchecksum="0xFB95" />
+    <checksum protected_blocks="5" bchecksum="0x03D8" cchecksum="0x03E2" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x001FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0xCF" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"     />
+      <value value="0x01" name="XT"           cname="_XT_OSC"     />
+      <value value="0x02" name="HS"           cname="_HS_OSC"     />
+      <value value="0x03" name="invalid" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"     />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"   />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"   />
+      <value value="0x08" name="INTRC_IO"     cname="_INTIO2_OSC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_INTIO1_OSC" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FSCM_OFF" />
+      <value value="0x40" name="On"  cname="_FSCM_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1K"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2K"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4K"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8K"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16K" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32K" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_B3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_C1" />
+    </mask>
+    <mask name="PBADEN" value="0x02" >
+      <value value="0x00" name="digital" cname="_PBAD_DIG" />
+      <value value="0x02" name="analog"  cname="_PBAD_ANA" />
+    </mask>
+    <mask name="MCLRE"  value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="1000:17FF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="1800:1FFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="1000:17FF" cname="_WRT2_ON"  />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="1800:1FFF" cname="_WRT3_ON"  />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="1000:17FF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="1800:1FFF" cname="_EBTR3_ON"  />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4321.xml b/src/devices/pic/xml_data/18F4321.xml
new file mode 100644
index 0000000..6bdd265
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4321.xml
@@ -0,0 +1,368 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4321" document="024610" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x2100" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x001FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO2" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO1" />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOR_OFF"   />
+      <value value="0x02" name="Software" cname="_BOR_SOFT"  />
+      <value value="0x04" name="On_run"   cname="_BOR_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOR_ON"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x87" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CPP2MX_RB3" />
+      <value value="0x01" name="RC1" cname="_CPP2MX_RC1" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_DIG" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ANA" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x38" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="ICPORT" value="0x08" >
+      <value value="0x00" name="Off" cname="_ICPORT_OFF" />
+      <value value="0x08" name="On"  cname="_ICPORT_ON" />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="256"  cname="_BBSIZ_BB256" />
+      <value value="0x10" name="512"  cname="_BBSIZ_BB512" />
+      <value value="0x20" name="1024" cname="_BBSIZ_BB512" />
+      <value value="0x30" name="1024" cname="_BBSIZ_BB512" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200/0400/0800:0FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200/0400/0800:0FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200/0400/0800:0FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4331.xml b/src/devices/pic/xml_data/18F4331.xml
new file mode 100644
index 0000000..a22e667
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4331.xml
@@ -0,0 +1,384 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4331" document="010288" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x08A0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xE464" cchecksum="0xE3BA" />
+    <checksum protected_blocks="1" bchecksum="0xE640" cchecksum="0xE5F5" />
+    <checksum protected_blocks="3" bchecksum="0x043D" cchecksum="0x0447" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x001FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0xCF" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC2"   />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRC"   />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC1"   />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRTEN_ON"  />
+      <value value="0x01" name="Off" cname="_PWRTEN_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOREN_OFF" />
+      <value value="0x02" name="On"  cname="_BOREN_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x3F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDTEN_OFF" />
+      <value value="0x01" name="On"  cname="_WDTEN_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDPS_32768" />
+    </mask>
+    <mask name="WINEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_WINEN_ON"  />
+      <value value="0x20" name="Off" cname="_WINEN_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x3C" >
+    <mask name="PWMPIN"  value="0x04" >
+      <value value="0x00" name="On"  cname="_PWMPIN_ON"  />
+      <value value="0x04" name="Off" cname="_PWMPIN_OFF" />
+    </mask>
+    <mask name="LPOL"    value="0x08" >
+      <value value="0x00" name="low"  cname="_LPOL_LOW"  />
+      <value value="0x08" name="high" cname="_LPOL_HIGH" />
+    </mask>
+    <mask name="HPOL"    value="0x10" >
+      <value value="0x00" name="low"  cname="_HPOL_LOW"  />
+      <value value="0x10" name="high" cname="_HPOL_HIGH" />
+    </mask>
+    <mask name="T1OSCMX" value="0x20" >
+      <value value="0x00" name="Legacy"    cname="_T1OSCMX_OFF" />
+      <value value="0x20" name="Low Power" cname="_T1OSCMX_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x9D" >
+    <mask name="FLTAMX" value="0x01" >
+      <value value="0x00" name="RD4" cname="_FLTAMX_RD4" />
+      <value value="0x01" name="RC1" cname="_FLTAMX_RC1"  />
+    </mask>
+    <mask name="SSPMX" value="0x04" >
+      <value value="0x00" name="RD3, RD2, RD1" cname="_SSPMX_RD1" />
+      <value value="0x04" name="RC5, RC4, RC7" cname="_SSPMX_RC7"  />
+    </mask>
+    <mask name="PWM4MX" value="0x08" >
+      <value value="0x00" name="RD5" cname="_PWM4MX_RD5" />
+      <value value="0x08" name="RB5" cname="_PWM4MX_RB5"  />
+    </mask>
+    <mask name="EXCLKMX" value="0x10" >
+      <value value="0x00" name="RD0" cname="_EXCLKMX_RD0" />
+      <value value="0x10" name="RC3" cname="_EXCLKMX_RC3"  />
+    </mask>
+    <mask name="MCLRE" value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4410.xml b/src/devices/pic/xml_data/18F4410.xml
new file mode 100644
index 0000000..8ca9b17
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4410.xml
@@ -0,0 +1,349 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4410" document="010417" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x10E0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F442.xml b/src/devices/pic/xml_data/18F442.xml
new file mode 100644
index 0000000..61f6a63
--- /dev/null
+++ b/src/devices/pic/xml_data/18F442.xml
@@ -0,0 +1,327 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F442" document="010289" status="NR" alternative="18F4420" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x04A0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xC2B4" cchecksum="0xC20A" />
+    <checksum protected_blocks="1" bchecksum="0xC491" cchecksum="0xC437" />
+    <checksum protected_blocks="3" bchecksum="0x028E" cchecksum="0x0289" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    sdcc_cname="_OSC_LP" />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    sdcc_cname="_OSC_XT" />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    sdcc_cname="_OSC_HS" />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    sdcc_cname="_OSC_RC" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    sdcc_cname="_OSC_EC_OSC2_Clock_Out" />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  sdcc_cname="_OSC_EC_OSC2_RA6" />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" sdcc_cname="_OSC_HS_PLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  sdcc_cname="_OSC_RC_OSC2" />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_OFF" sdcc_cname="_CCP2MUX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  sdcc_cname="_CCP2MUX_RC1"/>
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4420.xml b/src/devices/pic/xml_data/18F4420.xml
new file mode 100644
index 0000000..83a0022
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4420.xml
@@ -0,0 +1,358 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4420" document="010290" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x10C0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" cmask="0x80" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" cmask="0x80" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4423.xml b/src/devices/pic/xml_data/18F4423.xml
new file mode 100644
index 0000000..1760494
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4423.xml
@@ -0,0 +1,349 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4423" document="026426" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x10D0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="12.5"  nominal="9" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC"  />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" cmask="0x80" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" cmask="0x80" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+  
+  <!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+  
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+  
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4431.xml b/src/devices/pic/xml_data/18F4431.xml
new file mode 100644
index 0000000..c19b48a
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4431.xml
@@ -0,0 +1,409 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4431" document="010291" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0880" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xC488" cchecksum="0xC3DE" />
+    <checksum protected_blocks="1" bchecksum="0xC668" cchecksum="0xC61D" />
+    <checksum protected_blocks="3" bchecksum="0xE465" cchecksum="0xE41A" />
+    <checksum protected_blocks="5" bchecksum="0x0459" cchecksum="0x0463" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0xCF" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC2"   />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRC"   />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC1"   />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRTEN_ON"  />
+      <value value="0x01" name="Off" cname="_PWRTEN_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOREN_OFF" />
+      <value value="0x02" name="On"  cname="_BOREN_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x3F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDTEN_OFF" />
+      <value value="0x01" name="On"  cname="_WDTEN_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDPS_32768" />
+    </mask>
+    <mask name="WINEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_WINEN_ON"  />
+      <value value="0x20" name="Off" cname="_WINEN_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x3C" >
+    <mask name="PWMPIN"  value="0x04" >
+      <value value="0x00" name="On"  cname="_PWMPIN_ON"  />
+      <value value="0x04" name="Off" cname="_PWMPIN_OFF" />
+    </mask>
+    <mask name="LPOL"    value="0x08" >
+      <value value="0x00" name="low"  cname="_LPOL_LOW"  />
+      <value value="0x08" name="high" cname="_LPOL_HIGH" />
+    </mask>
+    <mask name="HPOL"    value="0x10" >
+      <value value="0x00" name="low"  cname="_HPOL_LOW"  />
+      <value value="0x10" name="high" cname="_HPOL_HIGH" />
+    </mask>
+    <mask name="T1OSCMX" value="0x20" >
+      <value value="0x00" name="Legacy"    cname="_T1OSCMX_OFF" />
+      <value value="0x20" name="Low Power" cname="_T1OSCMX_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x9D" >
+    <mask name="FLTAMX" value="0x01" >
+      <value value="0x00" name="RD4" cname="_FLTAMX_RD4" />
+      <value value="0x01" name="RC1" cname="_FLTAMX_RC1"  />
+    </mask>
+    <mask name="SSPMX" value="0x04" >
+      <value value="0x00" name="RD3, RD2, RD1" cname="_SSPMX_RD1" />
+      <value value="0x04" name="RC5, RC4, RC7" cname="_SSPMX_RC7"  />
+    </mask>
+    <mask name="PWM4MX" value="0x08" >
+      <value value="0x00" name="RD5" cname="_PWM4MX_RD5" />
+      <value value="0x08" name="RB5" cname="_PWM4MX_RB5"  />
+    </mask>
+    <mask name="EXCLKMX" value="0x10" >
+      <value value="0x00" name="RD0" cname="_EXCLKMX_RD0" />
+      <value value="0x10" name="RC3" cname="_EXCLKMX_RC3"  />
+    </mask>
+    <mask name="MCLRE" value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="2000:2FFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="3000:3FFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="2000:2FFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="3000:3FFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:0FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="1000:1FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="2000:2FFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="3000:3FFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4439.xml b/src/devices/pic/xml_data/18F4439.xml
new file mode 100644
index 0000000..3441809
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4439.xml
@@ -0,0 +1,316 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4439" document="010292" status="NR" alternative="18F4431" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x04A0" >
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xC2BF" cchecksum="0xC215" />
+    <checksum protected_blocks="1" bchecksum="0xC4A5" cchecksum="0xC43C" />
+    <checksum protected_blocks="2" bchecksum="0xE2A2" cchecksum="0xE239" />
+    <checksum protected_blocks="3" bchecksum="0x029E" cchecksum="0x028A" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC" value="0x07" >
+      <value value="default" name="invalid" />
+      <value value="0x02" name="HS"        cname="_OSC_HS"    />
+      <value value="0x04" name="EC_CLKOUT" cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"     cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"        cname="_OSC_HSPLL" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.5" cname="_BORV_25" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4450.xml b/src/devices/pic/xml_data/18F4450.xml
new file mode 100644
index 0000000..e634df1
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4450.xml
@@ -0,0 +1,378 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4450" document="023498" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x2400" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="8" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x07" cmask="0x00" >
+    <mask name="PLLDIV" value="0x07" >
+      <value value="0x00" name="1"  cname="_PLLDIV_1"  />
+      <value value="0x01" name="2"  cname="_PLLDIV_2"  />
+      <value value="0x02" name="3"  cname="_PLLDIV_3"  />
+      <value value="0x03" name="4"  cname="_PLLDIV_4"  />
+      <value value="0x04" name="5"  cname="_PLLDIV_5"  />
+      <value value="0x05" name="6"  cname="_PLLDIV_6"  />
+      <value value="0x06" name="10" cname="_PLLDIV_10" />
+      <value value="0x07" name="12" cname="_PLLDIV_12" />
+    </mask>
+    <mask name="CPUDIV" value="0x18" >
+      <value value="0x00" name="1" cname="_CPUDIV_OSC1_PLL2" />
+      <value value="0x08" name="2" cname="_CPUDIV_OSC2_PLL3" />
+      <value value="0x10" name="3" cname="_CPUDIV_OSC3_PLL4" />
+      <value value="0x18" name="4" cname="_CPUDIV_OSC4_PLL6" />
+    </mask>
+    <mask name="USBDIV" value="0x20" >
+      <value value="0x00" name="1" cname="_USBDIV_1" />
+      <value value="0x20" name="2" cname="_USBDIV_2" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" cmask="0x00" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="XT"           cname="_FOSC_XT_XT"       />
+      <value value="0x01" name="XT"           cname="_FOSC_XT_XT"       />
+      <value value="0x02" name="XTPLL"        cname="_FOSC_XTPLL"       />
+      <value value="0x03" name="XTPLL"        cname="_FOSC_XTPLL_XT"    />
+      <value value="0x04" name="EC_IO"        cname="_FOSC_ECIO_EC"     />
+      <value value="0x05" name="EC_CLKOUT"    cname="_FOSC_EC_EC"       />
+      <value value="0x06" name="ECPLL_IO"     cname="_FOSC_ECPLLIO_EC"  />
+      <value value="0x07" name="ECPLL_CLKOUT" cname="_FOSC_ECPLL_EC"    />
+      <value value="0x08" name="INTRC_IO"     cname="_FOSC_INTOSCIO_EC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_FOSC_INTOSC_EC"   />
+      <value value="0x0A" name="INTXT"        cname="_FOSC_INTOSC_XT"   />
+      <value value="0x0B" name="INTHS"        cname="_FOSC_INTOSC_HS"   />
+      <value value="0x0C" name="HS"           cname="_FOSC_HS"          />
+      <value value="0x0D" name="HS"           cname="_FOSC_HS"          />
+      <value value="0x0E" name="HSPLL"        cname="_FOSC_HSPLL_HS"    />
+      <value value="0x0F" name="HSPLL"        cname="_FOSC_HSPLL_HS"    />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE"  value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN"  value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOR_OFF"       />
+      <value value="0x02" name="Software" cname="_BOR_SOFT"      />
+      <value value="0x04" name="On_run"   cname="_BOR_ON_ACTIVE" />
+      <value value="0x06" name="On"       cname="_BOR_ON"        />
+    </mask>
+    <mask name="BORV"   value="0x18" >
+      <value value="0x00" name="4.6" cname="_BORV_46" />
+      <value value="0x08" name="4.3" cname="_BORV_43" />
+      <value value="0x10" name="2.8" cname="_BORV_28" />
+      <value value="0x18" name="2.1" cname="_BORV_21" />
+    </mask>
+    <mask name="VREGEN" value="0x20" >
+      <value value="0x00" name="Off" cname="_VREGEN_OFF" />
+      <value value="0x20" name="On"  cname="_VREGEN_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" cmask="0x00" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x28" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x08" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x08" name="2048" cname="_BBSIZ_2048" />
+    </mask>
+    <mask name="ICPORT" value="0x20" >
+      <value value="0x00" name="On"  cname="_ICPORT_ON" />
+      <value value="0x20" name="Off" cname="_ICPORT_OFF" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"            cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"            cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"            cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4455.xml b/src/devices/pic/xml_data/18F4455.xml
new file mode 100644
index 0000000..282decb
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4455.xml
@@ -0,0 +1,398 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4455" document="010293" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1220" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="48" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4"  end="16" vdd_min="3" vdd_max="5.5" />
+    <frequency start="16" end="25"  vdd_min="4" vdd_max="5.5" />
+    <frequency start="25"  end="48" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x005FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" >
+    <mask name="PLLDIV" value="0x07" >
+      <value value="0x00" name="1"  cname="_PLLDIV_1"  sdcc_cname="_PLLDIV_NO_DIVIDE__4MHZ_INPUT_" />
+      <value value="0x01" name="2"  cname="_PLLDIV_2"  sdcc_cname="_PLLDIV_DIVIDE_BY_2__8MHZ_INPUT_" />
+      <value value="0x02" name="3"  cname="_PLLDIV_3"  sdcc_cname="_PLLDIV_DIVIDE_BY_3__12MHZ_INPUT_" />
+      <value value="0x03" name="4"  cname="_PLLDIV_4"  sdcc_cname="_PLLDIV_DIVIDE_BY_4__16MHZ_INPUT_" />
+      <value value="0x04" name="5"  cname="_PLLDIV_5"  sdcc_cname="_PLLDIV_DIVIDE_BY_5__20MHZ_INPUT_" />
+      <value value="0x05" name="6"  cname="_PLLDIV_6"  sdcc_cname="_PLLDIV_DIVIDE_BY_6__24MHZ_INPUT_" />
+      <value value="0x06" name="10" cname="_PLLDIV_10" sdcc_cname="_PLLDIV_DIVIDE_BY_10__40MHZ_INPUT_" />
+      <value value="0x07" name="12" cname="_PLLDIV_12" sdcc_cname="_PLLDIV_DIVIDE_BY_12__48MHZ_INPUT_" />
+    </mask>
+    <mask name="CPUDIV" value="0x18" >
+      <value value="0x00" name="1" cname="_CPUDIV_OSC1_PLL2" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2_" />
+      <value value="0x08" name="2" cname="_CPUDIV_OSC2_PLL3" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___2__96MHZ_PLL_SRC___3_" />
+      <value value="0x10" name="3" cname="_CPUDIV_OSC3_PLL4" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___3__96MHZ_PLL_SRC___4_" />
+      <value value="0x18" name="4" cname="_CPUDIV_OSC4_PLL6" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___4__96MHZ_PLL_SRC___6_" />
+    </mask>
+    <mask name="USBDIV" value="0x20" >
+      <value value="0x00" name="1" cname="_USBDIV_1" sdcc_cname="_USBPLL_CLOCK_SRC_FROM_OSC1_OSC2" />
+      <value value="0x20" name="2" cname="_USBDIV_2" sdcc_cname="_USBPLL_CLOCK_SRC_FROM_96MHZ_PLL_2" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x05" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="XT"           cname="_FOSC_XT_XT"       sdcc_cname="_OSC_XT__USB_XT" />
+      <value value="0x01" name="XT"           cname="_FOSC_XT_XT"       sdcc_cname="_OSC_XT__USB_XT" />
+      <value value="0x02" name="XTPLL"        cname="_FOSC_XTPLL"       sdcc_cname="_OSC_XT__XT_PLL__USB_XT" />
+      <value value="0x03" name="XTPLL"        cname="_FOSC_XTPLL_XT"    sdcc_cname="_OSC_XT__XT_PLL__USB_XT" />
+      <value value="0x04" name="EC_IO"        cname="_FOSC_ECIO_EC"     sdcc_cname="_OSC_EC__EC_RA6__USB_EC" />
+      <value value="0x05" name="EC_CLKOUT"    cname="_FOSC_EC_EC"       sdcc_cname="_OSC_EC__EC_CLKO_RA6___USB_EC" />
+      <value value="0x06" name="ECPLL_IO"     cname="_FOSC_ECPLLIO_EC"  sdcc_cname="_OSC_EC__EC_PLL__EC_PLL_RA6__USB_EC" />
+      <value value="0x07" name="ECPLL_CLKOUT" cname="_FOSC_ECPLL_EC"    sdcc_cname="_OSC_EC__EC_PLL__EC_PLL_CLKO_RA6___USB_EC" />
+      <value value="0x08" name="INTRC_IO"     cname="_FOSC_INTOSCIO_EC" sdcc_cname="_OSC_INTOSC__INTOSC_RA6__USB_EC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_FOSC_INTOSC_EC"   sdcc_cname="_OSC_INTOSC__INTOSC_CLK0_RA6___USB_EC" />
+      <value value="0x0A" name="INTXT"        cname="_FOSC_INTOSC_XT"   sdcc_cname="_OSC_INTOSC__USB_XT" />
+      <value value="0x0B" name="INTHS"        cname="_FOSC_INTOSC_HS"   sdcc_cname="_OSC_INTOSC__USB_HS" />
+      <value value="0x0C" name="HS"           cname="_FOSC_HS"          sdcc_cname="_OSC_HS__USB_HS" />
+      <value value="0x0D" name="HS"           cname="_FOSC_HS"          sdcc_cname="_OSC_HS__USB_HS" />
+      <value value="0x0E" name="HSPLL"        cname="_FOSC_HSPLL_HS"    sdcc_cname="_OSC_HS__HS_PLL__USB_HS" />
+      <value value="0x0F" name="HSPLL"        cname="_FOSC_HSPLL_HS"    sdcc_cname="_OSC_HS__HS_PLL__USB_HS" />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEM_OFF" sdcc_cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEM_ON"  sdcc_cname="_FCMEN_ON" />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE"  value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN"  value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOR_OFF"       sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="Software" cname="_BOR_SOFT"      sdcc_cname="_BODEN_CONTROLLED_WITH_SBOREN_BIT" />
+      <value value="0x04" name="On_run"   cname="_BOR_ON_ACTIVE" sdcc_cname="_BODEN_ON_WHILE_ACTIVE" />
+      <value value="0x06" name="On"       cname="_BOR_ON"        sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"   value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x08" name="4.2" cname="_BORV_1" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x10" name="2.7" cname="_BORV_2" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x18" name="2.0" cname="_BORV_3" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+    <mask name="VREGEN" value="0x20" >
+      <value value="0x00" name="Off" cname="_VREGEN_OFF" />
+      <value value="0x20" name="On"  cname="_VREGEN_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" sdcc_cname="_WDT_DISABLED_CONTROLLED" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  sdcc_cname="_WDT_ON" />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   sdcc_cname="_WDTPS_1_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   sdcc_cname="_WDTPS_1_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   sdcc_cname="_WDTPS_1_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  sdcc_cname="_WDTPS_1_1024" />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  sdcc_cname="_WDTPS_1_2048" />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  sdcc_cname="_WDTPS_1_4096" />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  sdcc_cname="_WDTPS_1_8192" />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" sdcc_cname="_WDTPS_1_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" sdcc_cname="_WDTPS_1_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_OFF" sdcc_cname="_CCP2MUX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  sdcc_cname="_CCP2MUX_RC1" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" sdcc_cname="_MCLRE_MCLR_OFF_RE3_ON" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  sdcc_cname="_MCLRE_MCLR_ON_RE3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x20" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" sdcc_cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  sdcc_cname="_STVR_ON" />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="ICPORT" value="0x20" >
+      <value value="0x00" name="Off" cname="_ICPRT_OFF" sdcc_cname="_ENICPORT_OFF" />
+      <value value="0x20" name="On"  cname="_ICPRT_ON"  sdcc_cname="_ENICPORT_ON" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" sdcc_cname="_ENHCPU_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  sdcc_cname="_ENHCPU_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  sdcc_cname="_CP_2_ON" />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" sdcc_cname="_CP_2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON"  sdcc_cname="_WRT_2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" sdcc_cname="_WRT_2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" cmask="0xC0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  sdcc_cname="_EBTR_2_ON" />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" sdcc_cname="_EBTR_2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F448.xml b/src/devices/pic/xml_data/18F448.xml
new file mode 100644
index 0000000..40de124
--- /dev/null
+++ b/src/devices/pic/xml_data/18F448.xml
@@ -0,0 +1,322 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F448" document="010294" status="NR" alternative="18F4480" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0820" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xC2B3" cchecksum="0xC209" />
+    <checksum protected_blocks="1" bchecksum="0xC48F" cchecksum="0xC435" />
+    <checksum protected_blocks="3" bchecksum="0x028C" cchecksum="0x0287" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    sdcc_cname="_OSC_LP" />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    sdcc_cname="_OSC_XT" />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    sdcc_cname="_OSC_HS" />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    sdcc_cname="_OSC_RC" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    sdcc_cname="_OSC_EC_OSC2_Clock_Out" />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  sdcc_cname="_OSC_EC_OSC2_RA6" />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" sdcc_cname="_OSC_HS_PLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  sdcc_cname="_OSC_RC_OSC2" />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x0C" name="2.0" cname="_BORV_25" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4480.xml b/src/devices/pic/xml_data/18F4480.xml
new file mode 100644
index 0000000..b9a87da
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4480.xml
@@ -0,0 +1,358 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4480" document="010614" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1AA0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO67"/>
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRCIO7" />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"   />
+      <value value="0x02" name="Software" cname="_BOREN_SBORENCTRL"  />
+      <value value="0x04" name="On_run"   cname="_BOREN_BOACTIVE" />
+      <value value="0x06" name="On"       cname="_BOREN_BOHW"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x10" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x10" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x10" name="2048" cname="_BBSIZ_2048" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"            cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"            cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"            cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F44J10.xml b/src/devices/pic/xml_data/18F44J10.xml
new file mode 100644
index 0000000..ddf2019
--- /dev/null
+++ b/src/devices/pic/xml_data/18F44J10.xml
@@ -0,0 +1,129 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F44J10" status="IP" memory_technology="FLASH" architecture="18J" id="0x1D20" id_low_power="0x1D60">
+
+<!--* Documents ************************************************************-->
+  <documents webpage="024620" datasheet="39682" progsheet="39687" erratas="80265 80269" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="2.7" vdd_max="3.6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="2.7" />
+    <frequency start="4" end="40" vdd_min="2.35" vdd_max="2.7" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="2.7"   max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="2.7"   max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="2.7"   max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x003FF7" word_write_align="32" word_erase_align="512" />
+  <memory name="config"       start="0x003FF8" end="0x003FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0x7F" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x07" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0xFF" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0xF8" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+  </package>
+
+  <package types="qfn" nb_pins="44" >
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F4510.xml b/src/devices/pic/xml_data/18F4510.xml
new file mode 100644
index 0000000..b038b39
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4510.xml
@@ -0,0 +1,373 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4510" document="010418" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x10A0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4515.xml b/src/devices/pic/xml_data/18F4515.xml
new file mode 100644
index 0000000..4325432
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4515.xml
@@ -0,0 +1,361 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4515" document="010295" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x0C60" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00BFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F452.xml b/src/devices/pic/xml_data/18F452.xml
new file mode 100644
index 0000000..12ad5ce
--- /dev/null
+++ b/src/devices/pic/xml_data/18F452.xml
@@ -0,0 +1,352 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F452" document="010296" status="NR" alternative="18F4520" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0420" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0x82D8" cchecksum="0x822E" />
+    <checksum protected_blocks="1" bchecksum="0x84B7" cchecksum="0x845D" />
+    <checksum protected_blocks="3" bchecksum="0xC2B4" cchecksum="0xC25A" />
+    <checksum protected_blocks="5" bchecksum="0x02A8" cchecksum="0x02A3" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    sdcc_cname="_OSC_LP" />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    sdcc_cname="_OSC_XT" />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    sdcc_cname="_OSC_HS" />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    sdcc_cname="_OSC_RC" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    sdcc_cname="_OSC_EC_OSC2_Clock_Out" />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  sdcc_cname="_OSC_EC_OSC2_RA6" />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" sdcc_cname="_OSC_HS_PLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  sdcc_cname="_OSC_RC_OSC2" />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_OFF" sdcc_cname="_CCP2MUX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  sdcc_cname="_CCP2MUX_RC1" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  sdcc_cname="_CP_2_ON" />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" sdcc_cname="_CP_2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON"  sdcc_cname="_CP_3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" sdcc_cname="_CP_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON"  sdcc_cname="_WRT_2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" sdcc_cname="_WRT_2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON"  sdcc_cname="_WRT_3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" sdcc_cname="_WRT_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  sdcc_cname="_EBTR_2_ON" />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" sdcc_cname="_EBTR_2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON"  sdcc_cname="_EBTR_3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" sdcc_cname="_EBTR_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4520.xml b/src/devices/pic/xml_data/18F4520.xml
new file mode 100644
index 0000000..a1a1e75
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4520.xml
@@ -0,0 +1,382 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4520" document="010297" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1080" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4523.xml b/src/devices/pic/xml_data/18F4523.xml
new file mode 100644
index 0000000..29b2583
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4523.xml
@@ -0,0 +1,379 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4523" document="026425" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1090" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="12.5" nominal="9" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTB" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4525.xml b/src/devices/pic/xml_data/18F4525.xml
new file mode 100644
index 0000000..f37d90b
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4525.xml
@@ -0,0 +1,370 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4525" document="010298" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0C40" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00BFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4539.xml b/src/devices/pic/xml_data/18F4539.xml
new file mode 100644
index 0000000..71a1f4c
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4539.xml
@@ -0,0 +1,328 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4539" document="010299" status="NR" alternative="18F4431" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0420" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xA2BF" cchecksum="0xA215" />
+    <checksum protected_blocks="1" bchecksum="0xA4A5" cchecksum="0xA43C" />
+    <checksum protected_blocks="3" bchecksum="0xE2A2" cchecksum="0xE239" />
+    <checksum protected_blocks="4" bchecksum="0x029E" cchecksum="0x028A" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x005FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC" value="0x07" >
+      <value value="default" name="invalid" />
+      <value value="0x02" name="HS"        cname="_OSC_HS"    />
+      <value value="0x04" name="EC_CLKOUT" cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"     cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"        cname="_OSC_HSPLL" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.5" cname="_BORV_25" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4550.xml b/src/devices/pic/xml_data/18F4550.xml
new file mode 100644
index 0000000..b0e26c8
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4550.xml
@@ -0,0 +1,402 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4550" document="010300" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1200" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="48" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0"  end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4"  end="16" vdd_min="3" vdd_max="5.5" />
+    <frequency start="16" end="25"  vdd_min="4" vdd_max="5.5" />
+    <frequency start="25"  end="48" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" >
+    <mask name="PLLDIV" value="0x07" >
+      <value value="0x00" name="1"  cname="_PLLDIV_1"  sdcc_cname="_PLLDIV_NO_DIVIDE__4MHZ_INPUT_" />
+      <value value="0x01" name="2"  cname="_PLLDIV_2"  sdcc_cname="_PLLDIV_DIVIDE_BY_2__8MHZ_INPUT_" />
+      <value value="0x02" name="3"  cname="_PLLDIV_3"  sdcc_cname="_PLLDIV_DIVIDE_BY_3__12MHZ_INPUT_" />
+      <value value="0x03" name="4"  cname="_PLLDIV_4"  sdcc_cname="_PLLDIV_DIVIDE_BY_4__16MHZ_INPUT_" />
+      <value value="0x04" name="5"  cname="_PLLDIV_5"  sdcc_cname="_PLLDIV_DIVIDE_BY_5__20MHZ_INPUT_" />
+      <value value="0x05" name="6"  cname="_PLLDIV_6"  sdcc_cname="_PLLDIV_DIVIDE_BY_6__24MHZ_INPUT_" />
+      <value value="0x06" name="10" cname="_PLLDIV_10" sdcc_cname="_PLLDIV_DIVIDE_BY_10__40MHZ_INPUT_" />
+      <value value="0x07" name="12" cname="_PLLDIV_12" sdcc_cname="_PLLDIV_DIVIDE_BY_12__48MHZ_INPUT_" />
+    </mask>
+    <mask name="CPUDIV" value="0x18" >
+      <value value="0x00" name="1" cname="_CPUDIV_OSC1_PLL2" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2_" />
+      <value value="0x08" name="2" cname="_CPUDIV_OSC2_PLL3" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___2__96MHZ_PLL_SRC___3_" />
+      <value value="0x10" name="3" cname="_CPUDIV_OSC3_PLL4" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___3__96MHZ_PLL_SRC___4_" />
+      <value value="0x18" name="4" cname="_CPUDIV_OSC4_PLL6" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___4__96MHZ_PLL_SRC___6_" />
+    </mask>
+    <mask name="USBDIV" value="0x20" >
+      <value value="0x00" name="1" cname="_USBDIV_1" sdcc_cname="_USBPLL_CLOCK_SRC_FROM_OSC1_OSC2" />
+      <value value="0x20" name="2" cname="_USBDIV_2" sdcc_cname="_USBPLL_CLOCK_SRC_FROM_96MHZ_PLL_2" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x05" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="XT"           cname="_FOSC_XT_XT"       sdcc_cname="_OSC_XT__USB_XT" />
+      <value value="0x01" name="XT"           cname="_FOSC_XT_XT"       sdcc_cname="_OSC_XT__USB_XT" />
+      <value value="0x02" name="XTPLL"        cname="_FOSC_XTPLL"       sdcc_cname="_OSC_XT__XT_PLL__USB_XT" />
+      <value value="0x03" name="XTPLL"        cname="_FOSC_XTPLL_XT"    sdcc_cname="_OSC_XT__XT_PLL__USB_XT" />
+      <value value="0x04" name="EC_IO"        cname="_FOSC_ECIO_EC"     sdcc_cname="_OSC_EC__EC_RA6__USB_EC" />
+      <value value="0x05" name="EC_CLKOUT"    cname="_FOSC_EC_EC"       sdcc_cname="_OSC_EC__EC_CLKO_RA6___USB_EC" />
+      <value value="0x06" name="ECPLL_IO"     cname="_FOSC_ECPLLIO_EC"  sdcc_cname="_OSC_EC__EC_PLL__EC_PLL_RA6__USB_EC" />
+      <value value="0x07" name="ECPLL_CLKOUT" cname="_FOSC_ECPLL_EC"    sdcc_cname="_OSC_EC__EC_PLL__EC_PLL_CLKO_RA6___USB_EC" />
+      <value value="0x08" name="INTRC_IO"     cname="_FOSC_INTOSCIO_EC" sdcc_cname="_OSC_INTOSC__INTOSC_RA6__USB_EC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_FOSC_INTOSC_EC"   sdcc_cname="_OSC_INTOSC__INTOSC_CLK0_RA6___USB_EC" />
+      <value value="0x0A" name="INTXT"        cname="_FOSC_INTOSC_XT"   sdcc_cname="_OSC_INTOSC__USB_XT" />
+      <value value="0x0B" name="INTHS"        cname="_FOSC_INTOSC_HS"   sdcc_cname="_OSC_INTOSC__USB_HS" />
+      <value value="0x0C" name="HS"           cname="_FOSC_HS"          sdcc_cname="_OSC_HS__USB_HS" />
+      <value value="0x0D" name="HS"           cname="_FOSC_HS"          sdcc_cname="_OSC_HS__USB_HS" />
+      <value value="0x0E" name="HSPLL"        cname="_FOSC_HSPLL_HS"    sdcc_cname="_OSC_HS__HS_PLL__USB_HS" />
+      <value value="0x0F" name="HSPLL"        cname="_FOSC_HSPLL_HS"    sdcc_cname="_OSC_HS__HS_PLL__USB_HS" />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEM_OFF" sdcc_cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEM_ON"  sdcc_cname="_FCMEN_ON" />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE"  value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN"  value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOR_OFF"       sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="Software" cname="_BOR_SOFT"      sdcc_cname="_BODEN_CONTROLLED_WITH_SBOREN_BIT" />
+      <value value="0x04" name="On_run"   cname="_BOR_ON_ACTIVE" sdcc_cname="_BODEN_ON_WHILE_ACTIVE" />
+      <value value="0x06" name="On"       cname="_BOR_ON"        sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"   value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x08" name="4.2" cname="_BORV_1" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x10" name="2.7" cname="_BORV_2" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x18" name="2.0" cname="_BORV_3" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+    <mask name="VREGEN" value="0x20" >
+      <value value="0x00" name="Off" cname="_VREGEN_OFF" />
+      <value value="0x20" name="On"  cname="_VREGEN_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" sdcc_cname="_WDT_DISABLED_CONTROLLED" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  sdcc_cname="_WDT_ON" />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   sdcc_cname="_WDTPS_1_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   sdcc_cname="_WDTPS_1_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   sdcc_cname="_WDTPS_1_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  sdcc_cname="_WDTPS_1_1024" />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  sdcc_cname="_WDTPS_1_2048" />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  sdcc_cname="_WDTPS_1_4096" />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  sdcc_cname="_WDTPS_1_8192" />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" sdcc_cname="_WDTPS_1_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" sdcc_cname="_WDTPS_1_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_OFF" sdcc_cname="_CCP2MUX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  sdcc_cname="_CCP2MUX_RC1" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" sdcc_cname="_MCLRE_MCLR_OFF_RE3_ON" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  sdcc_cname="_MCLRE_MCLR_ON_RE3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x20" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" sdcc_cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  sdcc_cname="_STVR_ON" />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="ICPORT" value="0x20" >
+      <value value="0x00" name="Off" cname="_ICPRT_OFF" sdcc_cname="_ENICPORT_OFF" />
+      <value value="0x20" name="On"  cname="_ICPRT_ON"  sdcc_cname="_ENICPORT_ON" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" sdcc_cname="_ENHCPU_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  sdcc_cname="_ENHCPU_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  sdcc_cname="_CP_2_ON" />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" sdcc_cname="_CP_2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON"  sdcc_cname="_CP_3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" sdcc_cname="_CP_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON"  sdcc_cname="_WRT_2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" sdcc_cname="_WRT_2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON"  sdcc_cname="_WRT_3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" sdcc_cname="_WRT_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" cmask="0x40" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  sdcc_cname="_EBTR_2_ON" />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" sdcc_cname="_EBTR_2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON"  sdcc_cname="_EBTR_3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" sdcc_cname="_EBTR_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F458.xml b/src/devices/pic/xml_data/18F458.xml
new file mode 100644
index 0000000..33069dd
--- /dev/null
+++ b/src/devices/pic/xml_data/18F458.xml
@@ -0,0 +1,347 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F458" document="010301" status="NR" alternative="18F4580" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0860" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0x82D7" cchecksum="0x822D" />
+    <checksum protected_blocks="1" bchecksum="0x84B5" cchecksum="0x845B" />
+    <checksum protected_blocks="3" bchecksum="0xC2B2" cchecksum="0xC258" />
+    <checksum protected_blocks="5" bchecksum="0x02A6" cchecksum="0x02A1" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    sdcc_cname="_OSC_LP" />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    sdcc_cname="_OSC_XT" />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    sdcc_cname="_OSC_HS" />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    sdcc_cname="_OSC_RC" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    sdcc_cname="_OSC_EC_OSC2_Clock_Out" />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  sdcc_cname="_OSC_EC_OSC2_RA6" />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" sdcc_cname="_OSC_HS_PLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  sdcc_cname="_OSC_RC_OSC2" />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON"  />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  sdcc_cname="_CP_2_ON" />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" sdcc_cname="_CP_2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON"  sdcc_cname="_CP_3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" sdcc_cname="_CP_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON"  sdcc_cname="_WRT_2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" sdcc_cname="_WRT_2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON"  sdcc_cname="_WRT_3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" sdcc_cname="_WRT_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:1FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  sdcc_cname="_EBTR_2_ON" />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" sdcc_cname="_EBTR_2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON"  sdcc_cname="_EBTR_3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" sdcc_cname="_EBTR_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4580.xml b/src/devices/pic/xml_data/18F4580.xml
new file mode 100644
index 0000000..e6e105a
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4580.xml
@@ -0,0 +1,382 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4580" document="010615" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1A80" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="16" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRCIO7" />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"   />
+      <value value="0x02" name="Software" cname="_BOREN_SBORENCTRL"  />
+      <value value="0x04" name="On_run"   cname="_BOREN_BOACTIVE" />
+      <value value="0x06" name="On"       cname="_BOREN_BOHW"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x10" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x10" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x10" name="2048" cname="_BBSIZ_2048" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"            cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"            cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"            cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4585.xml b/src/devices/pic/xml_data/18F4585.xml
new file mode 100644
index 0000000..fb438b8
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4585.xml
@@ -0,0 +1,372 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4585" document="010302" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0EA0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00BFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRCIO7" />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"   />
+      <value value="0x02" name="Software" cname="_BOREN_SBORENCTRL"  />
+      <value value="0x04" name="On_run"   cname="_BOREN_BOACTIVE" />
+      <value value="0x06" name="On"       cname="_BOREN_BOHW"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x30" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x10" name="2048" cname="_BBSIZ_2048" />
+      <value value="0x20" name="4096" cname="_BBSIZ_4096" />
+      <value value="0x30" name="4096" cname="_BBSIZ_4096" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F45J10.xml b/src/devices/pic/xml_data/18F45J10.xml
new file mode 100644
index 0000000..af2c752
--- /dev/null
+++ b/src/devices/pic/xml_data/18F45J10.xml
@@ -0,0 +1,129 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F45J10" status="IP" memory_technology="FLASH" architecture="18J" id="0x1C20" id_low_power="0x1C60">
+
+<!--* Documents ************************************************************-->
+  <documents webpage="024619" datasheet="39682" progsheet="39687" erratas="80265 80269" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="2.7" vdd_max="3.6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="2.7" />
+    <frequency start="4" end="40" vdd_min="2.35" vdd_max="2.7" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="2.7"   max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="2.7"   max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="2.7"   max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x007FF7" word_write_align="32" word_erase_align="512" />
+  <memory name="config"       start="0x007FF8" end="0x007FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0x7F" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x07" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0xFF" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0xF8" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+  </package>
+
+  <package types="qfn" nb_pins="44" >
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F4610.xml b/src/devices/pic/xml_data/18F4610.xml
new file mode 100644
index 0000000..d105cdb
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4610.xml
@@ -0,0 +1,373 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4610" document="010303" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x0C20" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4620.xml b/src/devices/pic/xml_data/18F4620.xml
new file mode 100644
index 0000000..5964590
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4620.xml
@@ -0,0 +1,371 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4620" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0C00" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010304" datasheet="39626" progsheet="39622" erratas="80222 80200 80224 80282" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"      />
+      <value value="0x01" name="XT"           cname="_OSC_XT"      />
+      <value value="0x02" name="HS"           cname="_OSC_HS"      />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"      />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"      />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"   />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7"  />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"     sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON"      sdcc_cname="_BODEN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP"   sdcc_cname="_BODEN_ON_WHILE_ACTIVE" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" sdcc_cname="_BODEN_CONTROLLED_WITH_SBOREN_BIT" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.6" cname="_BORV_0" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x08" name="4.3" cname="_BORV_1" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x10" name="2.8" cname="_BORV_2" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x18" name="2.1" cname="_BORV_3" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" sdcc_cname="_WDT_DISABLED_CONTROLLED" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   sdcc_cname="_WDTPS_1_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   sdcc_cname="_WDTPS_1_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   sdcc_cname="_WDTPS_1_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  sdcc_cname="_WDTPS_1_1024" />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  sdcc_cname="_WDTPS_1_2048" />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  sdcc_cname="_WDTPS_1_4096" />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  sdcc_cname="_WDTPS_1_8192" />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" sdcc_cname="_WDTPS_1_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" sdcc_cname="_WDTPS_1_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" sdcc_cname="_CCP2MUX_RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC"  sdcc_cname="_CCP2MUX_RC1" />
+    </mask>
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON"  sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" sdcc_cname="_MCLRE_MCLR_OFF_RE3_ON" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  sdcc_cname="_MCLRE_MCLR_ON_RE3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" sdcc_cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  sdcc_cname="_STVR_ON" />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  sdcc_cname="_CP_2_ON" />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" sdcc_cname="_CP_2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  sdcc_cname="_CP_3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" sdcc_cname="_CP_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON"  sdcc_cname="_WRT_2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" sdcc_cname="_WRT_2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON"  sdcc_cname="_WRT_3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" sdcc_cname="_WRT_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  sdcc_cname="_EBTR_2_ON" />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" sdcc_cname="_EBTR_2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON"  sdcc_cname="_EBTR_3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" sdcc_cname="_EBTR_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4680.xml b/src/devices/pic/xml_data/18F4680.xml
new file mode 100644
index 0000000..f5ef137
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4680.xml
@@ -0,0 +1,384 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4680" document="010305" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0E80" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRCIO7" />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"   />
+      <value value="0x02" name="Software" cname="_BOREN_SBORENCTRL"  />
+      <value value="0x04" name="On_run"   cname="_BOREN_BOACTIVE" />
+      <value value="0x06" name="On"       cname="_BOREN_BOHW"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x30" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x10" name="2048" cname="_BBSIZ_2048" />
+      <value value="0x20" name="4096" cname="_BBSIZ_4096" />
+      <value value="0x30" name="4096" cname="_BBSIZ_4096" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4682.xml b/src/devices/pic/xml_data/18F4682.xml
new file mode 100644
index 0000000..19b387b
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4682.xml
@@ -0,0 +1,390 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4682" document="026325" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x2740" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x013FFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRCIO7" />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"   />
+      <value value="0x02" name="Software" cname="_BOREN_SBORENCTRL"  />
+      <value value="0x04" name="On_run"   cname="_BOREN_BOACTIVE" />
+      <value value="0x06" name="On"       cname="_BOREN_BOHW"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x30" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x10" name="2048" cname="_BBSIZ_2048" />
+      <value value="0x20" name="4096" cname="_BBSIZ_4096" />
+      <value value="0x30" name="4096" cname="_BBSIZ_4096" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+    <mask name="CP_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_CP4_ON" />
+      <value value="0x10" name="Off"         cname="_CP4_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+    <mask name="WRT_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_WRT4_ON" />
+      <value value="0x10" name="Off"         cname="_WRT4_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+    <mask name="EBTR_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_EBTR4_ON" />
+      <value value="0x10" name="Off"         cname="_EBTR4_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F4685.xml b/src/devices/pic/xml_data/18F4685.xml
new file mode 100644
index 0000000..7b68ee2
--- /dev/null
+++ b/src/devices/pic/xml_data/18F4685.xml
@@ -0,0 +1,402 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F4685" document="026324" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x2760" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9" max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="3" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x017FFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_IRCIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_IRCIO7" />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF"   />
+      <value value="0x02" name="Software" cname="_BOREN_SBORENCTRL"  />
+      <value value="0x04" name="On_run"   cname="_BOREN_BOACTIVE" />
+      <value value="0x06" name="On"       cname="_BOREN_BOHW"    />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"     />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"     />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"     />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"     />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"    />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"    />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"    />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128"   />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256"   />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512"   />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x82" >
+    <mask name="PBADEN"  value="0x02" >
+      <value value="0x00" name="digital" cname="_PBADEN_OFF" />
+      <value value="0x02" name="analog"  cname="_PBADEN_ON" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON"  />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x30" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x10" name="2048" cname="_BBSIZ_2048" />
+      <value value="0x20" name="4096" cname="_BBSIZ_4096" />
+      <value value="0x30" name="4096" cname="_BBSIZ_4096" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x3F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+    <mask name="CP_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_CP4_ON" />
+      <value value="0x10" name="Off"         cname="_CP4_OFF" />
+    </mask>
+    <mask name="CP_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_CP5_ON" />
+      <value value="0x20" name="Off"         cname="_CP5_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x3F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+    <mask name="WRT_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_WRT4_ON" />
+      <value value="0x10" name="Off"         cname="_WRT4_OFF" />
+    </mask>
+    <mask name="WRT_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_WRT5_ON" />
+      <value value="0x20" name="Off"         cname="_WRT5_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x3F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+    <mask name="EBTR_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_EBTR4_ON" />
+      <value value="0x10" name="Off"         cname="_EBTR4_OFF" />
+    </mask>
+    <mask name="EBTR_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_EBTR5_ON" />
+      <value value="0x20" name="Off"         cname="_EBTR5_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F6310.xml b/src/devices/pic/xml_data/18F6310.xml
new file mode 100644
index 0000000..9bdbfb7
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6310.xml
@@ -0,0 +1,250 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6310" document="019698" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x0BE0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xE20C" cchecksum="0xE162" />
+    <checksum protected="All" bchecksum="0x0227" cchecksum="0x0222" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"   max="12"  nominal="11" />
+  <voltages name="vdd_prog"       min="2.75" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"    max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x001FFF" word_write_align="8" word_erase_align="0" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xC3" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_PM_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_PM_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_PM_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_PM_MC" />
+    </mask>
+    <mask name="BW"   value="0x40" >
+      <value value="0x00" name="8"  cname="_BW_8" />
+      <value value="0x40" name="16" cname="_BW_16" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+  
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7/RB3" cname="_CCP2MX_PORTE" />
+      <value value="0x01" name="RC1"     cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x01" >
+    <mask name="CP" value="0x01" >
+      <value value="0x00" name="All" cname="_CP_ON" />
+      <value value="0x01" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x01" >
+    <mask name="EBTR" value="0x01" >
+      <value value="0x00" name="All" cname="_EBTR_ON" />
+      <value value="0x01" name="Off" cname="_EBTR_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F6390.xml b/src/devices/pic/xml_data/18F6390.xml
new file mode 100644
index 0000000..02f2498
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6390.xml
@@ -0,0 +1,250 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6390" document="019705" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x0BA0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xE20C" cchecksum="0xE162" />
+    <checksum protected="All" bchecksum="0x0227" cchecksum="0x0222" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"   max="12"  nominal="11" />
+  <voltages name="vdd_prog"       min="2.75" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"    max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x001FFF" word_write_align="8" word_erase_align="0" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xC3" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_PM_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_PM_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_PM_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_PM_MC" />
+    </mask>
+    <mask name="BW"   value="0x40" >
+      <value value="0x00" name="8"  cname="_BW_8" />
+      <value value="0x40" name="16" cname="_BW_16" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7/RB3" cname="_CCP2MX_PORTE" />
+      <value value="0x01" name="RC1"     cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x01" >
+    <mask name="CP" value="0x01" >
+      <value value="0x00" name="All" cname="_CP_ON" />
+      <value value="0x01" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x01" >
+    <mask name="EBTR" value="0x01" >
+      <value value="0x00" name="All" cname="_EBTR_ON" />
+      <value value="0x01" name="Off" cname="_EBTR_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F6393.xml b/src/devices/pic/xml_data/18F6393.xml
new file mode 100644
index 0000000..bc778f4
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6393.xml
@@ -0,0 +1,253 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6393" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x1A00" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="530835" datasheet="39896" progsheet="39624" erratas="" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xC20C" cchecksum="0xC162" />
+    <checksum protected="All" bchecksum="0x0225" cchecksum="0x0220" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"   max="12"  nominal="11" />
+  <voltages name="vdd_prog"       min="2.75" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"    max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x001FFF" word_write_align="8" word_erase_align="0" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xC3" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_PM_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_PM_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_PM_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_PM_MC" />
+    </mask>
+    <mask name="BW"   value="0x40" >
+      <value value="0x00" name="8"  cname="_BW_8" />
+      <value value="0x40" name="16" cname="_BW_16" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7/RB3" cname="_CCP2MX_PORTE" />
+      <value value="0x01" name="RC1"     cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x01" >
+    <mask name="CP" value="0x01" >
+      <value value="0x00" name="All" cname="_CP_ON" />
+      <value value="0x01" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x01" >
+    <mask name="EBTR" value="0x01" >
+      <value value="0x00" name="All" cname="_EBTR_ON" />
+      <value value="0x01" name="Off" cname="_EBTR_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F63J11.xml b/src/devices/pic/xml_data/18F63J11.xml
new file mode 100644
index 0000000..37273bc
--- /dev/null
+++ b/src/devices/pic/xml_data/18F63J11.xml
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F63J11" status="IP" memory_technology="FLASH" architecture="18J" id="0x3900" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026365" datasheet="39774" progsheet="39644" erratas="80318" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x001FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x001FF8" end="0x001FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F63J90.xml b/src/devices/pic/xml_data/18F63J90.xml
new file mode 100644
index 0000000..ef1310c
--- /dev/null
+++ b/src/devices/pic/xml_data/18F63J90.xml
@@ -0,0 +1,184 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F63J90" status="IP" memory_technology="FLASH" architecture="18J" id="0x3800" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026347" datasheet="39774" progsheet="39770" erratas="80286 80312" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x001FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x001FF8" end="0x001FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F6410.xml b/src/devices/pic/xml_data/18F6410.xml
new file mode 100644
index 0000000..c270208
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6410.xml
@@ -0,0 +1,250 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6410" document="019711" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x06E0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xC20C" cchecksum="0xC162" />
+    <checksum protected="All" bchecksum="0x0225" cchecksum="0x0220" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"   max="12"  nominal="11" />
+  <voltages name="vdd_prog"       min="2.75" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"    max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="8" word_erase_align="0" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xC3" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_PM_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_PM_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_PM_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_PM_MC" />
+    </mask>
+    <mask name="BW"   value="0x40" >
+      <value value="0x00" name="8"  cname="_BW_8" />
+      <value value="0x40" name="16" cname="_BW_16" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7/RB3" cname="_CCP2MX_PORTE" />
+      <value value="0x01" name="RC1"     cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x01" >
+    <mask name="CP" value="0x01" >
+      <value value="0x00" name="All" cname="_CP_ON" />
+      <value value="0x01" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x01" >
+    <mask name="EBTR" value="0x01" >
+      <value value="0x00" name="All" cname="_EBTR_ON" />
+      <value value="0x01" name="Off" cname="_EBTR_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F6490.xml b/src/devices/pic/xml_data/18F6490.xml
new file mode 100644
index 0000000..1727686
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6490.xml
@@ -0,0 +1,250 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6490" document="010307" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x06A0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xC20C" cchecksum="0xC162" />
+    <checksum protected="All" bchecksum="0x0225" cchecksum="0x0220" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"   max="12"  nominal="11" />
+  <voltages name="vdd_prog"       min="2.75" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"    max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="8" word_erase_align="0" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xC3" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_PM_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_PM_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_PM_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_PM_MC" />
+    </mask>
+    <mask name="BW"   value="0x40" >
+      <value value="0x00" name="8"  cname="_BW_8" />
+      <value value="0x40" name="16" cname="_BW_16" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7/RB3" cname="_CCP2MX_PORTE" />
+      <value value="0x01" name="RC1"     cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x01" >
+    <mask name="CP" value="0x01" >
+      <value value="0x00" name="All" cname="_CP_ON" />
+      <value value="0x01" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x01" >
+    <mask name="EBTR" value="0x01" >
+      <value value="0x00" name="All" cname="_EBTR_ON" />
+      <value value="0x01" name="Off" cname="_EBTR_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F6493.xml b/src/devices/pic/xml_data/18F6493.xml
new file mode 100644
index 0000000..89f409d
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6493.xml
@@ -0,0 +1,253 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6493" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x0E00" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="530834" datasheet="39896" progsheet="39624" erratas="" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xC20C" cchecksum="0xC162" />
+    <checksum protected="All" bchecksum="0x0225" cchecksum="0x0220" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"   max="12"  nominal="11" />
+  <voltages name="vdd_prog"       min="2.75" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"    max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x003FFF" word_write_align="8" word_erase_align="0" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xC3" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_PM_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_PM_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_PM_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_PM_MC" />
+    </mask>
+    <mask name="BW"   value="0x40" >
+      <value value="0x00" name="8"  cname="_BW_8" />
+      <value value="0x40" name="16" cname="_BW_16" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7/RB3" cname="_CCP2MX_PORTE" />
+      <value value="0x01" name="RC1"     cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x01" >
+    <mask name="CP" value="0x01" >
+      <value value="0x00" name="All" cname="_CP_ON" />
+      <value value="0x01" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x01" >
+    <mask name="EBTR" value="0x01" >
+      <value value="0x00" name="All" cname="_EBTR_ON" />
+      <value value="0x01" name="Off" cname="_EBTR_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F64J11.xml b/src/devices/pic/xml_data/18F64J11.xml
new file mode 100644
index 0000000..fd126a0
--- /dev/null
+++ b/src/devices/pic/xml_data/18F64J11.xml
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F64J11" status="IP" memory_technology="FLASH" architecture="18J" id="0x3920" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026364" datasheet="39774" progsheet="39644" erratas="80318" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x003FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x003FF8" end="0x003FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F64J90.xml b/src/devices/pic/xml_data/18F64J90.xml
new file mode 100644
index 0000000..fedf592
--- /dev/null
+++ b/src/devices/pic/xml_data/18F64J90.xml
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F64J90" status="IP" memory_technology="FLASH" architecture="18J" id="0x3820" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026346" datasheet="39774" progsheet="39644" erratas="80318" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x003FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x003FF8" end="0x003FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F6520.xml b/src/devices/pic/xml_data/18F6520.xml
new file mode 100644
index 0000000..a022295
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6520.xml
@@ -0,0 +1,283 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6520" document="010308" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0B20" >
+
+<!--* Checksums ************************************************************-->
+<!--
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0x85A8" cchecksum="0x84FE" />
+    <checksum protected_blocks="1" bchecksum="0x8787" cchecksum="0x873C" />
+    <checksum protected_blocks="3" bchecksum="0xC584" cchecksum="0xC539" />
+    <checksum protected_blocks="5" bchecksum="0xE480" cchecksum="0xE48A" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.5" cname="_BORV_25" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MUX_RE7" />
+      <value value="0x01" name="RC1" cname="_CCP2MUX_RC1" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F6525.xml b/src/devices/pic/xml_data/18F6525.xml
new file mode 100644
index 0000000..953e12a
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6525.xml
@@ -0,0 +1,287 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6525" document="010309" status="NR" alternative="18F6527" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0AE0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0x4642" cchecksum="0x4598" />
+    <checksum protected_blocks="1" bchecksum="0x4E12" cchecksum="0x4DC7" />
+    <checksum protected_blocks="3" bchecksum="0xC60F" cchecksum="0xC5C4" />
+    <checksum protected_blocks="4" bchecksum="0x060B" cchecksum="0x0615" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00BFFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x2F" >
+    <mask name="FOSC"   value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+      <value value="default" name="invalid" />
+      <value value="0x0C" name="E4_IO"        cname="_OSC_ECIOPLL" />
+      <value value="0x0D" name="E4S_IO"       cname="_OSC_ECIOSWPLL" />
+      <value value="0x0E" name="H4S"          cname="_OSC_HSSWPLL" />
+      <value value="0x0F" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="MCLRE"  value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F6527.xml b/src/devices/pic/xml_data/18F6527.xml
new file mode 100644
index 0000000..04a2bf1
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6527.xml
@@ -0,0 +1,302 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6527" document="021970" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1340" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00BFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"     />
+      <value value="0x01" name="XT"           cname="_XT_OSC"     />
+      <value value="0x02" name="HS"           cname="_HS_OSC"     />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"     />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"   />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"   />
+      <value value="0x08" name="INTRC_IO"     cname="_INTIO2_OSC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_INTIO1_OSC" />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FSCM_OFF" />
+      <value value="0x40" name="On"  cname="_FSCM_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1K"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2K"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4K"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8K"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16K" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32K" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x85" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_PORTE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_1024" />
+      <value value="0x10" name="2048" cname="_BBSIZ_2048" />
+      <value value="0x20" name="4096" cname="_BBSIZ_4096" />
+      <value value="0x30" name="4096" cname="_BBSIZ_4096" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F6585.xml b/src/devices/pic/xml_data/18F6585.xml
new file mode 100644
index 0000000..0bf9bab
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6585.xml
@@ -0,0 +1,350 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6585" document="010310" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0A60" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00BFFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x2F" >
+    <mask name="FOSC"   value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+      <value value="default" name="invalid" />
+      <value value="0x0C" name="E4_IO"        cname="_OSC_ECIOPLL" />
+      <value value="0x0D" name="E4S_IO"       cname="_OSC_ECIOSWPLL" />
+      <value value="0x0E" name="H4S"          cname="_OSC_HSSWPLL" />
+      <value value="0x0F" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" cmask="0x02" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_OFF" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON" />
+    </mask>
+    <mask name="MCLRE"  value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="68" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F65J10.xml b/src/devices/pic/xml_data/18F65J10.xml
new file mode 100644
index 0000000..a67fe87
--- /dev/null
+++ b/src/devices/pic/xml_data/18F65J10.xml
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F65J10" status="IP" memory_technology="FLASH" architecture="18J" id="0x1520" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="022354" datasheet="39663" progsheet="39644" erratas="80315 80246 80341 80340" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x007FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x007FF8" end="0x007FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F65J11.xml b/src/devices/pic/xml_data/18F65J11.xml
new file mode 100644
index 0000000..2ef5b3d
--- /dev/null
+++ b/src/devices/pic/xml_data/18F65J11.xml
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F65J11" status="IP" memory_technology="FLASH" architecture="18J" id="0x3960" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026363" datasheet="39774" progsheet="39644" erratas="80318" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x007FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x007FF8" end="0x007FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F65J15.xml b/src/devices/pic/xml_data/18F65J15.xml
new file mode 100644
index 0000000..f5f310a
--- /dev/null
+++ b/src/devices/pic/xml_data/18F65J15.xml
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F65J15" status="IP" memory_technology="FLASH" architecture="18J" id="0x1540" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="022355" datasheet="39663" progsheet="39644" erratas="80315 80246 80341 80340" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x00BFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x00BFF8" end="0x00BFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F65J50.xml b/src/devices/pic/xml_data/18F65J50.xml
new file mode 100644
index 0000000..d0cdd2b
--- /dev/null
+++ b/src/devices/pic/xml_data/18F65J50.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F65J50" status="IP" memory_technology="FLASH" architecture="18J" id="0x4100" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027180" datasheet="39775" progsheet="39644" erratas="80321" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="8" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="8" end="48" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x007FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x007FF8" end="0x007FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xEF" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="PLLDIV"  value="0x0E" >
+      <value value="0x00" name="12" cname="" />
+      <value value="0x02" name="10" cname="" />
+      <value value="0x04" name="6"  cname="" />
+      <value value="0x06" name="5"  cname="" />
+      <value value="0x08" name="4"  cname="" />
+      <value value="0x0A" name="3"  cname="" />
+      <value value="0x0C" name="2"  cname="" />
+      <value value="0x0E" name="1"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x09" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F65J90.xml b/src/devices/pic/xml_data/18F65J90.xml
new file mode 100644
index 0000000..91997da
--- /dev/null
+++ b/src/devices/pic/xml_data/18F65J90.xml
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F65J90" status="IP" memory_technology="FLASH" architecture="18J" id="0x3860" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026345" datasheet="39774" progsheet="39644" erratas="80318" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x007FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x007FF8" end="0x007FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F6620.xml b/src/devices/pic/xml_data/18F6620.xml
new file mode 100644
index 0000000..e88ee06
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6620.xml
@@ -0,0 +1,285 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6620" status="NR" alternative="18F6622" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0660" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="010311" datasheet="39609" progsheet="39583" erratas="80129 80172" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0x02D8" cchecksum="0x022E" />
+    <checksum protected_blocks="1" bchecksum="0x04AF" cchecksum="0x0455" />
+    <checksum protected_blocks="3" bchecksum="0x82AC" cchecksum="0x8252" />
+    <checksum protected_blocks="5" bchecksum="0x02A0" cchecksum="0x029B" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="25" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="16" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    sdcc_cname="_OSC_LP" />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    sdcc_cname="_OSC_XT" />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    sdcc_cname="_OSC_HS" />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    sdcc_cname="_OSC_RC" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    sdcc_cname="_OSC_EC_OSC2_Clock_Out" />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  sdcc_cname="_OSC_EC_OSC2_RA6" />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" sdcc_cname="_OSC_HS_PLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  sdcc_cname="_OSC_RC_OSC2" />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x0C" name="2.5" cname="_BORV_20" sdcc_cname="_BODENV_2_5V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_OFF" sdcc_cname="_CCP2MUX_RE7" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  sdcc_cname="_CCP2MUX_RC1" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:3FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  sdcc_cname="_CP_2_ON" />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" sdcc_cname="_CP_2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  sdcc_cname="_CP_3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" sdcc_cname="_CP_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:3FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON"  sdcc_cname="_WRT_2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" sdcc_cname="_WRT_2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON"  sdcc_cname="_WRT_3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" sdcc_cname="_WRT_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:3FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  sdcc_cname="_EBTR_2_ON" />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" sdcc_cname="_EBTR_2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON"  sdcc_cname="_EBTR_3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" sdcc_cname="_EBTR_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F6621.xml b/src/devices/pic/xml_data/18F6621.xml
new file mode 100644
index 0000000..664de3f
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6621.xml
@@ -0,0 +1,299 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6621" document="010312" status="NR" alternative="18F6622" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0AA0" >
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected_blocks="0" bchecksum="0x0642" cchecksum="0x0598" />
+    <checksum protected_blocks="1" bchecksum="0x0E0E" cchecksum="0x0DC3" />
+    <checksum protected_blocks="3" bchecksum="0x860B" cchecksum="0x85C0" />
+    <checksum protected_blocks="4" bchecksum="0x05FF" cchecksum="0x0609" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x2F" >
+    <mask name="FOSC"   value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+      <value value="default" name="invalid" />
+      <value value="0x0C" name="E4_IO"        cname="_OSC_ECIOPLL" />
+      <value value="0x0D" name="E4S_IO"       cname="_OSC_ECIOSWPLL" />
+      <value value="0x0E" name="H4S"          cname="_OSC_HSSWPLL" />
+      <value value="0x0F" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="MCLRE"  value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F6622.xml b/src/devices/pic/xml_data/18F6622.xml
new file mode 100644
index 0000000..6fb81d7
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6622.xml
@@ -0,0 +1,314 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6622" document="021969" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1380" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"     />
+      <value value="0x01" name="XT"           cname="_XT_OSC"     />
+      <value value="0x02" name="HS"           cname="_HS_OSC"     />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"     />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"   />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"   />
+      <value value="0x08" name="INTRC_IO"     cname="_INTIO2_OSC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_INTIO1_OSC" />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FSCM_OFF" />
+      <value value="0x40" name="On"  cname="_FSCM_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1K"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2K"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4K"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8K"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16K" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32K" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x85" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_PORTE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_BB2K" />
+      <value value="0x10" name="2048" cname="_BBSIZ_BB4K" />
+      <value value="0x20" name="4096" cname="_BBSIZ_BB8K" />
+      <value value="0x30" name="4096" cname="_BBSIZ_BB8K" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F6627.xml b/src/devices/pic/xml_data/18F6627.xml
new file mode 100644
index 0000000..74248c6
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6627.xml
@@ -0,0 +1,332 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6627" document="010313" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x13C0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x017FFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x85" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_PORTE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_BB2K" />
+      <value value="0x10" name="2048" cname="_BBSIZ_BB4K" />
+      <value value="0x20" name="4096" cname="_BBSIZ_BB8K" />
+      <value value="0x30" name="4096" cname="_BBSIZ_BB8K" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x3F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+    <mask name="CP_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_CP4_ON" />
+      <value value="0x10" name="Off"         cname="_CP4_OFF" />
+    </mask>
+    <mask name="CP_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_CP5_ON" />
+      <value value="0x20" name="Off"         cname="_CP5_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x3F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+    <mask name="WRT_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_WRT4_ON" />
+      <value value="0x10" name="Off"         cname="_WRT4_OFF" />
+    </mask>
+    <mask name="WRT_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_WRT5_ON" />
+      <value value="0x20" name="Off"         cname="_WRT5_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x3F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+    <mask name="EBTR_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_EBTR4_ON" />
+      <value value="0x10" name="Off"         cname="_EBTR4_OFF" />
+    </mask>
+    <mask name="EBTR_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_EBTR5_ON" />
+      <value value="0x20" name="Off"         cname="_EBTR5_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F6680.xml b/src/devices/pic/xml_data/18F6680.xml
new file mode 100644
index 0000000..d0a9922
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6680.xml
@@ -0,0 +1,362 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6680" document="010314" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0A20" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF"  word_write_align="4" word_erase_align="32"/>
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x2F" >
+    <mask name="FOSC"   value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+      <value value="default" name="invalid" />
+      <value value="0x0C" name="E4_IO"        cname="_OSC_ECIOPLL" />
+      <value value="0x0D" name="E4S_IO"       cname="_OSC_ECIOSWPLL" />
+      <value value="0x0E" name="H4S"          cname="_OSC_HSSWPLL" />
+      <value value="0x0F" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_OFF" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON" />
+    </mask>
+    <mask name="MCLRE"  value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" cmask="0x08" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" cmask="0x08" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" cmask="0x08" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+  <package types="plcc" nb_pins="68" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F66J10.xml b/src/devices/pic/xml_data/18F66J10.xml
new file mode 100644
index 0000000..7bb9aa7
--- /dev/null
+++ b/src/devices/pic/xml_data/18F66J10.xml
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F66J10" status="IP" memory_technology="FLASH" architecture="18J" id="0x1560" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="022356" datasheet="39663" progsheet="39644" erratas="80315 80246 80341 80340" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x00FFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x00FFF8" end="0x00FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F66J11.xml b/src/devices/pic/xml_data/18F66J11.xml
new file mode 100644
index 0000000..8fd1314
--- /dev/null
+++ b/src/devices/pic/xml_data/18F66J11.xml
@@ -0,0 +1,190 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F66J11" status="IP" memory_technology="FLASH" architecture="18J" id="0x4440" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027154" datasheet="39778" progsheet="39644" erratas="80305 80344" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="8"  vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="8" end="48" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x00FFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x00FFF8" end="0x00FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x09" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname="" />
+      <value value="0x01" name="RC1"  cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F66J15.xml b/src/devices/pic/xml_data/18F66J15.xml
new file mode 100644
index 0000000..c1c5c95
--- /dev/null
+++ b/src/devices/pic/xml_data/18F66J15.xml
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F66J15" status="IP" memory_technology="FLASH" architecture="18J" id="0x1580" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="020090" datasheet="39663" progsheet="39644" erratas="80315 80246 80341 80340" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x017FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x017FF8" end="0x017FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F66J16.xml b/src/devices/pic/xml_data/18F66J16.xml
new file mode 100644
index 0000000..cf84f44
--- /dev/null
+++ b/src/devices/pic/xml_data/18F66J16.xml
@@ -0,0 +1,189 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F66J16" status="IP" memory_technology="FLASH" architecture="18J" id="0x4460" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027153" datasheet="39778" progsheet="39644" erratas="80305 80344" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="8"  vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="8" end="48" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x017FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x017FF8" end="0x017FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x09" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname="" />
+      <value value="0x01" name="RC1"  cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F66J50.xml b/src/devices/pic/xml_data/18F66J50.xml
new file mode 100644
index 0000000..34dbe21
--- /dev/null
+++ b/src/devices/pic/xml_data/18F66J50.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F66J50" status="IP" memory_technology="FLASH" architecture="18J" id="0x4140" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027179" datasheet="39775" progsheet="39644" erratas="80321" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="8" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="8" end="48" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x00FFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x00FFF8" end="0x00FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xEF" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="PLLDIV"  value="0x0E" >
+      <value value="0x00" name="12" cname="" />
+      <value value="0x02" name="10" cname="" />
+      <value value="0x04" name="6"  cname="" />
+      <value value="0x06" name="5"  cname="" />
+      <value value="0x08" name="4"  cname="" />
+      <value value="0x0A" name="3"  cname="" />
+      <value value="0x0C" name="2"  cname="" />
+      <value value="0x0E" name="1"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x09" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F66J55.xml b/src/devices/pic/xml_data/18F66J55.xml
new file mode 100644
index 0000000..7e95978
--- /dev/null
+++ b/src/devices/pic/xml_data/18F66J55.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F66J55" status="IP" memory_technology="FLASH" architecture="18J" id="0x4160" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027178" datasheet="39775" progsheet="39644" erratas="80321" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="8" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="8" end="48" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x017FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x017FF8" end="0x017FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xEF" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="PLLDIV"  value="0x0E" >
+      <value value="0x00" name="12" cname="" />
+      <value value="0x02" name="10" cname="" />
+      <value value="0x04" name="6"  cname="" />
+      <value value="0x06" name="5"  cname="" />
+      <value value="0x08" name="4"  cname="" />
+      <value value="0x0A" name="3"  cname="" />
+      <value value="0x0C" name="2"  cname="" />
+      <value value="0x0E" name="1"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x09" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F66J60.xml b/src/devices/pic/xml_data/18F66J60.xml
new file mode 100644
index 0000000..e4ac5ea
--- /dev/null
+++ b/src/devices/pic/xml_data/18F66J60.xml
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F66J60" document="026447" status="IP" memory_technology="FLASH" architecture="18J" id="0x1800" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="41.6667" vdd_min="2.7" vdd_max="3.6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="2.7" />
+    <frequency start="4" end="41.6667" vdd_min="2.35" vdd_max="2.7" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3"   max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6"   nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3"   max="3.6"   nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFF7" word_write_align="32" word_erase_align="512" />
+  <memory name="config"       start="0x00FFF8" end="0x00FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="ETHLED" value="0x01" >
+      <value value="0x00" name="Off"  cname=""  />
+      <value value="0x01" name="On"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F66J65.xml b/src/devices/pic/xml_data/18F66J65.xml
new file mode 100644
index 0000000..8431ec8
--- /dev/null
+++ b/src/devices/pic/xml_data/18F66J65.xml
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F66J65" document="026446" status="IP" memory_technology="FLASH" architecture="18J" id="0x1F00" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="41.6667" vdd_min="2.7" vdd_max="3.6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="2.7" />
+    <frequency start="4" end="41.6667" vdd_min="2.35" vdd_max="2.7" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3"   max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6"   nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3"   max="3.6"   nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x017FF7" word_write_align="32" word_erase_align="512" />
+  <memory name="config"       start="0x017FF8" end="0x017FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="ETHLED" value="0x01" >
+      <value value="0x00" name="Off"  cname=""  />
+      <value value="0x01" name="On"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F6720.xml b/src/devices/pic/xml_data/18F6720.xml
new file mode 100644
index 0000000..c023b5e
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6720.xml
@@ -0,0 +1,330 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6720" document="010315" status="NR" alternative="18F6722" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0620" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0x05A8" cchecksum="0x04FE" />
+    <checksum protected_blocks="1" bchecksum="0x077F" cchecksum="0x0734" />
+    <checksum protected_blocks="3" bchecksum="0x857C" cchecksum="0x8531" />
+    <checksum protected_blocks="9" bchecksum="0x0480" cchecksum="0x048A" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="25" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="16" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x01FFFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_OFF" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+    <mask name="CP_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_CP4_ON" />
+      <value value="0x10" name="Off"         cname="_CP4_OFF" />
+    </mask>
+    <mask name="CP_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_CP5_ON" />
+      <value value="0x20" name="Off"         cname="_CP5_OFF" />
+    </mask>
+    <mask name="CP_6" value="0x40" >
+      <value value="0x00" name="18000:1BFFF" cname="_CP6_ON" />
+      <value value="0x40" name="Off"         cname="_CP6_OFF" />
+    </mask>
+    <mask name="CP_7" value="0x80" >
+      <value value="0x00" name="1C000:1FFFF" cname="_CP7_ON" />
+      <value value="0x80" name="Off"         cname="_CP7_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+    <mask name="WRT_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_WRT4_ON" />
+      <value value="0x10" name="Off"         cname="_WRT4_OFF" />
+    </mask>
+    <mask name="WRT_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_WRT5_ON" />
+      <value value="0x20" name="Off"         cname="_WRT5_OFF" />
+    </mask>
+    <mask name="WRT_6" value="0x40" >
+      <value value="0x00" name="18000:1BFFF" cname="_WRT6_ON" />
+      <value value="0x40" name="Off"         cname="_WRT6_OFF" />
+    </mask>
+    <mask name="WRT_7" value="0x80" >
+      <value value="0x00" name="1C000:1FFFF" cname="_WRT7_ON" />
+      <value value="0x80" name="Off"         cname="_WRT7_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+    <mask name="EBTR_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_EBTR4_ON" />
+      <value value="0x10" name="Off"         cname="_EBTR4_OFF" />
+    </mask>
+    <mask name="EBTR_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_EBTR5_ON" />
+      <value value="0x20" name="Off"         cname="_EBTR5_OFF" />
+    </mask>
+    <mask name="EBTR_6" value="0x40" >
+      <value value="0x00" name="18000:1BFFF" cname="_EBTR6_ON" />
+      <value value="0x40" name="Off"         cname="_EBTR6_OFF" />
+    </mask>
+    <mask name="EBTR_7" value="0x80" >
+      <value value="0x00" name="1C000:1FFFF" cname="_EBTR7_ON" />
+      <value value="0x80" name="Off"         cname="_EBTR7_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F6722.xml b/src/devices/pic/xml_data/18F6722.xml
new file mode 100644
index 0000000..fb30985
--- /dev/null
+++ b/src/devices/pic/xml_data/18F6722.xml
@@ -0,0 +1,356 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F6722" document="010316" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1400" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x01FFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+   </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x85" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_PORTE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_BB2K" />
+      <value value="0x10" name="2048" cname="_BBSIZ_BB4K" />
+      <value value="0x20" name="4096" cname="_BBSIZ_BB8K" />
+      <value value="0x30" name="4096" cname="_BBSIZ_BB8K" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+    <mask name="CP_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_CP4_ON" />
+      <value value="0x10" name="Off"         cname="_CP4_OFF" />
+    </mask>
+    <mask name="CP_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_CP5_ON" />
+      <value value="0x20" name="Off"         cname="_CP5_OFF" />
+    </mask>
+    <mask name="CP_6" value="0x40" >
+      <value value="0x00" name="18000:1BFFF" cname="_CP6_ON" />
+      <value value="0x40" name="Off"         cname="_CP6_OFF" />
+    </mask>
+    <mask name="CP_7" value="0x80" >
+      <value value="0x00" name="1C000:1FFFF" cname="_CP7_ON" />
+      <value value="0x80" name="Off"         cname="_CP7_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+    <mask name="WRT_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_WRT4_ON" />
+      <value value="0x10" name="Off"         cname="_WRT4_OFF" />
+    </mask>
+    <mask name="WRT_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_WRT5_ON" />
+      <value value="0x20" name="Off"         cname="_WRT5_OFF" />
+    </mask>
+    <mask name="WRT_6" value="0x40" >
+      <value value="0x00" name="18000:1BFFF" cname="_WRT6_ON" />
+      <value value="0x40" name="Off"         cname="_WRT6_OFF" />
+    </mask>
+    <mask name="WRT_7" value="0x80" >
+      <value value="0x00" name="1C000:1FFFF" cname="_WRT7_ON" />
+      <value value="0x80" name="Off"         cname="_WRT7_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+    <mask name="EBTR_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_EBTR4_ON" />
+      <value value="0x10" name="Off"         cname="_EBTR4_OFF" />
+    </mask>
+    <mask name="EBTR_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_EBTR5_ON" />
+      <value value="0x20" name="Off"         cname="_EBTR5_OFF" />
+    </mask>
+    <mask name="EBTR_6" value="0x40" >
+      <value value="0x00" name="18000:1BFFF" cname="_EBTR6_ON" />
+      <value value="0x40" name="Off"         cname="_EBTR6_OFF" />
+    </mask>
+    <mask name="EBTR_7" value="0x80" >
+      <value value="0x00" name="1C000:1FFFF" cname="_EBTR7_ON" />
+      <value value="0x80" name="Off"         cname="_EBTR7_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F67J10.xml b/src/devices/pic/xml_data/18F67J10.xml
new file mode 100644
index 0000000..78223c3
--- /dev/null
+++ b/src/devices/pic/xml_data/18F67J10.xml
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F67J10" status="IP" memory_technology="FLASH" architecture="18J" id="0x15A0" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="020089" datasheet="39663" progsheet="39644" erratas="80315 80246 80341 80340" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x01FFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x01FFF8" end="0x01FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F67J11.xml b/src/devices/pic/xml_data/18F67J11.xml
new file mode 100644
index 0000000..d13e7dc
--- /dev/null
+++ b/src/devices/pic/xml_data/18F67J11.xml
@@ -0,0 +1,190 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F67J11" status="IP" memory_technology="FLASH" architecture="18J" id="0x4480" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027152" datasheet="39778" progsheet="39644" erratas="80305 80344" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="8"  vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="8" end="48" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x01FFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x01FFF8" end="0x01FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x09" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname="" />
+      <value value="0x01" name="RC1"  cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F67J50.xml b/src/devices/pic/xml_data/18F67J50.xml
new file mode 100644
index 0000000..91eade3
--- /dev/null
+++ b/src/devices/pic/xml_data/18F67J50.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F67J50" status="IP" memory_technology="FLASH" architecture="18J" id="0x4180" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027177" datasheet="39775" progsheet="39644" erratas="80321" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="8" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="8" end="48" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x01FFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x01FFF8" end="0x01FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xEF" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="PLLDIV"  value="0x0E" >
+      <value value="0x00" name="12" cname="" />
+      <value value="0x02" name="10" cname="" />
+      <value value="0x04" name="6"  cname="" />
+      <value value="0x06" name="5"  cname="" />
+      <value value="0x08" name="4"  cname="" />
+      <value value="0x0A" name="3"  cname="" />
+      <value value="0x0C" name="2"  cname="" />
+      <value value="0x0E" name="1"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x09" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F67J60.xml b/src/devices/pic/xml_data/18F67J60.xml
new file mode 100644
index 0000000..29922db
--- /dev/null
+++ b/src/devices/pic/xml_data/18F67J60.xml
@@ -0,0 +1,185 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F67J60" document="026445" status="IP" memory_technology="FLASH" architecture="18J" id="0x1F20" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="41.6667" vdd_min="2.7" vdd_max="3.6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="2.7" />
+    <frequency start="4" end="41.6667" vdd_min="2.35" vdd_max="2.7" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3"   max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6"   nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3"   max="3.6"   nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x01FFF7" word_write_align="32" word_erase_align="512" />
+  <memory name="config"       start="0x01FFF8" end="0x01FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="ETHLED" value="0x01" >
+      <value value="0x00" name="Off"  cname=""  />
+      <value value="0x01" name="On"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F8310.xml b/src/devices/pic/xml_data/18F8310.xml
new file mode 100644
index 0000000..1fe084d
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8310.xml
@@ -0,0 +1,266 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8310" document="019695" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x0BC0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xE20C" cchecksum="0xE162" />
+    <checksum protected="All" bchecksum="0x0227" cchecksum="0x0222" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"   max="12"  nominal="11" />
+  <voltages name="vdd_prog"       min="2.75" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"    max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x001FFF" word_write_align="8" word_erase_align="0" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xC3" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_PM_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_PM_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_PM_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_PM_MC" />
+    </mask>
+    <mask name="BW"   value="0x40" >
+      <value value="0x00" name="8"  cname="_BW_8" />
+      <value value="0x40" name="16" cname="_BW_16" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7/RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1"     cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x01" >
+    <mask name="CP" value="0x01" >
+      <value value="0x00" name="All" cname="_CP_ON" />
+      <value value="0x01" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x01" >
+    <mask name="EBTR" value="0x01" >
+      <value value="0x00" name="All" cname="_EBTR_ON" />
+      <value value="0x01" name="Off" cname="_EBTR_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F8390.xml b/src/devices/pic/xml_data/18F8390.xml
new file mode 100644
index 0000000..4dbff0c
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8390.xml
@@ -0,0 +1,266 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8390" document="019709" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x0B80" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xE20C" cchecksum="0xE162" />
+    <checksum protected="All" bchecksum="0x0227" cchecksum="0x0222" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"   max="12"  nominal="11" />
+  <voltages name="vdd_prog"       min="2.75" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"    max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x001FFF" word_write_align="8" word_erase_align="0" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xC3" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_PM_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_PM_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_PM_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_PM_MC" />
+    </mask>
+    <mask name="BW"   value="0x40" >
+      <value value="0x00" name="8"  cname="_BW_8" />
+      <value value="0x40" name="16" cname="_BW_16" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7/RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1"     cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x01" >
+    <mask name="CP" value="0x01" >
+      <value value="0x00" name="All" cname="_CP_ON" />
+      <value value="0x01" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x01" >
+    <mask name="EBTR" value="0x01" >
+      <value value="0x00" name="All" cname="_EBTR_ON" />
+      <value value="0x01" name="Off" cname="_EBTR_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F8393.xml b/src/devices/pic/xml_data/18F8393.xml
new file mode 100644
index 0000000..ce846db
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8393.xml
@@ -0,0 +1,254 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8393" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x1A20" >
+  
+  <!--* Documents ************************************************************-->
+  <documents webpage="530833" datasheet="39896" progsheet="39624" erratas="" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xC20C" cchecksum="0xC162" />
+    <checksum protected="All" bchecksum="0x0225" cchecksum="0x0220" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"   max="12"  nominal="11" />
+  <voltages name="vdd_prog"       min="2.75" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"    max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x001FFF" word_write_align="8" word_erase_align="0" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xC3" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7/RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1"     cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x01" >
+    <mask name="CP" value="0x01" >
+      <value value="0x00" name="All" cname="_CP_ON" />
+      <value value="0x01" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x01" >
+    <mask name="EBTR" value="0x01" >
+      <value value="0x00" name="All" cname="_EBTR_ON" />
+      <value value="0x01" name="Off" cname="_EBTR_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F83J11.xml b/src/devices/pic/xml_data/18F83J11.xml
new file mode 100644
index 0000000..4a9d249
--- /dev/null
+++ b/src/devices/pic/xml_data/18F83J11.xml
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F83J11" status="IP" memory_technology="FLASH" architecture="18J" id="0x3980" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026362" datasheet="39774" progsheet="39644" erratas="80318" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x001FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x001FF8" end="0x001FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x03" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F83J90.xml b/src/devices/pic/xml_data/18F83J90.xml
new file mode 100644
index 0000000..8e10c27
--- /dev/null
+++ b/src/devices/pic/xml_data/18F83J90.xml
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F83J90" status="IP" memory_technology="FLASH" architecture="18J" id="0x3880" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026344" datasheet="39774" progsheet="39644" erratas="80318" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x001FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x001FF8" end="0x001FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x03" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F8410.xml b/src/devices/pic/xml_data/18F8410.xml
new file mode 100644
index 0000000..b5c49cd
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8410.xml
@@ -0,0 +1,251 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8410" document="010317" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x06C0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xC20C" cchecksum="0xC162" />
+    <checksum protected="All" bchecksum="0x0225" cchecksum="0x0220" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"   max="12"  nominal="11" />
+  <voltages name="vdd_prog"       min="2.75" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"    max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="8" word_erase_align="0" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xC3" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7/RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1"     cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x01" >
+    <mask name="CP" value="0x01" >
+      <value value="0x00" name="All" cname="_CP_ON" />
+      <value value="0x01" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x01" >
+    <mask name="EBTR" value="0x01" >
+      <value value="0x00" name="All" cname="_EBTR_ON" />
+      <value value="0x01" name="Off" cname="_EBTR_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F8490.xml b/src/devices/pic/xml_data/18F8490.xml
new file mode 100644
index 0000000..3871a60
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8490.xml
@@ -0,0 +1,251 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8490" document="010318" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x0680" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xC20C" cchecksum="0xC162" />
+    <checksum protected="All" bchecksum="0x0225" cchecksum="0x0220" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"   max="12"  nominal="11" />
+  <voltages name="vdd_prog"       min="2.75" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"    max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="8" word_erase_align="0" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xC3" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7/RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1"     cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x01" >
+    <mask name="CP" value="0x01" >
+      <value value="0x00" name="All" cname="_CP_ON" />
+      <value value="0x01" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x01" >
+    <mask name="EBTR" value="0x01" >
+      <value value="0x00" name="All" cname="_EBTR_ON" />
+      <value value="0x01" name="Off" cname="_EBTR_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F8493.xml b/src/devices/pic/xml_data/18F8493.xml
new file mode 100644
index 0000000..4e8bc52
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8493.xml
@@ -0,0 +1,254 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8493" status="IP" memory_technology="FLASH" self_write="no" architecture="18F" id="0x0E20" >
+  
+  <!--* Documents ************************************************************-->
+  <documents webpage="530832" datasheet="39896" progsheet="39624" erratas="" />
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected="Off" bchecksum="0xC20C" cchecksum="0xC162" />
+    <checksum protected="All" bchecksum="0x0225" cchecksum="0x0220" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="10"   max="12"  nominal="11" />
+  <voltages name="vdd_prog"       min="2.75" max="5.5" nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"    max="5.5" nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="8" word_erase_align="0" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xC3" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x81" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7/RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1"     cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x81" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x01" >
+    <mask name="CP" value="0x01" >
+      <value value="0x00" name="All" cname="_CP_ON" />
+      <value value="0x01" name="Off" cname="_CP_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x01" >
+    <mask name="EBTR" value="0x01" >
+      <value value="0x00" name="All" cname="_EBTR_ON" />
+      <value value="0x01" name="Off" cname="_EBTR_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x00" />
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F84J11.xml b/src/devices/pic/xml_data/18F84J11.xml
new file mode 100644
index 0000000..9c69d2b
--- /dev/null
+++ b/src/devices/pic/xml_data/18F84J11.xml
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F84J11" status="IP" memory_technology="FLASH" architecture="18J" id="0x39A0" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026361" datasheet="39774" progsheet="39644" erratas="80318" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x003FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x003FF8" end="0x003FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x03" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F84J90.xml b/src/devices/pic/xml_data/18F84J90.xml
new file mode 100644
index 0000000..59711f3
--- /dev/null
+++ b/src/devices/pic/xml_data/18F84J90.xml
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F84J90" status="IP" memory_technology="FLASH" architecture="18J" id="0x38A0" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026343" datasheet="39774" progsheet="39644" erratas="80318" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x003FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x003FF8" end="0x003FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x03" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F8520.xml b/src/devices/pic/xml_data/18F8520.xml
new file mode 100644
index 0000000..6bc1aae
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8520.xml
@@ -0,0 +1,311 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8520" document="010319" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0B00" >
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected_blocks="0" bchecksum="0x05AA" cchecksum="0x0500" />
+    <checksum protected_blocks="1" bchecksum="0x0783" cchecksum="0x071A" />
+    <checksum protected_blocks="3" bchecksum="0x8580" cchecksum="0x8517" />
+    <checksum protected_blocks="5" bchecksum="0x0484" cchecksum="0x0470" />
+  </checksums>
+-->
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+    <frequency start="4" end="25" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x007FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.5" cname="_BORV_25" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x83" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_MODE_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_MODE_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_MODE_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_MODE_MC" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" cmask="0x02" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MUX_RE7" />
+      <value value="0x01" name="RC1" cname="_CCP2MUX_RC1" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" cmask="0x40" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" cmask="0x40" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F8525.xml b/src/devices/pic/xml_data/18F8525.xml
new file mode 100644
index 0000000..e7b5219
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8525.xml
@@ -0,0 +1,312 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8525" document="010320" status="NR" alternative="18F8527" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0AC0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+    <frequency start="4" end="25" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00BFFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x2F" >
+    <mask name="FOSC"   value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+      <value value="default" name="invalid" />
+      <value value="0x0C" name="E4_IO"        cname="_OSC_ECIOPLL" />
+      <value value="0x0D" name="E4S_IO"       cname="_OSC_ECIOSWPLL" />
+      <value value="0x0E" name="H4S"          cname="_OSC_HSSWPLL" />
+      <value value="0x0F" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x83" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_MODE_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_MODE_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_MODE_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_MODE_MC" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x02" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4" cname="_ECCPMX_PORTH" />
+      <value value="0x02" name="RE6-RE3" cname="_ECCPMX_PORTE" />
+    </mask>
+    <mask name="MCLRE"  value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F8527.xml b/src/devices/pic/xml_data/18F8527.xml
new file mode 100644
index 0000000..62c01d4
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8527.xml
@@ -0,0 +1,346 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8527" document="021968" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1360" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="20" vdd_min="4.2" vdd_max="5.5" mode="8-bit external memory" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+    <frequency start="4" end="25" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" mode="8-bit external memory" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="20" vdd_min="4.2" vdd_max="5.5" mode="8-bit external memory" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00BFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"     />
+      <value value="0x01" name="XT"           cname="_XT_OSC"     />
+      <value value="0x02" name="HS"           cname="_HS_OSC"     />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"     />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"   />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"   />
+      <value value="0x08" name="INTRC_IO"     cname="_INTIO2_OSC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_INTIO1_OSC" />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FSCM_OFF" />
+      <value value="0x40" name="On"  cname="_FSCM_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1K"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2K"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4K"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8K"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16K" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32K" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF3" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_MODE_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_MODE_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_MODE_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_MODE_MC" />
+    </mask>
+    <mask name="ABW"  value="0x30" >
+      <value value="0x00" name="8"  cname="_ADDRBW_ADDR8BIT" />
+      <value value="0x10" name="12" cname="_ADDRBW_ADDR12BIT" />
+      <value value="0x20" name="16" cname="_ADDRBW_ADDR16BIT" />
+      <value value="0x30" name="20" cname="_ADDRBW_ADDR20BIT" />
+    </mask>
+    <mask name="BW"   value="0x40" >
+      <value value="0x00" name="8"  cname="_DATABW_DATA8BIT" />
+      <value value="0x40" name="16" cname="_DATABW_DATA16BIT" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x02" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="ECCPMX"  value="0x02" >
+      <value value="0x00" name="RH7-RH4" cname="_ECCPMX_PORTH" />
+      <value value="0x02" name="RE6-RE3" cname="_ECCPMX_PORTE" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_BB2K" />
+      <value value="0x10" name="2048" cname="_BBSIZ_BB4K" />
+      <value value="0x20" name="4096" cname="_BBSIZ_BB8K" />
+      <value value="0x30" name="4096" cname="_BBSIZ_BB8K" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F8585.xml b/src/devices/pic/xml_data/18F8585.xml
new file mode 100644
index 0000000..08367ab
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8585.xml
@@ -0,0 +1,312 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8585" document="010321" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0A40" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+    <frequency start="4" end="25" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00BFFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x2F" >
+    <mask name="FOSC"   value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+      <value value="default" name="invalid" />
+      <value value="0x0C" name="E4_IO"        cname="_OSC_ECIOPLL" />
+      <value value="0x0D" name="E4S_IO"       cname="_OSC_ECIOSWPLL" />
+      <value value="0x0E" name="H4S"          cname="_OSC_HSSWPLL" />
+      <value value="0x0F" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x83" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_MODE_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_MODE_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_MODE_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_MODE_MC" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x02" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_OFF" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH6" cname="_ECCPMX_PORTH" />
+      <value value="0x02" name="RE6-RE5" cname="_ECCPMX_PORTE" />
+    </mask>
+    <mask name="MCLRE"  value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x07" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x07" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F85J10.xml b/src/devices/pic/xml_data/18F85J10.xml
new file mode 100644
index 0000000..99b998c
--- /dev/null
+++ b/src/devices/pic/xml_data/18F85J10.xml
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F85J10" status="IP" memory_technology="FLASH" architecture="18J" id="0x15E0" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="022353" datasheet="39663" progsheet="39644" erratas="80315 80246 80341 80340" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x007FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x007FF8" end="0x007FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x03" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F85J11.xml b/src/devices/pic/xml_data/18F85J11.xml
new file mode 100644
index 0000000..91b4cc2
--- /dev/null
+++ b/src/devices/pic/xml_data/18F85J11.xml
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F85J11" status="IP" memory_technology="FLASH" architecture="18J" id="0x39E0" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026360" datasheet="39774" progsheet="39644" erratas="80318" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x007FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x007FF8" end="0x007FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x03" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F85J15.xml b/src/devices/pic/xml_data/18F85J15.xml
new file mode 100644
index 0000000..c2445ab
--- /dev/null
+++ b/src/devices/pic/xml_data/18F85J15.xml
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F85J15" status="IP" memory_technology="FLASH" architecture="18J" id="0x1700" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="022352" datasheet="39663" progsheet="39644" erratas="80315 80246 80341 80340" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x00BFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x00BFF8" end="0x00BFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x03" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F85J50.xml b/src/devices/pic/xml_data/18F85J50.xml
new file mode 100644
index 0000000..dee0637
--- /dev/null
+++ b/src/devices/pic/xml_data/18F85J50.xml
@@ -0,0 +1,161 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F85J50" status="IP" memory_technology="FLASH" architecture="18J" id="0x41A0" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027176" datasheet="39775" progsheet="39644" erratas="80321" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x007FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x007FF8" end="0x007FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xEF" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="PLLDIV"  value="0x0E" >
+      <value value="0x00" name="12" cname="" />
+      <value value="0x02" name="10" cname="" />
+      <value value="0x04" name="6"  cname="" />
+      <value value="0x06" name="5"  cname="" />
+      <value value="0x08" name="4"  cname="" />
+      <value value="0x0A" name="3"  cname="" />
+      <value value="0x0C" name="2"  cname="" />
+      <value value="0x0E" name="1"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+    <mask name="PMPMX" value="0x04" >
+      <value value="0x00" name="NotConnected"  cname="" />
+      <value value="0x04" name="Connected"     cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F85J90.xml b/src/devices/pic/xml_data/18F85J90.xml
new file mode 100644
index 0000000..61e7571
--- /dev/null
+++ b/src/devices/pic/xml_data/18F85J90.xml
@@ -0,0 +1,142 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F85J90" status="IP" memory_technology="FLASH" architecture="18J" id="0x38E0" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026342" datasheet="39770" progsheet="39644" erratas="80286 80312" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x007FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x007FF8" end="0x007FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x03" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F8620.xml b/src/devices/pic/xml_data/18F8620.xml
new file mode 100644
index 0000000..8503556
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8620.xml
@@ -0,0 +1,311 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8620" document="010322" status="NR" alternative="18F8622" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0640" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0x035B" cchecksum="0x02B1" />
+    <checksum protected_blocks="1" bchecksum="0x052E" cchecksum="0x04D4" />
+    <checksum protected_blocks="3" bchecksum="0x832B" cchecksum="0x82D1" />
+    <checksum protected_blocks="5" bchecksum="0x031F" cchecksum="0x031A" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="16" vdd_min="4.2" vdd_max="5.5" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="25" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+    <frequency start="4" end="16" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="16" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    sdcc_cname="_OSC_LP" />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    sdcc_cname="_OSC_XT" />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    sdcc_cname="_OSC_HS" />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    sdcc_cname="_OSC_RC" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    sdcc_cname="_OSC_EC_OSC2_Clock_Out" />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  sdcc_cname="_OSC_EC_OSC2_RA6" />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" sdcc_cname="_OSC_HS_PLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  sdcc_cname="_OSC_RC_OSC2" />
+   </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x0C" name="2.5" cname="_BORV_20" sdcc_cname="_BODENV_2_5V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x83" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_XMC_MODE" sdcc_cname="_PMODE_EXT" />
+      <value value="0x01" name="Microprocessor with boot" cname="_MPB_MODE" sdcc_cname="_PMODE_MICROPROCESSOR_w_Boot" />
+      <value value="0x02" name="Microprocessor"           cname="_MP_MODE"  sdcc_cname="_PMODE_MICROPROCESSOR_" />
+      <value value="0x03" name="Microcontroller"          cname="_MC_MODE"  sdcc_cname="_PMODE_MICROCONTROLLER" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_OFF" sdcc_cname="_CCP2MUX_RE7_MICROCONTROLLER__RB3" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON"  sdcc_cname="_CCP2MUX_RC1" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:3FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  sdcc_cname="_CP_2_ON" />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" sdcc_cname="_CP_2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  sdcc_cname="_CP_3_ON" />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" sdcc_cname="_CP_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:3FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON"  sdcc_cname="_WRT_2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" sdcc_cname="_WRT_2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON"  sdcc_cname="_WRT_3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" sdcc_cname="_WRT_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:3FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  sdcc_cname="_EBTR_2_ON" />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" sdcc_cname="_EBTR_2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON"  sdcc_cname="_EBTR_3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" sdcc_cname="_EBTR_3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F8621.xml b/src/devices/pic/xml_data/18F8621.xml
new file mode 100644
index 0000000..e5689ae
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8621.xml
@@ -0,0 +1,324 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8621" document="010323" status="NR" alternative="18F8622" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0A80" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+    <frequency start="4" end="25" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x2F" >
+    <mask name="FOSC"   value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+      <value value="default" name="invalid" />
+      <value value="0x0C" name="E4_IO"        cname="_OSC_ECIOPLL" />
+      <value value="0x0D" name="E4S_IO"       cname="_OSC_ECIOSWPLL" />
+      <value value="0x0E" name="H4S"          cname="_OSC_HSSWPLL" />
+      <value value="0x0F" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x83" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_MODE_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_MODE_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_MODE_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_MODE_MC" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x02" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4" cname="_ECCPMX_PORTH" />
+      <value value="0x02" name="RE6-RE3" cname="_ECCPMX_PORTE" />
+    </mask>
+    <mask name="MCLRE"  value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" cmask="0x08" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" cmask="0x08" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" cmask="0x08" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F8622.xml b/src/devices/pic/xml_data/18F8622.xml
new file mode 100644
index 0000000..fe29be9
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8622.xml
@@ -0,0 +1,358 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8622" document="021967" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x13A0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="20" vdd_min="4.2" vdd_max="5.5" mode="8-bit external memory" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+    <frequency start="4" end="25" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" mode="8-bit external memory" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="20" vdd_min="4.2" vdd_max="5.5" mode="8-bit external memory" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"     />
+      <value value="0x01" name="XT"           cname="_XT_OSC"     />
+      <value value="0x02" name="HS"           cname="_HS_OSC"     />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"     />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"   />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"   />
+      <value value="0x08" name="INTRC_IO"     cname="_INTIO2_OSC" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_INTIO1_OSC" />
+      <value value="0x0A" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0B" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0C" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0D" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0E" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+      <value value="0x0F" name="EXTRC_CLKOUT" cname="_RC_OSC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FSCM_OFF" />
+      <value value="0x40" name="On"  cname="_FSCM_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1K"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2K"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4K"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8K"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16K" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32K" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF3" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_MODE_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_MODE_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_MODE_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_MODE_MC" />
+    </mask>
+    <mask name="ABW"  value="0x30" >
+      <value value="0x00" name="8"  cname="_ADDRBW_ADDR8BIT" />
+      <value value="0x10" name="12" cname="_ADDRBW_ADDR12BIT" />
+      <value value="0x20" name="16" cname="_ADDRBW_ADDR16BIT" />
+      <value value="0x30" name="20" cname="_ADDRBW_ADDR20BIT" />
+    </mask>
+    <mask name="BW"   value="0x40" >
+      <value value="0x00" name="8"  cname="_DATABW_DATA8BIT" />
+      <value value="0x40" name="16" cname="_DATABW_DATA16BIT" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x02" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CPP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CPP2MX_PORTC" />
+    </mask>
+    <mask name="ECCPMX"  value="0x02" >
+      <value value="0x00" name="RH7-RH6" cname="_ECCPMX_PORTH" />
+      <value value="0x02" name="RE6-RE5" cname="_ECCPMX_PORTE" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_BB2K" />
+      <value value="0x10" name="2048" cname="_BBSIZ_BB4K" />
+      <value value="0x20" name="4096" cname="_BBSIZ_BB8K" />
+      <value value="0x30" name="4096" cname="_BBSIZ_BB7K" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F8627.xml b/src/devices/pic/xml_data/18F8627.xml
new file mode 100644
index 0000000..2b7f70b
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8627.xml
@@ -0,0 +1,376 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8627" document="010324" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x13E0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="20" vdd_min="4.2" vdd_max="5.5" mode="8-bit external memory" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+    <frequency start="4" end="25" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" mode="8-bit external memory" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="20" vdd_min="4.2" vdd_max="5.5" mode="8-bit external memory" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x017FFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF3" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_MODE_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_MODE_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_MODE_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_MODE_MC" />
+    </mask>
+    <mask name="ABW"  value="0x30" >
+      <value value="0x00" name="8"  cname="_ADDRBW_ADDR8BIT" />
+      <value value="0x10" name="12" cname="_ADDRBW_ADDR12BIT" />
+      <value value="0x20" name="16" cname="_ADDRBW_ADDR16BIT" />
+      <value value="0x30" name="20" cname="_ADDRBW_ADDR20BIT" />
+    </mask>
+    <mask name="BW"   value="0x40" >
+      <value value="0x00" name="8"  cname="_DATABW_DATA8BIT" />
+      <value value="0x40" name="16" cname="_DATABW_DATA16BIT" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x02" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="ECCPMX"  value="0x02" >
+      <value value="0x00" name="RH7-RH6" cname="_ECCPMX_PORTH" />
+      <value value="0x02" name="RE6-RE5" cname="_ECCPMX_PORTE" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_BB2K" />
+      <value value="0x10" name="2048" cname="_BBSIZ_BB4K" />
+      <value value="0x20" name="4096" cname="_BBSIZ_BB8K" />
+      <value value="0x30" name="4096" cname="_BBSIZ_BB8K" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x3F" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+    <mask name="CP_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_CP4_ON" />
+      <value value="0x10" name="Off"         cname="_CP4_OFF" />
+    </mask>
+    <mask name="CP_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_CP5_ON" />
+      <value value="0x20" name="Off"         cname="_CP5_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x3F" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+    <mask name="WRT_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_WRT4_ON" />
+      <value value="0x10" name="Off"         cname="_WRT4_OFF" />
+    </mask>
+    <mask name="WRT_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_WRT5_ON" />
+      <value value="0x20" name="Off"         cname="_WRT5_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x3F" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+    <mask name="EBTR_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_EBTR4_ON" />
+      <value value="0x10" name="Off"         cname="_EBTR4_OFF" />
+    </mask>
+    <mask name="EBTR_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_EBTR5_ON" />
+      <value value="0x20" name="Off"         cname="_EBTR5_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F8680.xml b/src/devices/pic/xml_data/18F8680.xml
new file mode 100644
index 0000000..97ec3c0
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8680.xml
@@ -0,0 +1,324 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8680" document="010325" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0A00" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+    <frequency start="4" end="25" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x2F" >
+    <mask name="FOSC"   value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"    />
+      <value value="0x01" name="XT"           cname="_OSC_XT"    />
+      <value value="0x02" name="HS"           cname="_OSC_HS"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_OSC_RC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"    />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO"  />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+      <value value="default" name="invalid" />
+      <value value="0x0C" name="E4_IO"        cname="_OSC_ECIOPLL" />
+      <value value="0x0D" name="E4S_IO"       cname="_OSC_ECIOSWPLL" />
+      <value value="0x0E" name="H4S"          cname="_OSC_HSSWPLL" />
+      <value value="0x0F" name="EXTRC_IO"     cname="_OSC_RCIO"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x83" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_MODE_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_MODE_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_MODE_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_MODE_MC" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x02" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_OFF" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH6" cname="_ECCPMX_PORTH" />
+      <value value="0x02" name="RE6-RE5" cname="_ECCPMX_PORTE" />
+    </mask>
+    <mask name="MCLRE"  value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" cmask="0x08" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" cmask="0x08" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" cmask="0x08" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F86J10.xml b/src/devices/pic/xml_data/18F86J10.xml
new file mode 100644
index 0000000..6cc1ec1
--- /dev/null
+++ b/src/devices/pic/xml_data/18F86J10.xml
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F86J10" status="IP" memory_technology="FLASH" architecture="18J" id="0x1720" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="022351" datasheet="39663" progsheet="39644" erratas="80315 80246 80341 80340" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x00FFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x00FFF8" end="0x00FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x03" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F86J11.xml b/src/devices/pic/xml_data/18F86J11.xml
new file mode 100644
index 0000000..05e065e
--- /dev/null
+++ b/src/devices/pic/xml_data/18F86J11.xml
@@ -0,0 +1,152 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F86J11" status="IP" memory_technology="FLASH" architecture="18J" id="0x44E0" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027151" datasheet="39778" progsheet="39644" erratas="80305 80344" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x00FFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x00FFF8" end="0x00FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+    <mask name="PMPMX" value="0x04" >
+      <value value="0x00" name="NotConnected"  cname="" />
+      <value value="0x04" name="Connected"     cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F86J15.xml b/src/devices/pic/xml_data/18F86J15.xml
new file mode 100644
index 0000000..bcebf10
--- /dev/null
+++ b/src/devices/pic/xml_data/18F86J15.xml
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F86J15" status="IP" memory_technology="FLASH" architecture="18J" id="0x1740" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="020088" datasheet="39663" progsheet="39644" erratas="80315 80246 80341 80340" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x017FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x017FF8" end="0x017FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x03" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F86J16.xml b/src/devices/pic/xml_data/18F86J16.xml
new file mode 100644
index 0000000..b06b858
--- /dev/null
+++ b/src/devices/pic/xml_data/18F86J16.xml
@@ -0,0 +1,151 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F86J16" status="IP" memory_technology="FLASH" architecture="18J" id="0x4500" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027150" datasheet="39778" progsheet="39644" erratas="80305 80344" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x017FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x017FF8" end="0x017FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+    <mask name="PMPMX" value="0x04" >
+      <value value="0x00" name="NotConnected"  cname="" />
+      <value value="0x04" name="Connected"     cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F86J50.xml b/src/devices/pic/xml_data/18F86J50.xml
new file mode 100644
index 0000000..fa67e08
--- /dev/null
+++ b/src/devices/pic/xml_data/18F86J50.xml
@@ -0,0 +1,161 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F86J50" status="IP" memory_technology="FLASH" architecture="18J" id="0x41E0" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027175" datasheet="39775" progsheet="39644" erratas="80321" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x00FFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x00FFF8" end="0x00FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xEF" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="PLLDIV"  value="0x0E" >
+      <value value="0x00" name="12" cname="" />
+      <value value="0x02" name="10" cname="" />
+      <value value="0x04" name="6"  cname="" />
+      <value value="0x06" name="5"  cname="" />
+      <value value="0x08" name="4"  cname="" />
+      <value value="0x0A" name="3"  cname="" />
+      <value value="0x0C" name="2"  cname="" />
+      <value value="0x0E" name="1"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+    <mask name="PMPMX" value="0x04" >
+      <value value="0x00" name="NotConnected"  cname="" />
+      <value value="0x04" name="Connected"     cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F86J55.xml b/src/devices/pic/xml_data/18F86J55.xml
new file mode 100644
index 0000000..9b29823
--- /dev/null
+++ b/src/devices/pic/xml_data/18F86J55.xml
@@ -0,0 +1,161 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F86J55" status="IP" memory_technology="FLASH" architecture="18J" id="0x4200" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027181" datasheet="39775" progsheet="39644" erratas="80321" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x017FF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x017FF8" end="0x017FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xEF" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="PLLDIV"  value="0x0E" >
+      <value value="0x00" name="12" cname="" />
+      <value value="0x02" name="10" cname="" />
+      <value value="0x04" name="6"  cname="" />
+      <value value="0x06" name="5"  cname="" />
+      <value value="0x08" name="4"  cname="" />
+      <value value="0x0A" name="3"  cname="" />
+      <value value="0x0C" name="2"  cname="" />
+      <value value="0x0E" name="1"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+    <mask name="PMPMX" value="0x04" >
+      <value value="0x00" name="NotConnected"  cname="" />
+      <value value="0x04" name="Connected"     cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F86J60.xml b/src/devices/pic/xml_data/18F86J60.xml
new file mode 100644
index 0000000..42f3d20
--- /dev/null
+++ b/src/devices/pic/xml_data/18F86J60.xml
@@ -0,0 +1,196 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F86J60" status="IP" memory_technology="FLASH" architecture="18J" id="0x1820" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026444" datasheet="39762" progsheet="39688" erratas="80292" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="41.6667" vdd_min="2.7" vdd_max="3.6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="2.7" />
+    <frequency start="4" end="41.6667" vdd_min="2.35" vdd_max="2.7" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3"   max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6"   nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3"   max="3.6"   nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFF7" word_write_align="32" word_erase_align="512" />
+  <memory name="config"       start="0x00FFF8" end="0x00FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x07" >
+    <mask name="ETHLED" value="0x01" >
+      <value value="0x00" name="Off"  cname=""  />
+      <value value="0x01" name="On"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"     cname="" />
+      <value value="0x02" name="RE6-RE3"     cname=""  />
+    </mask>
+    <mask name="CCP2MX"  value="0x04" >
+      <value value="0x00" name="RE7" cname="" />
+      <value value="0x04" name="RC1" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F86J65.xml b/src/devices/pic/xml_data/18F86J65.xml
new file mode 100644
index 0000000..c2cdf41
--- /dev/null
+++ b/src/devices/pic/xml_data/18F86J65.xml
@@ -0,0 +1,193 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F86J65" document="026443" status="IP" memory_technology="FLASH" architecture="18J" id="0x1F40" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="41.6667" vdd_min="2.7" vdd_max="3.6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="2.7" />
+    <frequency start="4" end="41.6667" vdd_min="2.35" vdd_max="2.7" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3"   max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6"   nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3"   max="3.6"   nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x017FF7" word_write_align="32" word_erase_align="512" />
+  <memory name="config"       start="0x017FF8" end="0x017FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x07" >
+    <mask name="ETHLED" value="0x01" >
+      <value value="0x00" name="Off"  cname=""  />
+      <value value="0x01" name="On"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"     cname="" />
+      <value value="0x02" name="RE6-RE3"     cname=""  />
+    </mask>
+    <mask name="CCP2MX"  value="0x04" >
+      <value value="0x00" name="RE7" cname="" />
+      <value value="0x04" name="RC1" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F8720.xml b/src/devices/pic/xml_data/18F8720.xml
new file mode 100644
index 0000000..f634b25
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8720.xml
@@ -0,0 +1,359 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8720" document="010326" status="NR" alternative="18F8722" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0600" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0x062B" cchecksum="0x0581" />
+    <checksum protected_blocks="1" bchecksum="0x07FE" cchecksum="0x07A4" />
+    <checksum protected_blocks="3" bchecksum="0x85FB" cchecksum="0x85A1" />
+    <checksum protected_blocks="9" bchecksum="0x04FF" cchecksum="0x04FA" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="16" vdd_min="4.2" vdd_max="5.5" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="25" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+    <frequency start="4" end="16" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" mode="not microcontroller" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="16" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x01FFFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
+    <mask name="FOSC"   value="0x07" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"    />
+      <value value="0x01" name="XT"           cname="_XT_OSC"    />
+      <value value="0x02" name="HS"           cname="_HS_OSC"    />
+      <value value="0x03" name="EXTRC_CLKOUT" cname="_RC_OSC"    />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"    />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  />
+    </mask>
+    <mask name="OSCSEN" value="0x20" >
+      <value value="0x00" name="On"  cname="_OSCS_ON" />
+      <value value="0x20" name="Off" cname="_OSCS_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" />
+      <value value="0x04" name="4.2" cname="_BORV_42" />
+      <value value="0x08" name="2.7" cname="_BORV_27" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x0E" >
+      <value value="0x00" name="1:1"   cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"   cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"   cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"   cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"  cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"  cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"  cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128" cname="_WDTPS_128" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x83" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_XMC_MODE" />
+      <value value="0x01" name="Microprocessor with boot" cname="_MPB_MODE" />
+      <value value="0x02" name="Microprocessor"           cname="_MP_MODE" />
+      <value value="0x03" name="Microcontroller"          cname="_MC_MODE" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RE7" cname="_CCP2MX_OFF" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_ON" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+    <mask name="CP_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_CP4_ON" />
+      <value value="0x10" name="Off"         cname="_CP4_OFF" />
+    </mask>
+    <mask name="CP_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_CP5_ON" />
+      <value value="0x20" name="Off"         cname="_CP5_OFF" />
+    </mask>
+    <mask name="CP_6" value="0x40" >
+      <value value="0x00" name="18000:1BFFF" cname="_CP6_ON" />
+      <value value="0x40" name="Off"         cname="_CP6_OFF" />
+    </mask>
+    <mask name="CP_7" value="0x80" >
+      <value value="0x00" name="1C000:1FFFF" cname="_CP7_ON" />
+      <value value="0x80" name="Off"         cname="_CP7_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+    <mask name="WRT_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_WRT4_ON" />
+      <value value="0x10" name="Off"         cname="_WRT4_OFF" />
+    </mask>
+    <mask name="WRT_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_WRT5_ON" />
+      <value value="0x20" name="Off"         cname="_WRT5_OFF" />
+    </mask>
+    <mask name="WRT_6" value="0x40" >
+      <value value="0x00" name="18000:1BFFF" cname="_WRT6_ON" />
+      <value value="0x40" name="Off"         cname="_WRT6_OFF" />
+    </mask>
+    <mask name="WRT_7" value="0x80" >
+      <value value="0x00" name="1C000:1FFFF" cname="_WRT7_ON" />
+      <value value="0x80" name="Off"         cname="_WRT7_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+    <mask name="EBTR_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_EBTR4_ON" />
+      <value value="0x10" name="Off"         cname="_EBTR4_OFF" />
+    </mask>
+    <mask name="EBTR_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_EBTR5_ON" />
+      <value value="0x20" name="Off"         cname="_EBTR5_OFF" />
+    </mask>
+    <mask name="EBTR_6" value="0x40" >
+      <value value="0x00" name="18000:1BFFF" cname="_EBTR6_ON" />
+      <value value="0x40" name="Off"         cname="_EBTR6_OFF" />
+    </mask>
+    <mask name="EBTR_7" value="0x80" >
+      <value value="0x00" name="1C000:1FFFF" cname="_EBTR7_ON" />
+      <value value="0x80" name="Off"         cname="_EBTR7_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:07FF" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F8722.xml b/src/devices/pic/xml_data/18F8722.xml
new file mode 100644
index 0000000..3db0bbd
--- /dev/null
+++ b/src/devices/pic/xml_data/18F8722.xml
@@ -0,0 +1,400 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F8722" document="010327" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x1420" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="20" vdd_min="4.2" vdd_max="5.5" mode="8-bit external memory" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+    <frequency start="4" end="25" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" mode="8-bit external memory" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+    <frequency start="0" end="20" vdd_min="4.2" vdd_max="5.5" mode="8-bit external memory" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x01FFFF" word_write_align="32" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0003FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x07" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_OSC_LP"     />
+      <value value="0x01" name="XT"           cname="_OSC_XT"     />
+      <value value="0x02" name="HS"           cname="_OSC_HS"     />
+      <value value="0x04" name="EC_CLKOUT"    cname="_OSC_EC"     />
+      <value value="0x05" name="EC_IO"        cname="_OSC_ECIO6"   />
+      <value value="0x06" name="H4"           cname="_OSC_HSPLL"  />
+      <value value="0x07" name="EXTRC_IO"     cname="_OSC_RCIO6"   />
+      <value value="0x08" name="INTRC_IO"     cname="_OSC_INTIO67" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_OSC_INTIO7" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_OSC_RC"     />
+   </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FCMEN_ON"  />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x06" >
+      <value value="0x00" name="Off"      cname="_BOREN_OFF" />
+      <value value="0x02" name="Software" cname="_BOREN_ON" />
+      <value value="0x04" name="On_run"   cname="_BOREN_NOSLP" />
+      <value value="0x06" name="On"       cname="_BOREN_SBORDIS" />
+    </mask>
+    <mask name="BORV"  value="0x18" >
+      <value value="0x00" name="4.5" cname="_BORV_0" />
+      <value value="0x08" name="4.2" cname="_BORV_1" />
+      <value value="0x10" name="2.7" cname="_BORV_2" />
+      <value value="0x18" name="2.0" cname="_BORV_3" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1024"  />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2048"  />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4096"  />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8192"  />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF3" >
+    <mask name="PM"   value="0x03" >
+      <value value="0x00" name="Extended microcontroller" cname="_MODE_EM" />
+      <value value="0x01" name="Microprocessor with boot" cname="_MODE_MPB" />
+      <value value="0x02" name="Microprocessor"           cname="_MODE_MP" />
+      <value value="0x03" name="Microcontroller"          cname="_MODE_MC" />
+    </mask>
+    <mask name="ABW"  value="0x30" >
+      <value value="0x00" name="8"  cname="_ADDRBW_ADDR8BIT" />
+      <value value="0x10" name="12" cname="_ADDRBW_ADDR12BIT" />
+      <value value="0x20" name="16" cname="_ADDRBW_ADDR16BIT" />
+      <value value="0x30" name="20" cname="_ADDRBW_ADDR20BIT" />
+    </mask>
+    <mask name="BW"   value="0x40" >
+      <value value="0x00" name="8"  cname="_DATABW_DATA8BIT" />
+      <value value="0x40" name="16" cname="_DATABW_DATA16BIT" />
+    </mask>
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On"  cname="_WAIT_ON" />
+      <value value="0x80" name="Off" cname="_WAIT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x02" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RB3" cname="_CCP2MX_PORTBE" />
+      <value value="0x01" name="RC1" cname="_CCP2MX_PORTC" />
+    </mask>
+    <mask name="ECCPMX"  value="0x02" >
+      <value value="0x00" name="RH7-RH6" cname="_ECCPMX_PORTH" />
+      <value value="0x02" name="RE6-RE5" cname="_ECCPMX_PORTE" />
+    </mask>
+    <mask name="LPT1OSC" value="0x04" >
+      <value value="0x00" name="Off" cname="_LPT1OSC_OFF" />
+      <value value="0x04" name="On"  cname="_LPT1OSC_ON" />
+    </mask>
+    <mask name="MCLRE"   value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVREN_OFF" />
+      <value value="0x01" name="On"  cname="_STVREN_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="BBSIZ"  value="0x30" >
+      <value value="0x00" name="1024" cname="_BBSIZ_BB2K" />
+      <value value="0x10" name="2048" cname="_BBSIZ_BB4K" />
+      <value value="0x20" name="4096" cname="_BBSIZ_BB8K" />
+      <value value="0x30" name="4096" cname="_BBSIZ_BB8K" />
+    </mask>
+    <mask name="XINST"  value="0x40" >
+      <value value="0x00" name="Off" cname="_XINST_OFF" />
+      <value value="0x40" name="On"  cname="_XINST_ON" />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_CP0_ON"  />
+      <value value="0x01" name="Off"                 cname="_CP0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_CP1_ON"  />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" />
+    </mask>
+    <mask name="CP_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_CP2_ON"  />
+      <value value="0x04" name="Off"       cname="_CP2_OFF" />
+    </mask>
+    <mask name="CP_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_CP3_ON"  />
+      <value value="0x08" name="Off"       cname="_CP3_OFF" />
+    </mask>
+    <mask name="CP_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_CP4_ON" />
+      <value value="0x10" name="Off"         cname="_CP4_OFF" />
+    </mask>
+    <mask name="CP_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_CP5_ON" />
+      <value value="0x20" name="Off"         cname="_CP5_OFF" />
+    </mask>
+    <mask name="CP_6" value="0x40" >
+      <value value="0x00" name="18000:1BFFF" cname="_CP6_ON" />
+      <value value="0x40" name="Off"         cname="_CP6_OFF" />
+    </mask>
+    <mask name="CP_7" value="0x80" >
+      <value value="0x00" name="1C000:1FFFF" cname="_CP7_ON" />
+      <value value="0x80" name="Off"         cname="_CP7_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="All" cname="_CPB_ON"  />
+      <value value="0x40" name="Off" cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_WRT0_ON"  />
+      <value value="0x01" name="Off"                 cname="_WRT0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_WRT1_ON"  />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" />
+    </mask>
+    <mask name="WRT_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_WRT2_ON" />
+      <value value="0x04" name="Off"       cname="_WRT2_OFF" />
+    </mask>
+    <mask name="WRT_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_WRT3_ON" />
+      <value value="0x08" name="Off"       cname="_WRT3_OFF" />
+    </mask>
+    <mask name="WRT_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_WRT4_ON" />
+      <value value="0x10" name="Off"         cname="_WRT4_OFF" />
+    </mask>
+    <mask name="WRT_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_WRT5_ON" />
+      <value value="0x20" name="Off"         cname="_WRT5_OFF" />
+    </mask>
+    <mask name="WRT_6" value="0x40" >
+      <value value="0x00" name="18000:1BFFF" cname="_WRT6_ON" />
+      <value value="0x40" name="Off"         cname="_WRT6_OFF" />
+    </mask>
+    <mask name="WRT_7" value="0x80" >
+      <value value="0x00" name="1C000:1FFFF" cname="_WRT7_ON" />
+      <value value="0x80" name="Off"         cname="_WRT7_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="All" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off" cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0xFF" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0800/1000/2000:3FFF" cname="_EBTR0_ON"  />
+      <value value="0x01" name="Off"                 cname="_EBTR0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="4000:7FFF" cname="_EBTR1_ON"  />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" />
+    </mask>
+    <mask name="EBTR_2" value="0x04" >
+      <value value="0x00" name="8000:BFFF" cname="_EBTR2_ON"  />
+      <value value="0x04" name="Off"       cname="_EBTR2_OFF" />
+    </mask>
+    <mask name="EBTR_3" value="0x08" >
+      <value value="0x00" name="C000:FFFF" cname="_EBTR3_ON" />
+      <value value="0x08" name="Off"       cname="_EBTR3_OFF" />
+    </mask>
+    <mask name="EBTR_4" value="0x10" >
+      <value value="0x00" name="10000:13FFF" cname="_EBTR4_ON" />
+      <value value="0x10" name="Off"         cname="_EBTR4_OFF" />
+    </mask>
+    <mask name="EBTR_5" value="0x20" >
+      <value value="0x00" name="14000:17FFF" cname="_EBTR5_ON" />
+      <value value="0x20" name="Off"         cname="_EBTR5_OFF" />
+    </mask>
+    <mask name="EBTR_6" value="0x40" >
+      <value value="0x00" name="18000:1BFFF" cname="_EBTR6_ON" />
+      <value value="0x40" name="Off"         cname="_EBTR6_OFF" />
+    </mask>
+    <mask name="EBTR_7" value="0x80" >
+      <value value="0x00" name="1C000:1FFFF" cname="_EBTR7_ON" />
+      <value value="0x80" name="Off"         cname="_EBTR7_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="All" cname="_EBTRB_ON" />
+      <value value="0x40" name="Off" cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/18F87J10.xml b/src/devices/pic/xml_data/18F87J10.xml
new file mode 100644
index 0000000..bc21af2
--- /dev/null
+++ b/src/devices/pic/xml_data/18F87J10.xml
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F87J10" status="IP" memory_technology="FLASH" architecture="18J" id="0x1760" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="020071" datasheet="39663" progsheet="39644" erratas="80315 80246 80341 80340" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="2.65"   max="3.6"   nominal="3.3" />
+  <voltages name="vdd_prog"       min="2.65"   max="3.6"   nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="2.65"   max="3.6"   nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x01FFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x01FFF8" end="0x01FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xC1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x03" >
+    <mask name="CCP2MX"  value="0x01" >
+      <value value="0x00" name="RE7" cname="" />
+      <value value="0x01" name="RC1" cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"     cname="" />
+      <value value="0x02" name="RE6-RE3"     cname=""  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F87J11.xml b/src/devices/pic/xml_data/18F87J11.xml
new file mode 100644
index 0000000..d3c84fb
--- /dev/null
+++ b/src/devices/pic/xml_data/18F87J11.xml
@@ -0,0 +1,151 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F87J11" status="IP" memory_technology="FLASH" architecture="18J" id="0x4520" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027149" datasheet="39778" progsheet="39644" erratas="80305 80344" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x01FFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x01FFF8" end="0x01FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+    <mask name="PMPMX" value="0x04" >
+      <value value="0x00" name="NotConnected"  cname="" />
+      <value value="0x04" name="Connected"     cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F87J50.xml b/src/devices/pic/xml_data/18F87J50.xml
new file mode 100644
index 0000000..1749435
--- /dev/null
+++ b/src/devices/pic/xml_data/18F87J50.xml
@@ -0,0 +1,161 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek                                   *-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F87J50" status="IP" memory_technology="FLASH" architecture="18J" id="0x4220" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="027172" datasheet="39775" progsheet="39644" erratas="80321" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="3.6" />
+    <frequency start="4" end="40" vdd_min="2.0" vdd_min_end="2.35" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6" nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3" max="3.6" nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"         start="0x000000" end="0x01FFF7" word_write_align="32" word_erase_align="0" />
+  <memory name="config"       start="0x01FFF8" end="0x01FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xEF" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="PLLDIV"  value="0x0E" >
+      <value value="0x00" name="12" cname="" />
+      <value value="0x02" name="10" cname="" />
+      <value value="0x04" name="6"  cname="" />
+      <value value="0x06" name="5"  cname="" />
+      <value value="0x08" name="4"  cname="" />
+      <value value="0x0A" name="3"  cname="" />
+      <value value="0x0C" name="2"  cname="" />
+      <value value="0x0E" name="1"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="EASHFT"  value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On"  cname="" />
+    </mask>
+    <mask name="EMB"  value="0x30" >
+      <value value="0x00" name="20BIT"    cname="" />
+      <value value="0x10" name="16BIT"    cname="" />
+      <value value="0x20" name="12BIT"    cname="" />
+      <value value="0x30" name="Disabled" cname="" />
+    </mask>
+    <mask name="BW"  value="0x40" >
+      <value value="0x00" name="8"  cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="WAIT"  value="0x80" >
+      <value value="0x00" name="On"  cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="CCP2MX" value="0x01" >
+      <value value="0x00" name="RB3"  cname=""  />
+      <value value="0x01" name="RC1"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"  cname=""  />
+      <value value="0x02" name="RE6-RE3"   cname="" />
+    </mask>
+    <mask name="PMPMX" value="0x04" >
+      <value value="0x00" name="NotConnected"  cname="" />
+      <value value="0x04" name="Connected"     cname="" />
+    </mask>
+    <mask name="MSSPSEL" value="0x08" >
+      <value value="0x00" name="5BIT"  cname="" />
+      <value value="0x08" name="7BIT"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F87J60.xml b/src/devices/pic/xml_data/18F87J60.xml
new file mode 100644
index 0000000..d101ed3
--- /dev/null
+++ b/src/devices/pic/xml_data/18F87J60.xml
@@ -0,0 +1,193 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F87J60" document="026442" status="IP" memory_technology="FLASH" architecture="18J" id="0x1F60" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="41.6667" vdd_min="2.7" vdd_max="3.6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="2.7" />
+    <frequency start="4" end="41.6667" vdd_min="2.35" vdd_max="2.7" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3"   max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6"   nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3"   max="3.6"   nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x01FFF7" word_write_align="32" word_erase_align="512" />
+  <memory name="config"       start="0x01FFF8" end="0x01FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="0000:FFF7" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x07" >
+    <mask name="ETHLED" value="0x01" >
+      <value value="0x00" name="Off"  cname=""  />
+      <value value="0x01" name="On"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"     cname="" />
+      <value value="0x02" name="RE6-RE3"     cname=""  />
+    </mask>
+    <mask name="CCP2MX"  value="0x04" >
+      <value value="0x00" name="RE7" cname="" />
+      <value value="0x04" name="RC1" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F96J60.xml b/src/devices/pic/xml_data/18F96J60.xml
new file mode 100644
index 0000000..655b586
--- /dev/null
+++ b/src/devices/pic/xml_data/18F96J60.xml
@@ -0,0 +1,211 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F96J60" document="026441" status="IP" memory_technology="FLASH" architecture="18J" id="0x1840" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="41.6667" vdd_min="2.7" vdd_max="3.6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="2.7" />
+    <frequency start="4" end="41.6667" vdd_min="2.35" vdd_max="2.7" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3"   max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6"   nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3"   max="3.6"   nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x00FFF7" word_write_align="32" word_erase_align="512" />
+  <memory name="config"       start="0x00FFF8" end="0x00FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+    <mask name="BW" value="0x40" >
+      <value value="0x00" name="8" cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="EMB" value="0x30" >
+      <value value="0x00" name="Disabled" cname="" />
+      <value value="0x10" name="12BIT" cname="" />
+      <value value="0x20" name="16BIT" cname="" />
+      <value value="0x30" name="20BIT" cname="" />
+    </mask>
+    <mask name="EASHFT" value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x07" >
+    <mask name="ETHLED" value="0x01" >
+      <value value="0x00" name="Off"  cname=""  />
+      <value value="0x01" name="On"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"     cname="" />
+      <value value="0x02" name="RE6-RE3"     cname=""  />
+    </mask>
+    <mask name="CCP2MX"  value="0x04" >
+      <value value="0x00" name="RE7" cname="" />
+      <value value="0x04" name="RC1" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F96J65.xml b/src/devices/pic/xml_data/18F96J65.xml
new file mode 100644
index 0000000..a61bb94
--- /dev/null
+++ b/src/devices/pic/xml_data/18F96J65.xml
@@ -0,0 +1,211 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F96J65" document="026440" status="IP" memory_technology="FLASH" architecture="18J" id="0x1F80" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="41.6667" vdd_min="2.7" vdd_max="3.6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="2.7" />
+    <frequency start="4" end="41.6667" vdd_min="2.35" vdd_max="2.7" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3"   max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6"   nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3"   max="3.6"   nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x017FF7" word_write_align="32" word_erase_align="512" />
+  <memory name="config"       start="0x017FF8" end="0x017FFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+    <mask name="BW" value="0x40" >
+      <value value="0x00" name="8" cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="EMB" value="0x30" >
+      <value value="0x00" name="Disabled" cname="" />
+      <value value="0x10" name="12BIT" cname="" />
+      <value value="0x20" name="16BIT" cname="" />
+      <value value="0x30" name="20BIT" cname="" />
+    </mask>
+    <mask name="EASHFT" value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x07" >
+    <mask name="ETHLED" value="0x01" >
+      <value value="0x00" name="Off"  cname=""  />
+      <value value="0x01" name="On"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"     cname="" />
+      <value value="0x02" name="RE6-RE3"     cname=""  />
+    </mask>
+    <mask name="CCP2MX"  value="0x04" >
+      <value value="0x00" name="RE7" cname="" />
+      <value value="0x04" name="RC1" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/18F97J60.xml b/src/devices/pic/xml_data/18F97J60.xml
new file mode 100644
index 0000000..ce570ba
--- /dev/null
+++ b/src/devices/pic/xml_data/18F97J60.xml
@@ -0,0 +1,211 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Alan Page                                         *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F97J60" document="026439" status="IP" memory_technology="FLASH" architecture="18J" id="0x1FA0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="41.6667" vdd_min="2.7" vdd_max="3.6" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4" vdd_min="2.0" vdd_max="2.7" />
+    <frequency start="4" end="41.6667" vdd_min="2.35" vdd_max="2.7" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3"   max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog"       min="3" max="3.6"   nominal="3.3"  />
+  <voltages name="vdd_prog_write" min="3"   max="3.6"   nominal="3.3"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x01FFF7" word_write_align="32" word_erase_align="512" />
+  <memory name="config"       start="0x01FFF8" end="0x01FFFF" />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0xE1" >
+    <mask name="WDT"  value="0x01" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x01" name="On"  cname="" />
+    </mask>
+    <mask name="STVREN" value="0x20" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x20" name="On"  cname="" />
+    </mask>
+    <mask name="XINST" value="0x40" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x40" name="On"  cname="" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xF7" bvalue="0x04" >
+    <mask name="CP" value="0x04" >
+      <value value="0x00" name="All" cname="" />
+      <value value="0x04" name="Off"  cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0xC7" >
+    <mask name="FOSC"   value="0x03" >
+      <value value="0x00" name="HS"           cname=""    />
+      <value value="0x01" name="HSPLL"        cname=""    />
+      <value value="0x02" name="EC"           cname=""    />
+      <value value="0x03" name="ECPLL_IO"     cname=""    />
+    </mask>
+    <mask name="FOSC2"  value="0x04" >
+      <value value="0x00" name="FOSC1:FOSC0"  cname=""    />
+      <value value="0x04" name="INTRC"        cname=""    />
+    </mask>
+    <mask name="FCMEN"  value="0x40" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x40" name="Off"  cname=""    />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="On"   cname=""    />
+      <value value="0x80" name="Off"  cname=""    />
+     </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WDTPS" value="0x0F" >
+      <value value="0x00" name="1:1"     cname=""   />
+      <value value="0x01" name="1:2"     cname=""   />
+      <value value="0x02" name="1:4"     cname=""   />
+      <value value="0x03" name="1:8"     cname=""   />
+      <value value="0x04" name="1:16"    cname=""  />
+      <value value="0x05" name="1:32"    cname=""  />
+      <value value="0x06" name="1:64"    cname=""  />
+      <value value="0x07" name="1:128"   cname="" />
+      <value value="0x08" name="1:256"   cname="" />
+      <value value="0x09" name="1:512"   cname="" />
+      <value value="0x0A" name="1:1024"  cname=""  />
+      <value value="0x0B" name="1:2048"  cname=""  />
+      <value value="0x0C" name="1:4096"  cname=""  />
+      <value value="0x0D" name="1:8192"  cname=""  />
+      <value value="0x0E" name="1:16384" cname="" />
+      <value value="0x0F" name="1:32768" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0xF8" >
+    <mask name="WAIT" value="0x80" >
+      <value value="0x00" name="On" cname="" />
+      <value value="0x80" name="Off" cname="" />
+    </mask>
+    <mask name="BW" value="0x40" >
+      <value value="0x00" name="8" cname="" />
+      <value value="0x40" name="16" cname="" />
+    </mask>
+    <mask name="EMB" value="0x30" >
+      <value value="0x00" name="Disabled" cname="" />
+      <value value="0x10" name="12BIT" cname="" />
+      <value value="0x20" name="16BIT" cname="" />
+      <value value="0x30" name="20BIT" cname="" />
+    </mask>
+    <mask name="EASHFT" value="0x08" >
+      <value value="0x00" name="Off" cname="" />
+      <value value="0x08" name="On" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x07" >
+    <mask name="ETHLED" value="0x01" >
+      <value value="0x00" name="Off"  cname=""  />
+      <value value="0x01" name="On"   cname="" />
+    </mask>
+    <mask name="ECCPMX" value="0x02" >
+      <value value="0x00" name="RH7-RH4"     cname="" />
+      <value value="0x02" name="RE6-RE3"     cname=""  />
+    </mask>
+    <mask name="CCP2MX"  value="0x04" >
+      <value value="0x00" name="RE7" cname="" />
+      <value value="0x04" name="RC1" cname="" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
+
diff --git a/src/devices/pic/xml_data/24FJ128GA006.xml b/src/devices/pic/xml_data/24FJ128GA006.xml
new file mode 100644
index 0000000..7f264b9
--- /dev/null
+++ b/src/devices/pic/xml_data/24FJ128GA006.xml
@@ -0,0 +1,122 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FJ128GA006" status="IP" memory_technology="FLASH" architecture="24F" id="0x0407" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="024807" datasheet="39747" progsheet="39768" erratas="80295 80330" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="32" vdd_min="2.0" vdd_max="2.75" />
+  </frequency_range>
+
+  <voltages name="vpp" min="2.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="2.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x0157FB" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0x0157FC" end="0x0157FF" />
+<!--   <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFFFF" /> -->
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x8007EF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0xFFFFFF" bvalue="0x007DDF" >
+    <mask name="WDTPOST" value="0x00000F" >
+      <value value="0x000000" name="1:1" />
+      <value value="0x000001" name="1:2" />
+      <value value="0x000002" name="1:4" />
+      <value value="0x000003" name="1:8" />
+      <value value="0x000004" name="1:16" />
+      <value value="0x000005" name="1:32" />
+      <value value="0x000006" name="1:64" />
+      <value value="0x000007" name="1:128" />
+      <value value="0x000008" name="1:256" />
+      <value value="0x000009" name="1:512" />
+      <value value="0x00000A" name="1:1024" />
+      <value value="0x00000B" name="1:2048" />
+      <value value="0x00000C" name="1:4096" />
+      <value value="0x00000D" name="1:8192" />
+      <value value="0x00000E" name="1:16384" />
+      <value value="0x00000F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x000010" >
+      <value value="0x000000" name="1:32" />
+      <value value="0x000010" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x000040" >
+      <value value="0x000000" name="On" />
+      <value value="0x000040" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x000080" >
+      <value value="0x000000" name="Software" />
+      <value value="0x000080" name="On" />
+    </mask>
+    <mask name="ICS" value="0x000100" >
+      <value value="0x000000" name="EMUC1, EMUD1" />
+      <value value="0x000100" name="EMUC2, EMUD2" />
+    </mask>
+    <mask name="DEBUG" value="0x000800" >
+      <value value="0x000000" name="On" />
+      <value value="0x000800" name="Off" />
+    </mask>
+    <mask name="GWRP" value="0x001000" >
+      <value value="0x000000" name="All" />
+      <value value="0x001000" name="Off" />
+    </mask>
+    <mask name="GCP" value="0x002000" >
+      <value value="0x000000" name="All" />
+      <value value="0x002000" name="Off" />
+    </mask>
+    <mask name="JTAGEN" value="0x004000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x004000" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFFFFFF" bvalue="0x0087E3" >
+    <mask name="POSCMD" value="0x000003" >
+      <value value="0x000000" name="EC" />
+      <value value="0x000001" name="XT" />
+      <value value="0x000002" name="HS" />
+      <value value="0x000003" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x000020" >
+      <value value="0x000000" name="IO" />
+      <value value="0x000020" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0x0000C0" >
+      <value value="0x000000" name="Switching on, monitor on" />
+      <value value="0x000040" name="Switching on, monitor off" />
+      <value value="0x000080" name="Switching off, monitor off" />
+      <value value="0x0000C0" name="Switching off, monitor off" />
+    </mask>
+    <mask name="FNOSC" value="0x000700" >
+      <value value="0x000000" name="EXTRC_F" />
+      <value value="0x000100" name="INTRC_F_PLL" />
+      <value value="0x000200" name="PRIM" />
+      <value value="0x000300" name="PRIM_PLL" />
+      <value value="0x000400" name="SECOND" />
+      <value value="0x000500" name="EXTRC_LP" />
+      <value value="0x000600" name="invalid" />
+      <value value="0x000700" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x008000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x008000" name="On" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24FJ128GA008.xml b/src/devices/pic/xml_data/24FJ128GA008.xml
new file mode 100644
index 0000000..b8d43d8
--- /dev/null
+++ b/src/devices/pic/xml_data/24FJ128GA008.xml
@@ -0,0 +1,122 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FJ128GA008" status="IP" memory_technology="FLASH" architecture="24F" id="0x040A" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="024806" datasheet="39747" progsheet="39768" erratas="80295 80330" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="32" vdd_min="2.0" vdd_max="2.75" />
+  </frequency_range>
+
+  <voltages name="vpp" min="2.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="2.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x0157FB" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0x0157FC" end="0x0157FF" />
+<!--   <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFFFF" /> -->
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x8007EF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0xFFFFFF" bvalue="0x007DDF" >
+    <mask name="WDTPOST" value="0x00000F" >
+      <value value="0x000000" name="1:1" />
+      <value value="0x000001" name="1:2" />
+      <value value="0x000002" name="1:4" />
+      <value value="0x000003" name="1:8" />
+      <value value="0x000004" name="1:16" />
+      <value value="0x000005" name="1:32" />
+      <value value="0x000006" name="1:64" />
+      <value value="0x000007" name="1:128" />
+      <value value="0x000008" name="1:256" />
+      <value value="0x000009" name="1:512" />
+      <value value="0x00000A" name="1:1024" />
+      <value value="0x00000B" name="1:2048" />
+      <value value="0x00000C" name="1:4096" />
+      <value value="0x00000D" name="1:8192" />
+      <value value="0x00000E" name="1:16384" />
+      <value value="0x00000F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x000010" >
+      <value value="0x000000" name="1:32" />
+      <value value="0x000010" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x000040" >
+      <value value="0x000000" name="On" />
+      <value value="0x000040" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x000080" >
+      <value value="0x000000" name="Software" />
+      <value value="0x000080" name="On" />
+    </mask>
+    <mask name="ICS" value="0x000100" >
+      <value value="0x000000" name="EMUC1, EMUD1" />
+      <value value="0x000100" name="EMUC2, EMUD2" />
+    </mask>
+    <mask name="DEBUG" value="0x000800" >
+      <value value="0x000000" name="On" />
+      <value value="0x000800" name="Off" />
+    </mask>
+    <mask name="GWRP" value="0x001000" >
+      <value value="0x000000" name="All" />
+      <value value="0x001000" name="Off" />
+    </mask>
+    <mask name="GCP" value="0x002000" >
+      <value value="0x000000" name="All" />
+      <value value="0x002000" name="Off" />
+    </mask>
+    <mask name="JTAGEN" value="0x004000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x004000" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFFFFFF" bvalue="0x0087E3" >
+    <mask name="POSCMD" value="0x000003" >
+      <value value="0x000000" name="EC" />
+      <value value="0x000001" name="XT" />
+      <value value="0x000002" name="HS" />
+      <value value="0x000003" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x000020" >
+      <value value="0x000000" name="IO" />
+      <value value="0x000020" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0x0000C0" >
+      <value value="0x000000" name="Switching on, monitor on" />
+      <value value="0x000040" name="Switching on, monitor off" />
+      <value value="0x000080" name="Switching off, monitor off" />
+      <value value="0x0000C0" name="Switching off, monitor off" />
+    </mask>
+    <mask name="FNOSC" value="0x000700" >
+      <value value="0x000000" name="EXTRC_F" />
+      <value value="0x000100" name="INTRC_F_PLL" />
+      <value value="0x000200" name="PRIM" />
+      <value value="0x000300" name="PRIM_PLL" />
+      <value value="0x000400" name="SECOND" />
+      <value value="0x000500" name="EXTRC_LP" />
+      <value value="0x000600" name="invalid" />
+      <value value="0x000700" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x008000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x008000" name="On" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24FJ128GA010.xml b/src/devices/pic/xml_data/24FJ128GA010.xml
new file mode 100644
index 0000000..d57c7ff
--- /dev/null
+++ b/src/devices/pic/xml_data/24FJ128GA010.xml
@@ -0,0 +1,122 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FJ128GA010" status="IP" memory_technology="FLASH" architecture="24F" id="0x040D" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="024805" datasheet="39747" progsheet="39768" erratas="80295 80330" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="32" vdd_min="2.0" vdd_max="2.75" />
+  </frequency_range>
+
+  <voltages name="vpp" min="2.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="2.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x0157FB" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0x0157FC" end="0x0157FF" />
+<!--   <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFFFF" /> -->
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x8007EF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0xFFFFFF" bvalue="0x007DDF" >
+    <mask name="WDTPOST" value="0x00000F" >
+      <value value="0x000000" name="1:1" />
+      <value value="0x000001" name="1:2" />
+      <value value="0x000002" name="1:4" />
+      <value value="0x000003" name="1:8" />
+      <value value="0x000004" name="1:16" />
+      <value value="0x000005" name="1:32" />
+      <value value="0x000006" name="1:64" />
+      <value value="0x000007" name="1:128" />
+      <value value="0x000008" name="1:256" />
+      <value value="0x000009" name="1:512" />
+      <value value="0x00000A" name="1:1024" />
+      <value value="0x00000B" name="1:2048" />
+      <value value="0x00000C" name="1:4096" />
+      <value value="0x00000D" name="1:8192" />
+      <value value="0x00000E" name="1:16384" />
+      <value value="0x00000F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x000010" >
+      <value value="0x000000" name="1:32" />
+      <value value="0x000010" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x000040" >
+      <value value="0x000000" name="On" />
+      <value value="0x000040" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x000080" >
+      <value value="0x000000" name="Software" />
+      <value value="0x000080" name="On" />
+    </mask>
+    <mask name="ICS" value="0x000100" >
+      <value value="0x000000" name="EMUC1, EMUD1" />
+      <value value="0x000100" name="EMUC2, EMUD2" />
+    </mask>
+    <mask name="DEBUG" value="0x000800" >
+      <value value="0x000000" name="On" />
+      <value value="0x000800" name="Off" />
+    </mask>
+    <mask name="GWRP" value="0x001000" >
+      <value value="0x000000" name="All" />
+      <value value="0x001000" name="Off" />
+    </mask>
+    <mask name="GCP" value="0x002000" >
+      <value value="0x000000" name="All" />
+      <value value="0x002000" name="Off" />
+    </mask>
+    <mask name="JTAGEN" value="0x004000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x004000" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFFFFFF" bvalue="0x0087E3" >
+    <mask name="POSCMD" value="0x000003" >
+      <value value="0x000000" name="EC" />
+      <value value="0x000001" name="XT" />
+      <value value="0x000002" name="HS" />
+      <value value="0x000003" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x000020" >
+      <value value="0x000000" name="IO" />
+      <value value="0x000020" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0x0000C0" >
+      <value value="0x000000" name="Switching on, monitor on" />
+      <value value="0x000040" name="Switching on, monitor off" />
+      <value value="0x000080" name="Switching off, monitor off" />
+      <value value="0x0000C0" name="Switching off, monitor off" />
+    </mask>
+    <mask name="FNOSC" value="0x000700" >
+      <value value="0x000000" name="EXTRC_F" />
+      <value value="0x000100" name="INTRC_F_PLL" />
+      <value value="0x000200" name="PRIM" />
+      <value value="0x000300" name="PRIM_PLL" />
+      <value value="0x000400" name="SECOND" />
+      <value value="0x000500" name="EXTRC_LP" />
+      <value value="0x000600" name="invalid" />
+      <value value="0x000700" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x008000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x008000" name="On" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="100" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24FJ64GA002.xml b/src/devices/pic/xml_data/24FJ64GA002.xml
new file mode 100644
index 0000000..e051b07
--- /dev/null
+++ b/src/devices/pic/xml_data/24FJ64GA002.xml
@@ -0,0 +1,132 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FJ64GA002" status="IP" memory_technology="FLASH" architecture="24F" id="0x0447" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026374" datasheet="39881" progsheet="39768" erratas="80333 80316" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="32" vdd_min="2.0" vdd_max="2.75" />
+  </frequency_range>
+
+  <voltages name="vpp" min="2.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="2.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x00ABFB" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0x00ABFC" end="0x00ABFF" />
+<!--   <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFFFF" /> -->
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x8007EF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0xFFFFFF" bvalue="0x007FDF" >
+    <mask name="WDTPOST" value="0x00000F" >
+      <value value="0x000000" name="1:1" />
+      <value value="0x000001" name="1:2" />
+      <value value="0x000002" name="1:4" />
+      <value value="0x000003" name="1:8" />
+      <value value="0x000004" name="1:16" />
+      <value value="0x000005" name="1:32" />
+      <value value="0x000006" name="1:64" />
+      <value value="0x000007" name="1:128" />
+      <value value="0x000008" name="1:256" />
+      <value value="0x000009" name="1:512" />
+      <value value="0x00000A" name="1:1024" />
+      <value value="0x00000B" name="1:2048" />
+      <value value="0x00000C" name="1:4096" />
+      <value value="0x00000D" name="1:8192" />
+      <value value="0x00000E" name="1:16384" />
+      <value value="0x00000F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x000010" >
+      <value value="0x000000" name="1:32" />
+      <value value="0x000010" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x000040" >
+      <value value="0x000000" name="On" />
+      <value value="0x000040" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x000080" >
+      <value value="0x000000" name="Software" />
+      <value value="0x000080" name="On" />
+    </mask>
+    <mask name="ICS" value="0x000300" >
+      <value value="0x000000" name="invalid" />
+      <value value="0x000100" name="EMUC3, EMUD3" />
+      <value value="0x000200" name="EMUC2, EMUD2" />
+      <value value="0x000300" name="EMUC1, EMUD1" />
+    </mask>
+    <mask name="DEBUG" value="0x000800" >
+      <value value="0x000000" name="On" />
+      <value value="0x000800" name="Off" />
+    </mask>
+    <mask name="GWRP" value="0x001000" >
+      <value value="0x000000" name="All" />
+      <value value="0x001000" name="Off" />
+    </mask>
+    <mask name="GCP" value="0x002000" >
+      <value value="0x000000" name="All" />
+      <value value="0x002000" name="Off" />
+    </mask>
+    <mask name="JTAGEN" value="0x004000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x004000" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFFFFFF" bvalue="0x0087F7" >
+    <mask name="POSCMD" value="0x000003" >
+      <value value="0x000000" name="EC" />
+      <value value="0x000001" name="XT" />
+      <value value="0x000002" name="HS" />
+      <value value="0x000003" name="Off" />
+    </mask>
+    <mask name="I2C1SEL" value="0x000004" >
+      <value value="0x000000" name="Alternate" />
+      <value value="0x000004" name="Default" />
+    </mask>
+    <mask name="IOL1WAY" value="0x000010" >
+      <value value="0x000000" name="Multiple reconfigurations" />
+      <value value="0x000010" name="One reconfiguration" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x000020" >
+      <value value="0x000000" name="IO" />
+      <value value="0x000020" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0x0000C0" >
+      <value value="0x000000" name="Switching on, monitor on" />
+      <value value="0x000040" name="Switching on, monitor off" />
+      <value value="0x000080" name="Switching off, monitor off" />
+      <value value="0x0000C0" name="Switching off, monitor off" />
+    </mask>
+    <mask name="FNOSC" value="0x000700" >
+      <value value="0x000000" name="EXTRC_F" />
+      <value value="0x000100" name="INTRC_F_PLL" />
+      <value value="0x000200" name="PRIM" />
+      <value value="0x000300" name="PRIM_PLL" />
+      <value value="0x000400" name="SECOND" />
+      <value value="0x000500" name="EXTRC_LP" />
+      <value value="0x000600" name="invalid" />
+      <value value="0x000700" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x008000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x008000" name="On" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="spdip ssop soic qfn" nb_pins="28" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24FJ64GA004.xml b/src/devices/pic/xml_data/24FJ64GA004.xml
new file mode 100644
index 0000000..c87748e
--- /dev/null
+++ b/src/devices/pic/xml_data/24FJ64GA004.xml
@@ -0,0 +1,132 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FJ64GA004" status="IP" memory_technology="FLASH" architecture="24F" id="0x044F" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="026375" datasheet="39881" progsheet="39768" erratas="80333 80316" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="32" vdd_min="2.0" vdd_max="2.75" />
+  </frequency_range>
+
+  <voltages name="vpp" min="2.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="2.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x00ABFB" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0x00ABFC" end="0x00ABFF" />
+<!--   <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFFFF" /> -->
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x8007EF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0xFFFFFF" bvalue="0x007FDF" >
+    <mask name="WDTPOST" value="0x00000F" >
+      <value value="0x000000" name="1:1" />
+      <value value="0x000001" name="1:2" />
+      <value value="0x000002" name="1:4" />
+      <value value="0x000003" name="1:8" />
+      <value value="0x000004" name="1:16" />
+      <value value="0x000005" name="1:32" />
+      <value value="0x000006" name="1:64" />
+      <value value="0x000007" name="1:128" />
+      <value value="0x000008" name="1:256" />
+      <value value="0x000009" name="1:512" />
+      <value value="0x00000A" name="1:1024" />
+      <value value="0x00000B" name="1:2048" />
+      <value value="0x00000C" name="1:4096" />
+      <value value="0x00000D" name="1:8192" />
+      <value value="0x00000E" name="1:16384" />
+      <value value="0x00000F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x000010" >
+      <value value="0x000000" name="1:32" />
+      <value value="0x000010" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x000040" >
+      <value value="0x000000" name="On" />
+      <value value="0x000040" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x000080" >
+      <value value="0x000000" name="Software" />
+      <value value="0x000080" name="On" />
+    </mask>
+    <mask name="ICS" value="0x000300" >
+      <value value="0x000000" name="invalid" />
+      <value value="0x000100" name="EMUC3, EMUD3" />
+      <value value="0x000200" name="EMUC2, EMUD2" />
+      <value value="0x000300" name="EMUC1, EMUD1" />
+    </mask>
+    <mask name="DEBUG" value="0x000800" >
+      <value value="0x000000" name="On" />
+      <value value="0x000800" name="Off" />
+    </mask>
+    <mask name="GWRP" value="0x001000" >
+      <value value="0x000000" name="All" />
+      <value value="0x001000" name="Off" />
+    </mask>
+    <mask name="GCP" value="0x002000" >
+      <value value="0x000000" name="All" />
+      <value value="0x002000" name="Off" />
+    </mask>
+    <mask name="JTAGEN" value="0x004000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x004000" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFFFFFF" bvalue="0x0087F7" >
+    <mask name="POSCMD" value="0x000003" >
+      <value value="0x000000" name="EC" />
+      <value value="0x000001" name="XT" />
+      <value value="0x000002" name="HS" />
+      <value value="0x000003" name="Off" />
+    </mask>
+    <mask name="I2C1SEL" value="0x000004" >
+      <value value="0x000000" name="Alternate" />
+      <value value="0x000004" name="Default" />
+    </mask>
+    <mask name="IOL1WAY" value="0x000010" >
+      <value value="0x000000" name="Multiple reconfigurations" />
+      <value value="0x000010" name="One reconfiguration" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x000020" >
+      <value value="0x000000" name="IO" />
+      <value value="0x000020" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0x0000C0" >
+      <value value="0x000000" name="Switching on, monitor on" />
+      <value value="0x000040" name="Switching on, monitor off" />
+      <value value="0x000080" name="Switching off, monitor off" />
+      <value value="0x0000C0" name="Switching off, monitor off" />
+    </mask>
+    <mask name="FNOSC" value="0x000700" >
+      <value value="0x000000" name="EXTRC_F" />
+      <value value="0x000100" name="INTRC_F_PLL" />
+      <value value="0x000200" name="PRIM" />
+      <value value="0x000300" name="PRIM_PLL" />
+      <value value="0x000400" name="SECOND" />
+      <value value="0x000500" name="EXTRC_LP" />
+      <value value="0x000600" name="invalid" />
+      <value value="0x000700" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x008000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x008000" name="On" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="qfn tqfp" nb_pins="44" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24FJ64GA006.xml b/src/devices/pic/xml_data/24FJ64GA006.xml
new file mode 100644
index 0000000..6492f51
--- /dev/null
+++ b/src/devices/pic/xml_data/24FJ64GA006.xml
@@ -0,0 +1,122 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FJ64GA006" status="IP" memory_technology="FLASH" architecture="24F" id="0x0405" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="024813" datasheet="39747" progsheet="39768" erratas="80295 80330" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="32" vdd_min="2.0" vdd_max="2.75" />
+  </frequency_range>
+
+  <voltages name="vpp" min="2.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="2.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x00ABFB" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0x00ABFC" end="0x00ABFF" />
+<!--   <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFFFF" /> -->
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x8007EF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0xFFFFFF" bvalue="0x007DDF" >
+    <mask name="WDTPOST" value="0x00000F" >
+      <value value="0x000000" name="1:1" />
+      <value value="0x000001" name="1:2" />
+      <value value="0x000002" name="1:4" />
+      <value value="0x000003" name="1:8" />
+      <value value="0x000004" name="1:16" />
+      <value value="0x000005" name="1:32" />
+      <value value="0x000006" name="1:64" />
+      <value value="0x000007" name="1:128" />
+      <value value="0x000008" name="1:256" />
+      <value value="0x000009" name="1:512" />
+      <value value="0x00000A" name="1:1024" />
+      <value value="0x00000B" name="1:2048" />
+      <value value="0x00000C" name="1:4096" />
+      <value value="0x00000D" name="1:8192" />
+      <value value="0x00000E" name="1:16384" />
+      <value value="0x00000F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x000010" >
+      <value value="0x000000" name="1:32" />
+      <value value="0x000010" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x000040" >
+      <value value="0x000000" name="On" />
+      <value value="0x000040" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x000080" >
+      <value value="0x000000" name="Software" />
+      <value value="0x000080" name="On" />
+    </mask>
+    <mask name="ICS" value="0x000100" >
+      <value value="0x000000" name="EMUC1, EMUD1" />
+      <value value="0x000100" name="EMUC2, EMUD2" />
+    </mask>
+    <mask name="DEBUG" value="0x000800" >
+      <value value="0x000000" name="On" />
+      <value value="0x000800" name="Off" />
+    </mask>
+    <mask name="GWRP" value="0x001000" >
+      <value value="0x000000" name="All" />
+      <value value="0x001000" name="Off" />
+    </mask>
+    <mask name="GCP" value="0x002000" >
+      <value value="0x000000" name="All" />
+      <value value="0x002000" name="Off" />
+    </mask>
+    <mask name="JTAGEN" value="0x004000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x004000" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFFFFFF" bvalue="0x0087E3" >
+    <mask name="POSCMD" value="0x000003" >
+      <value value="0x000000" name="EC" />
+      <value value="0x000001" name="XT" />
+      <value value="0x000002" name="HS" />
+      <value value="0x000003" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x000020" >
+      <value value="0x000000" name="IO" />
+      <value value="0x000020" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0x0000C0" >
+      <value value="0x000000" name="Switching on, monitor on" />
+      <value value="0x000040" name="Switching on, monitor off" />
+      <value value="0x000080" name="Switching off, monitor off" />
+      <value value="0x0000C0" name="Switching off, monitor off" />
+    </mask>
+    <mask name="FNOSC" value="0x000700" >
+      <value value="0x000000" name="EXTRC_F" />
+      <value value="0x000100" name="INTRC_F_PLL" />
+      <value value="0x000200" name="PRIM" />
+      <value value="0x000300" name="PRIM_PLL" />
+      <value value="0x000400" name="SECOND" />
+      <value value="0x000500" name="EXTRC_LP" />
+      <value value="0x000600" name="invalid" />
+      <value value="0x000700" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x008000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x008000" name="On" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24FJ64GA008.xml b/src/devices/pic/xml_data/24FJ64GA008.xml
new file mode 100644
index 0000000..2ead302
--- /dev/null
+++ b/src/devices/pic/xml_data/24FJ64GA008.xml
@@ -0,0 +1,122 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FJ64GA008" status="IP" memory_technology="FLASH" architecture="24F" id="0x0408" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="024812" datasheet="39747" progsheet="39768" erratas="80295 80330" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="32" vdd_min="2.0" vdd_max="2.75" />
+  </frequency_range>
+
+  <voltages name="vpp" min="2.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="2.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x00ABFB" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0x00ABFC" end="0x00ABFF" />
+<!--   <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFFFF" /> -->
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x8007EF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0xFFFFFF" bvalue="0x007DDF" >
+    <mask name="WDTPOST" value="0x00000F" >
+      <value value="0x000000" name="1:1" />
+      <value value="0x000001" name="1:2" />
+      <value value="0x000002" name="1:4" />
+      <value value="0x000003" name="1:8" />
+      <value value="0x000004" name="1:16" />
+      <value value="0x000005" name="1:32" />
+      <value value="0x000006" name="1:64" />
+      <value value="0x000007" name="1:128" />
+      <value value="0x000008" name="1:256" />
+      <value value="0x000009" name="1:512" />
+      <value value="0x00000A" name="1:1024" />
+      <value value="0x00000B" name="1:2048" />
+      <value value="0x00000C" name="1:4096" />
+      <value value="0x00000D" name="1:8192" />
+      <value value="0x00000E" name="1:16384" />
+      <value value="0x00000F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x000010" >
+      <value value="0x000000" name="1:32" />
+      <value value="0x000010" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x000040" >
+      <value value="0x000000" name="On" />
+      <value value="0x000040" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x000080" >
+      <value value="0x000000" name="Software" />
+      <value value="0x000080" name="On" />
+    </mask>
+    <mask name="ICS" value="0x000100" >
+      <value value="0x000000" name="EMUC1, EMUD1" />
+      <value value="0x000100" name="EMUC2, EMUD2" />
+    </mask>
+    <mask name="DEBUG" value="0x000800" >
+      <value value="0x000000" name="On" />
+      <value value="0x000800" name="Off" />
+    </mask>
+    <mask name="GWRP" value="0x001000" >
+      <value value="0x000000" name="All" />
+      <value value="0x001000" name="Off" />
+    </mask>
+    <mask name="GCP" value="0x002000" >
+      <value value="0x000000" name="All" />
+      <value value="0x002000" name="Off" />
+    </mask>
+    <mask name="JTAGEN" value="0x004000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x004000" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFFFFFF" bvalue="0x0087E3" >
+    <mask name="POSCMD" value="0x000003" >
+      <value value="0x000000" name="EC" />
+      <value value="0x000001" name="XT" />
+      <value value="0x000002" name="HS" />
+      <value value="0x000003" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x000020" >
+      <value value="0x000000" name="IO" />
+      <value value="0x000020" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0x0000C0" >
+      <value value="0x000000" name="Switching on, monitor on" />
+      <value value="0x000040" name="Switching on, monitor off" />
+      <value value="0x000080" name="Switching off, monitor off" />
+      <value value="0x0000C0" name="Switching off, monitor off" />
+    </mask>
+    <mask name="FNOSC" value="0x000700" >
+      <value value="0x000000" name="EXTRC_F" />
+      <value value="0x000100" name="INTRC_F_PLL" />
+      <value value="0x000200" name="PRIM" />
+      <value value="0x000300" name="PRIM_PLL" />
+      <value value="0x000400" name="SECOND" />
+      <value value="0x000500" name="EXTRC_LP" />
+      <value value="0x000600" name="invalid" />
+      <value value="0x000700" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x008000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x008000" name="On" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24FJ64GA010.xml b/src/devices/pic/xml_data/24FJ64GA010.xml
new file mode 100644
index 0000000..627da04
--- /dev/null
+++ b/src/devices/pic/xml_data/24FJ64GA010.xml
@@ -0,0 +1,122 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FJ64GA010" status="IP" memory_technology="FLASH" architecture="24F" id="0x040B" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="024811" datasheet="39747" progsheet="39768" erratas="80295 80330" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="32" vdd_min="2.0" vdd_max="2.75" />
+  </frequency_range>
+
+  <voltages name="vpp" min="2.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="2.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x00ABFB" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0x00ABFC" end="0x00ABFF" />
+<!--   <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFFFF" /> -->
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x8007EF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0xFFFFFF" bvalue="0x007DDF" >
+    <mask name="WDTPOST" value="0x00000F" >
+      <value value="0x000000" name="1:1" />
+      <value value="0x000001" name="1:2" />
+      <value value="0x000002" name="1:4" />
+      <value value="0x000003" name="1:8" />
+      <value value="0x000004" name="1:16" />
+      <value value="0x000005" name="1:32" />
+      <value value="0x000006" name="1:64" />
+      <value value="0x000007" name="1:128" />
+      <value value="0x000008" name="1:256" />
+      <value value="0x000009" name="1:512" />
+      <value value="0x00000A" name="1:1024" />
+      <value value="0x00000B" name="1:2048" />
+      <value value="0x00000C" name="1:4096" />
+      <value value="0x00000D" name="1:8192" />
+      <value value="0x00000E" name="1:16384" />
+      <value value="0x00000F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x000010" >
+      <value value="0x000000" name="1:32" />
+      <value value="0x000010" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x000040" >
+      <value value="0x000000" name="On" />
+      <value value="0x000040" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x000080" >
+      <value value="0x000000" name="Software" />
+      <value value="0x000080" name="On" />
+    </mask>
+    <mask name="ICS" value="0x000100" >
+      <value value="0x000000" name="EMUC1, EMUD1" />
+      <value value="0x000100" name="EMUC2, EMUD2" />
+    </mask>
+    <mask name="DEBUG" value="0x000800" >
+      <value value="0x000000" name="On" />
+      <value value="0x000800" name="Off" />
+    </mask>
+    <mask name="GWRP" value="0x001000" >
+      <value value="0x000000" name="All" />
+      <value value="0x001000" name="Off" />
+    </mask>
+    <mask name="GCP" value="0x002000" >
+      <value value="0x000000" name="All" />
+      <value value="0x002000" name="Off" />
+    </mask>
+    <mask name="JTAGEN" value="0x004000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x004000" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFFFFFF" bvalue="0x0087E3" >
+    <mask name="POSCMD" value="0x000003" >
+      <value value="0x000000" name="EC" />
+      <value value="0x000001" name="XT" />
+      <value value="0x000002" name="HS" />
+      <value value="0x000003" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x000020" >
+      <value value="0x000000" name="IO" />
+      <value value="0x000020" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0x0000C0" >
+      <value value="0x000000" name="Switching on, monitor on" />
+      <value value="0x000040" name="Switching on, monitor off" />
+      <value value="0x000080" name="Switching off, monitor off" />
+      <value value="0x0000C0" name="Switching off, monitor off" />
+    </mask>
+    <mask name="FNOSC" value="0x000700" >
+      <value value="0x000000" name="EXTRC_F" />
+      <value value="0x000100" name="INTRC_F_PLL" />
+      <value value="0x000200" name="PRIM" />
+      <value value="0x000300" name="PRIM_PLL" />
+      <value value="0x000400" name="SECOND" />
+      <value value="0x000500" name="EXTRC_LP" />
+      <value value="0x000600" name="invalid" />
+      <value value="0x000700" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x008000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x008000" name="On" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="100" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24FJ96GA006.xml b/src/devices/pic/xml_data/24FJ96GA006.xml
new file mode 100644
index 0000000..9f02be4
--- /dev/null
+++ b/src/devices/pic/xml_data/24FJ96GA006.xml
@@ -0,0 +1,122 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FJ96GA006" status="IP" memory_technology="FLASH" architecture="24F" id="0x0406" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="024808" datasheet="39747" progsheet="39768" erratas="80295 80330" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="32" vdd_min="2.0" vdd_max="2.75" />
+  </frequency_range>
+
+  <voltages name="vpp" min="2.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="2.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x00FFFB" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0x00FFFC" end="0x00FFFF" />
+<!--   <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFFFF" /> -->
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x8007EF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0xFFFFFF" bvalue="0x007DDF" >
+    <mask name="WDTPOST" value="0x00000F" >
+      <value value="0x000000" name="1:1" />
+      <value value="0x000001" name="1:2" />
+      <value value="0x000002" name="1:4" />
+      <value value="0x000003" name="1:8" />
+      <value value="0x000004" name="1:16" />
+      <value value="0x000005" name="1:32" />
+      <value value="0x000006" name="1:64" />
+      <value value="0x000007" name="1:128" />
+      <value value="0x000008" name="1:256" />
+      <value value="0x000009" name="1:512" />
+      <value value="0x00000A" name="1:1024" />
+      <value value="0x00000B" name="1:2048" />
+      <value value="0x00000C" name="1:4096" />
+      <value value="0x00000D" name="1:8192" />
+      <value value="0x00000E" name="1:16384" />
+      <value value="0x00000F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x000010" >
+      <value value="0x000000" name="1:32" />
+      <value value="0x000010" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x000040" >
+      <value value="0x000000" name="On" />
+      <value value="0x000040" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x000080" >
+      <value value="0x000000" name="Software" />
+      <value value="0x000080" name="On" />
+    </mask>
+    <mask name="ICS" value="0x000100" >
+      <value value="0x000000" name="EMUC1, EMUD1" />
+      <value value="0x000100" name="EMUC2, EMUD2" />
+    </mask>
+    <mask name="DEBUG" value="0x000800" >
+      <value value="0x000000" name="On" />
+      <value value="0x000800" name="Off" />
+    </mask>
+    <mask name="GWRP" value="0x001000" >
+      <value value="0x000000" name="All" />
+      <value value="0x001000" name="Off" />
+    </mask>
+    <mask name="GCP" value="0x002000" >
+      <value value="0x000000" name="All" />
+      <value value="0x002000" name="Off" />
+    </mask>
+    <mask name="JTAGEN" value="0x004000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x004000" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFFFFFF" bvalue="0x0087E3" >
+    <mask name="POSCMD" value="0x000003" >
+      <value value="0x000000" name="EC" />
+      <value value="0x000001" name="XT" />
+      <value value="0x000002" name="HS" />
+      <value value="0x000003" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x000020" >
+      <value value="0x000000" name="IO" />
+      <value value="0x000020" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0x0000C0" >
+      <value value="0x000000" name="Switching on, monitor on" />
+      <value value="0x000040" name="Switching on, monitor off" />
+      <value value="0x000080" name="Switching off, monitor off" />
+      <value value="0x0000C0" name="Switching off, monitor off" />
+    </mask>
+    <mask name="FNOSC" value="0x000700" >
+      <value value="0x000000" name="EXTRC_F" />
+      <value value="0x000100" name="INTRC_F_PLL" />
+      <value value="0x000200" name="PRIM" />
+      <value value="0x000300" name="PRIM_PLL" />
+      <value value="0x000400" name="SECOND" />
+      <value value="0x000500" name="EXTRC_LP" />
+      <value value="0x000600" name="invalid" />
+      <value value="0x000700" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x008000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x008000" name="On" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24FJ96GA008.xml b/src/devices/pic/xml_data/24FJ96GA008.xml
new file mode 100644
index 0000000..eeba6d2
--- /dev/null
+++ b/src/devices/pic/xml_data/24FJ96GA008.xml
@@ -0,0 +1,122 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FJ96GA008" status="IP" memory_technology="FLASH" architecture="24F" id="0x0409" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="024809" datasheet="39747" progsheet="39768" erratas="80295 80330" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="32" vdd_min="2.0" vdd_max="2.75" />
+  </frequency_range>
+
+  <voltages name="vpp" min="2.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="2.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x00FFFB" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0x00FFFC" end="0x00FFFF" />
+<!--   <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFFFF" /> -->
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x8007EF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0xFFFFFF" bvalue="0x007DDF" >
+    <mask name="WDTPOST" value="0x00000F" >
+      <value value="0x000000" name="1:1" />
+      <value value="0x000001" name="1:2" />
+      <value value="0x000002" name="1:4" />
+      <value value="0x000003" name="1:8" />
+      <value value="0x000004" name="1:16" />
+      <value value="0x000005" name="1:32" />
+      <value value="0x000006" name="1:64" />
+      <value value="0x000007" name="1:128" />
+      <value value="0x000008" name="1:256" />
+      <value value="0x000009" name="1:512" />
+      <value value="0x00000A" name="1:1024" />
+      <value value="0x00000B" name="1:2048" />
+      <value value="0x00000C" name="1:4096" />
+      <value value="0x00000D" name="1:8192" />
+      <value value="0x00000E" name="1:16384" />
+      <value value="0x00000F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x000010" >
+      <value value="0x000000" name="1:32" />
+      <value value="0x000010" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x000040" >
+      <value value="0x000000" name="On" />
+      <value value="0x000040" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x000080" >
+      <value value="0x000000" name="Software" />
+      <value value="0x000080" name="On" />
+    </mask>
+    <mask name="ICS" value="0x000100" >
+      <value value="0x000000" name="EMUC1, EMUD1" />
+      <value value="0x000100" name="EMUC2, EMUD2" />
+    </mask>
+    <mask name="DEBUG" value="0x000800" >
+      <value value="0x000000" name="On" />
+      <value value="0x000800" name="Off" />
+    </mask>
+    <mask name="GWRP" value="0x001000" >
+      <value value="0x000000" name="All" />
+      <value value="0x001000" name="Off" />
+    </mask>
+    <mask name="GCP" value="0x002000" >
+      <value value="0x000000" name="All" />
+      <value value="0x002000" name="Off" />
+    </mask>
+    <mask name="JTAGEN" value="0x004000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x004000" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFFFFFF" bvalue="0x0087E3" >
+    <mask name="POSCMD" value="0x000003" >
+      <value value="0x000000" name="EC" />
+      <value value="0x000001" name="XT" />
+      <value value="0x000002" name="HS" />
+      <value value="0x000003" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x000020" >
+      <value value="0x000000" name="IO" />
+      <value value="0x000020" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0x0000C0" >
+      <value value="0x000000" name="Switching on, monitor on" />
+      <value value="0x000040" name="Switching on, monitor off" />
+      <value value="0x000080" name="Switching off, monitor off" />
+      <value value="0x0000C0" name="Switching off, monitor off" />
+    </mask>
+    <mask name="FNOSC" value="0x000700" >
+      <value value="0x000000" name="EXTRC_F" />
+      <value value="0x000100" name="INTRC_F_PLL" />
+      <value value="0x000200" name="PRIM" />
+      <value value="0x000300" name="PRIM_PLL" />
+      <value value="0x000400" name="SECOND" />
+      <value value="0x000500" name="EXTRC_LP" />
+      <value value="0x000600" name="invalid" />
+      <value value="0x000700" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x008000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x008000" name="On" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24FJ96GA010.xml b/src/devices/pic/xml_data/24FJ96GA010.xml
new file mode 100644
index 0000000..700d288
--- /dev/null
+++ b/src/devices/pic/xml_data/24FJ96GA010.xml
@@ -0,0 +1,122 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24FJ96GA010" status="IP" memory_technology="FLASH" architecture="24F" id="0x040C" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="024810" datasheet="39747" progsheet="39768" erratas="80295 80330" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="32" vdd_min="2.0" vdd_max="2.75" />
+  </frequency_range>
+
+  <voltages name="vpp" min="2.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="2.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x00FFFB" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0x00FFFC" end="0x00FFFF" />
+<!--   <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFFFF" /> -->
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x8007EF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1" wmask="0xFFFFFF" bvalue="0x007DDF" >
+    <mask name="WDTPOST" value="0x00000F" >
+      <value value="0x000000" name="1:1" />
+      <value value="0x000001" name="1:2" />
+      <value value="0x000002" name="1:4" />
+      <value value="0x000003" name="1:8" />
+      <value value="0x000004" name="1:16" />
+      <value value="0x000005" name="1:32" />
+      <value value="0x000006" name="1:64" />
+      <value value="0x000007" name="1:128" />
+      <value value="0x000008" name="1:256" />
+      <value value="0x000009" name="1:512" />
+      <value value="0x00000A" name="1:1024" />
+      <value value="0x00000B" name="1:2048" />
+      <value value="0x00000C" name="1:4096" />
+      <value value="0x00000D" name="1:8192" />
+      <value value="0x00000E" name="1:16384" />
+      <value value="0x00000F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x000010" >
+      <value value="0x000000" name="1:32" />
+      <value value="0x000010" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x000040" >
+      <value value="0x000000" name="On" />
+      <value value="0x000040" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x000080" >
+      <value value="0x000000" name="Software" />
+      <value value="0x000080" name="On" />
+    </mask>
+    <mask name="ICS" value="0x000100" >
+      <value value="0x000000" name="EMUC1, EMUD1" />
+      <value value="0x000100" name="EMUC2, EMUD2" />
+    </mask>
+    <mask name="DEBUG" value="0x000800" >
+      <value value="0x000000" name="On" />
+      <value value="0x000800" name="Off" />
+    </mask>
+    <mask name="GWRP" value="0x001000" >
+      <value value="0x000000" name="All" />
+      <value value="0x001000" name="Off" />
+    </mask>
+    <mask name="GCP" value="0x002000" >
+      <value value="0x000000" name="All" />
+      <value value="0x002000" name="Off" />
+    </mask>
+    <mask name="JTAGEN" value="0x004000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x004000" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2" wmask="0xFFFFFF" bvalue="0x0087E3" >
+    <mask name="POSCMD" value="0x000003" >
+      <value value="0x000000" name="EC" />
+      <value value="0x000001" name="XT" />
+      <value value="0x000002" name="HS" />
+      <value value="0x000003" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x000020" >
+      <value value="0x000000" name="IO" />
+      <value value="0x000020" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0x0000C0" >
+      <value value="0x000000" name="Switching on, monitor on" />
+      <value value="0x000040" name="Switching on, monitor off" />
+      <value value="0x000080" name="Switching off, monitor off" />
+      <value value="0x0000C0" name="Switching off, monitor off" />
+    </mask>
+    <mask name="FNOSC" value="0x000700" >
+      <value value="0x000000" name="EXTRC_F" />
+      <value value="0x000100" name="INTRC_F_PLL" />
+      <value value="0x000200" name="PRIM" />
+      <value value="0x000300" name="PRIM_PLL" />
+      <value value="0x000400" name="SECOND" />
+      <value value="0x000500" name="EXTRC_LP" />
+      <value value="0x000600" name="invalid" />
+      <value value="0x000700" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x008000" >
+      <value value="0x000000" name="Off" />
+      <value value="0x008000" name="On" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="100" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ128GP206.xml b/src/devices/pic/xml_data/24HJ128GP206.xml
new file mode 100644
index 0000000..c065e99
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ128GP206.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ128GP206" document="024685" status="IP" memory_technology="FLASH" architecture="24H" id="0x005D" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x0157FF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="8192" />
+      <value value="0x02" name="4096" />
+      <value value="0x04" name="1024" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RBSSIZ" value="0xC0" >
+      <value value="0x00" name="1024" />
+      <value value="0x40" name="256"  />
+      <value value="0x80" name="128"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FSS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTSS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="SSSIZ"  value="0x06" >
+      <value value="0x00" name="32768" />
+      <value value="0x02" name="16384"  />
+      <value value="0x04" name="8192"  />
+      <value value="0x06" name="0"   />
+    </mask>
+    <mask name="SSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RSSSIZ" value="0xC0" >
+      <value value="0x00" name="4096" />
+      <value value="0x40" name="2048" />
+      <value value="0x80" name="256"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0xA7" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="TEMP" value="0x20" >
+      <value value="0x00" name="On" />
+      <value value="0x20" name="Off" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x07" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ128GP210.xml b/src/devices/pic/xml_data/24HJ128GP210.xml
new file mode 100644
index 0000000..b0922d0
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ128GP210.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ128GP210" document="024686" status="IP" memory_technology="FLASH" architecture="24H" id="0x005F" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x0157FF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="8192" />
+      <value value="0x02" name="4096" />
+      <value value="0x04" name="1024" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RBSSIZ" value="0xC0" >
+      <value value="0x00" name="1024" />
+      <value value="0x40" name="256"  />
+      <value value="0x80" name="128"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FSS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTSS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="SSSIZ"  value="0x06" >
+      <value value="0x00" name="32768" />
+      <value value="0x02" name="16384"  />
+      <value value="0x04" name="8192"  />
+      <value value="0x06" name="0"   />
+    </mask>
+    <mask name="SSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RSSSIZ" value="0xC0" >
+      <value value="0x00" name="4096" />
+      <value value="0x40" name="2048" />
+      <value value="0x80" name="256"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0xA7" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="TEMP" value="0x20" >
+      <value value="0x00" name="On" />
+      <value value="0x20" name="Off" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x07" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="100" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ128GP306.xml b/src/devices/pic/xml_data/24HJ128GP306.xml
new file mode 100644
index 0000000..97f23e1
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ128GP306.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ128GP306" document="024689" status="IP" memory_technology="FLASH" architecture="24H" id="0x0065" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x0157FF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="8192" />
+      <value value="0x02" name="4096" />
+      <value value="0x04" name="1024" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RBSSIZ" value="0xC0" >
+      <value value="0x00" name="1024" />
+      <value value="0x40" name="256"  />
+      <value value="0x80" name="128"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FSS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTSS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="SSSIZ"  value="0x06" >
+      <value value="0x00" name="32768" />
+      <value value="0x02" name="16384"  />
+      <value value="0x04" name="8192"  />
+      <value value="0x06" name="0"   />
+    </mask>
+    <mask name="SSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RSSSIZ" value="0xC0" >
+      <value value="0x00" name="4096" />
+      <value value="0x40" name="2048" />
+      <value value="0x80" name="256"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0xA7" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="TEMP" value="0x20" >
+      <value value="0x00" name="On" />
+      <value value="0x20" name="Off" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x07" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ128GP310.xml b/src/devices/pic/xml_data/24HJ128GP310.xml
new file mode 100644
index 0000000..a600601
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ128GP310.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ128GP310" document="024690" status="IP" memory_technology="FLASH" architecture="24H" id="0x0067" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x0157FF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="8192" />
+      <value value="0x02" name="4096" />
+      <value value="0x04" name="1024" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RBSSIZ" value="0xC0" >
+      <value value="0x00" name="1024" />
+      <value value="0x40" name="256"  />
+      <value value="0x80" name="128"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FSS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTSS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="SSSIZ"  value="0x06" >
+      <value value="0x00" name="32768" />
+      <value value="0x02" name="16384"  />
+      <value value="0x04" name="8192"  />
+      <value value="0x06" name="0"   />
+    </mask>
+    <mask name="SSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RSSSIZ" value="0xC0" >
+      <value value="0x00" name="4096" />
+      <value value="0x40" name="2048" />
+      <value value="0x80" name="256"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0xA7" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="TEMP" value="0x20" >
+      <value value="0x00" name="On" />
+      <value value="0x20" name="Off" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x07" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="100" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ128GP506.xml b/src/devices/pic/xml_data/24HJ128GP506.xml
new file mode 100644
index 0000000..ae2fd06
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ128GP506.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ128GP506" document="024687" status="IP" memory_technology="FLASH" architecture="24H" id="0x0061" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x0157FF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="8192" />
+      <value value="0x02" name="4096" />
+      <value value="0x04" name="1024" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RBSSIZ" value="0xC0" >
+      <value value="0x00" name="1024" />
+      <value value="0x40" name="256"  />
+      <value value="0x80" name="128"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FSS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTSS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="SSSIZ"  value="0x06" >
+      <value value="0x00" name="32768" />
+      <value value="0x02" name="16384"  />
+      <value value="0x04" name="8192"  />
+      <value value="0x06" name="0"   />
+    </mask>
+    <mask name="SSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RSSSIZ" value="0xC0" >
+      <value value="0x00" name="4096" />
+      <value value="0x40" name="2048" />
+      <value value="0x80" name="256"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0xA7" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="TEMP" value="0x20" >
+      <value value="0x00" name="On" />
+      <value value="0x20" name="Off" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x07" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ128GP510.xml b/src/devices/pic/xml_data/24HJ128GP510.xml
new file mode 100644
index 0000000..7195e60
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ128GP510.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ128GP510" document="024688" status="IP" memory_technology="FLASH" architecture="24H" id="0x0063" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x0157FF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="8192" />
+      <value value="0x02" name="4096" />
+      <value value="0x04" name="1024" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RBSSIZ" value="0xC0" >
+      <value value="0x00" name="1024" />
+      <value value="0x40" name="256"  />
+      <value value="0x80" name="128"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FSS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTSS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="SSSIZ"  value="0x06" >
+      <value value="0x00" name="32768" />
+      <value value="0x02" name="16384"  />
+      <value value="0x04" name="8192"  />
+      <value value="0x06" name="0"   />
+    </mask>
+    <mask name="SSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RSSSIZ" value="0xC0" >
+      <value value="0x00" name="4096" />
+      <value value="0x40" name="2048" />
+      <value value="0x80" name="256"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0xA7" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="TEMP" value="0x20" >
+      <value value="0x00" name="On" />
+      <value value="0x20" name="Off" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x07" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="100" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ12GP201.xml b/src/devices/pic/xml_data/24HJ12GP201.xml
new file mode 100644
index 0000000..b0c3357
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ12GP201.xml
@@ -0,0 +1,177 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ12GP201" document="520472" status="IP" memory_technology="FLASH" architecture="24H" id="0x080A" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x001FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="1792" />
+      <value value="0x02" name="768" />
+      <value value="0x04" name="256" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="reserved" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0x87" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="IOL1WAY" value="0x20" >
+      <value value="0x00" name="Multiple reconfigurations" />
+      <value value="0x20" name="One reconfiguration" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x17" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+    <mask name="ALTI2C" value="0x10" >
+      <value value="0x00" name="ASDA1/ASCL1" />
+      <value value="0x10" name="SDA1/SCL1" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ12GP202.xml b/src/devices/pic/xml_data/24HJ12GP202.xml
new file mode 100644
index 0000000..60fdce8
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ12GP202.xml
@@ -0,0 +1,177 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ12GP202" document="520471" status="IP" memory_technology="FLASH" architecture="24H" id="0x080B" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x001FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="1792" />
+      <value value="0x02" name="768" />
+      <value value="0x04" name="256" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="reserved" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0x87" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="IOL1WAY" value="0x20" >
+      <value value="0x00" name="Multiple reconfigurations" />
+      <value value="0x20" name="One reconfiguration" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x17" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+    <mask name="ALTI2C" value="0x10" >
+      <value value="0x00" name="ASDA1/ASCL1" />
+      <value value="0x10" name="SDA1/SCL1" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic qfn" nb_pins="28" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ16GP304.xml b/src/devices/pic/xml_data/24HJ16GP304.xml
new file mode 100644
index 0000000..f4d50d8
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ16GP304.xml
@@ -0,0 +1,180 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ16GP304" status="IP" memory_technology="FLASH" architecture="24H" id="0x0F17" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="530329" datasheet="70289" progsheet="70152" erratas="80339" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x002BFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="1792" />
+      <value value="0x02" name="768" />
+      <value value="0x04" name="256" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="reserved" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0x87" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="IOL1WAY" value="0x20" >
+      <value value="0x00" name="Multiple reconfigurations" />
+      <value value="0x20" name="One reconfiguration" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x17" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+    <mask name="ALTI2C" value="0x10" >
+      <value value="0x00" name="ASDA1/ASCL1" />
+      <value value="0x10" name="SDA1/SCL1" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="44" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ256GP206.xml b/src/devices/pic/xml_data/24HJ256GP206.xml
new file mode 100644
index 0000000..d977b29
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ256GP206.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ256GP206" document="024691" status="IP" memory_technology="FLASH" architecture="24H" id="0x0071" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x02ABFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="8192" />
+      <value value="0x02" name="4096" />
+      <value value="0x04" name="1024" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RBSSIZ" value="0xC0" >
+      <value value="0x00" name="1024" />
+      <value value="0x40" name="256"  />
+      <value value="0x80" name="128"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FSS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTSS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="SSSIZ"  value="0x06" >
+      <value value="0x00" name="32768" />
+      <value value="0x02" name="16384"  />
+      <value value="0x04" name="8192"  />
+      <value value="0x06" name="0"   />
+    </mask>
+    <mask name="SSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RSSSIZ" value="0xC0" >
+      <value value="0x00" name="4096" />
+      <value value="0x40" name="2048" />
+      <value value="0x80" name="256"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0xA7" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="TEMP" value="0x20" >
+      <value value="0x00" name="On" />
+      <value value="0x20" name="Off" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x07" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ256GP210.xml b/src/devices/pic/xml_data/24HJ256GP210.xml
new file mode 100644
index 0000000..000bc00
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ256GP210.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ256GP210" document="024692" status="IP" memory_technology="FLASH" architecture="24H" id="0x0073" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x02ABFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="8192" />
+      <value value="0x02" name="4096" />
+      <value value="0x04" name="1024" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RBSSIZ" value="0xC0" >
+      <value value="0x00" name="1024" />
+      <value value="0x40" name="256"  />
+      <value value="0x80" name="128"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FSS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTSS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="SSSIZ"  value="0x06" >
+      <value value="0x00" name="32768" />
+      <value value="0x02" name="16384"  />
+      <value value="0x04" name="8192"  />
+      <value value="0x06" name="0"   />
+    </mask>
+    <mask name="SSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RSSSIZ" value="0xC0" >
+      <value value="0x00" name="4096" />
+      <value value="0x40" name="2048" />
+      <value value="0x80" name="256"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0xA7" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="TEMP" value="0x20" >
+      <value value="0x00" name="On" />
+      <value value="0x20" name="Off" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x07" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="100" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ256GP610.xml b/src/devices/pic/xml_data/24HJ256GP610.xml
new file mode 100644
index 0000000..4c1e714
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ256GP610.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ256GP610" document="024693" status="IP" memory_technology="FLASH" architecture="24H" id="0x007B" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x02ABFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="8192" />
+      <value value="0x02" name="4096" />
+      <value value="0x04" name="1024" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RBSSIZ" value="0xC0" >
+      <value value="0x00" name="1024" />
+      <value value="0x40" name="256"  />
+      <value value="0x80" name="128"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FSS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTSS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="SSSIZ"  value="0x06" >
+      <value value="0x00" name="32768" />
+      <value value="0x02" name="16384"  />
+      <value value="0x04" name="8192"  />
+      <value value="0x06" name="0"   />
+    </mask>
+    <mask name="SSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RSSSIZ" value="0xC0" >
+      <value value="0x00" name="4096" />
+      <value value="0x40" name="2048" />
+      <value value="0x80" name="256"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0xA7" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="TEMP" value="0x20" >
+      <value value="0x00" name="On" />
+      <value value="0x20" name="Off" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x07" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="100" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ32GP202.xml b/src/devices/pic/xml_data/24HJ32GP202.xml
new file mode 100644
index 0000000..d93607a
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ32GP202.xml
@@ -0,0 +1,180 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ32GP202" status="IP" memory_technology="FLASH" architecture="24H" id="0x0F1D" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="530328" datasheet="70289" progsheet="70152" erratas="80339" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x0057FF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="1792" />
+      <value value="0x02" name="768" />
+      <value value="0x04" name="256" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="reserved" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0x87" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="IOL1WAY" value="0x20" >
+      <value value="0x00" name="Multiple reconfigurations" />
+      <value value="0x20" name="One reconfiguration" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x17" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+    <mask name="ALTI2C" value="0x10" >
+      <value value="0x00" name="ASDA1/ASCL1" />
+      <value value="0x10" name="SDA1/SCL1" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic qfn" nb_pins="28" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ32GP204.xml b/src/devices/pic/xml_data/24HJ32GP204.xml
new file mode 100644
index 0000000..5a9e126
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ32GP204.xml
@@ -0,0 +1,180 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ32GP204" status="IP" memory_technology="FLASH" architecture="24H" id="0x0F1F" >
+
+<!--* Documents ************************************************************-->
+  <documents webpage="530271" datasheet="70289" progsheet="70152" erratas="80339" />
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"              start="0x000200" end="0x0057FF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0x0F" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="1792" />
+      <value value="0x02" name="768" />
+      <value value="0x04" name="256" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="reserved" wmask="0xFF" bvalue="0x00" >
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0x87" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="IOL1WAY" value="0x20" >
+      <value value="0x00" name="Multiple reconfigurations" />
+      <value value="0x20" name="One reconfiguration" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x17" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+    <mask name="ALTI2C" value="0x10" >
+      <value value="0x00" name="ASDA1/ASCL1" />
+      <value value="0x10" name="SDA1/SCL1" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="44" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ64GP206.xml b/src/devices/pic/xml_data/24HJ64GP206.xml
new file mode 100644
index 0000000..a3266fa
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ64GP206.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ64GP206" document="024680" status="IP" memory_technology="FLASH" architecture="24H" id="0x0041" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x00ABFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="8192" />
+      <value value="0x02" name="4096" />
+      <value value="0x04" name="1024" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RBSSIZ" value="0xC0" >
+      <value value="0x00" name="1024" />
+      <value value="0x40" name="256"  />
+      <value value="0x80" name="128"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FSS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTSS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="SSSIZ"  value="0x06" >
+      <value value="0x00" name="16384" />
+      <value value="0x02" name="8192"  />
+      <value value="0x04" name="4096"  />
+      <value value="0x06" name="0"   />
+    </mask>
+    <mask name="SSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RSSSIZ" value="0xC0" >
+      <value value="0x00" name="4096" />
+      <value value="0x40" name="2048" />
+      <value value="0x80" name="256"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0xA7" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="TEMP" value="0x20" >
+      <value value="0x00" name="On" />
+      <value value="0x20" name="Off" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x07" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ64GP210.xml b/src/devices/pic/xml_data/24HJ64GP210.xml
new file mode 100644
index 0000000..630a12a
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ64GP210.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ64GP210" document="024681" status="IP" memory_technology="FLASH" architecture="24H" id="0x0047" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x00ABFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="8192" />
+      <value value="0x02" name="4096" />
+      <value value="0x04" name="1024" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RBSSIZ" value="0xC0" >
+      <value value="0x00" name="1024" />
+      <value value="0x40" name="256"  />
+      <value value="0x80" name="128"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FSS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTSS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="SSSIZ"  value="0x06" >
+      <value value="0x00" name="16384" />
+      <value value="0x02" name="8192"  />
+      <value value="0x04" name="4096"  />
+      <value value="0x06" name="0"   />
+    </mask>
+    <mask name="SSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RSSSIZ" value="0xC0" >
+      <value value="0x00" name="4096" />
+      <value value="0x40" name="2048" />
+      <value value="0x80" name="256"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0xA7" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="TEMP" value="0x20" >
+      <value value="0x00" name="On" />
+      <value value="0x20" name="Off" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x07" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="100" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ64GP506.xml b/src/devices/pic/xml_data/24HJ64GP506.xml
new file mode 100644
index 0000000..372c767
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ64GP506.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ64GP506" document="024682" status="IP" memory_technology="FLASH" architecture="24H" id="0x0049" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x00ABFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="8192" />
+      <value value="0x02" name="4096" />
+      <value value="0x04" name="1024" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RBSSIZ" value="0xC0" >
+      <value value="0x00" name="1024" />
+      <value value="0x40" name="256"  />
+      <value value="0x80" name="128"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FSS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTSS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="SSSIZ"  value="0x06" >
+      <value value="0x00" name="16384" />
+      <value value="0x02" name="8192"  />
+      <value value="0x04" name="4096"  />
+      <value value="0x06" name="0"   />
+    </mask>
+    <mask name="SSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RSSSIZ" value="0xC0" >
+      <value value="0x00" name="4096" />
+      <value value="0x40" name="2048" />
+      <value value="0x80" name="256"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0xA7" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="TEMP" value="0x20" >
+      <value value="0x00" name="On" />
+      <value value="0x20" name="Off" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x07" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/24HJ64GP510.xml b/src/devices/pic/xml_data/24HJ64GP510.xml
new file mode 100644
index 0000000..8711793
--- /dev/null
+++ b/src/devices/pic/xml_data/24HJ64GP510.xml
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2007 Nicolas Hadacek <hadacek@kde.org>                 *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="24HJ64GP510" document="024684" status="IP" memory_technology="FLASH" architecture="24H" id="0x004B" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="40" vdd_min="3.0" vdd_max="3.6" />
+  </frequency_range>
+
+  <voltages name="vpp" min="3.0" max="3.6" nominal="3.3" />
+  <voltages name="vdd_prog" min="3.0" max="3.6" nominal="3.3" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000200" end="0x00ABFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0xF80010" end="0xF80018" rmask="0xFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x800FFF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FBS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTBS" value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="BSSIZ"  value="0x06" >
+      <value value="0x00" name="8192" />
+      <value value="0x02" name="4096" />
+      <value value="0x04" name="1024" />
+      <value value="0x06" name="0"  />
+    </mask>
+    <mask name="BSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RBSSIZ" value="0xC0" >
+      <value value="0x00" name="1024" />
+      <value value="0x40" name="256"  />
+      <value value="0x80" name="128"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FSS" wmask="0xFF" bvalue="0xCF" >
+    <mask name="WRTSS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="SSSIZ"  value="0x06" >
+      <value value="0x00" name="16384" />
+      <value value="0x02" name="8192"  />
+      <value value="0x04" name="4096"  />
+      <value value="0x06" name="0"   />
+    </mask>
+    <mask name="SSSEC" value="0x08" >
+      <value value="0x00" name="High Security"     />
+      <value value="0x08" name="Standard Security" />
+    </mask>
+    <mask name="RSSSIZ" value="0xC0" >
+      <value value="0x00" name="4096" />
+      <value value="0x40" name="2048" />
+      <value value="0x80" name="256"  />
+      <value value="0xC0" name="0"    />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FGS" wmask="0xFF" bvalue="0x07" >
+    <mask name="WRTGS"  value="0x01" >
+      <value value="0x00" name="All"  />
+      <value value="0x01" name="Off" />
+    </mask>
+    <mask name="GSSEC" value="0x06" >
+      <value value="0x00" name="High Security" />
+      <value value="0x02" name="High Security" />
+      <value value="0x04" name="Standard Security" />
+      <value value="0x06" name="Off" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FOSCSEL" wmask="0xFF" bvalue="0xA7" >
+    <mask name="FNOSC" value="0x07" >
+      <value value="0x00" name="EXTRC_F" />
+      <value value="0x01" name="INTRC_F_PLL" />
+      <value value="0x02" name="PRIM" />
+      <value value="0x03" name="PRIM_PLL" />
+      <value value="0x04" name="SECOND" />
+      <value value="0x05" name="EXTRC_LP" />
+      <value value="0x06" name="invalid" />
+      <value value="0x07" name="INTRC_F_POST" />
+    </mask>
+    <mask name="TEMP" value="0x20" >
+      <value value="0x00" name="On" />
+      <value value="0x20" name="Off" />
+    </mask>
+    <mask name="IESO" value="0x80" >
+      <value value="0x00" name="Off" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FOSC" wmask="0xFF" bvalue="0xC7" >
+    <mask name="POSCMD" value="0x03" >
+      <value value="0x00" name="EC" />
+      <value value="0x01" name="XT" />
+      <value value="0x02" name="HS" />
+      <value value="0x03" name="Off" />
+    </mask>
+    <mask name="OSCIOFNC" value="0x04" >
+      <value value="0x00" name="IO" />
+      <value value="0x04" name="Clock" />
+    </mask>
+    <mask name="FCKSM" value="0xC0" >
+      <value value="0x00" name="Switching on, monitor on" />
+      <value value="0x40" name="Switching on, monitor off" />
+      <value value="0x80" name="Switching off, monitor off" />
+      <value value="0xC0" name="Switching off, monitor off" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FWDT" wmask="0xFF" bvalue="0xDF">
+    <mask name="WDTPOST" value="0x0F" >
+      <value value="0x00" name="1:1" />
+      <value value="0x01" name="1:2" />
+      <value value="0x02" name="1:4" />
+      <value value="0x03" name="1:8" />
+      <value value="0x04" name="1:16" />
+      <value value="0x05" name="1:32" />
+      <value value="0x06" name="1:64" />
+      <value value="0x07" name="1:128" />
+      <value value="0x08" name="1:256" />
+      <value value="0x09" name="1:512" />
+      <value value="0x0A" name="1:1024" />
+      <value value="0x0B" name="1:2048" />
+      <value value="0x0C" name="1:4096" />
+      <value value="0x0D" name="1:8192" />
+      <value value="0x0E" name="1:16384" />
+      <value value="0x0F" name="1:32768" />
+    </mask>
+    <mask name="WDTPRE" value="0x10" >
+      <value value="0x00" name="1:32" />
+      <value value="0x10" name="1:128" />
+    </mask>
+    <mask name="WINDIS" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="FWDTEN" value="0x80" >
+      <value value="0x00" name="Software" />
+      <value value="0x80" name="On" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="FPOR" wmask="0xFF" bvalue="0x07" >
+    <mask name="FPWRT" value="0x07" >
+      <value value="0x00" name="0" />
+      <value value="0x01" name="2" />
+      <value value="0x02" name="4" />
+      <value value="0x03" name="8" />
+      <value value="0x04" name="16" />
+      <value value="0x05" name="32" />
+      <value value="0x06" name="64" />
+      <value value="0x07" name="128" />
+    </mask>
+  </config>
+
+  <config offset="0xE" name="FICD" wmask="0xFF" bvalue="0xE3" >
+    <mask name="ICS" value="0x03" >
+      <value value="0x00" name="EMUC3, EMUD3" />
+      <value value="0x01" name="EMUC2, EMUD2" />
+      <value value="0x02" name="EMUC1, EMUD1" />
+      <value value="0x03" name="PGC/EMUC, PGD/EMUD" />
+    </mask>
+    <mask name="JTAGEN" value="0x20" >
+      <value value="0x00" name="Off" />
+      <value value="0x20" name="On" />
+    </mask>
+    <mask name="COE" value="0x40" >
+      <value value="0x00" name="On" />
+      <value value="0x40" name="Off" />
+    </mask>
+    <mask name="DEBUG" value="0x80" >
+      <value value="0x00" name="On" />
+      <value value="0x80" name="Off" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="100" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F1010.xml b/src/devices/pic/xml_data/30F1010.xml
new file mode 100644
index 0000000..1d59008
--- /dev/null
+++ b/src/devices/pic/xml_data/30F1010.xml
@@ -0,0 +1,221 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F1010" document="026448" status="IP" memory_technology="FLASH" architecture="30F" id="0x0404" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="5.5" nominal="5" />
+  <voltages name="vdd_prog"       min="3" max="5.5" nominal="5" />
+  <voltages name="vdd_prog_write" min="3" max="5.5" nominal="5" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x000FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+<config offset="0x0" name="FBS" wmask="0xFFFF" bvalue="0x000F" >
+  <mask name="WRTBS" value="0x0001" >
+    <value value="0x0000" name="All" />
+    <value value="0x0001" name="Off" />
+  </mask>
+  <mask name="BSSIZ"  value="0x0006" >
+    <value value="0x0000" name="0"  />
+    <value value="0x0002" name="invalid" />
+    <value value="0x0004" name="1024" />
+    <value value="0x0006" name="0"  />
+  </mask>
+  <mask name="BSSEC" value="0x0008" >
+    <value value="0x0000" name="High Security"     />
+    <value value="0x0008" name="Standard Security" />
+  </mask>
+</config>
+
+<config offset="0x2" name="reserved" wmask="0xFFFF" bvalue="0x0000" ></config>
+
+<config offset="0x4" name="FGS" wmask="0xFFFF" bvalue="0x0007" >
+  <mask name="WRTGS"  value="0x0001" >
+    <value value="0x0000" name="All"  />
+    <value value="0x0001" name="Off" />
+  </mask>
+  <mask name="GSSEC" value="0x0006" >
+    <value value="0x0000" name="High Security" />
+    <value value="0x0002" name="High Security" />
+    <value value="0x0004" name="Standard Security" />
+    <value value="0x0006" name="Off" />
+  </mask>
+</config>
+
+<config offset="0x6" name="FOSCSEL" wmask="0xFFFF" bvalue="0x0003" >
+  <mask name="FNOSC" value="0x0003" >
+    <value value="0x0000" name="INTRC_F" />
+    <value value="0x0001" name="INTRC_F_PLL" />
+    <value value="0x0002" name="PRIM" />
+    <value value="0x0003" name="PRIM_PLL" />
+  </mask>
+</config>
+
+<config offset="0x8" name="FOSC" wmask="0xFFFF" bvalue="0x00E7" >
+  <mask name="POSCMD" value="0x0003" >
+    <value value="0x0000" name="EC" />
+    <value value="0x0001" name="invalid" />
+    <value value="0x0002" name="HS" />
+    <value value="0x0003" name="Off" />
+  </mask>
+  <mask name="OSCIOFNC" value="0x0004" >
+    <value value="0x0000" name="IO" />
+    <value value="0x0004" name="Clock" />
+  </mask>
+  <mask name="FRANGE" value="0x0020" >
+    <value value="0x0000" name="Low range" />
+    <value value="0x0020" name="High range" />
+  </mask>
+  <mask name="FCKSM" value="0x00C0" >
+    <value value="0x0000" name="Switching on, monitor on" />
+    <value value="0x0040" name="Switching on, monitor off" />
+    <value value="0x0080" name="Switching off, monitor off" />
+    <value value="0x00C0" name="Switching off, monitor off" />
+  </mask>
+</config>
+
+<config offset="0xA" name="FWDT" wmask="0xFFFF" bvalue="0x00DF">
+  <mask name="WDTPOST" value="0x000F" >
+    <value value="0x0000" name="1:1" />
+    <value value="0x0001" name="1:2" />
+    <value value="0x0002" name="1:4" />
+    <value value="0x0003" name="1:8" />
+    <value value="0x0004" name="1:16" />
+    <value value="0x0005" name="1:32" />
+    <value value="0x0006" name="1:64" />
+    <value value="0x0007" name="1:128" />
+    <value value="0x0008" name="1:256" />
+    <value value="0x0009" name="1:512" />
+    <value value="0x000A" name="1:1024" />
+    <value value="0x000B" name="1:2048" />
+    <value value="0x000C" name="1:4096" />
+    <value value="0x000D" name="1:8192" />
+    <value value="0x000E" name="1:16384" />
+    <value value="0x000F" name="1:32768" />
+  </mask>
+  <mask name="WDTPRE" value="0x0010" >
+    <value value="0x0000" name="1:32" />
+    <value value="0x0010" name="1:128" />
+  </mask>
+  <mask name="WINDIS" value="0x0040" >
+    <value value="0x0000" name="On" />
+    <value value="0x0040" name="Off" />
+  </mask>
+  <mask name="FWDTEN" value="0x0080" >
+    <value value="0x0000" name="Software" />
+    <value value="0x0080" name="On" />
+  </mask>
+</config>
+
+<config offset="0xC" name="FPOR" wmask="0xFFFF" bvalue="0x0007" >
+  <mask name="FPWRT" value="0x0007" >
+    <value value="0x0000" name="0" />
+    <value value="0x0001" name="2" />
+    <value value="0x0002" name="4" />
+    <value value="0x0003" name="8" />
+    <value value="0x0004" name="16" />
+    <value value="0x0005" name="32" />
+    <value value="0x0006" name="64" />
+    <value value="0x0007" name="128" />
+  </mask>
+</config>
+
+<config offset="0xE" name="FICD" wmask="0xFFFF" bvalue="0x0083" >
+  <mask name="ICS" value="0x0003" >
+    <value value="0x0000" name="invalid" />
+    <value value="0x0001" name="EMUC2, EMUD2" />
+    <value value="0x0002" name="EMUC1, EMUD1" />
+    <value value="0x0003" name="PGC/EMUC, PGD/EMUD" />
+  </mask>
+  <mask name="DEBUG" value="0x0080" >
+    <value value="0x0000" name="On" />
+    <value value="0x0080" name="Off" />
+  </mask>
+</config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfns"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F2010.xml b/src/devices/pic/xml_data/30F2010.xml
new file mode 100644
index 0000000..f252785
--- /dev/null
+++ b/src/devices/pic/xml_data/30F2010.xml
@@ -0,0 +1,237 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F2010" document="010329" status="IP" memory_technology="FLASH" architecture="30F" id="0x0040" >
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected="Off" bchecksum="0xD406" cchecksum="0xD208" />
+    <checksum protected="All" bchecksum="0x0404" cchecksum="0x0404" />
+  </checksums>
+-->
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x001FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FFC00" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC30F" bvalue="0xC30F" cmask="0xC10F" >
+    <mask name="FPR"   value="0x000F" >
+      <value value="0x0000" name="XTL"          cname="XTL"        />
+      <value value="0x0001" name="XTL"          cname="XTL"        />
+      <value value="0x0002" name="HS"           cname="HS"         />
+      <value value="0x0003" name="HS"           cname="HS"         />
+      <value value="0x0004" name="XT"           cname="XT"         />
+      <value value="0x0005" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0006" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0007" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x0008" name="EXTRC_IO"     cname="ERCIO"      />
+      <value value="0x0009" name="EXTRC_CLKOUT" cname="ERC"        />
+      <value value="0x000A" name="invalid" />
+      <value value="0x000B" name="EC_CLKOUT"    cname="EC"         />
+      <value value="0x000C" name="EC_IO"        cname="ECIO"       />
+      <value value="0x000D" name="EC4"          cname="EC_PLL4"  />
+      <value value="0x000E" name="EC8"          cname="EC_PLL8"  />
+      <value value="0x000F" name="EC16"         cname="EC_PLL16" />
+    </mask>
+    <mask name="FOS"   value="0x0300" >
+      <value value="0x0000" name="TMR1"     cname="LP"   />
+      <value value="0x0100" name="INTRC_F"  cname="FRC"  />
+      <value value="0x0200" name="INTRC_LP" cname="LPRC" />
+      <value value="0x0300" name="PRIM"     cname="_"    />
+    </mask>
+    <mask name="FCKSM" value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="default" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x87B3" >
+    <mask name="FPWRT"  value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"   value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN"  value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="LPOL"   value="0x0100" >
+      <value value="0x0000" name="low"  cname="PWMxL_ACT_LO" />
+      <value value="0x0100" name="high" cname="PWMxL_ACT_HI" />
+    </mask>
+    <mask name="HPOL"   value="0x0200" >
+      <value value="0x0000" name="low"  cname="PWMxH_ACT_LO" />
+      <value value="0x0200" name="high" cname="PWMxH_ACT_HI" />
+    </mask>
+    <mask name="PWMPIN" value="0x0400" >
+      <value value="0x0000" name="On"  cname="RST_PWMPIN" />
+      <value value="0x0400" name="Off" cname="RST_IOPIN"  />
+    </mask>
+    <mask name="MCLRE"  value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F2011.xml b/src/devices/pic/xml_data/30F2011.xml
new file mode 100644
index 0000000..a767855
--- /dev/null
+++ b/src/devices/pic/xml_data/30F2011.xml
@@ -0,0 +1,203 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F2011" document="010340" status="IP" memory_technology="FLASH" architecture="30F" id="0x0240" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x001FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"        />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="default" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F2012.xml b/src/devices/pic/xml_data/30F2012.xml
new file mode 100644
index 0000000..6da9eb7
--- /dev/null
+++ b/src/devices/pic/xml_data/30F2012.xml
@@ -0,0 +1,213 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F2012" document="010341" status="IP" memory_technology="FLASH" architecture="30F" id="0x0241" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x001FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"        />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="default" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F2020.xml b/src/devices/pic/xml_data/30F2020.xml
new file mode 100644
index 0000000..3aa30e9
--- /dev/null
+++ b/src/devices/pic/xml_data/30F2020.xml
@@ -0,0 +1,221 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F2020" document="026339" status="IP" memory_technology="FLASH" architecture="30F" id="0x0400" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="5.5" nominal="5" />
+  <voltages name="vdd_prog"       min="3" max="5.5" nominal="5" />
+  <voltages name="vdd_prog_write" min="3" max="5.5" nominal="5" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x001FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+<config offset="0x0" name="FBS" wmask="0xFFFF" bvalue="0x000F" >
+  <mask name="WRTBS" value="0x0001" >
+    <value value="0x0000" name="All" />
+    <value value="0x0001" name="Off" />
+  </mask>
+  <mask name="BSSIZ"  value="0x0006" >
+    <value value="0x0000" name="0"  />
+    <value value="0x0002" name="4096" />
+    <value value="0x0004" name="1024" />
+    <value value="0x0006" name="0"  />
+  </mask>
+  <mask name="BSSEC" value="0x0008" >
+    <value value="0x0000" name="High Security"     />
+    <value value="0x0008" name="Standard Security" />
+  </mask>
+</config>
+
+<config offset="0x2" name="reserved" wmask="0xFFFF" bvalue="0x0000" ></config>
+
+<config offset="0x4" name="FGS" wmask="0xFFFF" bvalue="0x0007" >
+  <mask name="WRTGS"  value="0x0001" >
+    <value value="0x0000" name="All"  />
+    <value value="0x0001" name="Off" />
+  </mask>
+  <mask name="GSSEC" value="0x0006" >
+    <value value="0x0000" name="High Security" />
+    <value value="0x0002" name="High Security" />
+    <value value="0x0004" name="Standard Security" />
+    <value value="0x0006" name="Off" />
+  </mask>
+</config>
+
+<config offset="0x6" name="FOSCSEL" wmask="0xFFFF" bvalue="0x0003" >
+  <mask name="FNOSC" value="0x0003" >
+    <value value="0x0000" name="INTRC_F" />
+    <value value="0x0001" name="INTRC_F_PLL" />
+    <value value="0x0002" name="PRIM" />
+    <value value="0x0003" name="PRIM_PLL" />
+  </mask>
+</config>
+
+<config offset="0x8" name="FOSC" wmask="0xFFFF" bvalue="0x00E7" >
+  <mask name="POSCMD" value="0x0003" >
+    <value value="0x0000" name="EC" />
+    <value value="0x0001" name="invalid" />
+    <value value="0x0002" name="HS" />
+    <value value="0x0003" name="Off" />
+  </mask>
+  <mask name="OSCIOFNC" value="0x0004" >
+    <value value="0x0000" name="IO" />
+    <value value="0x0004" name="Clock" />
+  </mask>
+  <mask name="FRANGE" value="0x0020" >
+    <value value="0x0000" name="Low range" />
+    <value value="0x0020" name="High range" />
+  </mask>
+  <mask name="FCKSM" value="0x00C0" >
+    <value value="0x0000" name="Switching on, monitor on" />
+    <value value="0x0040" name="Switching on, monitor off" />
+    <value value="0x0080" name="Switching off, monitor off" />
+    <value value="0x00C0" name="Switching off, monitor off" />
+  </mask>
+</config>
+
+<config offset="0xA" name="FWDT" wmask="0xFFFF" bvalue="0x00DF">
+  <mask name="WDTPOST" value="0x000F" >
+    <value value="0x0000" name="1:1" />
+    <value value="0x0001" name="1:2" />
+    <value value="0x0002" name="1:4" />
+    <value value="0x0003" name="1:8" />
+    <value value="0x0004" name="1:16" />
+    <value value="0x0005" name="1:32" />
+    <value value="0x0006" name="1:64" />
+    <value value="0x0007" name="1:128" />
+    <value value="0x0008" name="1:256" />
+    <value value="0x0009" name="1:512" />
+    <value value="0x000A" name="1:1024" />
+    <value value="0x000B" name="1:2048" />
+    <value value="0x000C" name="1:4096" />
+    <value value="0x000D" name="1:8192" />
+    <value value="0x000E" name="1:16384" />
+    <value value="0x000F" name="1:32768" />
+  </mask>
+  <mask name="WDTPRE" value="0x0010" >
+    <value value="0x0000" name="1:32" />
+    <value value="0x0010" name="1:128" />
+  </mask>
+  <mask name="WINDIS" value="0x0040" >
+    <value value="0x0000" name="On" />
+    <value value="0x0040" name="Off" />
+  </mask>
+  <mask name="FWDTEN" value="0x0080" >
+    <value value="0x0000" name="Software" />
+    <value value="0x0080" name="On" />
+  </mask>
+</config>
+
+<config offset="0xC" name="FPOR" wmask="0xFFFF" bvalue="0x0007" >
+  <mask name="FPWRT" value="0x0007" >
+    <value value="0x0000" name="0" />
+    <value value="0x0001" name="2" />
+    <value value="0x0002" name="4" />
+    <value value="0x0003" name="8" />
+    <value value="0x0004" name="16" />
+    <value value="0x0005" name="32" />
+    <value value="0x0006" name="64" />
+    <value value="0x0007" name="128" />
+  </mask>
+</config>
+
+<config offset="0xE" name="FICD" wmask="0xFFFF" bvalue="0x0083" >
+  <mask name="ICS" value="0x0003" >
+    <value value="0x0000" name="invalid" />
+    <value value="0x0001" name="EMUC2, EMUD2" />
+    <value value="0x0002" name="EMUC1, EMUD1" />
+    <value value="0x0003" name="PGC/EMUC, PGD/EMUD" />
+  </mask>
+  <mask name="DEBUG" value="0x0080" >
+    <value value="0x0000" name="On" />
+    <value value="0x0080" name="Off" />
+  </mask>
+</config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfns"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F2023.xml b/src/devices/pic/xml_data/30F2023.xml
new file mode 100644
index 0000000..8241600
--- /dev/null
+++ b/src/devices/pic/xml_data/30F2023.xml
@@ -0,0 +1,162 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F2023" document="026341" status="IP" memory_technology="FLASH" architecture="30F" id="0x0403" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="3" max="5.5" nominal="5" />
+  <voltages name="vdd_prog"       min="3" max="5.5" nominal="5" />
+  <voltages name="vdd_prog_write" min="3" max="5.5" nominal="5" />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x001FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000F" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+<config offset="0x0" name="FBS" wmask="0xFFFF" bvalue="0x000F" >
+  <mask name="WRTBS" value="0x0001" >
+    <value value="0x0000" name="All" />
+    <value value="0x0001" name="Off" />
+  </mask>
+  <mask name="BSSIZ"  value="0x0006" >
+    <value value="0x0000" name="0"  />
+    <value value="0x0002" name="4096" />
+    <value value="0x0004" name="1024" />
+    <value value="0x0006" name="0"  />
+  </mask>
+  <mask name="BSSEC" value="0x0008" >
+    <value value="0x0000" name="High Security"     />
+    <value value="0x0008" name="Standard Security" />
+  </mask>
+</config>
+
+<config offset="0x2" name="reserved" wmask="0xFFFF" bvalue="0x0000" ></config>
+
+<config offset="0x4" name="FGS" wmask="0xFFFF" bvalue="0x0007" >
+  <mask name="WRTGS"  value="0x0001" >
+    <value value="0x0000" name="All"  />
+    <value value="0x0001" name="Off" />
+  </mask>
+  <mask name="GSSEC" value="0x0006" >
+    <value value="0x0000" name="High Security" />
+    <value value="0x0002" name="High Security" />
+    <value value="0x0004" name="Standard Security" />
+    <value value="0x0006" name="Off" />
+  </mask>
+</config>
+
+<config offset="0x6" name="FOSCSEL" wmask="0xFFFF" bvalue="0x0003" >
+  <mask name="FNOSC" value="0x0003" >
+    <value value="0x0000" name="INTRC_F" />
+    <value value="0x0001" name="INTRC_F_PLL" />
+    <value value="0x0002" name="PRIM" />
+    <value value="0x0003" name="PRIM_PLL" />
+  </mask>
+</config>
+
+<config offset="0x8" name="FOSC" wmask="0xFFFF" bvalue="0x00E7" >
+  <mask name="POSCMD" value="0x0003" >
+    <value value="0x0000" name="EC" />
+    <value value="0x0001" name="invalid" />
+    <value value="0x0002" name="HS" />
+    <value value="0x0003" name="Off" />
+  </mask>
+  <mask name="OSCIOFNC" value="0x0004" >
+    <value value="0x0000" name="IO" />
+    <value value="0x0004" name="Clock" />
+  </mask>
+  <mask name="FRANGE" value="0x0020" >
+    <value value="0x0000" name="Low range" />
+    <value value="0x0020" name="High range" />
+  </mask>
+  <mask name="FCKSM" value="0x00C0" >
+    <value value="0x0000" name="Switching on, monitor on" />
+    <value value="0x0040" name="Switching on, monitor off" />
+    <value value="0x0080" name="Switching off, monitor off" />
+    <value value="0x00C0" name="Switching off, monitor off" />
+  </mask>
+</config>
+
+<config offset="0xA" name="FWDT" wmask="0xFFFF" bvalue="0x00DF">
+  <mask name="WDTPOST" value="0x000F" >
+    <value value="0x0000" name="1:1" />
+    <value value="0x0001" name="1:2" />
+    <value value="0x0002" name="1:4" />
+    <value value="0x0003" name="1:8" />
+    <value value="0x0004" name="1:16" />
+    <value value="0x0005" name="1:32" />
+    <value value="0x0006" name="1:64" />
+    <value value="0x0007" name="1:128" />
+    <value value="0x0008" name="1:256" />
+    <value value="0x0009" name="1:512" />
+    <value value="0x000A" name="1:1024" />
+    <value value="0x000B" name="1:2048" />
+    <value value="0x000C" name="1:4096" />
+    <value value="0x000D" name="1:8192" />
+    <value value="0x000E" name="1:16384" />
+    <value value="0x000F" name="1:32768" />
+  </mask>
+  <mask name="WDTPRE" value="0x0010" >
+    <value value="0x0000" name="1:32" />
+    <value value="0x0010" name="1:128" />
+  </mask>
+  <mask name="WINDIS" value="0x0040" >
+    <value value="0x0000" name="On" />
+    <value value="0x0040" name="Off" />
+  </mask>
+  <mask name="FWDTEN" value="0x0080" >
+    <value value="0x0000" name="Software" />
+    <value value="0x0080" name="On" />
+  </mask>
+</config>
+
+<config offset="0xC" name="FPOR" wmask="0xFFFF" bvalue="0x0007" >
+  <mask name="FPWRT" value="0x0007" >
+    <value value="0x0000" name="0" />
+    <value value="0x0001" name="2" />
+    <value value="0x0002" name="4" />
+    <value value="0x0003" name="8" />
+    <value value="0x0004" name="16" />
+    <value value="0x0005" name="32" />
+    <value value="0x0006" name="64" />
+    <value value="0x0007" name="128" />
+  </mask>
+</config>
+
+<config offset="0xE" name="FICD" wmask="0xFFFF" bvalue="0x0083" >
+  <mask name="ICS" value="0x0003" >
+    <value value="0x0000" name="invalid" />
+    <value value="0x0001" name="EMUC2, EMUD2" />
+    <value value="0x0002" name="EMUC1, EMUD1" />
+    <value value="0x0003" name="PGC/EMUC, PGD/EMUD" />
+  </mask>
+  <mask name="DEBUG" value="0x0080" >
+    <value value="0x0000" name="On" />
+    <value value="0x0080" name="Off" />
+  </mask>
+</config>
+
+<!--* Packages *************************************************************-->
+  <package types="qfn tqfp"       nb_pins="44" >
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F3010.xml b/src/devices/pic/xml_data/30F3010.xml
new file mode 100644
index 0000000..1041c86
--- /dev/null
+++ b/src/devices/pic/xml_data/30F3010.xml
@@ -0,0 +1,242 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F3010" document="010335" status="IP" memory_technology="FLASH" architecture="30F" id="0x01C0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x003FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FFC00" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"        />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="default" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x87B3" >
+    <mask name="FPWRT"  value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"   value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN"  value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="LPOL"   value="0x0100" >
+      <value value="0x0000" name="low"  cname="PWMxL_ACT_LO" />
+      <value value="0x0100" name="high" cname="PWMxL_ACT_HI" />
+    </mask>
+    <mask name="HPOL"   value="0x0200" >
+      <value value="0x0000" name="low"  cname="PWMxH_ACT_LO" />
+      <value value="0x0200" name="high" cname="PWMxH_ACT_HI" />
+    </mask>
+    <mask name="PWMPIN" value="0x0400" >
+      <value value="0x0000" name="On"  cname="RST_PWMPIN" />
+      <value value="0x0400" name="Off" cname="RST_IOPIN"  />
+    </mask>
+    <mask name="MCLRE"  value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F3011.xml b/src/devices/pic/xml_data/30F3011.xml
new file mode 100644
index 0000000..b092d8b
--- /dev/null
+++ b/src/devices/pic/xml_data/30F3011.xml
@@ -0,0 +1,302 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F3011" document="010336" status="IP" memory_technology="FLASH" architecture="30F" id="0x01C1" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x003FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FFC00" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"         />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x87B3" >
+    <mask name="FPWRT"  value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"   value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN"  value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="LPOL"   value="0x0100" >
+      <value value="0x0000" name="low"  cname="PWMxL_ACT_LO" />
+      <value value="0x0100" name="high" cname="PWMxL_ACT_HI" />
+    </mask>
+    <mask name="HPOL"   value="0x0200" >
+      <value value="0x0000" name="low"  cname="PWMxH_ACT_LO" />
+      <value value="0x0200" name="high" cname="PWMxH_ACT_HI" />
+    </mask>
+    <mask name="PWMPIN" value="0x0400" >
+      <value value="0x0000" name="On"  cname="RST_PWMPIN" />
+      <value value="0x0400" name="Off" cname="RST_IOPIN"  />
+    </mask>
+    <mask name="MCLRE"  value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F3012.xml b/src/devices/pic/xml_data/30F3012.xml
new file mode 100644
index 0000000..b87d96a
--- /dev/null
+++ b/src/devices/pic/xml_data/30F3012.xml
@@ -0,0 +1,220 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F3012" document="010342" status="IP" memory_technology="FLASH" architecture="30F" id="0x00C1" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x003FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FFC00" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"         />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="default" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F3013.xml b/src/devices/pic/xml_data/30F3013.xml
new file mode 100644
index 0000000..702e415
--- /dev/null
+++ b/src/devices/pic/xml_data/30F3013.xml
@@ -0,0 +1,230 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F3013" document="010343" status="IP" memory_technology="FLASH" architecture="30F" id="0x00C3" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x003FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FFC00" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"         />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="default" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F3014.xml b/src/devices/pic/xml_data/30F3014.xml
new file mode 100644
index 0000000..13bd387
--- /dev/null
+++ b/src/devices/pic/xml_data/30F3014.xml
@@ -0,0 +1,289 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F3014" document="010344" status="IP" memory_technology="FLASH" architecture="30F" id="0x0160" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x003FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FFC00" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"        />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="default" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F4011.xml b/src/devices/pic/xml_data/30F4011.xml
new file mode 100644
index 0000000..89791c2
--- /dev/null
+++ b/src/devices/pic/xml_data/30F4011.xml
@@ -0,0 +1,305 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F4011" document="010337" status="IP" memory_technology="FLASH" architecture="30F" id="0x0101" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x007FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FFC00" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC30F" bvalue="0xC30F" cmask="0xC10F" >
+    <mask name="FPR"   value="0x000F" >
+      <value value="0x0000" name="XTL"          cname="XTL"      />
+      <value value="0x0001" name="XTL"          cname="XTL"      />
+      <value value="0x0002" name="HS"           cname="HS"       />
+      <value value="0x0003" name="HS"           cname="HS"       />
+      <value value="0x0004" name="XT"           cname="XTL"      />
+      <value value="0x0005" name="XT4"          cname="XT_PLL4"  />
+      <value value="0x0006" name="XT8"          cname="XT_PLL8"  />
+      <value value="0x0007" name="XT16"         cname="XT_PLL16" />
+      <value value="0x0008" name="EXTRC_IO"     cname="ERCIO"    />
+      <value value="0x0009" name="EXTRC_CLKOUT" cname="ERC"      />
+      <value value="0x000A" name="FRC8"         cname="FRC_PLL8" />
+      <value value="0x000B" name="EC_CLKOUT"    cname="EC"       />
+      <value value="0x000C" name="EC_IO"        cname="ECIO"     />
+      <value value="0x000D" name="EC4"          cname="EC_PLL4"  />
+      <value value="0x000E" name="EC8"          cname="EC_PLL8"  />
+      <value value="0x000F" name="EC16"         cname="EC_PLL16" />
+    </mask>
+    <mask name="FOS"   value="0x0300" >
+      <value value="0x0000" name="TMR1"     cname="EXT" />
+      <value value="0x0100" name="INTRC_F"  cname="FRC" />
+      <value value="0x0200" name="INTRC_LP" cname="LP"  />
+      <value value="0x0300" name="PRIM"     cname="_"    />
+    </mask>
+    <mask name="FCKSM" value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x87B3" >
+    <mask name="FPWRT"  value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"   value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN"  value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="LPOL"   value="0x0100" >
+      <value value="0x0000" name="low"  cname="PWMxL_ACT_LO" />
+      <value value="0x0100" name="high" cname="PWMxL_ACT_HI" />
+    </mask>
+    <mask name="HPOL"   value="0x0200" >
+      <value value="0x0000" name="low"  cname="PWMxH_ACT_LO" />
+      <value value="0x0200" name="high" cname="PWMxH_ACT_HI" />
+    </mask>
+    <mask name="PWMPIN" value="0x0400" >
+      <value value="0x0000" name="On"  cname="RST_PWMPIN" />
+      <value value="0x0400" name="Off" cname="RST_IOPIN"  />
+    </mask>
+    <mask name="MCLRE"  value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F4012.xml b/src/devices/pic/xml_data/30F4012.xml
new file mode 100644
index 0000000..e42b34c
--- /dev/null
+++ b/src/devices/pic/xml_data/30F4012.xml
@@ -0,0 +1,246 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F4012" document="010338" status="IP" memory_technology="FLASH" architecture="30F" id="0x0100" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x007FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FFC00" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC30F" bvalue="0xC30F" cmask="0xC10F" >
+    <mask name="FPR"   value="0x000F" >
+      <value value="0x0000" name="XTL"          cname="XTL"      />
+      <value value="0x0001" name="XTL"          cname="XTL"      />
+      <value value="0x0002" name="HS"           cname="HS"       />
+      <value value="0x0003" name="HS"           cname="HS"       />
+      <value value="0x0004" name="XT"           cname="XTL"      />
+      <value value="0x0005" name="XT4"          cname="XT_PLL4"  />
+      <value value="0x0006" name="XT8"          cname="XT_PLL8"  />
+      <value value="0x0007" name="XT16"         cname="XT_PLL16" />
+      <value value="0x0008" name="EXTRC_IO"     cname="ERCIO"    />
+      <value value="0x0009" name="EXTRC_CLKOUT" cname="ERC"      />
+      <value value="0x000A" name="FRC8"         cname="FRC_PLL8" />
+      <value value="0x000B" name="EC_CLKOUT"    cname="EC"       />
+      <value value="0x000C" name="EC_IO"        cname="ECIO"     />
+      <value value="0x000D" name="EC4"          cname="EC_PLL4"  />
+      <value value="0x000E" name="EC8"          cname="EC_PLL8"  />
+      <value value="0x000F" name="EC16"         cname="EC_PLL16" />
+    </mask>
+    <mask name="FOS"   value="0x0300" >
+      <value value="0x0000" name="TMR1"     cname="EXT" />
+      <value value="0x0100" name="INTRC_F"  cname="FRC" />
+      <value value="0x0200" name="INTRC_LP" cname="LP"  />
+      <value value="0x0300" name="PRIM"     cname="_"    />
+    </mask>
+    <mask name="FCKSM" value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x87B3" >
+    <mask name="FPWRT"  value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"   value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN"  value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="LPOL"   value="0x0100" >
+      <value value="0x0000" name="low"  cname="PWMxL_ACT_LO" />
+      <value value="0x0100" name="high" cname="PWMxL_ACT_HI" />
+    </mask>
+    <mask name="HPOL"   value="0x0200" >
+      <value value="0x0000" name="low"  cname="PWMxH_ACT_LO" />
+      <value value="0x0200" name="high" cname="PWMxH_ACT_HI" />
+    </mask>
+    <mask name="PWMPIN" value="0x0400" >
+      <value value="0x0000" name="On"  cname="RST_PWMPIN" />
+      <value value="0x0400" name="Off" cname="RST_IOPIN"  />
+    </mask>
+    <mask name="MCLRE"  value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="sdip soic" nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F4013.xml b/src/devices/pic/xml_data/30F4013.xml
new file mode 100644
index 0000000..1732e6e
--- /dev/null
+++ b/src/devices/pic/xml_data/30F4013.xml
@@ -0,0 +1,290 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F4013" document="010345" status="IP" memory_technology="FLASH" architecture="30F" id="0x0141" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x007FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FFC00" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"        />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip" nb_pins="40" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+  </package>
+
+  <package types="qfn"  nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+  <package types="tqfp" nb_pins="44" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F5011.xml b/src/devices/pic/xml_data/30F5011.xml
new file mode 100644
index 0000000..a1f311d
--- /dev/null
+++ b/src/devices/pic/xml_data/30F5011.xml
@@ -0,0 +1,276 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F5011" document="010346" status="IP" memory_technology="FLASH" architecture="30F" id="0x0080" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="7.5" vdd_min="2.5"  vdd_max="5.5" />
+    <frequency start="7.5" end="15"  vdd_min="3"    vdd_max="5.5" />
+    <frequency start="15"  end="30"  vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="10" vdd_min="3"    vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x00AFFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FFC00" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC" wmask="0xC30F" bvalue="0xC30F" cmask="0xC10F" >
+    <mask name="FPR"   value="0x000F" >
+      <value value="0x0000" name="XTL"          cname="XTL"      />
+      <value value="0x0001" name="XTL"          cname="XTL"      />
+      <value value="0x0002" name="HS"           cname="HS"       />
+      <value value="0x0003" name="HS"           cname="HS"       />
+      <value value="0x0004" name="XT"           cname="XTL"      />
+      <value value="0x0005" name="XT4"          cname="XT_PLL4"  />
+      <value value="0x0006" name="XT8"          cname="XT_PLL8"  />
+      <value value="0x0007" name="XT16"         cname="XT_PLL16" />
+      <value value="0x0008" name="EXTRC_IO"     cname="ERCIO"    />
+      <value value="0x0009" name="EXTRC_CLKOUT" cname="ERC"      />
+      <value value="0x000A" name="FRC8"         cname="FRC_PLL8" />
+      <value value="0x000B" name="EC_CLKOUT"    cname="EC"       />
+      <value value="0x000C" name="EC_IO"        cname="ECIO"     />
+      <value value="0x000D" name="EC4"          cname="EC_PLL4"  />
+      <value value="0x000E" name="EC8"          cname="EC_PLL8"  />
+      <value value="0x000F" name="EC16"         cname="EC_PLL16" />
+    </mask>
+    <mask name="FOS"   value="0x0300" >
+      <value value="0x0000" name="TMR1"     cname="EXT" />
+      <value value="0x0100" name="INTRC_F"  cname="FRC" />
+      <value value="0x0200" name="INTRC_LP" cname="LP"  />
+      <value value="0x0300" name="PRIM"     cname="_"    />
+    </mask>
+    <mask name="FCKSM" value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FBS"       wmask="0x310F" bvalue="0x310F" >
+    <mask name="WRTBS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_BOOT_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_BOOT_OFF" />
+    </mask>
+    <mask name="BSSEC" value="0x0008" >
+      <value value="0x0000" name="High Security"     cname="" />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="BSSIZ"  value="0x0006" >
+      <value value="0x0000" name="4196" cname=""  />
+      <value value="0x0002" name="2048" cname="" />
+      <value value="0x0004" name="512"  cname="" />
+      <value value="0x0006" name="0"    cname="" />
+    </mask>
+    <mask name="EBSSIZ" value="0x0100" >
+      <value value="0x0000" name="128" cname="SMALL_BOOT_EEPROM" />
+      <value value="0x0100" name="0"   cname="NO_BOOT_EEPROM" />
+    </mask>
+    <mask name="RBSSIZ"  value="0x3000" >
+      <value value="0x0000" name="512" cname="LAR_BOOT_RAM"  />
+      <value value="0x1000" name="256" cname="MED_BOOT_RAM" />
+      <value value="0x2000" name="128" cname="SMALL_BOOT_RAM" />
+      <value value="0x3000" name="0"   cname="NO_BOOT_RAM" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FSS"       wmask="0x330F" bvalue="0x330F" >
+    <mask name="WRTSS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_SEC_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_SEC_OFF" />
+    </mask>
+    <mask name="SSSEC"  value="0x0008" >
+      <value value="0x0000" name="High Security"     cname=""  />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="SSSIZ"  value="0x0006" >
+      <value value="0x0000" name="16384" cname=""  />
+      <value value="0x0002" name="8192"  cname="" />
+      <value value="0x0004" name="4096"  cname="" />
+      <value value="0x0006" name="0"     cname="" />
+    </mask>
+    <mask name="ESSSIZ" value="0x0300" >
+      <value value="0x0000" name="512" cname="LAR_SEC_EEPROM" />
+      <value value="0x0100" name="256" cname="MED_SEC_EEPROM" />
+      <value value="0x0200" name="128" cname="SMALL_SEC_EEPROM" />
+      <value value="0x0300" name="0"   cname="NO_SEC_EEPROM" />
+    </mask>
+    <mask name="RSSSIZ"  value="0x3000" >
+      <value value="0x0000" name="1024" cname="LAR_SEC_RAM"  />
+      <value value="0x1000" name="768" cname="MED_SEC_RAM" />
+      <value value="0x2000" name="256" cname="SMALL_SEC_RAM" />
+      <value value="0x3000" name="0"   cname="NO_SEC_RAM" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0007" >
+    <mask name="WRTGS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_GEN_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_GEN_OFF" />
+    </mask>
+    <mask name="GSSEC"  value="0x0006" >
+      <value value="default" name="High Security"     cname="HIGH_PROT"  />
+      <value value="0x0004" name="Standard Security" cname="STAND_PROT" />
+      <value value="0x0006" name="Off"               cname="GEN_PROT"  />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F5013.xml b/src/devices/pic/xml_data/30F5013.xml
new file mode 100644
index 0000000..debd97f
--- /dev/null
+++ b/src/devices/pic/xml_data/30F5013.xml
@@ -0,0 +1,292 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F5013" document="010347" status="IP" memory_technology="FLASH" architecture="30F" id="0x0081" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="7.5" vdd_min="2.5"  vdd_max="5.5" />
+    <frequency start="7.5" end="15"  vdd_min="3"    vdd_max="5.5" />
+    <frequency start="15"  end="30"  vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="10" vdd_min="3"    vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x00AFFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FFC00" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC30F" bvalue="0xC30F" cmask="0xC10F" >
+    <mask name="FPR"   value="0x000F" >
+      <value value="0x0000" name="XTL"          cname="XTL"      />
+      <value value="0x0001" name="XTL"          cname="XTL"      />
+      <value value="0x0002" name="HS"           cname="HS"       />
+      <value value="0x0003" name="HS"           cname="HS"       />
+      <value value="0x0004" name="XT"           cname="XTL"      />
+      <value value="0x0005" name="XT4"          cname="XT_PLL4"  />
+      <value value="0x0006" name="XT8"          cname="XT_PLL8"  />
+      <value value="0x0007" name="XT16"         cname="XT_PLL16" />
+      <value value="0x0008" name="EXTRC_IO"     cname="ERCIO"    />
+      <value value="0x0009" name="EXTRC_CLKOUT" cname="ERC"      />
+      <value value="0x000A" name="FRC8"         cname="FRC_PLL8" />
+      <value value="0x000B" name="EC_CLKOUT"    cname="EC"       />
+      <value value="0x000C" name="EC_IO"        cname="ECIO"     />
+      <value value="0x000D" name="EC4"          cname="EC_PLL4"  />
+      <value value="0x000E" name="EC8"          cname="EC_PLL8"  />
+      <value value="0x000F" name="EC16"         cname="EC_PLL16" />
+    </mask>
+    <mask name="FOS"   value="0x0300" >
+      <value value="0x0000" name="TMR1"     cname="EXT" />
+      <value value="0x0100" name="INTRC_F"  cname="FRC" />
+      <value value="0x0200" name="INTRC_LP" cname="LP"  />
+      <value value="0x0300" name="PRIM"     cname="_"    />
+    </mask>
+    <mask name="FCKSM" value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FBS"       wmask="0x310F" bvalue="0x310F" >
+    <mask name="WRTBS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_BOOT_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_BOOT_OFF" />
+    </mask>
+    <mask name="BSSEC" value="0x0008" >
+      <value value="0x0000" name="High Security"     cname="" />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="BSSIZ"  value="0x0006" >
+      <value value="0x0000" name="4096" cname=""  />
+      <value value="0x0002" name="2048" cname="" />
+      <value value="0x0004" name="512" cname="" />
+      <value value="0x0006" name="0"    cname="" />
+    </mask>
+    <mask name="EBSSIZ" value="0x0100" >
+      <value value="0x0000" name="128" cname="SMALL_BOOT_EEPROM" />
+      <value value="0x0100" name="0"   cname="NO_BOOT_EEPROM" />
+    </mask>
+    <mask name="RBSSIZ"  value="0x3000" >
+      <value value="0x0000" name="512" cname="LAR_BOOT_RAM"  />
+      <value value="0x1000" name="256" cname="MED_BOOT_RAM" />
+      <value value="0x2000" name="128" cname="SMALL_BOOT_RAM" />
+      <value value="0x3000" name="0"   cname="NO_BOOT_RAM" />
+    </mask>
+  </config>
+
+  <config offset="0x8" name="FSS"       wmask="0x330F" bvalue="0x330F" >
+    <mask name="WRTSS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_SEC_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_SEC_OFF" />
+    </mask>
+    <mask name="SSSEC"  value="0x0008" >
+      <value value="0x0000" name="High Security"     cname=""  />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="SSSIZ"  value="0x0006" >
+      <value value="0x0000" name="16384" cname=""  />
+      <value value="0x0002" name="8192" cname="" />
+      <value value="0x0004" name="4096"  cname="" />
+      <value value="0x0006" name="0"     cname="" />
+    </mask>
+    <mask name="ESSSIZ" value="0x0300" >
+      <value value="0x0000" name="512" cname="LAR_SEC_EEPROM" />
+      <value value="0x0100" name="256" cname="MED_SEC_EEPROM" />
+      <value value="0x0200" name="128" cname="SMALL_SEC_EEPROM" />
+      <value value="0x0300" name="0"   cname="NO_SEC_EEPROM" />
+    </mask>
+    <mask name="RSSSIZ"  value="0x3000" >
+      <value value="0x0000" name="1024" cname="LAR_SEC_RAM"  />
+      <value value="0x1000" name="768" cname="MED_SEC_RAM" />
+      <value value="0x2000" name="256" cname="SMALL_SEC_RAM" />
+      <value value="0x3000" name="0"   cname="NO_SEC_RAM" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0007" >
+    <mask name="WRTGS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_GEN_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_GEN_OFF" />
+    </mask>
+    <mask name="GSSEC"  value="0x0006" >
+      <value value="default" name="High Security"     cname="HIGH_PROT"  />
+      <value value="0x0004" name="Standard Security" cname="STAND_PROT" />
+      <value value="0x0006" name="Off"               cname="GEN_PROT"  />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F5015.xml b/src/devices/pic/xml_data/30F5015.xml
new file mode 100644
index 0000000..af7c20a
--- /dev/null
+++ b/src/devices/pic/xml_data/30F5015.xml
@@ -0,0 +1,232 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F5015" document="010339" status="IP" memory_technology="FLASH" architecture="30F" id="0x0200" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x00AFFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FFC00" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"        />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x87B3" >
+    <mask name="FPWRT"  value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"   value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN"  value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="LPOL"   value="0x0100" >
+      <value value="0x0000" name="low"  cname="PWMxL_ACT_LO" />
+      <value value="0x0100" name="high" cname="PWMxL_ACT_HI" />
+    </mask>
+    <mask name="HPOL"   value="0x0200" >
+      <value value="0x0000" name="low"  cname="PWMxH_ACT_LO" />
+      <value value="0x0200" name="high" cname="PWMxH_ACT_HI" />
+    </mask>
+    <mask name="PWMPIN" value="0x0400" >
+      <value value="0x0000" name="On"  cname="RST_PWMPIN" />
+      <value value="0x0400" name="Off" cname="RST_IOPIN"  />
+    </mask>
+    <mask name="MCLRE"  value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F5016.xml b/src/devices/pic/xml_data/30F5016.xml
new file mode 100644
index 0000000..aa2e7e1
--- /dev/null
+++ b/src/devices/pic/xml_data/30F5016.xml
@@ -0,0 +1,248 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F5016" document="024210" status="IP" memory_technology="FLASH" architecture="30F" id="0x0201" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x00AFFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FFC00" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"        />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x87B3" >
+    <mask name="FPWRT"  value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"   value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN"  value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="LPOL"   value="0x0100" >
+      <value value="0x0000" name="low"  cname="PWMxL_ACT_LO" />
+      <value value="0x0100" name="high" cname="PWMxL_ACT_HI" />
+    </mask>
+    <mask name="HPOL"   value="0x0200" >
+      <value value="0x0000" name="low"  cname="PWMxH_ACT_LO" />
+      <value value="0x0200" name="high" cname="PWMxH_ACT_HI" />
+    </mask>
+    <mask name="PWMPIN" value="0x0400" >
+      <value value="0x0000" name="On"  cname="RST_PWMPIN" />
+      <value value="0x0400" name="Off" cname="RST_IOPIN"  />
+    </mask>
+    <mask name="MCLRE"  value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F6010.xml b/src/devices/pic/xml_data/30F6010.xml
new file mode 100644
index 0000000..8b26c7c
--- /dev/null
+++ b/src/devices/pic/xml_data/30F6010.xml
@@ -0,0 +1,252 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F6010" document="010330" status="Mature" alternative="30F6010A" memory_technology="FLASH" architecture="30F" id="0x0188" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="7.5" vdd_min="2.5"  vdd_max="5.5" />
+    <frequency start="7.5" end="15"  vdd_min="3"    vdd_max="5.5" />
+    <frequency start="15"  end="30"  vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="10" vdd_min="3"    vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x017FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FF000" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC30F" bvalue="0xC30F" cmask="0xC10F" >
+    <mask name="FPR"   value="0x000F" >
+      <value value="0x0000" name="XTL"          cname="XTL"        />
+      <value value="0x0001" name="XTL"          cname="XTL"        />
+      <value value="0x0002" name="HS"           cname="HS"         />
+      <value value="0x0003" name="HS"           cname="HS"         />
+      <value value="0x0004" name="XT"           cname="XT"         />
+      <value value="0x0005" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0006" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0007" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x0008" name="EXTRC_IO"     cname="ERCIO"      />
+      <value value="0x0009" name="EXTRC_CLKOUT" cname="ERC"        />
+      <value value="0x000A" name="invalid" />
+      <value value="0x000B" name="EC_CLKOUT"    cname="EC"         />
+      <value value="0x000C" name="EC_IO"        cname="ECIO"       />
+      <value value="0x000D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x000E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x000F" name="EC16"         cname="ECIO_PLL16" />
+    </mask>
+    <mask name="FOS"   value="0x0300" >
+      <value value="0x0000" name="TMR1"     cname="EXT" />
+      <value value="0x0100" name="INTRC_F"  cname="FRC" />
+      <value value="0x0200" name="INTRC_LP" cname="LP"  />
+      <value value="0x0300" name="PRIM"     cname="_"    />
+    </mask>
+    <mask name="FCKSM" value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x87B3" >
+    <mask name="FPWRT"  value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"   value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN"  value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="LPOL"   value="0x0100" >
+      <value value="0x0000" name="low"  cname="PWMxL_ACT_LO" />
+      <value value="0x0100" name="high" cname="PWMxL_ACT_HI" />
+    </mask>
+    <mask name="HPOL"   value="0x0200" >
+      <value value="0x0000" name="low"  cname="PWMxH_ACT_LO" />
+      <value value="0x0200" name="high" cname="PWMxH_ACT_HI" />
+    </mask>
+    <mask name="PWMPIN" value="0x0400" >
+      <value value="0x0000" name="On"  cname="RST_PWMPIN" />
+      <value value="0x0400" name="Off" cname="RST_IO"     />
+    </mask>
+    <mask name="MCLRE"  value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F6010A.xml b/src/devices/pic/xml_data/30F6010A.xml
new file mode 100644
index 0000000..2f5e976
--- /dev/null
+++ b/src/devices/pic/xml_data/30F6010A.xml
@@ -0,0 +1,308 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F6010A" document="025842" status="IP" memory_technology="FLASH" architecture="30F" id="0x0281" >
+
+<!--* Checksums ************************************************************-->
+<!--  <checksums>
+    <checksum protected="Off"           bchecksum="0xC406" cchecksum="0xC208" />
+    <checksum protected="High Securiry" bchecksum="0x0404" cchecksum="0x0404" />
+  </checksums>
+-->
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x017FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FF000" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" cmask="0xC10F">
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"        />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x87B3" >
+    <mask name="FPWRT"  value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"   value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN"  value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="LPOL"   value="0x0100" >
+      <value value="0x0000" name="low"  cname="PWMxL_ACT_LO" />
+      <value value="0x0100" name="high" cname="PWMxL_ACT_HI" />
+    </mask>
+    <mask name="HPOL"   value="0x0200" >
+      <value value="0x0000" name="low"  cname="PWMxH_ACT_LO" />
+      <value value="0x0200" name="high" cname="PWMxH_ACT_HI" />
+    </mask>
+    <mask name="PWMPIN" value="0x0400" >
+      <value value="0x0000" name="On"  cname="RST_PWMPIN" />
+      <value value="0x0400" name="Off" cname="RST_IOPIN"  />
+    </mask>
+    <mask name="MCLRE"  value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FBS"       wmask="0x310F" bvalue="0x310F" >
+    <mask name="WRTBS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_BOOT_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_BOOT_OFF" />
+    </mask>
+    <mask name="BSSEC" value="0x0008" >
+      <value value="0x0000" name="High Security"     cname="" />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="BSSIZ"  value="0x0006" >
+      <value value="0x0000" name="4096" cname=""  />
+      <value value="0x0002" name="2048" cname="" />
+      <value value="0x0004" name="512"  cname="" />
+      <value value="0x0006" name="0"    cname="" />
+    </mask>
+    <mask name="EBSSIZ" value="0x0100" >
+      <value value="0x0000" name="256" cname="SMALL_BOOT_EEPROM" />
+      <value value="0x0100" name="0"   cname="NO_BOOT_EEPROM" />
+    </mask>
+    <mask name="RBSSIZ"  value="0x3000" >
+      <value value="0x0000" name="1024" cname="LAR_BOOT_RAM"  />
+      <value value="0x1000" name="256" cname="MED_BOOT_RAM" />
+      <value value="0x2000" name="128" cname="SMALL_BOOT_RAM" />
+      <value value="0x3000" name="0"   cname="NO_BOOT_RAM" />
+    </mask>
+  </config>
+  
+  <config offset="0x8" name="FSS"       wmask="0x330F" bvalue="0x330F" >
+    <mask name="WRTSS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_SEC_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_SEC_OFF" />
+    </mask>
+    <mask name="SSSEC"  value="0x0008" >
+      <value value="0x0000" name="High Security"     cname=""  />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="SSSIZ"  value="0x0006" >
+      <value value="0x0000" name="16384" cname=""  />
+      <value value="0x0002" name="8192"  cname="" />
+      <value value="0x0004" name="4096"  cname="" />
+      <value value="0x0006" name="0"     cname="" />
+    </mask>
+    <mask name="ESSSIZ" value="0x0300" >
+      <value value="0x0000" name="1024" cname="LAR_SEC_EEPROM" />
+      <value value="0x0100" name="512" cname="MED_SEC_EEPROM" />
+      <value value="0x0200" name="256" cname="SMALL_SEC_EEPROM" />
+      <value value="0x0300" name="0"   cname="NO_SEC_EEPROM" />
+    </mask>
+    <mask name="RSSSIZ"  value="0x3000" >
+      <value value="0x0000" name="4096" cname="LAR_SEC_RAM"  />
+      <value value="0x1000" name="2048" cname="MED_SEC_RAM" />
+      <value value="0x2000" name="256" cname="SMALL_SEC_RAM" />
+      <value value="0x3000" name="0"   cname="NO_SEC_RAM" />
+    </mask>
+  </config>
+  
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0007" >
+    <mask name="WRTGS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_GEN_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_GEN_OFF" />
+    </mask>
+    <mask name="GSSEC"  value="0x0006" >
+      <value value="default" name="High Security"     cname="HIGH_PROT"  />
+      <value value="0x0004" name="Standard Security" cname="STAND_PROT" />
+      <value value="0x0006" name="Off"               cname="GEN_PROT"  />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F6011.xml b/src/devices/pic/xml_data/30F6011.xml
new file mode 100644
index 0000000..60e6f5f
--- /dev/null
+++ b/src/devices/pic/xml_data/30F6011.xml
@@ -0,0 +1,224 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F6011" document="010331" status="Mature" alternative="30F6011A" memory_technology="FLASH" architecture="30F" id="0x0192" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="7.5" vdd_min="2.5"  vdd_max="5.5" />
+    <frequency start="7.5" end="15"  vdd_min="3"    vdd_max="5.5" />
+    <frequency start="15"  end="30"  vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="10" vdd_min="3"    vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x015FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FF800" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x8005BF" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC30F" bvalue="0xC30F" cmask="0xC10F" >
+    <mask name="FPR"   value="0x000F" >
+      <value value="0x0000" name="XTL"          cname="XTL"        />
+      <value value="0x0001" name="XTL"          cname="XTL"        />
+      <value value="0x0002" name="HS"           cname="HS"         />
+      <value value="0x0003" name="HS"           cname="HS"         />
+      <value value="0x0004" name="XT"           cname="XT"         />
+      <value value="0x0005" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0006" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0007" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x0008" name="EXTRC_IO"     cname="ERCIO"      />
+      <value value="0x0009" name="EXTRC_CLKOUT" cname="ERC"        />
+      <value value="0x000A" name="invalid" />
+      <value value="0x000B" name="EC_CLKOUT"    cname="EC"         />
+      <value value="0x000C" name="EC_IO"        cname="ECIO"       />
+      <value value="0x000D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x000E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x000F" name="EC16"         cname="ECIO_PLL16" />
+    </mask>
+    <mask name="FOS"   value="0x0300" >
+      <value value="0x0000" name="TMR1"     cname="EXT" />
+      <value value="0x0100" name="INTRC_F"  cname="FRC" />
+      <value value="0x0200" name="INTRC_LP" cname="LP"  />
+      <value value="0x0300" name="PRIM"     cname="_"    />
+    </mask>
+    <mask name="FCKSM" value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F6011A.xml b/src/devices/pic/xml_data/30F6011A.xml
new file mode 100644
index 0000000..bb499b1
--- /dev/null
+++ b/src/devices/pic/xml_data/30F6011A.xml
@@ -0,0 +1,273 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F6011A" document="024762" status="IP" memory_technology="FLASH" architecture="30F" id="0x02C0" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x015FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FF800" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"        />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FBS"       wmask="0x310F" bvalue="0x310F" >
+    <mask name="WRTBS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_BOOT_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_BOOT_OFF" />
+    </mask>
+    <mask name="BSSEC" value="0x0008" >
+      <value value="0x0000" name="High Security"     cname="" />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="BSSIZ"  value="0x0006" >
+      <value value="0x0000" name="4096" cname=""  />
+      <value value="0x0002" name="2048" cname="" />
+      <value value="0x0004" name="512"  cname="" />
+      <value value="0x0006" name="0"    cname="" />
+    </mask>
+    <mask name="EBSSIZ" value="0x0100" >
+      <value value="0x0000" name="256" cname="SMALL_BOOT_EEPROM" />
+      <value value="0x0100" name="0"   cname="NO_BOOT_EEPROM" />
+    </mask>
+    <mask name="RBSSIZ"  value="0x3000" >
+      <value value="0x0000" name="1024" cname="LAR_BOOT_RAM"  />
+      <value value="0x1000" name="256" cname="MED_BOOT_RAM" />
+      <value value="0x2000" name="128" cname="SMALL_BOOT_RAM" />
+      <value value="0x3000" name="0"   cname="NO_BOOT_RAM" />
+    </mask>
+  </config>
+  
+  <config offset="0x8" name="FSS"       wmask="0x330F" bvalue="0x330F" >
+    <mask name="WRTSS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_SEC_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_SEC_OFF" />
+    </mask>
+    <mask name="SSSEC"  value="0x0008" >
+      <value value="0x0000" name="High Security"     cname=""  />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="SSSIZ"  value="0x0006" >
+      <value value="0x0000" name="16384" cname=""  />
+      <value value="0x0002" name="8192"  cname="" />
+      <value value="0x0004" name="4096"  cname="" />
+      <value value="0x0006" name="0"     cname="" />
+    </mask>
+    <mask name="ESSSIZ" value="0x0300" >
+      <value value="0x0000" name="1024" cname="LAR_SEC_EEPROM" />
+      <value value="0x0100" name="512" cname="MED_SEC_EEPROM" />
+      <value value="0x0200" name="256" cname="SMALL_SEC_EEPROM" />
+      <value value="0x0300" name="0"   cname="NO_SEC_EEPROM" />
+    </mask>
+    <mask name="RSSSIZ"  value="0x3000" >
+      <value value="0x0000" name="4096" cname="LAR_SEC_RAM"  />
+      <value value="0x1000" name="2048" cname="MED_SEC_RAM" />
+      <value value="0x2000" name="256" cname="SMALL_SEC_RAM" />
+      <value value="0x3000" name="0"   cname="NO_SEC_RAM" />
+    </mask>
+  </config>
+  
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0007" >
+    <mask name="WRTGS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_GEN_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_GEN_OFF" />
+    </mask>
+    <mask name="GSSEC"  value="0x0006" >
+      <value value="default" name="High Security"     cname="HIGH_PROT"  />
+      <value value="0x0004" name="Standard Security" cname="STAND_PROT" />
+      <value value="0x0006" name="Off"               cname="GEN_PROT"  />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F6012.xml b/src/devices/pic/xml_data/30F6012.xml
new file mode 100644
index 0000000..e7c1797
--- /dev/null
+++ b/src/devices/pic/xml_data/30F6012.xml
@@ -0,0 +1,224 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F6012" document="010332" status="Mature" alternative="30F6012A" memory_technology="FLASH" architecture="30F" id="0x0193" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="7.5" vdd_min="2.5"  vdd_max="5.5" />
+    <frequency start="7.5" end="15"  vdd_min="3"    vdd_max="5.5" />
+    <frequency start="15"  end="30"  vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="10" vdd_min="3"    vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x017FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FF000" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC30F" bvalue="0xC30F" cmask="0xC10F" >
+    <mask name="FPR"   value="0x000F" >
+      <value value="0x0000" name="XTL"          cname="XTL"        />
+      <value value="0x0001" name="XTL"          cname="XTL"        />
+      <value value="0x0002" name="HS"           cname="HS"         />
+      <value value="0x0003" name="HS"           cname="HS"         />
+      <value value="0x0004" name="XT"           cname="XT"         />
+      <value value="0x0005" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0006" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0007" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x0008" name="EXTRC_IO"     cname="ERCIO"      />
+      <value value="0x0009" name="EXTRC_CLKOUT" cname="ERC"        />
+      <value value="0x000A" name="invalid" />
+      <value value="0x000B" name="EC_CLKOUT"    cname="EC"         />
+      <value value="0x000C" name="EC_IO"        cname="ECIO"       />
+      <value value="0x000D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x000E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x000F" name="EC16"         cname="ECIO_PLL16" />
+    </mask>
+    <mask name="FOS"   value="0x0300" >
+      <value value="0x0000" name="TMR1"     cname="EXT" />
+      <value value="0x0100" name="INTRC_F"  cname="FRC" />
+      <value value="0x0200" name="INTRC_LP" cname="LP"  />
+      <value value="0x0300" name="PRIM"     cname="_"    />
+    </mask>
+    <mask name="FCKSM" value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F6012A.xml b/src/devices/pic/xml_data/30F6012A.xml
new file mode 100644
index 0000000..6dd84fb
--- /dev/null
+++ b/src/devices/pic/xml_data/30F6012A.xml
@@ -0,0 +1,273 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F6012A" document="024764" status="IP" memory_technology="FLASH" architecture="30F" id="0x02C2" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x017FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FF000" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"        />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FBS"       wmask="0x310F" bvalue="0x310F" >
+    <mask name="WRTBS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_BOOT_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_BOOT_OFF" />
+    </mask>
+    <mask name="BSSEC" value="0x0008" >
+      <value value="0x0000" name="High Security"     cname="" />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="BSSIZ"  value="0x0006" >
+      <value value="0x0000" name="4096" cname=""  />
+      <value value="0x0002" name="2048" cname="" />
+      <value value="0x0004" name="512"  cname="" />
+      <value value="0x0006" name="0"    cname="" />
+    </mask>
+    <mask name="EBSSIZ" value="0x0100" >
+      <value value="0x0000" name="256" cname="SMALL_BOOT_EEPROM" />
+      <value value="0x0100" name="0"   cname="NO_BOOT_EEPROM" />
+    </mask>
+    <mask name="RBSSIZ"  value="0x3000" >
+      <value value="0x0000" name="1024" cname="LAR_BOOT_RAM"  />
+      <value value="0x1000" name="256" cname="MED_BOOT_RAM" />
+      <value value="0x2000" name="128" cname="SMALL_BOOT_RAM" />
+      <value value="0x3000" name="0"   cname="NO_BOOT_RAM" />
+    </mask>
+  </config>
+  
+  <config offset="0x8" name="FSS"       wmask="0x330F" bvalue="0x330F" >
+    <mask name="WRTSS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_SEC_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_SEC_OFF" />
+    </mask>
+    <mask name="SSSEC"  value="0x0008" >
+      <value value="0x0000" name="High Security"     cname=""  />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="SSSIZ"  value="0x0006" >
+      <value value="0x0000" name="16384" cname=""  />
+      <value value="0x0002" name="8192"  cname="" />
+      <value value="0x0004" name="4096"  cname="" />
+      <value value="0x0006" name="0"     cname="" />
+    </mask>
+    <mask name="ESSSIZ" value="0x0300" >
+      <value value="0x0000" name="1024" cname="LAR_SEC_EEPROM" />
+      <value value="0x0100" name="512" cname="MED_SEC_EEPROM" />
+      <value value="0x0200" name="256" cname="SMALL_SEC_EEPROM" />
+      <value value="0x0300" name="0"   cname="NO_SEC_EEPROM" />
+    </mask>
+    <mask name="RSSSIZ"  value="0x3000" >
+      <value value="0x0000" name="4096" cname="LAR_SEC_RAM"  />
+      <value value="0x1000" name="2048" cname="MED_SEC_RAM" />
+      <value value="0x2000" name="256" cname="SMALL_SEC_RAM" />
+      <value value="0x3000" name="0"   cname="NO_SEC_RAM" />
+    </mask>
+  </config>
+  
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0007" >
+    <mask name="WRTGS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_GEN_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_GEN_OFF" />
+    </mask>
+    <mask name="GSSEC"  value="0x0006" >
+      <value value="default" name="High Security"     cname="HIGH_PROT"  />
+      <value value="0x0004" name="Standard Security" cname="STAND_PROT" />
+      <value value="0x0006" name="Off"               cname="GEN_PROT"  />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F6013.xml b/src/devices/pic/xml_data/30F6013.xml
new file mode 100644
index 0000000..34b66cf
--- /dev/null
+++ b/src/devices/pic/xml_data/30F6013.xml
@@ -0,0 +1,240 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F6013" document="010333" status="Mature" alternative="30F6013A" memory_technology="FLASH" architecture="30F" id="0x0197" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="7.5" vdd_min="2.5"  vdd_max="5.5" />
+    <frequency start="7.5" end="15"  vdd_min="3"    vdd_max="5.5" />
+    <frequency start="15"  end="30"  vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="10" vdd_min="3"    vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x015FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FF800" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC30F" bvalue="0xC30F" cmask="0xC10F" >
+    <mask name="FPR"   value="0x000F" >
+      <value value="0x0000" name="XTL"          cname="XTL"        />
+      <value value="0x0001" name="XTL"          cname="XTL"        />
+      <value value="0x0002" name="HS"           cname="HS"         />
+      <value value="0x0003" name="HS"           cname="HS"         />
+      <value value="0x0004" name="XT"           cname="XT"         />
+      <value value="0x0005" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0006" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0007" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x0008" name="EXTRC_IO"     cname="ERCIO"      />
+      <value value="0x0009" name="EXTRC_CLKOUT" cname="ERC"        />
+      <value value="0x000A" name="invalid" />
+      <value value="0x000B" name="EC_CLKOUT"    cname="EC"         />
+      <value value="0x000C" name="EC_IO"        cname="ECIO"       />
+      <value value="0x000D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x000E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x000F" name="EC16"         cname="ECIO_PLL16" />
+    </mask>
+    <mask name="FOS"   value="0x0300" >
+      <value value="0x0000" name="TMR1"     cname="EXT" />
+      <value value="0x0100" name="INTRC_F"  cname="FRC" />
+      <value value="0x0200" name="INTRC_LP" cname="LP"  />
+      <value value="0x0300" name="PRIM"     cname="_"    />
+    </mask>
+    <mask name="FCKSM" value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F6013A.xml b/src/devices/pic/xml_data/30F6013A.xml
new file mode 100644
index 0000000..e0a5758
--- /dev/null
+++ b/src/devices/pic/xml_data/30F6013A.xml
@@ -0,0 +1,289 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F6013A" document="024765" status="IP" memory_technology="FLASH" architecture="30F" id="0x02C1" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x015FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FF800" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"        />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FBS"       wmask="0x310F" bvalue="0x310F" >
+    <mask name="WRTBS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_BOOT_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_BOOT_OFF" />
+    </mask>
+    <mask name="BSSEC" value="0x0008" >
+      <value value="0x0000" name="High Security"     cname="" />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="BSSIZ"  value="0x0006" >
+      <value value="0x0000" name="4096" cname=""  />
+      <value value="0x0002" name="2048" cname="" />
+      <value value="0x0004" name="512"  cname="" />
+      <value value="0x0006" name="0"    cname="" />
+    </mask>
+    <mask name="EBSSIZ" value="0x0100" >
+      <value value="0x0000" name="256" cname="SMALL_BOOT_EEPROM" />
+      <value value="0x0100" name="0"   cname="NO_BOOT_EEPROM" />
+    </mask>
+    <mask name="RBSSIZ"  value="0x3000" >
+      <value value="0x0000" name="1024" cname="LAR_BOOT_RAM"  />
+      <value value="0x1000" name="256" cname="MED_BOOT_RAM" />
+      <value value="0x2000" name="128" cname="SMALL_BOOT_RAM" />
+      <value value="0x3000" name="0"   cname="NO_BOOT_RAM" />
+    </mask>
+  </config>
+  
+  <config offset="0x8" name="FSS"       wmask="0x330F" bvalue="0x330F" >
+    <mask name="WRTSS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_SEC_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_SEC_OFF" />
+    </mask>
+    <mask name="SSSEC"  value="0x0008" >
+      <value value="0x0000" name="High Security"     cname=""  />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="SSSIZ"  value="0x0006" >
+      <value value="0x0000" name="16384" cname=""  />
+      <value value="0x0002" name="8192"  cname="" />
+      <value value="0x0004" name="4096"  cname="" />
+      <value value="0x0006" name="0"     cname="" />
+    </mask>
+    <mask name="ESSSIZ" value="0x0300" >
+      <value value="0x0000" name="1024" cname="LAR_SEC_EEPROM" />
+      <value value="0x0100" name="512" cname="MED_SEC_EEPROM" />
+      <value value="0x0200" name="256" cname="SMALL_SEC_EEPROM" />
+      <value value="0x0300" name="0"   cname="NO_SEC_EEPROM" />
+    </mask>
+    <mask name="RSSSIZ"  value="0x3000" >
+      <value value="0x0000" name="4096" cname="LAR_SEC_RAM"  />
+      <value value="0x1000" name="2048" cname="MED_SEC_RAM" />
+      <value value="0x2000" name="256" cname="SMALL_SEC_RAM" />
+      <value value="0x3000" name="0"   cname="NO_SEC_RAM" />
+    </mask>
+  </config>
+  
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0007" >
+    <mask name="WRTGS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_GEN_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_GEN_OFF" />
+    </mask>
+    <mask name="GSSEC"  value="0x0006" >
+      <value value="default" name="High Security"     cname="HIGH_PROT"  />
+      <value value="0x0004" name="Standard Security" cname="STAND_PROT" />
+      <value value="0x0006" name="Off"               cname="GEN_PROT"  />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F6014.xml b/src/devices/pic/xml_data/30F6014.xml
new file mode 100644
index 0000000..8cf7766
--- /dev/null
+++ b/src/devices/pic/xml_data/30F6014.xml
@@ -0,0 +1,240 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F6014" document="010334" status="Mature" alternative="30F6014A" memory_technology="FLASH" architecture="30F" id="0x0198" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"   end="7.5" vdd_min="2.5"  vdd_max="5.5" />
+    <frequency start="7.5" end="15"  vdd_min="3"    vdd_max="5.5" />
+    <frequency start="15"  end="30"  vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="10" vdd_min="3"    vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="4.75" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x017FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FF000" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC30F" bvalue="0xC30F" cmask="0xC10F" >
+    <mask name="FPR"   value="0x000F" >
+      <value value="0x0000" name="XTL"          cname="XTL"        />
+      <value value="0x0001" name="XTL"          cname="XTL"        />
+      <value value="0x0002" name="HS"           cname="HS"         />
+      <value value="0x0003" name="HS"           cname="HS"         />
+      <value value="0x0004" name="XT"           cname="XT"         />
+      <value value="0x0005" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0006" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0007" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x0008" name="EXTRC_IO"     cname="ERCIO"      />
+      <value value="0x0009" name="EXTRC_CLKOUT" cname="ERC"        />
+      <value value="0x000A" name="invalid" />
+      <value value="0x000B" name="EC_CLKOUT"    cname="EC"         />
+      <value value="0x000C" name="EC_IO"        cname="ECIO"       />
+      <value value="0x000D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x000E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x000F" name="EC16"         cname="ECIO_PLL16" />
+    </mask>
+    <mask name="FOS"   value="0x0300" >
+      <value value="0x0000" name="TMR1"     cname="EXT" />
+      <value value="0x0100" name="INTRC_F"  cname="FRC" />
+      <value value="0x0200" name="INTRC_LP" cname="LP"  />
+      <value value="0x0300" name="PRIM"     cname="_"    />
+    </mask>
+    <mask name="FCKSM" value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="RESERVED1" wmask="0x310F" bvalue="0x0000" cmask="0x310F" />
+
+  <config offset="0x8" name="RESERVED2" wmask="0x330F" bvalue="0x0000" cmask="0x330F" />
+
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0003" cmask="0x0007" >
+    <mask name="GWRP" value="0x0001" >
+      <value value="0x0000" name="All" cname="0xFFFE" />
+      <value value="0x0001" name="Off" cname="_" />
+    </mask>
+    <mask name="GCP"  value="0x0002" >
+      <value value="0x0000" name="All" cname="CODE_PROT_ON"  />
+      <value value="0x0002" name="Off" cname="CODE_PROT_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F6014A.xml b/src/devices/pic/xml_data/30F6014A.xml
new file mode 100644
index 0000000..c6a6efe
--- /dev/null
+++ b/src/devices/pic/xml_data/30F6014A.xml
@@ -0,0 +1,289 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F6014A" document="024766" status="IP" memory_technology="FLASH" architecture="30F" id="0x02C3" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x017FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FF000" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"        />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x80B3" cmask="0x87B3" >
+    <mask name="FPWRT" value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"  value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN" value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="MCLRE" value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FBS"       wmask="0x310F" bvalue="0x310F" >
+    <mask name="WRTBS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_BOOT_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_BOOT_OFF" />
+    </mask>
+    <mask name="BSSEC" value="0x0008" >
+      <value value="0x0000" name="High Security"     cname="" />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="BSSIZ"  value="0x0006" >
+      <value value="0x0000" name="4096" cname=""  />
+      <value value="0x0002" name="2048" cname="" />
+      <value value="0x0004" name="512"  cname="" />
+      <value value="0x0006" name="0"    cname="" />
+    </mask>
+    <mask name="EBSSIZ" value="0x0100" >
+      <value value="0x0000" name="256" cname="SMALL_BOOT_EEPROM" />
+      <value value="0x0100" name="0"   cname="NO_BOOT_EEPROM" />
+    </mask>
+    <mask name="RBSSIZ"  value="0x3000" >
+      <value value="0x0000" name="1024" cname="LAR_BOOT_RAM"  />
+      <value value="0x1000" name="256" cname="MED_BOOT_RAM" />
+      <value value="0x2000" name="128" cname="SMALL_BOOT_RAM" />
+      <value value="0x3000" name="0"   cname="NO_BOOT_RAM" />
+    </mask>
+  </config>
+  
+  <config offset="0x8" name="FSS"       wmask="0x330F" bvalue="0x330F" >
+    <mask name="WRTSS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_SEC_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_SEC_OFF" />
+    </mask>
+    <mask name="SSSEC"  value="0x0008" >
+      <value value="0x0000" name="High Security"     cname=""  />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="SSSIZ"  value="0x0006" >
+      <value value="0x0000" name="16384" cname=""  />
+      <value value="0x0002" name="8192"  cname="" />
+      <value value="0x0004" name="4096"  cname="" />
+      <value value="0x0006" name="0"     cname="" />
+    </mask>
+    <mask name="ESSSIZ" value="0x0300" >
+      <value value="0x0000" name="1024" cname="LAR_SEC_EEPROM" />
+      <value value="0x0100" name="512" cname="MED_SEC_EEPROM" />
+      <value value="0x0200" name="256" cname="SMALL_SEC_EEPROM" />
+      <value value="0x0300" name="0"   cname="NO_SEC_EEPROM" />
+    </mask>
+    <mask name="RSSSIZ"  value="0x3000" >
+      <value value="0x0000" name="4096" cname="LAR_SEC_RAM"  />
+      <value value="0x1000" name="2048" cname="MED_SEC_RAM" />
+      <value value="0x2000" name="256" cname="SMALL_SEC_RAM" />
+      <value value="0x3000" name="0"   cname="NO_SEC_RAM" />
+    </mask>
+  </config>
+  
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0007" >
+    <mask name="WRTGS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_GEN_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_GEN_OFF" />
+    </mask>
+    <mask name="GSSEC"  value="0x0006" >
+      <value value="default" name="High Security"     cname="HIGH_PROT"  />
+      <value value="0x0004" name="Standard Security" cname="STAND_PROT" />
+      <value value="0x0006" name="Off"               cname="GEN_PROT"  />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="80" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+    <pin index="65" name="" />
+    <pin index="66" name="" />
+    <pin index="67" name="" />
+    <pin index="68" name="" />
+    <pin index="69" name="" />
+    <pin index="70" name="" />
+    <pin index="71" name="" />
+    <pin index="72" name="" />
+    <pin index="73" name="" />
+    <pin index="74" name="" />
+    <pin index="75" name="" />
+    <pin index="76" name="" />
+    <pin index="77" name="" />
+    <pin index="78" name="" />
+    <pin index="79" name="" />
+    <pin index="80" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/30F6015.xml b/src/devices/pic/xml_data/30F6015.xml
new file mode 100644
index 0000000..784f38d
--- /dev/null
+++ b/src/devices/pic/xml_data/30F6015.xml
@@ -0,0 +1,285 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="30F6015" document="025864" status="IP" memory_technology="FLASH" architecture="30F" id="0x0280" >
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0"  end="10" vdd_min="2.5" vdd_max="5.5" />
+    <frequency start="10" end="20" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="20" end="30" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0"  end="15" vdd_min="3"   vdd_max="5.5" />
+    <frequency start="15" end="20" vdd_min="4.5" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"      min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog" min="4.5" max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"           start="0x000000" end="0x017FFF" />
+  <memory name="device_id"         start="0xFF0000" end="0xFF0004" />
+  <memory name="config"            start="0xF80000" end="0xF8000D" />
+  <memory name="eeprom"            start="0x7FF000" end="0x7FFFFF" />
+  <memory name="user_ids"          start="0x8005C0" end="0x8005FF" rmask="0xFFFFFF" />
+  <memory name="debug_vector"      start="0x800000" end="0x800007" />
+  <memory name="program_executive" start="0x800000" end="0x80053F" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="FOSC"      wmask="0xC71F" bvalue="0xC71F" >
+    <mask name="FOSFPR" value="0x071F" >
+      <value value="default" name="invalid" />
+      <value value="0x001F" name="TMR1"         cname="LP"        />
+      <value value="0x011F" name="INTRC_F"      cname="FRC"        />
+      <value value="0x021F" name="INTRC_LP"     cname="LPRC"       />
+      <value value="0x0701" name="FRC4"         cname="FRC_PLL4"   />
+      <value value="0x0703" name="FRC16"        cname="FRC_PLL16"  />
+      <value value="0x0705" name="XT4"          cname="XT_PLL4"    />
+      <value value="0x0706" name="XT8"          cname="XT_PLL8"    />
+      <value value="0x0707" name="XT16"         cname="XT_PLL16"   />
+      <value value="0x070A" name="FRC8"         cname="FRC_PLL8"   />
+      <value value="0x070D" name="EC4"          cname="ECIO_PLL4"  />
+      <value value="0x070E" name="EC8"          cname="ECIO_PLL8"  />
+      <value value="0x070F" name="EC16"         cname="ECIO_PLL16" />
+      <value value="0x0711" name="HS2_4"        cname="HS2_PLL4"   />
+      <value value="0x0712" name="HS2_8"        cname="HS2_PLL8"   />
+      <value value="0x0713" name="HS2_16"       cname="HS2_PLL16"  />
+      <value value="0x0715" name="HS3_4"        cname="HS3_PLL4"   />
+      <value value="0x0716" name="HS3_8"        cname="HS3_PLL8"   />
+      <value value="0x0717" name="HS3_16"       cname="HS3_PLL16"  />
+    </mask>
+    <mask name="FCKSM"  value="0xC000" >
+      <value value="0x0000" name="Switching on, monitor on"   cname="CSW_FSCM_ON"     />
+      <value value="0x4000" name="Switching on, monitor off"  cname="CSW_ON_FSCM_OFF" />
+      <value value="0x8000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+      <value value="0xC000" name="Switching off, monitor off" cname="CSW_FSCM_OFF"    />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="FWDT"      wmask="0x803F" bvalue="0x803F" >
+    <mask name="FWPSB"  value="0x000F" >
+      <value value="0x0000" name="1:1"  cname="WDTPSB_1"  />
+      <value value="0x0001" name="1:2"  cname="WDTPSB_2"  />
+      <value value="0x0002" name="1:3"  cname="WDTPSB_3"  />
+      <value value="0x0003" name="1:4"  cname="WDTPSB_4"  />
+      <value value="0x0004" name="1:5"  cname="WDTPSB_5"  />
+      <value value="0x0005" name="1:6"  cname="WDTPSB_6"  />
+      <value value="0x0006" name="1:7"  cname="WDTPSB_7"  />
+      <value value="0x0007" name="1:8"  cname="WDTPSB_8"  />
+      <value value="0x0008" name="1:9"  cname="WDTPSB_9"  />
+      <value value="0x0009" name="1:10" cname="WDTPSB_10" />
+      <value value="0x000A" name="1:11" cname="WDTPSB_11" />
+      <value value="0x000B" name="1:12" cname="WDTPSB_12" />
+      <value value="0x000C" name="1:13" cname="WDTPSB_13" />
+      <value value="0x000D" name="1:14" cname="WDTPSB_14" />
+      <value value="0x000E" name="1:15" cname="WDTPSB_15" />
+      <value value="0x000F" name="1:16" cname="WDTPSB_16" />
+    </mask>
+    <mask name="FWPSA"  value="0x0030" >
+      <value value="0x0000" name="1:1"   cname="WDTPSA_1"   />
+      <value value="0x0010" name="1:8"   cname="WDTPSA_8"   />
+      <value value="0x0020" name="1:64"  cname="WDTPSA_64"  />
+      <value value="0x0030" name="1:512" cname="WDTPSA_512" />
+    </mask>
+    <mask name="FWDTEN" value="0x8000" >
+      <value value="0x0000" name="Off" cname="WDT_OFF" />
+      <value value="0x8000" name="On"  cname="WDT_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="FBORPOR"   wmask="0x87B3" bvalue="0x87B3" >
+    <mask name="FPWRT"  value="0x0003" >
+      <value value="0x0000" name="0"  cname="PWRT_OFF" />
+      <value value="0x0001" name="4"  cname="PWRT_4"   />
+      <value value="0x0002" name="16" cname="PWRT_16"  />
+      <value value="0x0003" name="64" cname="PWRT_64"  />
+    </mask>
+    <mask name="BORV"   value="0x0030" >
+      <value value="0x0000" name="4.5" cname="BORV_45" />
+      <value value="0x0010" name="4.2" cname="BORV_42" />
+      <value value="0x0020" name="2.7" cname="BORV_27" />
+      <value value="0x0030" name="2.0" cname="BORV_20" />
+    </mask>
+    <mask name="BODEN"  value="0x0080" >
+      <value value="0x0000" name="Off" cname="PBOR_OFF" />
+      <value value="0x0080" name="On"  cname="PBOR_ON"  />
+    </mask>
+    <mask name="LPOL"   value="0x0100" >
+      <value value="0x0000" name="low"  cname="PWMxL_ACT_LO" />
+      <value value="0x0100" name="high" cname="PWMxL_ACT_HI" />
+    </mask>
+    <mask name="HPOL"   value="0x0200" >
+      <value value="0x0000" name="low"  cname="PWMxH_ACT_LO" />
+      <value value="0x0200" name="high" cname="PWMxH_ACT_HI" />
+    </mask>
+    <mask name="PWMPIN" value="0x0400" >
+      <value value="0x0000" name="On"  cname="RST_PWMPIN" />
+      <value value="0x0400" name="Off" cname="RST_IOPIN"  />
+    </mask>
+    <mask name="MCLRE"  value="0x8000" >
+      <value value="0x0000" name="Internal" cname="MCLR_DIS" />
+      <value value="0x8000" name="External" cname="MCLR_EN"  />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="FBS"       wmask="0x310F" bvalue="0x310F" >
+    <mask name="WRTBS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_BOOT_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_BOOT_OFF" />
+    </mask>
+    <mask name="BSSEC" value="0x0008" >
+      <value value="0x0000" name="High Security"     cname="" />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="BSSIZ"  value="0x0006" >
+      <value value="0x0000" name="4096" cname=""  />
+      <value value="0x0002" name="2048" cname="" />
+      <value value="0x0004" name="512"  cname="" />
+      <value value="0x0006" name="0"    cname="" />
+    </mask>
+    <mask name="EBSSIZ" value="0x0100" >
+      <value value="0x0000" name="256" cname="SMALL_BOOT_EEPROM" />
+      <value value="0x0100" name="0"   cname="NO_BOOT_EEPROM" />
+    </mask>
+    <mask name="RBSSIZ"  value="0x3000" >
+      <value value="0x0000" name="1024" cname="LAR_BOOT_RAM"  />
+      <value value="0x1000" name="256" cname="MED_BOOT_RAM" />
+      <value value="0x2000" name="128" cname="SMALL_BOOT_RAM" />
+      <value value="0x3000" name="0"   cname="NO_BOOT_RAM" />
+    </mask>
+  </config>
+  
+  <config offset="0x8" name="FSS"       wmask="0x330F" bvalue="0x330F" >
+    <mask name="WRTSS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_SEC_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_SEC_OFF" />
+    </mask>
+    <mask name="SSSEC"  value="0x0008" >
+      <value value="0x0000" name="High Security"     cname=""  />
+      <value value="0x0008" name="Standard Security" cname="" />
+    </mask>
+    <mask name="SSSIZ"  value="0x0006" >
+      <value value="0x0000" name="16384" cname=""  />
+      <value value="0x0002" name="8192"  cname="" />
+      <value value="0x0004" name="4096"  cname="" />
+      <value value="0x0006" name="0"     cname="" />
+    </mask>
+    <mask name="ESSSIZ" value="0x0300" >
+      <value value="0x0000" name="1024" cname="LAR_SEC_EEPROM" />
+      <value value="0x0100" name="512" cname="MED_SEC_EEPROM" />
+      <value value="0x0200" name="256" cname="SMALL_SEC_EEPROM" />
+      <value value="0x0300" name="0"   cname="NO_SEC_EEPROM" />
+    </mask>
+    <mask name="RSSSIZ"  value="0x3000" >
+      <value value="0x0000" name="4096" cname="LAR_SEC_RAM"  />
+      <value value="0x1000" name="2048" cname="MED_SEC_RAM" />
+      <value value="0x2000" name="256" cname="SMALL_SEC_RAM" />
+      <value value="0x3000" name="0"   cname="NO_SEC_RAM" />
+    </mask>
+  </config>
+  
+  <config offset="0xA" name="FGS"       wmask="0x0007" bvalue="0x0007" >
+    <mask name="WRTGS" value="0x0001" >
+      <value value="0x0000" name="All" cname="WR_PROT_GEN_ON" />
+      <value value="0x0001" name="Off" cname="WR_PROT_GEN_OFF" />
+    </mask>
+    <mask name="GSSEC"  value="0x0006" >
+      <value value="default" name="High Security"     cname="HIGH_PROT"  />
+      <value value="0x0004" name="Standard Security" cname="STAND_PROT" />
+      <value value="0x0006" name="Off"               cname="GEN_PROT"  />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="ICD"       wmask="0xC003" bvalue="0xC003" >
+    <mask name="ICS"   value="0x0003" >
+      <value value="0x0000" name="EMUC3, EMUD3"       cname="0xFFFC" />
+      <value value="0x0001" name="EMUC2, EMUD2"       cname="0xFFFD" />
+      <value value="0x0002" name="EMUC1, EMUD1"       cname="0xFFFE" />
+      <value value="0x0003" name="PGC/EMUC, PGD/EMUD" cname="_" />
+    </mask>
+    <mask name="COE"   value="0x4000" >
+      <value value="0x0000" name="On"  cname="0xBFFF" />
+      <value value="0x4000" name="Off" cname="_" />
+    </mask>
+    <mask name="DEBUG" value="0x8000" >
+      <value value="0x0000" name="On"  cname="0x7FFF" />
+      <value value="0x8000" name="Off" cname="_" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="tqfp" nb_pins="64" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+    <pin index="29" name="" />
+    <pin index="30" name="" />
+    <pin index="31" name="" />
+    <pin index="32" name="" />
+    <pin index="33" name="" />
+    <pin index="34" name="" />
+    <pin index="35" name="" />
+    <pin index="36" name="" />
+    <pin index="37" name="" />
+    <pin index="38" name="" />
+    <pin index="39" name="" />
+    <pin index="40" name="" />
+    <pin index="41" name="" />
+    <pin index="42" name="" />
+    <pin index="43" name="" />
+    <pin index="44" name="" />
+    <pin index="45" name="" />
+    <pin index="46" name="" />
+    <pin index="47" name="" />
+    <pin index="48" name="" />
+    <pin index="49" name="" />
+    <pin index="50" name="" />
+    <pin index="51" name="" />
+    <pin index="52" name="" />
+    <pin index="53" name="" />
+    <pin index="54" name="" />
+    <pin index="55" name="" />
+    <pin index="56" name="" />
+    <pin index="57" name="" />
+    <pin index="58" name="" />
+    <pin index="59" name="" />
+    <pin index="60" name="" />
+    <pin index="61" name="" />
+    <pin index="62" name="" />
+    <pin index="63" name="" />
+    <pin index="64" name="" />
+  </package>
+
+</device>
diff --git a/src/devices/pic/xml_data/Makefile.am b/src/devices/pic/xml_data/Makefile.am
new file mode 100644
index 0000000..43b13d4
--- /dev/null
+++ b/src/devices/pic/xml_data/Makefile.am
@@ -0,0 +1,12 @@
+INCLUDES = -I$(top_srcdir)/src $(all_includes)
+METASOURCES = AUTO
+
+noinst_LTLIBRARIES = libpicxml.la
+libpicxml_la_SOURCES = pic_data.cpp
+libpicxml_la_DEPENDENCIES = pic_data.cpp
+
+include deps.mak
+noinst_DATA += registers/registers.xml registers/registers_missing.xml
+pic_data.cpp: ../xml/pic_xml_to_data $(noinst_DATA)
+	../xml/pic_xml_to_data
+CLEANFILES = pic_data.cpp
diff --git a/src/devices/pic/xml_data/deps.mak b/src/devices/pic/xml_data/deps.mak
new file mode 100644
index 0000000..ac8dcee
--- /dev/null
+++ b/src/devices/pic/xml_data/deps.mak
@@ -0,0 +1,43 @@
+noinst_DATA = \
+     10F200.xml 10F202.xml 10F204.xml 10F206.xml 10F220.xml 10F222.xml 12C508.xml 12C508A.xml 12C509.xml 12C509A.xml\
+     12C671.xml 12C672.xml 12CE518.xml 12CE519.xml 12CE673.xml 12CE674.xml 12CR509A.xml 12F508.xml 12F509.xml 12F510.xml\
+     12F519.xml 12F609.xml 12F615.xml 12F629.xml 12F635.xml 12F675.xml 12F683.xml 14000.xml 16C432.xml 16C433.xml\
+     16C505.xml 16C52.xml 16C54.xml 16C54A.xml 16C54B.xml 16C54C.xml 16C55.xml 16C554.xml 16C557.xml 16C558.xml\
+     16C55A.xml 16C56.xml 16C56A.xml 16C57.xml 16C57C.xml 16C58A.xml 16C58B.xml 16C61.xml 16C62.xml 16C620.xml\
+     16C620A.xml 16C621.xml 16C621A.xml 16C622.xml 16C622A.xml 16C62A.xml 16C62B.xml 16C63.xml 16C63A.xml 16C64.xml\
+     16C641.xml 16C642.xml 16C64A.xml 16C65.xml 16C65A.xml 16C65B.xml 16C66.xml 16C661.xml 16C662.xml 16C67.xml\
+     16C71.xml 16C710.xml 16C711.xml 16C712.xml 16C715.xml 16C716.xml 16C717.xml 16C72.xml 16C72A.xml 16C73.xml\
+     16C73A.xml 16C73B.xml 16C74.xml 16C745.xml 16C74A.xml 16C74B.xml 16C76.xml 16C765.xml 16C77.xml 16C770.xml\
+     16C771.xml 16C773.xml 16C774.xml 16C781.xml 16C782.xml 16C84.xml 16C923.xml 16C924.xml 16C925.xml 16C926.xml\
+     16CE623.xml 16CE624.xml 16CE625.xml 16CR54A.xml 16CR54B.xml 16CR54C.xml 16CR56A.xml 16CR57B.xml 16CR57C.xml 16CR58A.xml\
+     16CR58B.xml 16CR62.xml 16CR620A.xml 16CR63.xml 16CR64.xml 16CR65.xml 16CR72.xml 16CR73.xml 16CR74.xml 16CR76.xml\
+     16CR77.xml 16CR83.xml 16CR84.xml 16F505.xml 16F506.xml 16F54.xml 16F57.xml 16F59.xml 16F610.xml 16F616.xml\
+     16F627.xml 16F627A.xml 16F628.xml 16F628A.xml 16F630.xml 16F631.xml 16F636.xml 16F639.xml 16F648A.xml 16F676.xml\
+     16F677.xml 16F684.xml 16F685.xml 16F687.xml 16F688.xml 16F689.xml 16F690.xml 16F716.xml 16F72.xml 16F73.xml\
+     16F737.xml 16F74.xml 16F747.xml 16F76.xml 16F767.xml 16F77.xml 16F777.xml 16F785.xml 16F818.xml 16F819.xml\
+     16F83.xml 16F84.xml 16F84A.xml 16F87.xml 16F870.xml 16F871.xml 16F872.xml 16F873.xml 16F873A.xml 16F874.xml\
+     16F874A.xml 16F876.xml 16F876A.xml 16F877.xml 16F877A.xml 16F88.xml 16F882.xml 16F883.xml 16F884.xml 16F886.xml\
+     16F887.xml 16F913.xml 16F914.xml 16F916.xml 16F917.xml 16F946.xml 16HV540.xml 17C42.xml 17C42A.xml 17C43.xml\
+     17C44.xml 17C752.xml 17C756.xml 17C756A.xml 17C762.xml 17C766.xml 17CR42.xml 17CR43.xml 18C242.xml 18C252.xml\
+     18C442.xml 18C452.xml 18C601.xml 18C658.xml 18C801.xml 18C858.xml 18F1220.xml 18F1230.xml 18F1320.xml 18F1330.xml\
+     18F2220.xml 18F2221.xml 18F2320.xml 18F2321.xml 18F2331.xml 18F2410.xml 18F242.xml 18F2420.xml 18F2423.xml 18F2431.xml\
+     18F2439.xml 18F2450.xml 18F2455.xml 18F248.xml 18F2480.xml 18F24J10.xml 18F2510.xml 18F2515.xml 18F252.xml 18F2520.xml\
+     18F2523.xml 18F2525.xml 18F2539.xml 18F2550.xml 18F258.xml 18F2580.xml 18F2585.xml 18F25J10.xml 18F2610.xml 18F2620.xml\
+     18F2680.xml 18F2682.xml 18F2685.xml 18F4220.xml 18F4221.xml 18F4320.xml 18F4321.xml 18F4331.xml 18F4410.xml 18F442.xml\
+     18F4420.xml 18F4423.xml 18F4431.xml 18F4439.xml 18F4450.xml 18F4455.xml 18F448.xml 18F4480.xml 18F44J10.xml 18F4510.xml\
+     18F4515.xml 18F452.xml 18F4520.xml 18F4523.xml 18F4525.xml 18F4539.xml 18F4550.xml 18F458.xml 18F4580.xml 18F4585.xml\
+     18F45J10.xml 18F4610.xml 18F4620.xml 18F4680.xml 18F4682.xml 18F4685.xml 18F6310.xml 18F6390.xml 18F6393.xml 18F63J11.xml\
+     18F63J90.xml 18F6410.xml 18F6490.xml 18F6493.xml 18F64J11.xml 18F64J90.xml 18F6520.xml 18F6525.xml 18F6527.xml 18F6585.xml\
+     18F65J10.xml 18F65J11.xml 18F65J15.xml 18F65J50.xml 18F65J90.xml 18F6620.xml 18F6621.xml 18F6622.xml 18F6627.xml 18F6680.xml\
+     18F66J10.xml 18F66J11.xml 18F66J15.xml 18F66J16.xml 18F66J50.xml 18F66J55.xml 18F66J60.xml 18F66J65.xml 18F6720.xml 18F6722.xml\
+     18F67J10.xml 18F67J11.xml 18F67J50.xml 18F67J60.xml 18F8310.xml 18F8390.xml 18F8393.xml 18F83J11.xml 18F83J90.xml 18F8410.xml\
+     18F8490.xml 18F8493.xml 18F84J11.xml 18F84J90.xml 18F8520.xml 18F8525.xml 18F8527.xml 18F8585.xml 18F85J10.xml 18F85J11.xml\
+     18F85J15.xml 18F85J50.xml 18F85J90.xml 18F8620.xml 18F8621.xml 18F8622.xml 18F8627.xml 18F8680.xml 18F86J10.xml 18F86J11.xml\
+     18F86J15.xml 18F86J16.xml 18F86J50.xml 18F86J55.xml 18F86J60.xml 18F86J65.xml 18F8720.xml 18F8722.xml 18F87J10.xml 18F87J11.xml\
+     18F87J50.xml 18F87J60.xml 18F96J60.xml 18F96J65.xml 18F97J60.xml 24FJ128GA006.xml 24FJ128GA008.xml 24FJ128GA010.xml 24FJ64GA002.xml 24FJ64GA004.xml\
+     24FJ64GA006.xml 24FJ64GA008.xml 24FJ64GA010.xml 24FJ96GA006.xml 24FJ96GA008.xml 24FJ96GA010.xml 24HJ128GP206.xml 24HJ128GP210.xml 24HJ128GP306.xml 24HJ128GP310.xml\
+     24HJ128GP506.xml 24HJ128GP510.xml 24HJ12GP201.xml 24HJ12GP202.xml 24HJ16GP304.xml 24HJ256GP206.xml 24HJ256GP210.xml 24HJ256GP610.xml 24HJ32GP202.xml 24HJ32GP204.xml\
+     24HJ64GP206.xml 24HJ64GP210.xml 24HJ64GP506.xml 24HJ64GP510.xml 30F1010.xml 30F2010.xml 30F2011.xml 30F2012.xml 30F2020.xml 30F2023.xml\
+     30F3010.xml 30F3011.xml 30F3012.xml 30F3013.xml 30F3014.xml 30F4011.xml 30F4012.xml 30F4013.xml 30F5011.xml 30F5013.xml\
+     30F5015.xml 30F5016.xml 30F6010.xml 30F6010A.xml 30F6011.xml 30F6011A.xml 30F6012.xml 30F6012A.xml 30F6013.xml 30F6013A.xml\
+     30F6014.xml 30F6014A.xml 30F6015.xml
diff --git a/src/devices/pic/xml_data/pic.xsd b/src/devices/pic/xml_data/pic.xsd
new file mode 100644
index 0000000..f358f68
--- /dev/null
+++ b/src/devices/pic/xml_data/pic.xsd
@@ -0,0 +1,295 @@
+<?xml version="1.0"?>
+<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema">
+
+<!-- simple types definition -->
+  <xs:simpleType name="hex">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="0x[0-9A-F]+"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <xs:simpleType name="hex4">
+    <xs:restriction base="hex">
+      <xs:length value="6"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="empty">
+    <xs:restriction base="xs:string">
+      <xs:length value="0"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="word">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[A-Za-z]+[A-Za-z0-9]*"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="status">
+    <xs:restriction base="xs:string">
+      <xs:enumeration value="EOL"/>
+      <xs:enumeration value="NR"/>
+      <xs:enumeration value="IP"/>
+      <xs:enumeration value="Future"/>
+      <xs:enumeration value="?"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="memory_technology">
+    <xs:restriction base="xs:string">
+      <xs:enumeration value="EE"/>
+      <xs:enumeration value="EEE"/>
+      <xs:enumeration value="EPROM"/>
+      <xs:enumeration value="ROM"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="architecture">
+    <xs:restriction base="xs:string">
+      <xs:enumeration value="10X"/>
+      <xs:enumeration value="16X"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="document_type">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[0-9]+"/>
+      <xs:pattern value="[?]"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <xs:simpleType name="errata_type">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[0-9]+[a-z0-9]*"/>
+      <xs:pattern value="er[a-z0-9]+"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <xs:simpleType name="erratas_type">
+    <xs:list itemType="errata_type"/>
+  </xs:simpleType>
+
+  <xs:simpleType name="checksum_type">
+    <xs:restriction base="xs:string">
+      <xs:enumeration value="XOR4"/>
+      <xs:enumeration value="XNOR7"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="frequency_type">
+    <xs:restriction base="xs:string">
+      <xs:enumeration value="commercial"/>
+      <xs:enumeration value="industrial"/>
+      <xs:enumeration value="extended"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <xs:simpleType name="frequency_special">
+    <xs:restriction base="xs:string">
+      <xs:enumeration value="low power"/>
+      <xs:enumeration value="low voltage"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <xs:simpleType name="frequency_value">
+    <xs:restriction base="xs:float">
+      <xs:minInclusive value="0.0"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="voltage_type">
+    <xs:restriction base="xs:string">
+      <xs:enumeration value="vpp"/>
+      <xs:enumeration value="vdd_prog"/>
+      <xs:enumeration value="vdd_prog_write"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <xs:simpleType name="voltage_value">
+    <xs:restriction base="xs:float">
+      <xs:minExclusive value="0.0"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="memory_type">
+    <xs:restriction base="xs:string">
+      <xs:enumeration value="program"/>
+      <xs:enumeration value="eeprom"/>
+      <xs:enumeration value="calibration"/>
+      <xs:enumeration value="calibration_backup"/>
+      <xs:enumeration value="user_ids"/>
+      <xs:enumeration value="config"/>
+      <xs:enumeration value="device_id"/>
+      <xs:enumeration value="debug_vector"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <xs:simpleType name="hexfile_offset_unknown">
+    <xs:restriction base="xs:string">
+      <xs:enumeration value="?"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <xs:simpleType name="hexfile_offset">
+    <xs:union memberTypes="hex hexfile_offset_unknown"/>
+  </xs:simpleType>
+
+  <xs:simpleType name="value_default_value">
+    <xs:restriction base="xs:string">
+      <xs:enumeration value="default"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <xs:simpleType name="value_value">
+    <xs:union memberTypes="hex value_default_value"/>
+  </xs:simpleType>
+  <xs:simpleType name="cname">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="_[_0-9A-Za-z]+"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <xs:simpleType name="cnames">
+    <xs:list itemType="cname"/>
+  </xs:simpleType>
+
+  <xs:simpleType name="pin_name">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[A-Z][A-Z0-9-+]*(/[A-Z][A-Z0-9-+]*)*"/>
+      <xs:pattern value="N/C"/>
+      <xs:pattern value=""/>
+    </xs:restriction>
+  </xs:simpleType>
+  <xs:simpleType name="pin_type">
+    <xs:restriction base="xs:string">
+      <xs:enumeration value="dfns"/>
+      <xs:enumeration value="mlf"/>
+      <xs:enumeration value="mqfp"/>
+      <xs:enumeration value="msop"/>
+      <xs:enumeration value="pdip"/>
+      <xs:enumeration value="plcc"/>
+      <xs:enumeration value="qfn"/>
+      <xs:enumeration value="sdip"/>
+      <xs:enumeration value="soic"/>
+      <xs:enumeration value="sot23"/>
+      <xs:enumeration value="spdip"/>
+      <xs:enumeration value="ssop"/>
+      <xs:enumeration value="tqfp"/>
+      <xs:enumeration value="tssop"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <xs:simpleType name="pin_types">
+    <xs:list itemType="pin_type"/>
+  </xs:simpleType>
+
+<!-- complex types definition -->
+  <xs:complexType name="DocumentsType">
+    <xs:attribute name="webpage"       type="document_type" use="required"/>
+    <xs:attribute name="datasheet"     type="document_type" use="required"/>
+    <xs:attribute name="progsheet"     type="document_type" use="required"/>
+    <xs:attribute name="erratas"       type="erratas_type"  use="required"/>
+  </xs:complexType>
+
+  <xs:complexType name="ChecksumType">
+    <xs:attribute name="protected"       type="xs:string" />
+    <xs:attribute name="type"            type="checksum_type" />
+    <xs:attribute name="constant"        type="hex4" />
+    <xs:attribute name="block_protected" type="xs:nonNegativeInteger"/>
+    <xs:attribute name="bbsize"          type="xs:positiveInteger"/>
+    <xs:attribute name="mprotected"      type="word"/>
+    <xs:attribute name="bchecksum"       type="hex4" use="required"/>
+    <xs:attribute name="cchecksum"       type="hex4" use="required"/>
+  </xs:complexType>
+  <xs:complexType name="ChecksumsType">
+    <xs:sequence>
+      <xs:element name="checksum" type="ChecksumType" maxOccurs="unbounded"/>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:complexType name="FrequencyType">
+    <xs:attribute name="start"       type="frequency_value" use="required"/>
+    <xs:attribute name="end"         type="frequency_value" use="required"/>
+    <xs:attribute name="vdd_min"     type="voltage_value"   use="required"/>
+    <xs:attribute name="vdd_min_end" type="voltage_value"                 />
+    <xs:attribute name="vdd_max"     type="voltage_value"   use="required"/>
+    <xs:attribute name="special"     type="xs:string"                     />
+    <xs:attribute name="osc"         type="xs:string"                     />
+  </xs:complexType>
+  <xs:complexType name="FrequencyRangeType">
+    <xs:sequence>
+      <xs:element name="frequency" type="FrequencyType" maxOccurs="unbounded"/>
+    </xs:sequence>
+    <xs:attribute name="name"    type="frequency_type"    use="required"/>
+    <xs:attribute name="special" type="frequency_special"               />
+  </xs:complexType>
+
+  <xs:complexType name="VoltagesType">
+    <xs:attribute name="name"    type="voltage_type"  use="required"/>
+    <xs:attribute name="min"     type="voltage_value" use="required"/>
+    <xs:attribute name="max"     type="voltage_value" use="required"/>
+    <xs:attribute name="nominal" type="voltage_value" use="required"/>
+  </xs:complexType>
+
+  <xs:complexType name="MemoryType">
+    <xs:attribute name="name"           type="memory_type"   use="required"/>
+    <xs:attribute name="start"          type="hex"           use="required"/>
+    <xs:attribute name="end"            type="hex"           use="required"/>
+    <xs:attribute name="cal_opmask"     type="hex"                         />
+    <xs:attribute name="cal_opcode"     type="hex"                         />
+    <xs:attribute name="rmask"          type="hex"                         />
+    <xs:attribute name="hexfile_offset" type="hexfile_offset"              />
+  </xs:complexType>
+
+  <xs:complexType name="ValueType">
+    <xs:attribute name="name"    type="xs:string"   use="required"/>
+    <xs:attribute name="value"   type="value_value" use="required"/>
+    <xs:attribute name="cname"   type="cnames"                    />
+    <xs:attribute name="ecnames" type="cnames"                    />
+  </xs:complexType>
+  <xs:complexType name="MaskType">
+    <xs:sequence>
+      <xs:element name="value" type="ValueType" maxOccurs="unbounded"/>
+    </xs:sequence>
+    <xs:attribute name="name"   type="word" use="required"/>
+    <xs:attribute name="value"  type="hex"  use="required"/>
+  </xs:complexType>
+  <xs:complexType name="ConfigType">
+    <xs:sequence>
+      <xs:element name="mask" type="MaskType" maxOccurs="unbounded"/>
+    </xs:sequence>
+    <xs:attribute name="name"    type="xs:string" use="required"/>
+    <xs:attribute name="offset"  type="hex"       use="required"/>
+    <xs:attribute name="wmask"   type="hex"       use="required"/>
+    <xs:attribute name="bvalue"  type="hex"       use="required"/>
+    <xs:attribute name="cmask"   type="hex"                     />
+    <xs:attribute name="pmask"   type="hex"                     />
+    <xs:attribute name="icnames" type="cnames"                  />
+  </xs:complexType>
+
+  <xs:complexType name="PinType">
+    <xs:attribute name="index" type="xs:positiveInteger" use="required"/>
+    <xs:attribute name="name"  type="pin_name"                         />
+  </xs:complexType>
+  <xs:complexType name="PackageType">
+    <xs:sequence>
+      <xs:element name="pin" type="PinType" maxOccurs="unbounded"/>
+    </xs:sequence>
+    <xs:attribute name="types"    type="pin_types"          use="required"/>
+    <xs:attribute name="nb_pins"  type="xs:positiveInteger" use="required"/>
+  </xs:complexType>
+
+<!-- document -->
+  <xs:complexType name="deviceType">
+    <xs:sequence>
+      <xs:element name="documents"       type="DocumentsType"      minOccurs="0"        />
+      <xs:element name="checksums"       type="ChecksumsType"      minOccurs="0"        />
+      <xs:element name="frequency_range" type="FrequencyRangeType" maxOccurs="unbounded"/>
+      <xs:element name="voltages"        type="VoltagesType"       maxOccurs="unbounded"/>
+      <xs:element name="memory"          type="MemoryType"         maxOccurs="unbounded"/>
+      <xs:element name="config"          type="ConfigType"         maxOccurs="unbounded"/>
+      <xs:element name="package"         type="PackageType"        maxOccurs="unbounded"/>
+    </xs:sequence>
+    <xs:attribute name="name"              type="xs:string"         use="required"/>
+    <xs:attribute name="alternative"       type="xs:string"                       />
+    <xs:attribute name="document"          type="document_type"                   />
+    <xs:attribute name="status"            type="status"            use="required"/>
+    <xs:attribute name="memory_technology" type="memory_technology" use="required"/>
+    <xs:attribute name="architecture"      type="architecture"      use="required"/>
+    <xs:attribute name="pc"                type="xs:positiveInteger"              />
+    <xs:attribute name="id"                type="hex4"                            />
+  </xs:complexType>
+
+  <xs:element name="device" type="deviceType"/>
+
+</xs:schema>
\ No newline at end of file
diff --git a/src/devices/pic/xml_data/registers/registers.xml b/src/devices/pic/xml_data/registers/registers.xml
new file mode 100644
index 0000000..d7c0884
--- /dev/null
+++ b/src/devices/pic/xml_data/registers/registers.xml
@@ -0,0 +1,57694 @@
+<!DOCTYPE piklab>
+<!--This file is generated. Do not edit.--><registers>
+  <device nb_banks="1" name="30F1010" >
+    <unused end="0x007F" start="0x0054" />
+    <unused end="0x0093" start="0x008A" />
+    <unused end="0x00A3" start="0x009A" />
+    <unused end="0x00B5" start="0x00B4" />
+    <unused end="0x00C3" start="0x00C2" />
+    <unused end="0x00C7" start="0x00C6" />
+    <unused end="0x00FF" start="0x00C8" />
+    <unused end="0x010B" start="0x0108" />
+    <unused end="0x010F" start="0x010E" />
+    <unused end="0x013F" start="0x0112" />
+    <unused end="0x017F" start="0x0140" />
+    <unused end="0x01AF" start="0x0186" />
+    <unused end="0x01BF" start="0x01B0" />
+    <unused end="0x0457" start="0x0430" />
+    <unused end="0x047F" start="0x0458" />
+    <unused end="0x023F" start="0x022A" />
+    <unused end="0x022B" start="0x0226" />
+    <unused end="0x023F" start="0x022C" />
+    <unused end="0x025F" start="0x0240" />
+    <unused end="0x027F" start="0x0260" />
+    <unused end="0x0304" start="0x0304" />
+    <unused end="0x031E" start="0x030E" />
+    <unused end="0x033E" start="0x0330" />
+    <unused end="0x02D1" start="0x02CC" />
+    <unused end="0x02E9" start="0x02E4" />
+    <unused end="0x02FF" start="0x02EA" />
+    <unused end="0x03BF" start="0x039C" />
+    <unused end="0x03FF" start="0x03C0" />
+    <unused end="0x04BF" start="0x0480" />
+    <unused end="0x04FF" start="0x04C8" />
+    <unused end="0x073F" start="0x0500" />
+    <unused end="0x074F" start="0x0744" />
+    <unused end="0x0755" start="0x0750" />
+    <unused end="0x075F" start="0x0756" />
+    <unused end="0x076F" start="0x0768" />
+    <unused end="0x0775" start="0x0774" />
+    <unused end="0x07FF" start="0x0776" />
+    <sfr address="0x0000" access="3333333333333333" name="WREG0" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0002" access="3333333333333333" name="WREG1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0004" access="3333333333333333" name="WREG2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0006" access="3333333333333333" name="WREG3" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0008" access="3333333333333333" name="WREG4" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x000A" access="3333333333333333" name="WREG5" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x000C" access="3333333333333333" name="WREG6" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x000E" access="3333333333333333" name="WREG7" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0010" access="3333333333333333" name="WREG8" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0012" access="3333333333333333" name="WREG9" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0014" access="3333333333333333" name="WREG10" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0016" access="3333333333333333" name="WREG11" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0018" access="3333333333333333" name="WREG12" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x001A" access="3333333333333333" name="WREG13" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x001C" access="3333333333333333" name="WREG14" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x001E" access="3333333333333330" name="WREG15" mclr="1111211111111111" por="1111211111111111" />
+    <sfr address="0x0020" access="3333333333333331" name="SPLIM" mclr="1111111111111111" por="1111111111111111" />
+    <combined address="0x0022" size="5" name="ACCA" />
+    <sfr address="0x0022" access="3333333333333333" name="ACCAL" mclr="3333333333333333" por="0000000000000000" />
+    <sfr address="0x0024" access="3333333333333333" name="ACCAH" mclr="3333333333333333" por="0000000000000000" />
+    <sfr address="0x0026" access="1111111133333333" name="ACCAU" mclr="1111111133333333" por="1111111100000000" />
+    <combined address="0x0028" size="5" name="ACCB" />
+    <sfr address="0x0028" access="3333333333333333" name="ACCBL" mclr="3333333333333333" por="0000000000000000" />
+    <sfr address="0x002A" access="3333333333333333" name="ACCBH" mclr="3333333333333333" por="0000000000000000" />
+    <sfr address="0x002C" access="1111111133333333" name="ACCBU" mclr="1111111133333333" por="1111111100000000" />
+    <combined address="0x002E" size="3" name="PC" />
+    <sfr address="0x002E" access="1111111111111111" name="PCL" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0030" access="0000000001111111" name="PCH" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0032" access="0000000033333333" name="TBLPAG" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0034" access="0000000033333333" name="PSVPAG" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0036" access="0033333333333333" name="RCOUNT" mclr="0033333333333333" por="0000000000000000" />
+    <sfr address="0x0038" access="0033333333333333" name="DCOUNT" mclr="0033333333333333" por="0000000000000000" />
+    <combined address="0x003A" size="3" name="DOSTART" />
+    <sfr address="0x003A" access="3333333333333331" name="DOSTARTL" mclr="3333333333333331" por="0000000000000001" />
+    <sfr address="0x003C" access="0000000003333333" name="DOSTARTH" mclr="0000000003333333" por="0000000000000000" />
+    <combined address="0x003E" size="3" name="DOEND" />
+    <sfr address="0x003E" access="3333333333333331" name="DOENDL" mclr="3333333333333331" por="0000000000000001" />
+    <sfr address="0x0040" access="0000000003333333" name="DOENDH" mclr="0000000003333333" por="0000000000000000" />
+    <sfr address="0x0042" access="1155151333313333" name="SR" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0044" access="0003211133335333" name="CORCON" mclr="0001111111211111" por="0001111111211111" />
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+    <sfr address="0x039A" access="1111111111111111" name="C1EC" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0740" access="3300000033333333" name="RCON" mclr="3300000023333333" por="1100000011111122" />
+    <sfr address="0x0742" access="0111033333105033" name="OSCCON" mclr="0555055511101011" por="0555055511101011" />
+    <sfr address="0x0744" access="0000000000333333" name="OSCTUN" mclr="0000000000333333" por="0000000000111111" />
+    <sfr address="0x0760" access="3330000003333333" name="NVMCON" mclr="1110000001111111" por="1110000001111111" />
+    <sfr address="0x0762" access="3333333333333333" name="NVMADR" mclr="1111111111111111" por="0000000000000000" />
+    <sfr address="0x0764" access="0000000033333333" name="NVMADRU" mclr="0000000011111111" por="0000000000000000" />
+    <sfr address="0x0766" access="0000000022222222" name="NVMKEY" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0770" access="3333333033333333" name="PMD1" mclr="1111111011111111" por="1111111011111111" />
+    <sfr address="0x0772" access="3333333333333333" name="PMD2" mclr="1111111111111111" por="1111111111111111" />
+  </device>
+  <device nb_banks="1" name="10F200" >
+    <unused end="0x000F" start="0x0008" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33011333" name="STATUS" mclr="40044333" por="10022000" />
+    <sfr address="0x0004" access="11133333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="33333333" name="OSCCAL" mclr="33333333" por="22222221" />
+    <sfr address="0x0006" access="00001333" name="GPIO" mclr="00003333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444444" por="44444444" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00003333" name="TRISIO" mclr="00002222" por="00002222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="1" name="10F202" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33011333" name="STATUS" mclr="40044333" por="10022000" />
+    <sfr address="0x0004" access="11133333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="33333333" name="OSCCAL" mclr="33333333" por="22222221" />
+    <sfr address="0x0006" access="00001333" name="GPIO" mclr="00003333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444444" por="44444444" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00003333" name="TRISIO" mclr="00002222" por="00002222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="1" name="10F204" >
+    <unused end="0x000F" start="0x0008" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33011333" name="STATUS" mclr="44044333" por="11022000" />
+    <sfr address="0x0004" access="11133333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="33333333" name="OSCCAL" mclr="33333333" por="22222221" />
+    <sfr address="0x0006" access="00001333" name="GPIO" mclr="00003333" por="00000000" />
+    <sfr address="0x0007" access="13333333" name="CMCON0" mclr="33333333" por="22222222" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444444" por="44444444" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00003333" name="TRISIO" mclr="00002222" por="00002222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="1" name="10F206" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33011333" name="STATUS" mclr="44044333" por="11022000" />
+    <sfr address="0x0004" access="11133333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="33333333" name="OSCCAL" mclr="33333333" por="22222221" />
+    <sfr address="0x0006" access="00001333" name="GPIO" mclr="00003333" por="00000000" />
+    <sfr address="0x0007" access="13333333" name="CMCON0" mclr="22222222" por="22222222" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444444" por="44444444" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00003333" name="TRISIO" mclr="00002222" por="00002222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="1" name="10F220" >
+    <unused end="0x000F" start="0x0009" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33011333" name="STATUS" mclr="40044333" por="10022000" />
+    <sfr address="0x0004" access="11133333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="33333333" name="OSCCAL" mclr="22222221" por="22222221" />
+    <sfr address="0x0006" access="00001333" name="GPIO" mclr="00003333" por="00000000" />
+    <sfr address="0x0007" access="33003333" name="ADCON0" mclr="22002211" por="22002211" />
+    <sfr address="0x0008" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444444" por="44444444" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00003333" name="TRISIO" mclr="00000222" por="00000222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="1" name="10F222" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33011333" name="STATUS" mclr="40044333" por="10022000" />
+    <sfr address="0x0004" access="11133333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="33333333" name="OSCCAL" mclr="22222221" por="22222221" />
+    <sfr address="0x0006" access="00001333" name="GPIO" mclr="00003333" por="00000000" />
+    <sfr address="0x0007" access="33003333" name="ADCON0" mclr="22002211" por="22002211" />
+    <sfr address="0x0008" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444444" por="44444444" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00003333" name="TRISIO" mclr="00000222" por="00000222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="1" name="12C508" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="30311333" name="STATUS" mclr="40144333" por="10122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="33330000" name="OSCCAL" mclr="33330000" por="12220000" />
+    <sfr address="0x0006" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44443333" por="44440000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00333333" name="TRIS" mclr="00222222" por="00222222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="1" name="12C508A" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="41144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="33333300" name="OSCCAL" mclr="33333300" por="21111100" />
+    <sfr address="0x0006" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444433" por="44444400" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00333333" name="TRIS" mclr="00222222" por="00222222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="2" name="12C509" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="30311333" name="STATUS" mclr="40144333" por="10122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22333333" por="22100000" />
+    <sfr address="0x0005" access="33330000" name="OSCCAL" mclr="33330000" por="12220000" />
+    <sfr address="0x0006" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44443333" por="44440000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00333333" name="TRIS" mclr="00222222" por="00222222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="2" name="12C509A" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="41144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22333333" por="22100000" />
+    <sfr address="0x0005" access="33333300" name="OSCCAL" mclr="33333300" por="21111100" />
+    <sfr address="0x0006" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444433" por="44444400" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00333333" name="TRIS" mclr="00222222" por="00222222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="2" name="12C671" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0006" />
+    <unused end="0x001D" start="0x000D" />
+    <unused end="0x0089" start="0x0086" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x0090" />
+    <unused end="0x00EF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33033303" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRIS" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000030" name="PCON" mclr="00000030" por="00000010" />
+    <sfr address="0x008F" access="33333300" name="OSCCAL" mclr="33333300" por="12221100" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="2" name="12C672" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0006" />
+    <unused end="0x001D" start="0x000D" />
+    <unused end="0x0089" start="0x0086" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x0090" />
+    <unused end="0x00EF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33033303" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRIS" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000030" name="PCON" mclr="00000030" por="00000010" />
+    <sfr address="0x008F" access="33333300" name="OSCCAL" mclr="33333300" por="12221100" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="1" name="12CE518" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="41144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="33333300" name="OSCCAL" mclr="33333300" por="21111100" />
+    <sfr address="0x0006" access="22331333" name="GPIO" mclr="22333333" por="22000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444433" por="44444400" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00333333" name="TRIS" mclr="00222222" por="00222222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="2" name="12CE519" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="41144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22333333" por="22100000" />
+    <sfr address="0x0005" access="33333300" name="OSCCAL" mclr="33333300" por="21111100" />
+    <sfr address="0x0006" access="22331333" name="GPIO" mclr="22333333" por="22000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444433" por="44444400" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00333333" name="TRIS" mclr="00222222" por="00222222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="2" name="12CE673" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0006" />
+    <unused end="0x001D" start="0x000D" />
+    <unused end="0x0089" start="0x0086" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x0090" />
+    <unused end="0x00EF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="GPIO" mclr="22333333" por="22000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33033303" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRIS" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000030" name="PCON" mclr="00000030" por="00000010" />
+    <sfr address="0x008F" access="33333300" name="OSCCAL" mclr="33333300" por="12221100" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="2" name="12CE674" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0006" />
+    <unused end="0x001D" start="0x000D" />
+    <unused end="0x0089" start="0x0086" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x0090" />
+    <unused end="0x00EF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="GPIO" mclr="22333333" por="22000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33033303" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRIS" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000030" name="PCON" mclr="00000030" por="00000010" />
+    <sfr address="0x008F" access="33333300" name="OSCCAL" mclr="33333300" por="12221100" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="2" name="12CR509A" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="41144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22333333" por="22100000" />
+    <sfr address="0x0005" access="33333300" name="OSCCAL" mclr="33333300" por="21111100" />
+    <sfr address="0x0006" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444433" por="44444400" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00333333" name="TRIS" mclr="00222222" por="00222222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="1" name="12F508" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="30011333" name="STATUS" mclr="40044333" por="10022000" />
+    <sfr address="0x0004" access="11133333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="33333330" name="OSCCAL" mclr="33333330" por="00000000" />
+    <sfr address="0x0006" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444444" por="44444444" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00333333" name="TRISIO" mclr="00222222" por="00222222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="2" name="12F509" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="30311333" name="STATUS" mclr="40144333" por="10122000" />
+    <sfr address="0x0004" access="11333333" name="FSR" mclr="22133333" por="22100000" />
+    <sfr address="0x0005" access="33333330" name="OSCCAL" mclr="33333330" por="00000000" />
+    <sfr address="0x0006" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444444" por="44444444" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00333333" name="TRISIO" mclr="00222222" por="00222222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="2" name="12F510" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11122333" por="11122000" />
+    <sfr address="0x0004" access="11333333" name="FSR" mclr="22133333" por="22100000" />
+    <sfr address="0x0005" access="33333330" name="OSCCAL" mclr="22222220" por="22222220" />
+    <sfr address="0x0006" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x0007" access="13333333" name="CM1CON0" mclr="22222222" por="22222222" />
+    <sfr address="0x0008" access="33333333" name="ADCON0" mclr="22222211" por="22222211" />
+    <sfr address="0x0009" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444444" por="44444444" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00333333" name="TRISIO" mclr="00222222" por="00222222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="4" name="12F615" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0005" start="0x0005" />
+      <range end="0x0105" start="0x0105" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x000C" start="0x000C" />
+      <range end="0x010C" start="0x010C" />
+    </mirror>
+    <mirror>
+      <range end="0x001A" start="0x000E" />
+      <range end="0x011A" start="0x010E" />
+    </mirror>
+    <mirror>
+      <range end="0x006F" start="0x001E" />
+      <range end="0x016F" start="0x011E" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0085" start="0x0085" />
+      <range end="0x0185" start="0x0185" />
+    </mirror>
+    <mirror>
+      <range end="0x0087" start="0x0087" />
+      <range end="0x0187" start="0x0187" />
+    </mirror>
+    <mirror>
+      <range end="0x008C" start="0x008C" />
+      <range end="0x018C" start="0x018C" />
+    </mirror>
+    <mirror>
+      <range end="0x0092" start="0x008E" />
+      <range end="0x0192" start="0x018E" />
+    </mirror>
+    <mirror>
+      <range end="0x0096" start="0x0095" />
+      <range end="0x0196" start="0x0195" />
+    </mirror>
+    <mirror>
+      <range end="0x00BF" start="0x009B" />
+      <range end="0x01BF" start="0x019B" />
+    </mirror>
+    <unused end="0x0006" start="0x0006" />
+    <unused end="0x0007" start="0x0007" />
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0018" start="0x0018" />
+    <unused end="0x001B" start="0x001B" />
+    <unused end="0x001D" start="0x001D" />
+    <unused end="0x0086" start="0x0086" />
+    <unused end="0x0087" start="0x0087" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x0091" />
+    <unused end="0x0094" start="0x0094" />
+    <unused end="0x009A" start="0x0097" />
+    <unused end="0x009D" start="0x009B" />
+    <unused end="0x00EF" start="0x00C0" />
+    <unused end="0x0106" start="0x0106" />
+    <unused end="0x0107" start="0x0107" />
+    <unused end="0x0109" start="0x0108" />
+    <unused end="0x010D" start="0x010D" />
+    <unused end="0x011D" start="0x011B" />
+    <unused end="0x0186" start="0x0186" />
+    <unused end="0x0187" start="0x0187" />
+    <unused end="0x0189" start="0x0188" />
+    <unused end="0x018D" start="0x018D" />
+    <unused end="0x018F" start="0x018E" />
+    <unused end="0x0191" start="0x0191" />
+    <unused end="0x0194" start="0x0193" />
+    <unused end="0x0198" start="0x0197" />
+    <unused end="0x019B" start="0x019B" />
+    <unused end="0x01EF" start="0x01C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="03303033" name="PIR1" mclr="01101011" por="01101011" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="33333333" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0013" size="2" name="CCPR1" />
+    <sfr address="0x0013" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="30333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0016" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0017" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x0019" access="30333333" name="VRCON" mclr="10111111" por="10111111" />
+    <sfr address="0x001A" access="31330303" name="CMCON0" mclr="11110101" por="11110101" />
+    <sfr address="0x001C" access="00033033" name="CMCON1" mclr="00011021" por="00011021" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33033333" name="ADCON0" mclr="11011111" por="11011111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISIO" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="03303033" name="PIE1" mclr="01101011" por="01101011" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="00030033" name="APFCON" mclr="00010011" por="00010011" />
+    <sfr address="0x0095" access="00330333" name="WPU" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOC" mclr="00111111" por="00111111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03333333" name="ANSEL" mclr="01112222" por="01112222" />
+  </device>
+  <device nb_banks="2" name="12F629" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x005F" start="0x0020" />
+      <range end="0x00DF" start="0x00A0" />
+    </mirror>
+    <unused end="0x0009" start="0x0006" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0018" start="0x0011" />
+    <unused end="0x001F" start="0x001A" />
+    <unused end="0x007F" start="0x0060" />
+    <unused end="0x0089" start="0x0086" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x008F" start="0x008F" />
+    <unused end="0x0094" start="0x0091" />
+    <unused end="0x0098" start="0x0097" />
+    <unused end="0x009F" start="0x009E" />
+    <unused end="0x00FF" start="0x00E0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="33003003" name="PIR1" mclr="11001001" por="11001001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="03333333" name="T1CON" mclr="03333333" por="01111111" />
+    <sfr address="0x0019" access="01033333" name="CMCON" mclr="01011111" por="01011111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISIO" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="33003003" name="PIE1" mclr="11001001" por="11001001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000010" />
+    <sfr address="0x0090" access="33333300" name="OSCCAL" mclr="21111100" por="21111100" />
+    <sfr address="0x0095" access="00330333" name="WPU" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOC" mclr="00111111" por="00111111" />
+    <sfr address="0x0099" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009A" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="03333333" name="EEADR" mclr="01111111" por="01111111" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="12F635" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0005" start="0x0005" />
+      <range end="0x0105" start="0x0105" />
+    </mirror>
+    <mirror>
+      <range end="0x000A" start="0x000A" />
+      <range end="0x010A" start="0x010A" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000B" />
+      <range end="0x008B" start="0x008B" />
+      <range end="0x010B" start="0x010B" />
+      <range end="0x018B" start="0x018B" />
+    </mirror>
+    <mirror>
+      <range end="0x008A" start="0x008A" />
+      <range end="0x018A" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0085" start="0x0085" />
+      <range end="0x0185" start="0x0185" />
+    </mirror>
+    <unused end="0x0009" start="0x0006" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0017" start="0x0011" />
+    <unused end="0x003F" start="0x001B" />
+    <unused end="0x0089" start="0x0086" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0093" start="0x0091" />
+    <unused end="0x0098" start="0x0098" />
+    <unused end="0x00EF" start="0x009E" />
+    <unused end="0x0109" start="0x0106" />
+    <unused end="0x010F" start="0x010C" />
+    <unused end="0x016F" start="0x0115" />
+    <unused end="0x0189" start="0x0186" />
+    <unused end="0x01EF" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="33103303" name="PIR1" mclr="11101101" por="11101101" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0018" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0019" access="01033333" name="CMCON0" mclr="01011111" por="01011111" />
+    <sfr address="0x001A" access="00000030" name="CMCON1" mclr="00000020" por="00000020" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISIO" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="33303303" name="PIE1" mclr="11101101" por="11101101" />
+    <sfr address="0x008E" access="00333033" name="PCON" mclr="00131033" por="00121044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0094" access="00130333" name="LVDCON" mclr="00110111" por="00110111" />
+    <sfr address="0x0095" access="00330333" name="WPUDA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0097" access="00330333" name="WDA" mclr="00220222" por="00220222" />
+    <sfr address="0x0099" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009A" access="33333333" name="EEDAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0110" access="93000033" name="CRCON" mclr="11000011" por="11000011" />
+    <sfr address="0x0111" access="33333333" name="CRDAT0" mclr="11111111" por="11111111" />
+    <sfr address="0x0112" access="33333333" name="CRDAT1" mclr="11111111" por="11111111" />
+    <sfr address="0x0113" access="33333333" name="CRDAT2" mclr="11111111" por="11111111" />
+    <sfr address="0x0114" access="33333333" name="CRDAT3" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="2" name="12F675" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x005F" start="0x0020" />
+      <range end="0x00DF" start="0x00A0" />
+    </mirror>
+    <unused end="0x0009" start="0x0006" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0018" start="0x0011" />
+    <unused end="0x001D" start="0x001A" />
+    <unused end="0x007F" start="0x0060" />
+    <unused end="0x0089" start="0x0086" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x008F" start="0x008F" />
+    <unused end="0x0094" start="0x0091" />
+    <unused end="0x0098" start="0x0097" />
+    <unused end="0x00FF" start="0x00E0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="33003003" name="PIR1" mclr="11001001" por="11001001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="03333333" name="T1CON" mclr="03333333" por="01111111" />
+    <sfr address="0x0019" access="01033333" name="CMCON" mclr="01011111" por="01011111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33003333" name="ADCON0" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISIO" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="33003003" name="PIE1" mclr="11001001" por="11001001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000010" />
+    <sfr address="0x0090" access="33333300" name="OSCCAL" mclr="21111100" por="21111100" />
+    <sfr address="0x0095" access="00330333" name="WPU" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOC" mclr="00111111" por="00111111" />
+    <sfr address="0x0099" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009A" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="03333333" name="EEADR" mclr="01111111" por="01111111" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03333333" name="ANSEL" mclr="01112222" por="01112222" />
+  </device>
+  <device nb_banks="2" name="12F683" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0006" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0017" start="0x0016" />
+    <unused end="0x001D" start="0x001B" />
+    <unused end="0x0089" start="0x0086" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x0091" />
+    <unused end="0x0094" start="0x0093" />
+    <unused end="0x0098" start="0x0097" />
+    <unused end="0x00EF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="GPIO" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="33303333" name="PIR1" mclr="11101111" por="11101111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="33333333" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0013" size="2" name="CCPR1" />
+    <sfr address="0x0013" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0019" access="01033333" name="CMCON0" mclr="01011111" por="01011111" />
+    <sfr address="0x001A" access="00000033" name="CMCON1" mclr="00000021" por="00000021" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33003333" name="ADCON0" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISIO" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="33303333" name="PIE1" mclr="11101111" por="11101111" />
+    <sfr address="0x008E" access="00330033" name="PCON" mclr="00130033" por="00120044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0095" access="00330333" name="WPU" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOC" mclr="00111111" por="00111111" />
+    <sfr address="0x0099" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009A" access="33333333" name="EEDAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03333333" name="ANSEL" mclr="01112222" por="01112222" />
+  </device>
+  <device nb_banks="2" name="16C432" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001E" start="0x000D" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x008F" start="0x008F" />
+    <unused end="0x009E" start="0x0091" />
+    <unused end="0x00EF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033313" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001F" access="11003333" name="CMCON" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033313" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000034" por="00000010" />
+    <sfr address="0x0090" access="00000303" name="LININTF" mclr="00000202" por="00000202" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="2" name="16C433" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0006" />
+    <unused end="0x001D" start="0x000D" />
+    <unused end="0x0089" start="0x0086" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x0090" />
+    <unused end="0x00EF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="GPIO" mclr="22333333" por="22000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33033303" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00330333" name="TRIS" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000030" name="PCON" mclr="00000030" por="00000010" />
+    <sfr address="0x008F" access="33333300" name="OSCCAL" mclr="33333300" por="12221100" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="4" name="16C505" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+      <range end="0x004F" start="0x0040" />
+      <range end="0x006F" start="0x0060" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="41144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22333333" por="22100000" />
+    <sfr address="0x0005" access="33333300" name="OSCCAL" mclr="33333300" por="21111100" />
+    <sfr address="0x0006" access="00331333" name="PORTB" mclr="00333333" por="00000000" />
+    <sfr address="0x0007" access="00333333" name="PORTC" mclr="00333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444444" por="44444444" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00333333" name="TRISB" mclr="00222222" por="00222222" />
+    <sfr address="0x0004" access="00333333" name="TRISC" mclr="00222222" por="00222222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="1" name="16C54" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="1" name="16C54C" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="1" name="16C55" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0004" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="2" name="16C554" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001F" start="0x000C" />
+    <unused end="0x007F" start="0x0070" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008C" />
+    <unused end="0x00FF" start="0x008F" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="30333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008E" access="00000030" name="PCON" mclr="00000030" por="00000010" />
+  </device>
+  <device nb_banks="2" name="16C557" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x001F" start="0x000C" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008C" />
+    <unused end="0x009F" start="0x008F" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="30333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008E" access="00000030" name="PCON" mclr="00000030" por="00000010" />
+  </device>
+  <device nb_banks="2" name="16C558" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001F" start="0x000C" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008C" />
+    <unused end="0x009F" start="0x008F" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="30333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008E" access="00000030" name="PCON" mclr="00000030" por="00000010" />
+  </device>
+  <device nb_banks="1" name="16C55A" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0004" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="1" name="16C56" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="1" name="16C56A" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="4" name="16C57" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+      <range end="0x004F" start="0x0040" />
+      <range end="0x006F" start="0x0060" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="23333333" por="20000000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0004" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="4" name="16C57C" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+      <range end="0x004F" start="0x0040" />
+      <range end="0x006F" start="0x0060" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="23333333" por="20000000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0004" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="4" name="16C58A" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+      <range end="0x004F" start="0x0040" />
+      <range end="0x006F" start="0x0060" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="23333333" por="20000000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="4" name="16C58B" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+      <range end="0x004F" start="0x0040" />
+      <range end="0x006F" start="0x0060" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="23333333" por="20000000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="2" name="16C620" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001E" start="0x000D" />
+    <unused end="0x007F" start="0x0070" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x008F" />
+    <unused end="0x00FF" start="0x00A0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001F" access="11003333" name="CMCON" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000034" por="00000010" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="2" name="16C620A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001E" start="0x000D" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x008F" />
+    <unused end="0x00EF" start="0x00A0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001F" access="11003333" name="CMCON" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000034" por="00000010" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="2" name="16C621" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001E" start="0x000D" />
+    <unused end="0x007F" start="0x0070" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x008F" />
+    <unused end="0x00FF" start="0x00A0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001F" access="11003333" name="CMCON" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000034" por="00000010" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="2" name="16C621A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001E" start="0x000D" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x008F" />
+    <unused end="0x00EF" start="0x00A0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001F" access="11003333" name="CMCON" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000034" por="00000010" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="2" name="16C622" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001E" start="0x000D" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x008F" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001F" access="11003333" name="CMCON" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000034" por="00000010" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="2" name="16C622A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001E" start="0x000D" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x008F" />
+    <unused end="0x00EF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001F" access="11003333" name="CMCON" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000034" por="00000010" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="2" name="16C62A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001F" start="0x0018" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009F" start="0x0095" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="00003333" name="PIR1" mclr="11001111" por="11001111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="00003333" name="PIE1" mclr="11001111" por="11001111" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+  </device>
+  <device nb_banks="2" name="16C62B" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001F" start="0x0018" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009F" start="0x0095" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="00003333" name="PIR1" mclr="00001111" por="00001111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="00003333" name="PIE1" mclr="00001111" por="00001111" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000034" por="00000014" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="2" name="16C63" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x001F" start="0x001E" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009F" start="0x009A" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="00113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="00333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="2" name="16C63A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009E" start="0x009A" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="00113333" name="PIR1" mclr="00111111" por="00111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="00333333" name="PIE1" mclr="00111111" por="00111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="2" name="16C642" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x001E" start="0x000D" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x008F" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00031111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001F" access="11003333" name="CMCON" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="10000333" name="PCON" mclr="30000333" por="30000444" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="2" name="16C64A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001F" start="0x0018" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009F" start="0x0095" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33003333" name="PIR1" mclr="11001111" por="11001111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33003333" name="PIE1" mclr="11001111" por="11001111" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+  </device>
+  <device nb_banks="2" name="16C65A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x001F" start="0x001E" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009F" start="0x009A" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="2" name="16C65B" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009E" start="0x009A" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="30113333" name="PIR1" mclr="10111111" por="10111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="30333333" name="PIE1" mclr="10111111" por="10111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="4" name="16C66" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x001F" start="0x001E" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009F" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x010F" start="0x010C" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="00113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="00333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="2" name="16C662" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x001E" start="0x000D" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x008F" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00031111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33000000" name="PIR1" mclr="11000000" por="11000000" />
+    <sfr address="0x001F" access="11003333" name="CMCON" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33000000" name="PIE1" mclr="11000000" por="11000000" />
+    <sfr address="0x008E" access="10000333" name="PCON" mclr="30000333" por="30000444" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="4" name="16C67" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x001F" start="0x001E" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009F" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x010F" start="0x010C" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="2" name="16C71" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x002F" start="0x0009" />
+      <range end="0x00AF" start="0x0089" />
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+    <unused end="0x0007" start="0x0007" />
+    <unused end="0x0087" start="0x0087" />
+    <unused end="0x007F" start="0x0030" />
+    <unused end="0x00FF" start="0x00B0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00031111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33033333" name="ADCON0" mclr="11011111" por="11011111" />
+    <sfr address="0x0009" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="00000033" name="ADCON1" mclr="00000011" por="00000011" />
+  </device>
+  <device nb_banks="2" name="16C710" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x002F" start="0x0009" />
+      <range end="0x00AF" start="0x0089" />
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+    <unused end="0x0007" start="0x0007" />
+    <unused end="0x007F" start="0x0030" />
+    <unused end="0x00FF" start="0x00B0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00031111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0009" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0088" access="00000033" name="ADCON1" mclr="00000011" por="00000011" />
+  </device>
+  <device nb_banks="2" name="16C711" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x004F" start="0x0009" />
+      <range end="0x00CF" start="0x0089" />
+    </mirror>
+    <unused end="0x0007" start="0x0007" />
+    <unused end="0x007F" start="0x0050" />
+    <unused end="0x00FF" start="0x00D0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00031111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0009" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0088" access="00000033" name="ADCON1" mclr="00000011" por="00000011" />
+  </device>
+  <device nb_banks="2" name="16C712" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
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+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0014" start="0x0013" />
+    <unused end="0x001D" start="0x0018" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009E" start="0x0093" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="00000303" name="DATACCP" mclr="00000303" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000333" name="PIR1" mclr="01000111" por="01000111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="00000303" name="TRISCCP" mclr="00000202" por="00000202" />
+    <sfr address="0x008C" access="03000333" name="PIE1" mclr="01000111" por="01000111" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="2" name="16C715" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
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+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001D" start="0x000D" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x008F" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00031111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="10000333" name="PCON" mclr="30000333" por="30000444" />
+    <sfr address="0x009F" access="00000033" name="ADCON1" mclr="00000011" por="00000011" />
+  </device>
+  <device nb_banks="2" name="16C716" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
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+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0014" start="0x0013" />
+    <unused end="0x001D" start="0x0018" />
+    <unused end="0x0089" start="0x0088" />
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+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009E" start="0x0093" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="00000303" name="DATACCP" mclr="00000303" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000333" name="PIR1" mclr="01000111" por="01000111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="00000303" name="TRISCCP" mclr="00000202" por="00000202" />
+    <sfr address="0x008C" access="03000333" name="PIE1" mclr="01000111" por="01000111" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="4" name="16C717" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001D" start="0x0018" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x0090" start="0x008F" />
+    <unused end="0x009A" start="0x0098" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x0110" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x01EF" start="0x018D" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133333" name="PORTA" mclr="33331111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333322" por="00000022" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03003333" name="PIR1" mclr="01001111" por="01001111" />
+    <sfr address="0x000D" access="30003000" name="PIR2" mclr="10001000" por="10001000" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33033333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03003333" name="PIE1" mclr="01001111" por="01001111" />
+    <sfr address="0x008D" access="30003000" name="PIE2" mclr="10001000" por="10001000" />
+    <sfr address="0x008E" access="00003033" name="PCON" mclr="00002033" por="00002044" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33333333" name="IOCB" mclr="22221111" por="22221111" />
+    <sfr address="0x0097" access="33333333" name="P1DEL" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33330000" name="REFCON" mclr="11110000" por="11110000" />
+    <sfr address="0x009C" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x009D" access="00333333" name="ANSEL" mclr="00222222" por="00222222" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33330000" name="ADCON1" mclr="11110000" por="11110000" />
+    <sfr address="0x010C" access="11111111" name="PMDATL" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="PMADRL" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00111111" name="PMDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00003333" name="PMADRH" mclr="00003333" por="00000000" />
+    <sfr address="0x018C" access="10000009" name="PMCON1" mclr="20000001" por="20000001" />
+  </device>
+  <device nb_banks="2" name="16C72" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001D" start="0x0018" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009E" start="0x0095" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03003333" name="PIR1" mclr="01001111" por="01001111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03003333" name="PIE1" mclr="01001111" por="01001111" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="2" name="16C72A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001D" start="0x0018" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009E" start="0x0095" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03003333" name="PIR1" mclr="01001111" por="01001111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03003333" name="PIE1" mclr="01001111" por="01001111" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000034" por="00000014" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="2" name="16C73A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009E" start="0x009A" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="2" name="16C73B" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009E" start="0x009A" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="4" name="16C745" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0014" start="0x0013" />
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0093" />
+    <unused end="0x009E" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x010C" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018C" />
+    <unused end="0x019F" start="0x019B" />
+    <unused end="0x01EF" start="0x01E0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33000333" name="PORTC" mclr="33000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33000333" name="TRISC" mclr="22000222" por="22000222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+    <sfr address="0x0190" access="00555555" name="UIR" mclr="00111111" por="00111111" />
+    <sfr address="0x0191" access="00333333" name="UIE" mclr="00111111" por="00111111" />
+    <sfr address="0x0192" access="55555555" name="UEIR" mclr="11111111" por="11111111" />
+    <sfr address="0x0193" access="33333333" name="UEIE" mclr="11111111" por="11111111" />
+    <sfr address="0x0194" access="00011100" name="USTAT" mclr="00033300" por="00000000" />
+    <sfr address="0x0195" access="00153330" name="UCTRL" mclr="00044440" por="00011110" />
+    <sfr address="0x0196" access="03333333" name="UADDR" mclr="01111111" por="01111111" />
+    <sfr address="0x0197" access="33333333" name="USWSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0198" access="00003333" name="UEP0" mclr="00001111" por="00001111" />
+    <sfr address="0x0199" access="00003333" name="UEP1" mclr="00001111" por="00001111" />
+    <sfr address="0x019A" access="00003333" name="UEP2" mclr="00001111" por="00001111" />
+    <sfr address="0x01A0" access="33333300" name="BD0OST" mclr="33333333" por="00000000" />
+    <sfr address="0x01A1" access="00003333" name="BD0OBC" mclr="33333333" por="00000000" />
+    <sfr address="0x01A2" access="33333333" name="BD0OAL" mclr="33333333" por="00000000" />
+    <sfr address="0x01A4" access="33333300" name="BD0IST" mclr="33333333" por="00000000" />
+    <sfr address="0x01A5" access="00003333" name="BD0IBC" mclr="33333333" por="00000000" />
+    <sfr address="0x01A6" access="33333333" name="BD0IAL" mclr="33333333" por="00000000" />
+    <sfr address="0x01A8" access="33333300" name="BD1OST" mclr="33333333" por="00000000" />
+    <sfr address="0x01A9" access="00003333" name="BD1OBC" mclr="33333333" por="00000000" />
+    <sfr address="0x01AA" access="33333333" name="BD1OAL" mclr="33333333" por="00000000" />
+    <sfr address="0x01AC" access="33333300" name="BD1IST" mclr="33333333" por="00000000" />
+    <sfr address="0x01AD" access="00003333" name="BD1IBC" mclr="33333333" por="00000000" />
+    <sfr address="0x01AE" access="33333333" name="BD1IAL" mclr="33333333" por="00000000" />
+    <sfr address="0x01B0" access="33333300" name="BD2OST" mclr="33333333" por="00000000" />
+    <sfr address="0x01B1" access="00003333" name="BD2OBC" mclr="33333333" por="00000000" />
+    <sfr address="0x01B2" access="33333333" name="BD2OAL" mclr="33333333" por="00000000" />
+    <sfr address="0x01B4" access="33333300" name="BD2IST" mclr="33333333" por="00000000" />
+    <sfr address="0x01B5" access="00003333" name="BD2IBC" mclr="33333333" por="00000000" />
+    <sfr address="0x01B6" access="33333333" name="BD2IAL" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="2" name="16C74A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009E" start="0x009A" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="2" name="16C74B" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009E" start="0x009A" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="4" name="16C76" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009E" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x010F" start="0x010C" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="4" name="16C765" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0014" start="0x0013" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0093" />
+    <unused end="0x009E" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x010C" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018C" />
+    <unused end="0x019F" start="0x019B" />
+    <unused end="0x01EF" start="0x01E0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33000333" name="PORTC" mclr="33000333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33000333" name="TRISC" mclr="22000222" por="22000222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+    <sfr address="0x0190" access="00555555" name="UIR" mclr="00111111" por="00111111" />
+    <sfr address="0x0191" access="00333333" name="UIE" mclr="00111111" por="00111111" />
+    <sfr address="0x0192" access="55555555" name="UEIR" mclr="11111111" por="11111111" />
+    <sfr address="0x0193" access="33333333" name="UEIE" mclr="11111111" por="11111111" />
+    <sfr address="0x0194" access="00011100" name="USTAT" mclr="00033300" por="00000000" />
+    <sfr address="0x0195" access="00153330" name="UCTRL" mclr="00044440" por="00011110" />
+    <sfr address="0x0196" access="03333333" name="UADDR" mclr="01111111" por="01111111" />
+    <sfr address="0x0197" access="33333333" name="USWSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0198" access="00003333" name="UEP0" mclr="00001111" por="00001111" />
+    <sfr address="0x0199" access="00003333" name="UEP1" mclr="00001111" por="00001111" />
+    <sfr address="0x019A" access="00003333" name="UEP2" mclr="00001111" por="00001111" />
+    <sfr address="0x01A0" access="33333300" name="BD0OST" mclr="33333333" por="00000000" />
+    <sfr address="0x01A1" access="00003333" name="BD0OBC" mclr="33333333" por="00000000" />
+    <sfr address="0x01A2" access="33333333" name="BD0OAL" mclr="33333333" por="00000000" />
+    <sfr address="0x01A4" access="33333300" name="BD0IST" mclr="33333333" por="00000000" />
+    <sfr address="0x01A5" access="00003333" name="BD0IBC" mclr="33333333" por="00000000" />
+    <sfr address="0x01A6" access="33333333" name="BD0IAL" mclr="33333333" por="00000000" />
+    <sfr address="0x01A8" access="33333300" name="BD1OST" mclr="33333333" por="00000000" />
+    <sfr address="0x01A9" access="00003333" name="BD1OBC" mclr="33333333" por="00000000" />
+    <sfr address="0x01AA" access="33333333" name="BD1OAL" mclr="33333333" por="00000000" />
+    <sfr address="0x01AC" access="33333300" name="BD1IST" mclr="33333333" por="00000000" />
+    <sfr address="0x01AD" access="00003333" name="BD1IBC" mclr="33333333" por="00000000" />
+    <sfr address="0x01AE" access="33333333" name="BD1IAL" mclr="33333333" por="00000000" />
+    <sfr address="0x01B0" access="33333300" name="BD2OST" mclr="33333333" por="00000000" />
+    <sfr address="0x01B1" access="00003333" name="BD2OBC" mclr="33333333" por="00000000" />
+    <sfr address="0x01B2" access="33333333" name="BD2OAL" mclr="33333333" por="00000000" />
+    <sfr address="0x01B4" access="33333300" name="BD2IST" mclr="33333333" por="00000000" />
+    <sfr address="0x01B5" access="00003333" name="BD2IBC" mclr="33333333" por="00000000" />
+    <sfr address="0x01B6" access="33333333" name="BD2IAL" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16C77" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009E" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x010F" start="0x010C" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="4" name="16C770" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001D" start="0x0018" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x0090" start="0x008F" />
+    <unused end="0x009A" start="0x0098" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x0110" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x01EF" start="0x018D" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133333" name="PORTA" mclr="33331111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333322" por="00000022" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03003333" name="PIR1" mclr="01001111" por="01001111" />
+    <sfr address="0x000D" access="30003000" name="PIR2" mclr="10001000" por="10001000" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33033333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03003333" name="PIE1" mclr="01001111" por="01001111" />
+    <sfr address="0x008D" access="30003000" name="PIE2" mclr="10001000" por="10001000" />
+    <sfr address="0x008E" access="00003033" name="PCON" mclr="00002033" por="00002044" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33333333" name="IOCB" mclr="22221111" por="22221111" />
+    <sfr address="0x0097" access="33333333" name="P1DEL" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33330000" name="REFCON" mclr="11110000" por="11110000" />
+    <sfr address="0x009C" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x009D" access="00333333" name="ANSEL" mclr="00222222" por="00222222" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33330000" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x010C" access="11111111" name="PMDATL" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="PMADRL" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00111111" name="PMDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00003333" name="PMADRH" mclr="00003333" por="00000000" />
+    <sfr address="0x018C" access="10000009" name="PMCON1" mclr="20000001" por="20000001" />
+  </device>
+  <device nb_banks="4" name="16C771" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001D" start="0x0018" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x0090" start="0x008F" />
+    <unused end="0x009A" start="0x0098" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x0110" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x01EF" start="0x018D" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133333" name="PORTA" mclr="33331111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333322" por="00000022" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03003333" name="PIR1" mclr="01001111" por="01001111" />
+    <sfr address="0x000D" access="30003000" name="PIR2" mclr="10001000" por="10001000" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33033333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03003333" name="PIE1" mclr="01001111" por="01001111" />
+    <sfr address="0x008D" access="30003000" name="PIE2" mclr="10001000" por="10001000" />
+    <sfr address="0x008E" access="00003033" name="PCON" mclr="00002033" por="00002044" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33333333" name="IOCB" mclr="22221111" por="22221111" />
+    <sfr address="0x0097" access="33333333" name="P1DEL" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33330000" name="REFCON" mclr="11110000" por="11110000" />
+    <sfr address="0x009C" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x009D" access="00333333" name="ANSEL" mclr="00222222" por="00222222" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33330000" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x010C" access="11111111" name="PMDATL" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="PMADRL" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00111111" name="PMDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00003333" name="PMADRH" mclr="00003333" por="00000000" />
+    <sfr address="0x018C" access="10000009" name="PMCON1" mclr="20000001" por="20000001" />
+  </device>
+  <device nb_banks="4" name="16C773" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0090" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009A" start="0x009A" />
+    <unused end="0x009D" start="0x009D" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x010C" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x01EF" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00031111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33332233" por="00002200" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000111" por="00000111" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="30003003" name="PIR2" mclr="10001001" por="10001001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="30003003" name="PIE2" mclr="10001001" por="10001001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33330000" name="REFCON" mclr="11110000" por="11110000" />
+    <sfr address="0x009C" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="4" name="16C774" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0090" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009A" start="0x009A" />
+    <unused end="0x009D" start="0x009D" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x010C" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x01EF" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33332233" por="00002200" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000111" por="00000111" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="30003003" name="PIR2" mclr="10001001" por="10001001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="30003003" name="PIE2" mclr="10001001" por="10001001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33330000" name="REFCON" mclr="11110000" por="11110000" />
+    <sfr address="0x009C" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="4" name="16C781" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001D" start="0x0011" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0094" start="0x008F" />
+    <unused end="0x009A" start="0x0097" />
+    <unused end="0x009E" start="0x009E" />
+    <unused end="0x00EF" start="0x00C0" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x0118" start="0x0113" />
+    <unused end="0x011D" start="0x011D" />
+    <unused end="0x016F" start="0x0120" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x01EF" start="0x018D" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133311" name="PORTA" mclr="33331111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33331111" por="00001111" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33330003" name="PIR1" mclr="11110001" por="11110001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="03333333" name="T1CON" mclr="03333333" por="01111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33133311" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="33330003" name="PIE1" mclr="11110001" por="11110001" />
+    <sfr address="0x008E" access="00033033" name="PCON" mclr="00012033" por="00012044" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33333333" name="IOCB" mclr="22221111" por="22221111" />
+    <sfr address="0x009B" access="00003300" name="REFCON" mclr="00001100" por="00001100" />
+    <sfr address="0x009C" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x009D" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x009F" access="00330000" name="ADCON1" mclr="00110000" por="00110000" />
+    <sfr address="0x010C" access="33333333" name="PMDATL" mclr="11111111" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="PMADRL" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="PMDATH" mclr="00111111" por="00111111" />
+    <sfr address="0x010F" access="00033333" name="PMADRH" mclr="00000333" por="00000000" />
+    <sfr address="0x0110" access="91300000" name="CALCON" mclr="11100000" por="11100000" />
+    <sfr address="0x0111" access="33333333" name="PSMCCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0112" access="33303333" name="PSMCCON1" mclr="11101111" por="11101111" />
+    <sfr address="0x0119" access="31333333" name="CM1CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011A" access="31333333" name="CM2CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011B" access="11000003" name="CM2CON1" mclr="11000001" por="11000001" />
+    <sfr address="0x011C" access="33000003" name="OPACON" mclr="11000001" por="11000001" />
+    <sfr address="0x011E" access="33333333" name="DAC" mclr="11111111" por="11111111" />
+    <sfr address="0x011F" access="33000033" name="DACON0" mclr="11000011" por="11000011" />
+    <sfr address="0x018C" access="10000009" name="PMCON1" mclr="20000001" por="20000001" />
+  </device>
+  <device nb_banks="4" name="16C782" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001D" start="0x0011" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0094" start="0x008F" />
+    <unused end="0x009A" start="0x0097" />
+    <unused end="0x009E" start="0x009E" />
+    <unused end="0x00EF" start="0x00C0" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x0118" start="0x0113" />
+    <unused end="0x011D" start="0x011D" />
+    <unused end="0x016F" start="0x0120" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x01EF" start="0x018D" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133311" name="PORTA" mclr="33331111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33331111" por="00001111" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33330003" name="PIR1" mclr="11110001" por="11110001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="03333333" name="T1CON" mclr="03333333" por="01111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33133311" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="33330003" name="PIE1" mclr="11110001" por="11110001" />
+    <sfr address="0x008E" access="00033033" name="PCON" mclr="00012033" por="00012044" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33333333" name="IOCB" mclr="22221111" por="22221111" />
+    <sfr address="0x009B" access="00003300" name="REFCON" mclr="00001100" por="00001100" />
+    <sfr address="0x009C" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x009D" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x009F" access="00330000" name="ADCON1" mclr="00110000" por="00110000" />
+    <sfr address="0x010C" access="33333333" name="PMDATL" mclr="11111111" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="PMADRL" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="PMDATH" mclr="00111111" por="00111111" />
+    <sfr address="0x010F" access="00033333" name="PMADRH" mclr="00000333" por="00000000" />
+    <sfr address="0x0110" access="91300000" name="CALCON" mclr="11100000" por="11100000" />
+    <sfr address="0x0111" access="33333333" name="PSMCCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0112" access="33303333" name="PSMCCON1" mclr="11101111" por="11101111" />
+    <sfr address="0x0119" access="31333333" name="CM1CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011A" access="31333333" name="CM2CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011B" access="11000003" name="CM2CON1" mclr="11000001" por="11000001" />
+    <sfr address="0x011C" access="33000003" name="OPACON" mclr="11000001" por="11000001" />
+    <sfr address="0x011E" access="33333333" name="DAC" mclr="11111111" por="11111111" />
+    <sfr address="0x011F" access="33000033" name="DACON0" mclr="11000011" por="11000011" />
+    <sfr address="0x018C" access="10000009" name="PMCON1" mclr="20000001" por="20000001" />
+  </device>
+  <device nb_banks="4" name="16C923" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001F" start="0x0018" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009F" start="0x0095" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0109" />
+    <unused end="0x010C" start="0x010C" />
+    <unused end="0x016F" start="0x0120" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0189" />
+    <unused end="0x01EF" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="00333333" name="PORTC" mclr="00333333" por="00000000" />
+    <sfr address="0x0008" access="11133333" name="PORTD" mclr="11111111" por="11111111" />
+    <sfr address="0x0009" access="11111111" name="PORTE" mclr="11111111" por="11111111" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="30003333" name="PIR1" mclr="10001111" por="10001111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="00333333" name="TRISC" mclr="00222222" por="00222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="30003333" name="PIE1" mclr="10001111" por="10001111" />
+    <sfr address="0x008E" access="00000030" name="PCON" mclr="00000030" por="00000010" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0107" access="11111111" name="PORTF" mclr="11111111" por="11111111" />
+    <sfr address="0x0108" access="11111111" name="PORTG" mclr="11111111" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="LCDSE" mclr="22222222" por="22222222" />
+    <sfr address="0x010E" access="00003333" name="LCDPS" mclr="00001111" por="00001111" />
+    <sfr address="0x010F" access="33033333" name="LCDCON" mclr="11011111" por="11011111" />
+    <sfr address="0x0110" access="33333333" name="LCDD00" mclr="33333333" por="00000000" />
+    <sfr address="0x0111" access="33333333" name="LCDD01" mclr="33333333" por="00000000" />
+    <sfr address="0x0112" access="33333333" name="LCDD02" mclr="33333333" por="00000000" />
+    <sfr address="0x0113" access="33333333" name="LCDD03" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="33333333" name="LCDD04" mclr="33333333" por="00000000" />
+    <sfr address="0x0115" access="33333333" name="LCDD05" mclr="33333333" por="00000000" />
+    <sfr address="0x0116" access="33333333" name="LCDD06" mclr="33333333" por="00000000" />
+    <sfr address="0x0117" access="33333333" name="LCDD07" mclr="33333333" por="00000000" />
+    <sfr address="0x0118" access="33333333" name="LCDD08" mclr="33333333" por="00000000" />
+    <sfr address="0x0119" access="33333333" name="LCDD09" mclr="33333333" por="00000000" />
+    <sfr address="0x011A" access="33333333" name="LCDD10" mclr="33333333" por="00000000" />
+    <sfr address="0x011B" access="33333333" name="LCDD11" mclr="33333333" por="00000000" />
+    <sfr address="0x011C" access="33333333" name="LCDD12" mclr="33333333" por="00000000" />
+    <sfr address="0x011D" access="33333333" name="LCDD13" mclr="33333333" por="00000000" />
+    <sfr address="0x011E" access="33333333" name="LCDD14" mclr="33333333" por="00000000" />
+    <sfr address="0x011F" access="33333333" name="LCDD15" mclr="33333333" por="00000000" />
+    <sfr address="0x0187" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0188" access="33333333" name="TRISG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="4" name="16C924" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001D" start="0x0018" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009E" start="0x0095" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0109" />
+    <unused end="0x010C" start="0x010C" />
+    <unused end="0x016F" start="0x0120" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0189" />
+    <unused end="0x01EF" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="00333333" name="PORTC" mclr="00333333" por="00000000" />
+    <sfr address="0x0008" access="11133333" name="PORTD" mclr="11111111" por="11111111" />
+    <sfr address="0x0009" access="11111111" name="PORTE" mclr="11111111" por="11111111" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33003333" name="PIR1" mclr="11001111" por="11001111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="00333333" name="TRISC" mclr="00222222" por="00222222" />
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+  </device>
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+  </device>
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+  </device>
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+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001E" start="0x000D" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x008F" start="0x008F" />
+    <unused end="0x009E" start="0x0091" />
+    <unused end="0x00EF" start="0x00A0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00031111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001F" access="11003333" name="CMCON" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000034" por="00000010" />
+    <sfr address="0x0090" access="00000333" name="EEINTF" mclr="00000222" por="00000222" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="2" name="16CE624" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001E" start="0x000D" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x008F" start="0x008F" />
+    <unused end="0x009E" start="0x0091" />
+    <unused end="0x00EF" start="0x00A0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00031111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001F" access="11003333" name="CMCON" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000034" por="00000010" />
+    <sfr address="0x0090" access="00000333" name="EEINTF" mclr="00000222" por="00000222" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="2" name="16CE625" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001E" start="0x000D" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x008F" start="0x008F" />
+    <unused end="0x009E" start="0x0091" />
+    <unused end="0x00EF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00031111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001F" access="11003333" name="CMCON" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000034" por="00000010" />
+    <sfr address="0x0090" access="00000333" name="EEINTF" mclr="00000222" por="00000222" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="1" name="16CR54A" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="1" name="16CR54C" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="1" name="16CR56A" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="4" name="16CR57C" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+      <range end="0x004F" start="0x0040" />
+      <range end="0x006F" start="0x0060" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="23333333" por="20000000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0004" access="22222222" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="4" name="16CR58B" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+      <range end="0x004F" start="0x0040" />
+      <range end="0x006F" start="0x0060" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="23333333" por="20000000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="2" name="16CR62" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001F" start="0x0018" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009F" start="0x0095" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33003333" name="PIR1" mclr="11001111" por="11001111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="33003333" name="PIE1" mclr="11001111" por="11001111" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+  </device>
+  <device nb_banks="2" name="16CR620A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001E" start="0x000D" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x009E" start="0x008F" />
+    <unused end="0x00EF" start="0x00A0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000000" name="PIR1" mclr="01000000" por="01000000" />
+    <sfr address="0x001F" access="11003333" name="CMCON" mclr="11001111" por="11001111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000000" name="PIE1" mclr="01000000" por="01000000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000034" por="00000010" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="2" name="16CR63" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x001F" start="0x001E" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009F" start="0x009A" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="00113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="00333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="2" name="16CR64" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001F" start="0x0018" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009F" start="0x0095" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33003333" name="PIR1" mclr="11001111" por="11001111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33003333" name="PIE1" mclr="11001111" por="11001111" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+  </device>
+  <device nb_banks="2" name="16CR65" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x001F" start="0x001E" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009F" start="0x009A" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="00333333" name="SSPSTAT" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="2" name="16CR72" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001D" start="0x0018" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009E" start="0x0095" />
+    <unused end="0x00FF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03003333" name="PIR1" mclr="01001111" por="01001111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03003333" name="PIE1" mclr="01001111" por="01001111" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="2" name="16CR83" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x002F" start="0x000A" />
+      <range end="0x00AF" start="0x008A" />
+    </mirror>
+    <unused end="0x0007" start="0x0007" />
+    <unused end="0x007F" start="0x0030" />
+    <unused end="0x0087" start="0x0087" />
+    <unused end="0x00FF" start="0x00B0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="00033399" name="EECON1" mclr="00014111" por="00010111" />
+    <sfr address="0x0089" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="2" name="16CR84" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x004F" start="0x000A" />
+      <range end="0x00CF" start="0x008A" />
+    </mirror>
+    <unused end="0x0007" start="0x0007" />
+    <unused end="0x007F" start="0x0050" />
+    <unused end="0x0087" start="0x0087" />
+    <unused end="0x00FF" start="0x00D0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="00033399" name="EECON1" mclr="00014111" por="00010111" />
+    <sfr address="0x0089" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F505" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+      <range end="0x004F" start="0x0040" />
+      <range end="0x006F" start="0x0060" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="31311333" name="STATUS" mclr="40144333" por="10122000" />
+    <sfr address="0x0004" access="13333333" name="FSR" mclr="22133333" por="22100000" />
+    <sfr address="0x0005" access="33333330" name="OSCCAL" mclr="33333330" por="00000000" />
+    <sfr address="0x0006" access="00331333" name="PORTB" mclr="00333333" por="00000000" />
+    <sfr address="0x0007" access="00333333" name="PORTC" mclr="00333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="44444444" por="44444444" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="00333333" name="TRISB" mclr="00222222" por="00222222" />
+    <sfr address="0x0004" access="00333333" name="TRISC" mclr="00222222" por="00222222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+  </device>
+  <device nb_banks="4" name="16F506" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+      <range end="0x004F" start="0x0040" />
+      <range end="0x006F" start="0x0060" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11122333" por="11122000" />
+    <sfr address="0x0004" access="13333333" name="FSR" mclr="21133333" por="21100000" />
+    <sfr address="0x0005" access="33333330" name="OSCCAL" mclr="22222220" por="22222220" />
+    <sfr address="0x0006" access="00331333" name="PORTB" mclr="00333333" por="00000000" />
+    <sfr address="0x0007" access="00333333" name="PORTC" mclr="00333333" por="00000000" />
+    <sfr address="0x0008" access="13333333" name="CM1CON0" mclr="22222222" por="22222222" />
+    <sfr address="0x0009" access="33333333" name="ADCON0" mclr="22222211" por="22222211" />
+    <sfr address="0x000A" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x000B" access="13333333" name="CM2CON0" mclr="22222222" por="22222222" />
+    <sfr address="0x000C" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0004" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="1" name="16F54" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="11133333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="4" name="16F57" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+      <range end="0x004F" start="0x0040" />
+      <range end="0x006F" start="0x0060" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="13333333" name="FSR" mclr="23333333" por="20000000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0004" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="8" name="16F59" >
+    <mirror>
+      <range end="0x000F" start="0x0000" />
+      <range end="0x002F" start="0x0020" />
+      <range end="0x004F" start="0x0040" />
+      <range end="0x006F" start="0x0060" />
+      <range end="0x008F" start="0x0080" />
+      <range end="0x00AF" start="0x00A0" />
+      <range end="0x00CF" start="0x00C0" />
+      <range end="0x00EF" start="0x00E0" />
+    </mirror>
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11122333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="33330000" name="PORTE" mclr="33330000" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0004" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="00333333" name="OPTION_REG" mclr="00222222" por="00222222" />
+    <sfr address="0x0007" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0008" access="33330000" name="TRISE" mclr="22220000" por="22220000" />
+  </device>
+  <device nb_banks="4" name="16F616" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0005" start="0x0005" />
+      <range end="0x0105" start="0x0105" />
+    </mirror>
+    <mirror>
+      <range end="0x0007" start="0x0007" />
+      <range end="0x0107" start="0x0107" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x000C" start="0x000C" />
+      <range end="0x010C" start="0x010C" />
+    </mirror>
+    <mirror>
+      <range end="0x001A" start="0x000E" />
+      <range end="0x011A" start="0x010E" />
+    </mirror>
+    <mirror>
+      <range end="0x006F" start="0x001E" />
+      <range end="0x016F" start="0x011E" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0085" start="0x0085" />
+      <range end="0x0185" start="0x0185" />
+    </mirror>
+    <mirror>
+      <range end="0x0087" start="0x0087" />
+      <range end="0x0187" start="0x0187" />
+    </mirror>
+    <mirror>
+      <range end="0x008C" start="0x008C" />
+      <range end="0x018C" start="0x018C" />
+    </mirror>
+    <mirror>
+      <range end="0x0092" start="0x008E" />
+      <range end="0x0192" start="0x018E" />
+    </mirror>
+    <mirror>
+      <range end="0x0096" start="0x0095" />
+      <range end="0x0196" start="0x0195" />
+    </mirror>
+    <mirror>
+      <range end="0x00BF" start="0x0099" />
+      <range end="0x01BF" start="0x0199" />
+    </mirror>
+    <unused end="0x0006" start="0x0006" />
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0018" start="0x0018" />
+    <unused end="0x001D" start="0x001D" />
+    <unused end="0x0086" start="0x0086" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0094" start="0x0093" />
+    <unused end="0x0098" start="0x0097" />
+    <unused end="0x009D" start="0x009B" />
+    <unused end="0x00EF" start="0x00C0" />
+    <unused end="0x0106" start="0x0106" />
+    <unused end="0x0109" start="0x0108" />
+    <unused end="0x010D" start="0x010D" />
+    <unused end="0x011D" start="0x011B" />
+    <unused end="0x0186" start="0x0186" />
+    <unused end="0x0189" start="0x0188" />
+    <unused end="0x018D" start="0x018D" />
+    <unused end="0x018F" start="0x018E" />
+    <unused end="0x0194" start="0x0193" />
+    <unused end="0x0198" start="0x0197" />
+    <unused end="0x01EF" start="0x01C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0007" access="00333333" name="PORTC" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="33333333" name="PIR1" mclr="11111111" por="11111111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="33333333" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0013" size="2" name="CCPR1" />
+    <sfr address="0x0013" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0016" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0017" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x0019" access="33333333" name="VRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="31330333" name="CM1CON0" mclr="11110111" por="11110111" />
+    <sfr address="0x001B" access="31330333" name="CM2CON0" mclr="11110111" por="11110111" />
+    <sfr address="0x001C" access="11033333" name="CM2CON1" mclr="11011121" por="11011121" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0087" access="00333333" name="TRISC" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0091" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0095" access="00330333" name="WPUA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0099" access="33333303" name="SRCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x009A" access="33000000" name="SRCON1" mclr="22000000" por="22000000" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+  </device>
+  <device nb_banks="4" name="16F627" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0014" start="0x0013" />
+    <unused end="0x001E" start="0x001B" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0093" />
+    <unused end="0x009E" start="0x009E" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x010C" />
+    <unused end="0x016F" start="0x0150" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x01EF" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133333" name="PORTA" mclr="00031111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33110333" name="PIR1" mclr="11110111" por="11110111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001F" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33133333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="33330333" name="PIE1" mclr="11110111" por="11110111" />
+    <sfr address="0x008E" access="00003033" name="PCON" mclr="00002034" por="00002010" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009A" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x009B" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="4" name="16F627A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0014" start="0x0013" />
+    <unused end="0x001E" start="0x001B" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0093" />
+    <unused end="0x009E" start="0x009E" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x010C" />
+    <unused end="0x016F" start="0x0150" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x01EF" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133333" name="PORTA" mclr="00001111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33110333" name="PIR1" mclr="11110111" por="11110111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001F" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33133333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="33330333" name="PIE1" mclr="11110111" por="11110111" />
+    <sfr address="0x008E" access="00003033" name="PCON" mclr="00002034" por="00002010" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009A" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x009B" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="4" name="16F628" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0014" start="0x0013" />
+    <unused end="0x001E" start="0x001B" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0093" />
+    <unused end="0x009E" start="0x009E" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x010C" />
+    <unused end="0x016F" start="0x0150" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x01EF" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133333" name="PORTA" mclr="00031111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33110333" name="PIR1" mclr="11110111" por="11110111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001F" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33133333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="33330333" name="PIE1" mclr="11110111" por="11110111" />
+    <sfr address="0x008E" access="00003033" name="PCON" mclr="00002034" por="00002010" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009A" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x009B" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="4" name="16F628A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0014" start="0x0013" />
+    <unused end="0x001E" start="0x001B" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0093" />
+    <unused end="0x009E" start="0x009E" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x010C" />
+    <unused end="0x016F" start="0x0150" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x01EF" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133333" name="PORTA" mclr="00001111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33110333" name="PIR1" mclr="11110111" por="11110111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001F" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33133333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="33330333" name="PIE1" mclr="11110111" por="11110111" />
+    <sfr address="0x008E" access="00003033" name="PCON" mclr="00002034" por="00002010" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009A" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x009B" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="2" name="16F630" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x005F" start="0x0020" />
+      <range end="0x00DF" start="0x00A0" />
+    </mirror>
+    <unused end="0x0006" start="0x0006" />
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0018" start="0x0011" />
+    <unused end="0x001F" start="0x001A" />
+    <unused end="0x007F" start="0x0060" />
+    <unused end="0x0086" start="0x0086" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x008F" start="0x008F" />
+    <unused end="0x0094" start="0x0091" />
+    <unused end="0x0098" start="0x0097" />
+    <unused end="0x009F" start="0x009E" />
+    <unused end="0x00FF" start="0x00E0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0007" access="00333333" name="PORTC" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="33003003" name="PIR1" mclr="11001001" por="11001001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="03333333" name="T1CON" mclr="03333333" por="01111111" />
+    <sfr address="0x0019" access="01033333" name="CMCON" mclr="01011111" por="01011111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0087" access="00333333" name="TRISC" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="33003003" name="PIE1" mclr="11001001" por="11001001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000010" />
+    <sfr address="0x0090" access="33333300" name="OSCCAL" mclr="21111100" por="21111100" />
+    <sfr address="0x0095" access="00330333" name="WPUA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0099" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009A" access="33333333" name="EEDAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="03333333" name="EEADR" mclr="01111111" por="01111111" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F631" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0007" start="0x0005" />
+      <range end="0x0107" start="0x0105" />
+    </mirror>
+    <mirror>
+      <range end="0x0087" start="0x0085" />
+      <range end="0x0187" start="0x0185" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x003F" start="0x0011" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0094" start="0x0091" />
+    <unused end="0x00EF" start="0x0098" />
+    <unused end="0x0109" start="0x0108" />
+    <unused end="0x0114" start="0x010E" />
+    <unused end="0x0117" start="0x0117" />
+    <unused end="0x016F" start="0x011C" />
+    <unused end="0x0189" start="0x0188" />
+    <unused end="0x019D" start="0x018E" />
+    <unused end="0x01EF" start="0x019F" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33330000" name="PORTB" mclr="33330000" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="33330000" name="PIR2" mclr="11110000" por="11110000" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33330000" name="TRISB" mclr="22220000" por="22220000" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="33330000" name="PIE2" mclr="11110000" por="11110000" />
+    <sfr address="0x008E" access="00330033" name="PCON" mclr="00130033" por="00120044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0095" access="00330333" name="WPUA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0097" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x010C" access="33333333" name="EEDAT" mclr="11111111" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0115" access="33330000" name="WPUB" mclr="22220000" por="22220000" />
+    <sfr address="0x0116" access="33330000" name="IOCB" mclr="11110000" por="11110000" />
+    <sfr address="0x0118" access="33333333" name="VRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0119" access="31333333" name="CM1CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011A" access="31333333" name="CM2CON0" mclr="11111121" por="11111121" />
+    <sfr address="0x011B" access="11000033" name="CM2CON1" mclr="11000021" por="11000021" />
+    <sfr address="0x018C" access="10003399" name="EECON1" mclr="30004111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x019E" access="33333300" name="SRCON" mclr="11111100" por="11111100" />
+  </device>
+  <device nb_banks="4" name="16F636" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0005" start="0x0005" />
+      <range end="0x0105" start="0x0105" />
+    </mirror>
+    <mirror>
+      <range end="0x0007" start="0x0007" />
+      <range end="0x0107" start="0x0107" />
+    </mirror>
+    <mirror>
+      <range end="0x000A" start="0x000A" />
+      <range end="0x010A" start="0x010A" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000B" />
+      <range end="0x008B" start="0x008B" />
+      <range end="0x010B" start="0x010B" />
+      <range end="0x018B" start="0x018B" />
+    </mirror>
+    <mirror>
+      <range end="0x008A" start="0x008A" />
+      <range end="0x018A" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0085" start="0x0085" />
+      <range end="0x0185" start="0x0185" />
+    </mirror>
+    <mirror>
+      <range end="0x0087" start="0x0087" />
+      <range end="0x0187" start="0x0187" />
+    </mirror>
+    <unused end="0x0006" start="0x0006" />
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0017" start="0x0011" />
+    <unused end="0x001F" start="0x001B" />
+    <unused end="0x0086" start="0x0086" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0093" start="0x0091" />
+    <unused end="0x0098" start="0x0098" />
+    <unused end="0x009F" start="0x009E" />
+    <unused end="0x00EF" start="0x00C0" />
+    <unused end="0x0106" start="0x0106" />
+    <unused end="0x0109" start="0x0108" />
+    <unused end="0x010F" start="0x010C" />
+    <unused end="0x016F" start="0x0115" />
+    <unused end="0x0186" start="0x0186" />
+    <unused end="0x0189" start="0x0188" />
+    <unused end="0x01EF" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0007" access="00333333" name="PORTC" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="33133303" name="PIR1" mclr="11111101" por="11111101" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0018" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0019" access="11333333" name="CMCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="00000033" name="CMCON1" mclr="00000021" por="00000021" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0087" access="00333333" name="TRISC" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="33333303" name="PIE1" mclr="11111101" por="11111101" />
+    <sfr address="0x008E" access="00333033" name="PCON" mclr="00131033" por="00121044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0094" access="00130333" name="LVDCON" mclr="00110111" por="00110111" />
+    <sfr address="0x0095" access="00330333" name="WPUDA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0097" access="00330333" name="WDA" mclr="00220222" por="00220222" />
+    <sfr address="0x0099" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009A" access="33333333" name="EEDAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0110" access="93000033" name="CRCON" mclr="11000011" por="11000011" />
+    <sfr address="0x0111" access="33333333" name="CRDAT0" mclr="11111111" por="11111111" />
+    <sfr address="0x0112" access="33333333" name="CRDAT1" mclr="11111111" por="11111111" />
+    <sfr address="0x0113" access="33333333" name="CRDAT2" mclr="11111111" por="11111111" />
+    <sfr address="0x0114" access="33333333" name="CRDAT3" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="4" name="16F639" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0005" start="0x0005" />
+      <range end="0x0105" start="0x0105" />
+    </mirror>
+    <mirror>
+      <range end="0x0007" start="0x0007" />
+      <range end="0x0107" start="0x0107" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x000C" start="0x000C" />
+      <range end="0x010C" start="0x010C" />
+    </mirror>
+    <mirror>
+      <range end="0x000F" start="0x000E" />
+      <range end="0x010F" start="0x010E" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0085" start="0x0085" />
+      <range end="0x0185" start="0x0185" />
+    </mirror>
+    <mirror>
+      <range end="0x0087" start="0x0087" />
+      <range end="0x0187" start="0x0187" />
+    </mirror>
+    <mirror>
+      <range end="0x008C" start="0x008C" />
+      <range end="0x018C" start="0x018C" />
+    </mirror>
+    <mirror>
+      <range end="0x0090" start="0x008E" />
+      <range end="0x0190" start="0x018E" />
+    </mirror>
+    <mirror>
+      <range end="0x0097" start="0x0094" />
+      <range end="0x0197" start="0x0194" />
+    </mirror>
+    <mirror>
+      <range end="0x009D" start="0x0099" />
+      <range end="0x019D" start="0x0199" />
+    </mirror>
+    <mirror>
+      <range end="0x00BF" start="0x00A0" />
+      <range end="0x01BF" start="0x01A0" />
+    </mirror>
+    <unused end="0x0006" start="0x0006" />
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0017" start="0x0011" />
+    <unused end="0x001F" start="0x001B" />
+    <unused end="0x0086" start="0x0086" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0093" start="0x0091" />
+    <unused end="0x0098" start="0x0098" />
+    <unused end="0x009F" start="0x009E" />
+    <unused end="0x00EF" start="0x00C0" />
+    <unused end="0x0106" start="0x0106" />
+    <unused end="0x0109" start="0x0108" />
+    <unused end="0x010D" start="0x010D" />
+    <unused end="0x016F" start="0x0115" />
+    <unused end="0x0186" start="0x0186" />
+    <unused end="0x0189" start="0x0188" />
+    <unused end="0x018D" start="0x018D" />
+    <unused end="0x0193" start="0x0191" />
+    <unused end="0x0198" start="0x0198" />
+    <unused end="0x019F" start="0x019E" />
+    <unused end="0x01EF" start="0x01C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="31311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0007" access="00333333" name="PORTC" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="33133303" name="PIR1" mclr="11111101" por="11111101" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0018" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0019" access="11333333" name="CMCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="00000033" name="CMCON1" mclr="00000021" por="00000021" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0087" access="00333333" name="TRISC" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="33333303" name="PIE1" mclr="11111101" por="11111101" />
+    <sfr address="0x008E" access="00333033" name="PCON" mclr="00131033" por="00121044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0094" access="31300333" name="LVDCON" mclr="11100111" por="11100111" />
+    <sfr address="0x0095" access="00330333" name="WPUDA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0097" access="00330333" name="WDA" mclr="00220222" por="00220222" />
+    <sfr address="0x0099" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009A" access="33333333" name="EEDAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0110" access="93000033" name="CRCON" mclr="11000011" por="11000011" />
+    <sfr address="0x0111" access="33333333" name="CRDAT0" mclr="11111111" por="11111111" />
+    <sfr address="0x0112" access="33333333" name="CRDAT1" mclr="11111111" por="11111111" />
+    <sfr address="0x0113" access="33333333" name="CRDAT2" mclr="11111111" por="11111111" />
+    <sfr address="0x0114" access="33333333" name="CRDAT3" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="4" name="16F648A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0014" start="0x0013" />
+    <unused end="0x001E" start="0x001B" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0093" />
+    <unused end="0x009E" start="0x009E" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x010C" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x01EF" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133333" name="PORTA" mclr="00001111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33110333" name="PIR1" mclr="11110111" por="11110111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001F" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33133333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="33330333" name="PIE1" mclr="11110111" por="11110111" />
+    <sfr address="0x008E" access="00003033" name="PCON" mclr="00002034" por="00002010" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009A" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x009B" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x009F" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+  </device>
+  <device nb_banks="2" name="16F676" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x005F" start="0x0020" />
+      <range end="0x00DF" start="0x00A0" />
+    </mirror>
+    <unused end="0x0006" start="0x0006" />
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0018" start="0x0011" />
+    <unused end="0x001D" start="0x001A" />
+    <unused end="0x007F" start="0x0060" />
+    <unused end="0x0086" start="0x0086" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x008F" start="0x008F" />
+    <unused end="0x0094" start="0x0092" />
+    <unused end="0x0098" start="0x0097" />
+    <unused end="0x00FF" start="0x00E0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0007" access="00333333" name="PORTC" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="33003003" name="PIR1" mclr="11001001" por="11001001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="03333333" name="T1CON" mclr="03333333" por="01111111" />
+    <sfr address="0x0019" access="01033333" name="CMCON" mclr="01011111" por="01011111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33033333" name="ADCON0" mclr="11011111" por="11011111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0087" access="00333333" name="TRISC" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="33003003" name="PIE1" mclr="11001001" por="11001001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000010" />
+    <sfr address="0x0090" access="33333300" name="OSCCAL" mclr="21111100" por="21111100" />
+    <sfr address="0x0091" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x0095" access="00330333" name="WPUA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0099" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009A" access="33333333" name="EEDAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="03333333" name="EEADR" mclr="01111111" por="01111111" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+  </device>
+  <device nb_banks="4" name="16F677" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0007" start="0x0005" />
+      <range end="0x0107" start="0x0105" />
+    </mirror>
+    <mirror>
+      <range end="0x0087" start="0x0085" />
+      <range end="0x0187" start="0x0185" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0012" start="0x0011" />
+    <unused end="0x001D" start="0x0015" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0092" start="0x0091" />
+    <unused end="0x009D" start="0x0098" />
+    <unused end="0x00EF" start="0x00C0" />
+    <unused end="0x0109" start="0x0108" />
+    <unused end="0x0114" start="0x010E" />
+    <unused end="0x0117" start="0x0117" />
+    <unused end="0x011D" start="0x011C" />
+    <unused end="0x016F" start="0x0120" />
+    <unused end="0x0189" start="0x0188" />
+    <unused end="0x018D" start="0x018E" />
+    <unused end="0x01EF" start="0x019F" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33330000" name="PORTB" mclr="33330000" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="33330000" name="PIR2" mclr="11110000" por="11110000" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33330000" name="TRISB" mclr="22220000" por="22220000" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="33330000" name="PIE2" mclr="11110000" por="11110000" />
+    <sfr address="0x008E" access="00330033" name="PCON" mclr="00130033" por="00120044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="00330333" name="WPUA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0097" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+    <sfr address="0x010C" access="33333333" name="EEDAT" mclr="11111111" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0115" access="33330000" name="WPUB" mclr="22220000" por="22220000" />
+    <sfr address="0x0116" access="33330000" name="IOCB" mclr="11110000" por="11110000" />
+    <sfr address="0x0118" access="33333333" name="VRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0119" access="31333333" name="CM1CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011A" access="31333333" name="CM2CON0" mclr="11111121" por="11111121" />
+    <sfr address="0x011B" access="11000033" name="CM2CON1" mclr="11000021" por="11000021" />
+    <sfr address="0x011E" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x011F" access="00003333" name="ANSELH" mclr="00002222" por="00002222" />
+    <sfr address="0x018C" access="10003399" name="EECON1" mclr="30004111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x019E" access="33333300" name="SRCON" mclr="11111100" por="11111100" />
+  </device>
+  <device nb_banks="2" name="16F684" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x0005" start="0x0005" />
+    </mirror>
+    <mirror>
+      <range end="0x0007" start="0x0007" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x000C" start="0x000C" />
+    </mirror>
+    <mirror>
+      <range end="0x001A" start="0x000E" />
+    </mirror>
+    <mirror>
+      <range end="0x006F" start="0x001E" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+    </mirror>
+    <mirror>
+      <range end="0x0085" start="0x0085" />
+    </mirror>
+    <mirror>
+      <range end="0x0087" start="0x0087" />
+    </mirror>
+    <mirror>
+      <range end="0x008C" start="0x008C" />
+    </mirror>
+    <mirror>
+      <range end="0x0092" start="0x008E" />
+    </mirror>
+    <mirror>
+      <range end="0x0096" start="0x0095" />
+    </mirror>
+    <mirror>
+      <range end="0x00BF" start="0x0099" />
+    </mirror>
+    <unused end="0x0006" start="0x0006" />
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001D" start="0x001B" />
+    <unused end="0x0086" start="0x0086" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0094" start="0x0093" />
+    <unused end="0x0098" start="0x0097" />
+    <unused end="0x00EF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0007" access="00333333" name="PORTC" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="33333333" name="PIR1" mclr="11111111" por="11111111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="33333333" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0013" size="2" name="CCPR1" />
+    <sfr address="0x0013" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0016" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0017" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x0018" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0019" access="11333333" name="CMCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="00000033" name="CMCON1" mclr="00000021" por="00000021" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33033333" name="ADCON0" mclr="11011111" por="11011111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0087" access="00333333" name="TRISC" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008E" access="00330033" name="PCON" mclr="00130033" por="00120044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0091" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0095" access="00330333" name="WPUA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0099" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009A" access="33333333" name="EEDAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+  </device>
+  <device nb_banks="4" name="16F685" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0007" start="0x0005" />
+      <range end="0x0107" start="0x0105" />
+    </mirror>
+    <mirror>
+      <range end="0x0087" start="0x0085" />
+      <range end="0x0187" start="0x0185" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0014" start="0x0013" />
+    <unused end="0x001B" start="0x0018" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0091" start="0x0091" />
+    <unused end="0x0094" start="0x0093" />
+    <unused end="0x009D" start="0x0098" />
+    <unused end="0x0109" start="0x0108" />
+    <unused end="0x0114" start="0x0110" />
+    <unused end="0x0117" start="0x0117" />
+    <unused end="0x011D" start="0x011C" />
+    <unused end="0x0189" start="0x0188" />
+    <unused end="0x018F" start="0x018E" />
+    <unused end="0x019C" start="0x0190" />
+    <unused end="0x01EF" start="0x019F" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33330000" name="PORTB" mclr="33330000" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="33330000" name="PIR2" mclr="11110000" por="11110000" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0015" size="2" name="CCPR" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x001C" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x001D" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33330000" name="TRISB" mclr="22220000" por="22220000" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="33330000" name="PIE2" mclr="11110000" por="11110000" />
+    <sfr address="0x008E" access="00330033" name="PCON" mclr="00130033" por="00120044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0095" access="00330333" name="WPUA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0097" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00111111" por="00111111" />
+    <sfr address="0x010F" access="00003333" name="EEADRH" mclr="00001111" por="00001111" />
+    <sfr address="0x0115" access="33330000" name="WPUB" mclr="22220000" por="22220000" />
+    <sfr address="0x0116" access="33330000" name="IOCB" mclr="11110000" por="11110000" />
+    <sfr address="0x0118" access="33333333" name="VRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0119" access="31333333" name="CM1CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011A" access="31333333" name="CM2CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011B" access="11000033" name="CM2CON1" mclr="11000021" por="11000021" />
+    <sfr address="0x011E" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x011F" access="00003333" name="ANSELH" mclr="00002222" por="00002222" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30004111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x019D" access="00033333" name="PSTRCON" mclr="00011112" por="00011112" />
+    <sfr address="0x019E" access="33333300" name="SRCON" mclr="11111100" por="11111100" />
+  </device>
+  <device nb_banks="4" name="16F687" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0007" start="0x0005" />
+      <range end="0x0107" start="0x0105" />
+    </mirror>
+    <mirror>
+      <range end="0x0087" start="0x0085" />
+      <range end="0x0187" start="0x0185" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0012" start="0x0011" />
+    <unused end="0x0017" start="0x0015" />
+    <unused end="0x001D" start="0x001B" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0092" start="0x0091" />
+    <unused end="0x009D" start="0x009C" />
+    <unused end="0x00EF" start="0x00C0" />
+    <unused end="0x0109" start="0x0108" />
+    <unused end="0x0114" start="0x0110" />
+    <unused end="0x0117" start="0x0117" />
+    <unused end="0x011D" start="0x011C" />
+    <unused end="0x016F" start="0x0120" />
+    <unused end="0x0189" start="0x0188" />
+    <unused end="0x018F" start="0x018E" />
+    <unused end="0x019D" start="0x0190" />
+    <unused end="0x01EF" start="0x019F" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33330000" name="PORTB" mclr="33330000" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="33330000" name="PIR2" mclr="11110000" por="11110000" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="00000000" por="00000000" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="00000000" por="00000000" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33330000" name="TRISB" mclr="22220000" por="22220000" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="33330000" name="PIE2" mclr="11110000" por="11110000" />
+    <sfr address="0x008E" access="00330033" name="PCON" mclr="00130033" por="00120044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="00330333" name="WPUA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0097" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0098" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009A" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="21033033" name="BAUDCTL" mclr="12011011" por="12011011" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00111111" por="00111111" />
+    <sfr address="0x0115" access="33330000" name="WPUB" mclr="22220000" por="22220000" />
+    <sfr address="0x0116" access="33330000" name="IOCB" mclr="11110000" por="11110000" />
+    <sfr address="0x0118" access="33333333" name="VRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0119" access="31333333" name="CM1CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011A" access="31333333" name="CM2CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011B" access="11000033" name="CM2CON1" mclr="11000021" por="11000021" />
+    <sfr address="0x011E" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x011F" access="00003333" name="ANSELH" mclr="00002222" por="00002222" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30004111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x019E" access="33333300" name="SRCON" mclr="11111100" por="11111100" />
+  </device>
+  <device nb_banks="4" name="16F688" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0005" start="0x0005" />
+      <range end="0x0105" start="0x0105" />
+    </mirror>
+    <mirror>
+      <range end="0x0007" start="0x0007" />
+      <range end="0x0107" start="0x0107" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0085" start="0x0085" />
+      <range end="0x0185" start="0x0185" />
+    </mirror>
+    <mirror>
+      <range end="0x0087" start="0x0087" />
+      <range end="0x0187" start="0x0187" />
+    </mirror>
+    <mirror>
+      <range end="0x008B" start="0x008A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0006" start="0x0006" />
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x001D" start="0x001B" />
+    <unused end="0x0086" start="0x0086" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0094" start="0x0092" />
+    <unused end="0x0106" start="0x0106" />
+    <unused end="0x0109" start="0x0108" />
+    <unused end="0x011F" start="0x010C" />
+    <unused end="0x0186" start="0x0186" />
+    <unused end="0x0189" start="0x0188" />
+    <unused end="0x01EF" start="0x018C" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0007" access="00333333" name="PORTC" mclr="00333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="33133313" name="PIR1" mclr="11111111" por="11111111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0011" access="21033033" name="BAUDCTL" mclr="12011011" por="12011011" />
+    <sfr address="0x0012" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0013" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0014" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0015" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0016" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0017" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0018" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0019" access="11333333" name="CMCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="00000033" name="CMCON1" mclr="00000021" por="00000021" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33033333" name="ADCON0" mclr="11011111" por="11011111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0087" access="00333333" name="TRISC" mclr="00222222" por="00222222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008E" access="00330033" name="PCON" mclr="00130033" por="00120044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0091" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x0095" access="00330333" name="WPUA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0097" access="00333333" name="EEDATH" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="00003333" name="EEADRH" mclr="00001111" por="00001111" />
+    <sfr address="0x0099" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009A" access="33333333" name="EEDAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="30003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+  </device>
+  <device nb_banks="4" name="16F689" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0007" start="0x0005" />
+      <range end="0x0107" start="0x0105" />
+    </mirror>
+    <mirror>
+      <range end="0x0087" start="0x0085" />
+      <range end="0x0187" start="0x0185" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0012" start="0x0011" />
+    <unused end="0x0017" start="0x0015" />
+    <unused end="0x001D" start="0x001B" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0092" start="0x0091" />
+    <unused end="0x009D" start="0x009C" />
+    <unused end="0x0109" start="0x0108" />
+    <unused end="0x0114" start="0x0110" />
+    <unused end="0x0117" start="0x0117" />
+    <unused end="0x011D" start="0x011C" />
+    <unused end="0x0189" start="0x0188" />
+    <unused end="0x018F" start="0x018E" />
+    <unused end="0x019D" start="0x0190" />
+    <unused end="0x01EF" start="0x019F" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33330000" name="PORTB" mclr="33330000" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="33330000" name="PIR2" mclr="11110000" por="11110000" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="00000000" por="00000000" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="00000000" por="00000000" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33330000" name="TRISB" mclr="22220000" por="22220000" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="33330000" name="PIE2" mclr="11110000" por="11110000" />
+    <sfr address="0x008E" access="00330033" name="PCON" mclr="00130033" por="00120044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="00330333" name="WPUA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0097" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0098" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009A" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="21033033" name="BAUDCTL" mclr="12011011" por="12011011" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+    <sfr address="0x010C" access="33333333" name="EEDAT" mclr="11111111" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00111111" por="00111111" />
+    <sfr address="0x010F" access="00003333" name="EEADRH" mclr="00001111" por="00001111" />
+    <sfr address="0x0115" access="33330000" name="WPUB" mclr="22220000" por="22220000" />
+    <sfr address="0x0116" access="33330000" name="IOCB" mclr="11110000" por="11110000" />
+    <sfr address="0x0118" access="33333333" name="VRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0119" access="31333333" name="CM1CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011A" access="31333333" name="CM2CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011B" access="11000033" name="CM2CON1" mclr="11000021" por="11000021" />
+    <sfr address="0x011E" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x011F" access="00003333" name="ANSELH" mclr="00002222" por="00002222" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30004111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x019E" access="33333300" name="SRCON" mclr="11111100" por="11111100" />
+  </device>
+  <device nb_banks="4" name="16F690" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0007" start="0x0005" />
+      <range end="0x0107" start="0x0105" />
+    </mirror>
+    <mirror>
+      <range end="0x0087" start="0x0085" />
+      <range end="0x0187" start="0x0185" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x001B" start="0x001B" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0091" start="0x0091" />
+    <unused end="0x009D" start="0x009C" />
+    <unused end="0x0109" start="0x0108" />
+    <unused end="0x0114" start="0x0110" />
+    <unused end="0x0117" start="0x0117" />
+    <unused end="0x011D" start="0x011C" />
+    <unused end="0x0189" start="0x0188" />
+    <unused end="0x018F" start="0x018E" />
+    <unused end="0x019C" start="0x0190" />
+    <unused end="0x01EF" start="0x019F" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00331333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33330000" name="PORTB" mclr="33330000" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="33330000" name="PIR2" mclr="11110000" por="11110000" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="00000000" por="00000000" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="00000000" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x001D" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00331333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33330000" name="TRISB" mclr="22220000" por="22220000" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="33330000" name="PIE2" mclr="11110000" por="11110000" />
+    <sfr address="0x008E" access="00330033" name="PCON" mclr="00130033" por="00120044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="00330333" name="WPUA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0097" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0098" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009A" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="21033033" name="BAUDCTL" mclr="12011011" por="12011011" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+    <sfr address="0x010C" access="33333333" name="EEDAT" mclr="11111111" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00111111" por="00111111" />
+    <sfr address="0x010F" access="00003333" name="EEADRH" mclr="00001111" por="00001111" />
+    <sfr address="0x0115" access="33330000" name="WPUB" mclr="22220000" por="22220000" />
+    <sfr address="0x0116" access="33330000" name="IOCB" mclr="11110000" por="11110000" />
+    <sfr address="0x0118" access="33333333" name="VRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0119" access="31333333" name="CM1CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011A" access="31333333" name="CM2CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011B" access="11000033" name="CM2CON1" mclr="11000021" por="11000021" />
+    <sfr address="0x011E" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x011F" access="00003333" name="ANSELH" mclr="00002222" por="00002222" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30004111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x019D" access="00033333" name="PSTRCON" mclr="00011112" por="00011112" />
+    <sfr address="0x019E" access="33333300" name="SRCON" mclr="11111100" por="11111100" />
+  </device>
+  <device nb_banks="2" name="16F716" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0014" start="0x0013" />
+    <unused end="0x001D" start="0x001A" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009E" start="0x0093" />
+    <unused end="0x00EF" start="0x00C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00031111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03000333" name="PIR1" mclr="01000111" por="01000111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0018" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0019" access="33033333" name="ECCPAS" mclr="11011111" por="11011111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03000333" name="PIE1" mclr="01000111" por="01000111" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+  </device>
+  <device nb_banks="4" name="16F72" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0040" />
+      <range end="0x00FF" start="0x00C0" />
+      <range end="0x017F" start="0x0140" />
+      <range end="0x01FF" start="0x01C0" />
+    </mirror>
+    <mirror>
+      <range end="0x003F" start="0x0020" />
+      <range end="0x013F" start="0x0120" />
+    </mirror>
+    <mirror>
+      <range end="0x00BF" start="0x00A0" />
+      <range end="0x01BF" start="0x01A0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x001D" start="0x0018" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x009E" start="0x0095" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x0110" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x019F" start="0x018D" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03003333" name="PIR1" mclr="01001111" por="01001111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03003333" name="PIE1" mclr="01001111" por="01001111" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+    <sfr address="0x010C" access="33333333" name="PMDATL" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="PMADRL" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="PMDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="PMADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="10000009" name="PMCON1" mclr="20000001" por="20000001" />
+  </device>
+  <device nb_banks="4" name="16F73" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0020" />
+      <range end="0x017F" start="0x0120" />
+    </mirror>
+    <mirror>
+      <range end="0x00FF" start="0x00A0" />
+      <range end="0x01FF" start="0x01A0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009E" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x0110" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x019F" start="0x018D" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+    <sfr address="0x010C" access="33333333" name="PMDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="PMADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="PMDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="PMADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="10000009" name="PMCON1" mclr="20000001" por="20000001" />
+  </device>
+  <device nb_banks="4" name="16F737" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0008" start="0x0008" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x009A" start="0x009A" />
+    <unused end="0x0108" start="0x0107" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018D" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33111111" por="00111111" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00001000" name="PORTE" mclr="00003000" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="33303033" name="PIR2" mclr="11101011" por="11101011" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="03333333" name="T1CON" mclr="03333333" por="01111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="33303033" name="PIE2" mclr="11101011" por="11101011" />
+    <sfr address="0x008E" access="00000333" name="PCON" mclr="00000333" por="00000244" />
+    <sfr address="0x008F" access="03331133" name="OSCCON" mclr="01112111" por="01112111" />
+    <sfr address="0x0090" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <combined address="0x0095" size="2" name="CCPR3" />
+    <sfr address="0x0095" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0096" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0097" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="00333000" name="ADCON2" mclr="00111000" por="00111000" />
+    <sfr address="0x009C" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x009D" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0109" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x010C" access="33333333" name="PMDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="PMADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="PMDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00003333" name="PMADRH" mclr="00003333" por="00000000" />
+    <sfr address="0x018C" access="00000009" name="PMCON1" mclr="00000001" por="00000001" />
+  </device>
+  <device nb_banks="4" name="16F74" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0020" />
+      <range end="0x017F" start="0x0120" />
+    </mirror>
+    <mirror>
+      <range end="0x00FF" start="0x00A0" />
+      <range end="0x01FF" start="0x01A0" />
+    </mirror>
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009E" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x0110" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x019F" start="0x018D" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+    <sfr address="0x010C" access="33333333" name="PMDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="PMADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="PMDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="PMADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="10000009" name="PMCON1" mclr="20000001" por="20000001" />
+  </device>
+  <device nb_banks="4" name="16F747" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
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+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
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+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
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+    <unused end="0x0108" start="0x0107" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018D" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33111111" por="00111111" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00001333" name="PORTE" mclr="00003111" por="00000111" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="33303033" name="PIR2" mclr="11101011" por="11101011" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="03333333" name="T1CON" mclr="03333333" por="01111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
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+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
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+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
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+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
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+    <sfr address="0x008E" access="00000333" name="PCON" mclr="00000333" por="00000244" />
+    <sfr address="0x008F" access="03331133" name="OSCCON" mclr="01112111" por="01112111" />
+    <sfr address="0x0090" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
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+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <combined address="0x0095" size="2" name="CCPR3" />
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+    <sfr address="0x0096" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0097" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="00333000" name="ADCON2" mclr="00111000" por="00111000" />
+    <sfr address="0x009C" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x009D" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0109" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x010C" access="33333333" name="PMDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="PMADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="PMDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00003333" name="PMADRH" mclr="00003333" por="00000000" />
+    <sfr address="0x018C" access="00000009" name="PMCON1" mclr="00000001" por="00000001" />
+  </device>
+  <device nb_banks="4" name="16F76" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
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+      <range end="0x0181" start="0x0181" />
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+      <range end="0x0186" start="0x0186" />
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+      <range end="0x01FF" start="0x01F0" />
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+    <combined address="0x0015" size="2" name="CCPR1" />
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+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+    <sfr address="0x010C" access="33333333" name="PMDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="PMADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="PMDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="PMADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="10000009" name="PMCON1" mclr="20000001" por="20000001" />
+  </device>
+  <device nb_banks="4" name="16F767" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
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+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
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+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
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+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
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+    <mirror>
+      <range end="0x0006" start="0x0006" />
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+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
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+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
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+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33111111" por="00111111" />
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+    <sfr address="0x0009" access="00001000" name="PORTE" mclr="00003000" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="33303033" name="PIR2" mclr="11101011" por="11101011" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="03333333" name="T1CON" mclr="03333333" por="01111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
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+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="33303033" name="PIE2" mclr="11101011" por="11101011" />
+    <sfr address="0x008E" access="00000333" name="PCON" mclr="00000333" por="00000244" />
+    <sfr address="0x008F" access="03331133" name="OSCCON" mclr="01112111" por="01112111" />
+    <sfr address="0x0090" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <combined address="0x0095" size="2" name="CCPR3" />
+    <sfr address="0x0095" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0096" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0097" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="00333000" name="ADCON2" mclr="00111000" por="00111000" />
+    <sfr address="0x009C" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x009D" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0109" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x010C" access="33333333" name="PMDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="PMADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="PMDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00003333" name="PMADRH" mclr="00003333" por="00000000" />
+    <sfr address="0x018C" access="00000009" name="PMCON1" mclr="00000001" por="00000001" />
+  </device>
+  <device nb_banks="4" name="16F77" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0091" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009E" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018D" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="00000003" name="PIR2" mclr="00000001" por="00000001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33330111" name="RCSTA" mclr="11110110" por="11110110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRES" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="00000003" name="PIE2" mclr="00000001" por="00000001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009F" access="00000333" name="ADCON1" mclr="00000111" por="00000111" />
+    <sfr address="0x010C" access="33333333" name="PMDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="PMADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="PMDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="PMADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="10000009" name="PMCON1" mclr="20000001" por="20000001" />
+  </device>
+  <device nb_banks="4" name="16F777" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x009A" start="0x009A" />
+    <unused end="0x0108" start="0x0107" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018D" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33111111" por="00111111" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00001333" name="PORTE" mclr="00003111" por="00000111" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="33303033" name="PIR2" mclr="11101011" por="11101011" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="03333333" name="T1CON" mclr="03333333" por="01111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11331333" name="TRISE" mclr="11112222" por="11112222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="33303033" name="PIE2" mclr="11101011" por="11101011" />
+    <sfr address="0x008E" access="00000333" name="PCON" mclr="00000333" por="00000244" />
+    <sfr address="0x008F" access="03331133" name="OSCCON" mclr="01112111" por="01112111" />
+    <sfr address="0x0090" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <combined address="0x0095" size="2" name="CCPR3" />
+    <sfr address="0x0095" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0096" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0097" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="00333000" name="ADCON2" mclr="00111000" por="00111000" />
+    <sfr address="0x009C" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x009D" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0109" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x010C" access="33333333" name="PMDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="PMADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="PMDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00003333" name="PMADRH" mclr="00003333" por="00000000" />
+    <sfr address="0x018C" access="00000009" name="PMCON1" mclr="00000001" por="00000001" />
+  </device>
+  <device nb_banks="4" name="16F785" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0007" start="0x0005" />
+      <range end="0x0107" start="0x0105" />
+    </mirror>
+    <mirror>
+      <range end="0x0087" start="0x0085" />
+      <range end="0x0187" start="0x0185" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x000D" start="0x000D" />
+    <unused end="0x0017" start="0x0016" />
+    <unused end="0x001D" start="0x0019" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x008D" start="0x008D" />
+    <unused end="0x0094" start="0x0094" />
+    <unused end="0x0097" start="0x0097" />
+    <unused end="0x00EF" start="0x00C0" />
+    <unused end="0x0109" start="0x0108" />
+    <unused end="0x010F" start="0x010C" />
+    <unused end="0x0118" start="0x0115" />
+    <unused end="0x016F" start="0x011E" />
+    <unused end="0x0189" start="0x0188" />
+    <unused end="0x018D" start="0x018C" />
+    <unused end="0x018F" start="0x018E" />
+    <unused end="0x01EF" start="0x0190" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00333333" por="00000000" />
+    <sfr address="0x0006" access="33330000" name="PORTB" mclr="33330000" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111111" />
+    <sfr address="0x000C" access="33333333" name="PIR1" mclr="11111111" por="11111111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="33333333" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0013" size="2" name="CCPR" />
+    <sfr address="0x0013" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33330000" name="TRISB" mclr="22220000" por="22220000" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008E" access="00030033" name="PCON" mclr="00030033" por="00020044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0091" access="33333333" name="ANSEL0" mclr="22222222" por="22222222" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="00003333" name="ANSEL1" mclr="00002222" por="00002222" />
+    <sfr address="0x0095" access="00333333" name="WPUA" mclr="00220222" por="00220222" />
+    <sfr address="0x0096" access="00333333" name="IOCA" mclr="00111111" por="00111111" />
+    <sfr address="0x0098" access="00333330" name="REFCON" mclr="00111110" por="00111110" />
+    <sfr address="0x0099" access="33303333" name="VRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x009A" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="00003399" name="EECON1" mclr="00004111" por="00000111" />
+    <sfr address="0x009D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+    <sfr address="0x0110" access="33333333" name="PWMCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0111" access="33333333" name="PWMCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0112" access="33333333" name="PWMCLK" mclr="11111111" por="11111111" />
+    <sfr address="0x0113" access="33333333" name="PWMPH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0114" access="33333333" name="PWMPH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0119" access="31333333" name="CM1CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011A" access="31333333" name="CM2CON0" mclr="11111111" por="11111111" />
+    <sfr address="0x011B" access="11000033" name="CM2CON1" mclr="11000021" por="11000021" />
+    <sfr address="0x011C" access="30000000" name="OPA1CON" mclr="10000000" por="10000000" />
+    <sfr address="0x011D" access="30000000" name="OPA2CON" mclr="10000000" por="10000000" />
+  </device>
+  <device nb_banks="4" name="16F818" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x003F" start="0x0020" />
+      <range end="0x013F" start="0x0120" />
+      <range end="0x01BF" start="0x01A0" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0040" />
+      <range end="0x00FF" start="0x00C0" />
+      <range end="0x017F" start="0x0140" />
+      <range end="0x01FF" start="0x01C0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001D" start="0x0018" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x0091" start="0x0091" />
+    <unused end="0x009D" start="0x0095" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x0110" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x019F" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133333" name="PORTA" mclr="33311111" por="00011111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03003333" name="PIR1" mclr="01001111" por="01001111" />
+    <sfr address="0x000D" access="00030000" name="PIR2" mclr="00010000" por="00010000" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33133333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03003333" name="PIE1" mclr="01001111" por="01001111" />
+    <sfr address="0x008D" access="00030000" name="PIE2" mclr="00010000" por="00010000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x008F" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0090" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00000333" name="EEADRH" mclr="00000333" por="00000000" />
+    <sfr address="0x018C" access="30033399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F819" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x006F" start="0x0020" />
+      <range end="0x01EF" start="0x01A0" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001D" start="0x0018" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x0091" start="0x0091" />
+    <unused end="0x009D" start="0x0095" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x0110" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x019F" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133333" name="PORTA" mclr="33311111" por="00011111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03003333" name="PIR1" mclr="01001111" por="01001111" />
+    <sfr address="0x000D" access="00030000" name="PIR2" mclr="00010000" por="00010000" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33133333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03003333" name="PIE1" mclr="01001111" por="01001111" />
+    <sfr address="0x008D" access="00030000" name="PIE2" mclr="00010000" por="00010000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x008F" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0090" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00000333" name="EEADRH" mclr="00000333" por="00000000" />
+    <sfr address="0x018C" access="30033399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="2" name="16F83" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x002F" start="0x000A" />
+      <range end="0x00AF" start="0x008A" />
+    </mirror>
+    <unused end="0x0007" start="0x0007" />
+    <unused end="0x007F" start="0x0030" />
+    <unused end="0x0087" start="0x0087" />
+    <unused end="0x00FF" start="0x00B0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="00033399" name="EECON1" mclr="00014111" por="00010111" />
+    <sfr address="0x0089" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="2" name="16F84" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x004F" start="0x000A" />
+      <range end="0x00CF" start="0x008A" />
+    </mirror>
+    <unused end="0x0007" start="0x0007" />
+    <unused end="0x007F" start="0x0050" />
+    <unused end="0x0087" start="0x0087" />
+    <unused end="0x00FF" start="0x00D0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="00033399" name="EECON1" mclr="00014111" por="00010111" />
+    <sfr address="0x0089" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="2" name="16F84A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x004F" start="0x000A" />
+      <range end="0x00CF" start="0x008A" />
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+    <unused end="0x007F" start="0x0050" />
+    <unused end="0x0087" start="0x0087" />
+    <unused end="0x00FF" start="0x00D0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="00033399" name="EECON1" mclr="00014111" por="00010111" />
+    <sfr address="0x0089" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F87" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
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+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001F" start="0x001B" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x0091" start="0x0091" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009A" start="0x009A" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133333" name="PORTA" mclr="33331111" por="00001111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="00111333" name="PIR1" mclr="00111111" por="00111111" />
+    <sfr address="0x000D" access="33030000" name="PIR2" mclr="11010000" por="11010000" />
+    <combined address="0x000E" size="2" name="TMR1" />
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+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="01333333" name="T1CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33133333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="00333333" name="PIE1" mclr="00111111" por="00111111" />
+    <sfr address="0x008D" access="33030000" name="PIE2" mclr="11010000" por="11010000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x008F" access="03331133" name="OSCCON" mclr="00000000" por="01111111" />
+    <sfr address="0x0090" access="00333333" name="OSCTUNE" mclr="00000000" por="00111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x009D" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00000000" por="00012111" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="00000000" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="00000000" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00000000" por="00000000" />
+    <sfr address="0x010F" access="00003333" name="EEADRH" mclr="00000000" por="00000000" />
+    <sfr address="0x018C" access="30033399" name="EECON1" mclr="00000111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F870" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
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+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
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+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
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+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
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+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
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+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
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+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
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+      <range end="0x017F" start="0x0120" />
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+    <mirror>
+      <range end="0x00BF" start="0x00A0" />
+      <range end="0x01BF" start="0x01A0" />
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+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
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+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03110333" name="PIR1" mclr="01110111" por="01110111" />
+    <sfr address="0x000D" access="00030000" name="PIR2" mclr="00010000" por="00010000" />
+    <combined address="0x000E" size="2" name="TMR1" />
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+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
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+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
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+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03330333" name="PIE1" mclr="01110111" por="01110111" />
+    <sfr address="0x008D" access="00030000" name="PIE2" mclr="00010000" por="00010000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="30003333" name="ADCON1" mclr="10001111" por="10001111" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F871" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
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+      <range end="0x0001" start="0x0001" />
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+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
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+      <range end="0x0104" start="0x0102" />
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+      <range end="0x0186" start="0x0186" />
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+      <range end="0x008B" start="0x008A" />
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+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33110333" name="PIR1" mclr="11110111" por="11110111" />
+    <sfr address="0x000D" access="00030000" name="PIR2" mclr="00010000" por="00010000" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33330333" name="PIE1" mclr="11110111" por="11110111" />
+    <sfr address="0x008D" access="00030000" name="PIE2" mclr="00010000" por="00010000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="30003333" name="ADCON1" mclr="10001111" por="10001111" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F872" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0020" />
+      <range end="0x017F" start="0x0120" />
+    </mirror>
+    <mirror>
+      <range end="0x00BF" start="0x00A0" />
+      <range end="0x01BF" start="0x01A0" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x001D" start="0x0018" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0090" start="0x008F" />
+    <unused end="0x009D" start="0x0095" />
+    <unused end="0x00EF" start="0x00C0" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x0110" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x019F" start="0x018E" />
+    <unused end="0x01EF" start="0x01C0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33333333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="03033003" name="PIR2" mclr="01011001" por="01011001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="03033003" name="PIE2" mclr="01011001" por="01011001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="30003333" name="ADCON1" mclr="10001111" por="10001111" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F873" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0020" />
+      <range end="0x017F" start="0x0120" />
+    </mirror>
+    <mirror>
+      <range end="0x00FF" start="0x00A0" />
+      <range end="0x01FF" start="0x01A0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0090" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009D" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x011F" start="0x0110" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x019F" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="03033003" name="PIR2" mclr="01011001" por="01011001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="03033003" name="PIE2" mclr="01011001" por="01011001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="30003333" name="ADCON1" mclr="10001111" por="10001111" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F873A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0020" />
+      <range end="0x017F" start="0x0120" />
+    </mirror>
+    <mirror>
+      <range end="0x00FF" start="0x00A0" />
+      <range end="0x01FF" start="0x01A0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0090" start="0x008F" />
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+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x019F" start="0x018E" />
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+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
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+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
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+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
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+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
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+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
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+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x009D" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
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+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00003333" name="EEADRH" mclr="00003333" por="00000000" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="00000000" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F874" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
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+      <range end="0x0101" start="0x0101" />
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+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
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+      <range end="0x0184" start="0x0182" />
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+    <mirror>
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+    <mirror>
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+      <range end="0x0186" start="0x0186" />
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+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
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+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
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+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
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+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="03033003" name="PIE2" mclr="01011001" por="01011001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="30003333" name="ADCON1" mclr="10001111" por="10001111" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F874A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
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+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
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+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
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+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
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+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
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+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
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+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x009D" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
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+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00003333" name="EEADRH" mclr="00003333" por="00000000" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="00000000" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F876" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0090" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009D" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="03033003" name="PIR2" mclr="01011001" por="01011001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="03033003" name="PIE2" mclr="01011001" por="01011001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="30003333" name="ADCON1" mclr="10001111" por="10001111" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F876A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
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+    <unused end="0x0009" start="0x0008" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x0090" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009B" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="03033003" name="PIR2" mclr="01011001" por="01011001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="03033003" name="PIE2" mclr="01011001" por="01011001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x009D" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="00000000" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F877" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
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+    <unused end="0x0090" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009D" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="03033003" name="PIR2" mclr="01011001" por="01011001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="03033003" name="PIE2" mclr="01011001" por="01011001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="30003333" name="ADCON1" mclr="10001111" por="10001111" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F877A" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0090" start="0x008F" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009B" start="0x009A" />
+    <unused end="0x0105" start="0x0105" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="03033003" name="PIR2" mclr="01011001" por="01011001" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="03033003" name="PIE2" mclr="01011001" por="01011001" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x009D" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F88" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x001D" start="0x001B" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x0091" start="0x0091" />
+    <unused end="0x0097" start="0x0095" />
+    <unused end="0x009A" start="0x009A" />
+    <unused end="0x0109" start="0x0107" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33133333" name="PORTA" mclr="33311111" por="00011111" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="11333333" por="11000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03111333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="33030000" name="PIR2" mclr="11010000" por="11010000" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="01333333" name="T1CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33033333" name="TRISA" mclr="22022222" por="22022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="33030000" name="PIE2" mclr="11010000" por="11010000" />
+    <sfr address="0x008E" access="00000033" name="PCON" mclr="00000033" por="00000044" />
+    <sfr address="0x008F" access="03331133" name="OSCCON" mclr="00000000" por="01111111" />
+    <sfr address="0x0090" access="00333333" name="OSCTUNE" mclr="00000000" por="00111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="03333333" name="ANSEL" mclr="00000000" por="02222222" />
+    <sfr address="0x009C" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x009D" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="33330000" name="ADCON1" mclr="00000000" por="11110000" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00000000" por="00012111" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="00000000" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="00000000" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00000000" por="00000000" />
+    <sfr address="0x010F" access="00003333" name="EEADRH" mclr="00000000" por="00000000" />
+    <sfr address="0x018C" access="30033399" name="EECON1" mclr="00000111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F883" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0008" start="0x0008" />
+    <unused end="0x0088" start="0x0088" />
+    <unused end="0x011F" start="0x0110" />
+    <unused end="0x01EF" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="33333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00003000" name="PORTE" mclr="00003000" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="33033003" name="PIR2" mclr="11111111" por="11111111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="00001000" name="TRISE" mclr="00002000" por="00002000" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="33333303" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x008E" access="00130033" name="PCON" mclr="00120033" por="00120044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33333333" name="IOCB" mclr="11111111" por="11111111" />
+    <sfr address="0x0097" access="33333333" name="VRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009A" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x009D" access="00033333" name="PSTRCON" mclr="00011112" por="00011112" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="30330000" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00022111" por="00022111" />
+    <sfr address="0x0107" access="31333033" name="CM1CON0" mclr="11110111" por="11110111" />
+    <sfr address="0x0108" access="31333033" name="CM2CON0" mclr="11110111" por="11110111" />
+    <sfr address="0x0109" access="11330033" name="CM2CON1" mclr="11111121" por="11111121" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x0185" access="33333303" name="SRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0187" access="21033033" name="BAUDCTL" mclr="12011011" por="12011011" />
+    <sfr address="0x0188" access="00033333" name="ANSEL" mclr="00022222" por="00022222" />
+    <sfr address="0x0189" access="00333333" name="ANSELH" mclr="00222222" por="00222222" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F884" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x011F" start="0x0110" />
+    <unused end="0x01EF" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="33333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00003333" name="PORTE" mclr="00003333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="33033003" name="PIR2" mclr="11111111" por="11111111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="00001333" name="TRISE" mclr="00002222" por="00002222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="33333303" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x008E" access="00130033" name="PCON" mclr="00120033" por="00120044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33333333" name="IOCB" mclr="11111111" por="11111111" />
+    <sfr address="0x0097" access="33333333" name="VRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009A" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x009D" access="00033333" name="PSTRCON" mclr="00011112" por="00011112" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="30330000" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00022111" por="00022111" />
+    <sfr address="0x0107" access="31333033" name="CM1CON0" mclr="11110111" por="11110111" />
+    <sfr address="0x0108" access="31333033" name="CM2CON0" mclr="11110111" por="11110111" />
+    <sfr address="0x0109" access="11330033" name="CM2CON1" mclr="11111121" por="11111121" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x0185" access="33333303" name="SRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0187" access="21033033" name="BAUDCTL" mclr="12011011" por="12011011" />
+    <sfr address="0x0188" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x0189" access="00333333" name="ANSELH" mclr="00222222" por="00222222" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F886" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0008" start="0x0008" />
+    <unused end="0x0088" start="0x0088" />
+    <unused end="0x018F" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="33333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00003000" name="PORTE" mclr="00003000" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="33033003" name="PIR2" mclr="11111111" por="11111111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="00001000" name="TRISE" mclr="00002000" por="00002000" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="33333303" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x008E" access="00130033" name="PCON" mclr="00120033" por="00120044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33333333" name="IOCB" mclr="11111111" por="11111111" />
+    <sfr address="0x0097" access="33333333" name="VRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009A" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x009D" access="00033333" name="PSTRCON" mclr="00011112" por="00011112" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="30330000" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00022111" por="00022111" />
+    <sfr address="0x0107" access="31333033" name="CM1CON0" mclr="11110111" por="11110111" />
+    <sfr address="0x0108" access="31333033" name="CM2CON0" mclr="11110111" por="11110111" />
+    <sfr address="0x0109" access="11330033" name="CM2CON1" mclr="11111121" por="11111121" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x0185" access="33333303" name="SRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0187" access="21033033" name="BAUDCTL" mclr="12011011" por="12011011" />
+    <sfr address="0x0188" access="00033333" name="ANSEL" mclr="00022222" por="00022222" />
+    <sfr address="0x0189" access="00333333" name="ANSELH" mclr="00222222" por="00222222" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F887" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x018F" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00333333" name="PORTA" mclr="33333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00003333" name="PORTE" mclr="00003333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x000C" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x000D" access="33033003" name="PIR2" mclr="11111111" por="11111111" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="00333333" name="T1CON" mclr="00333333" por="00111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="00001333" name="TRISE" mclr="00002222" por="00002222" />
+    <sfr address="0x008C" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x008D" access="33333303" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x008E" access="00130033" name="PCON" mclr="00120033" por="00120044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0091" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33333333" name="IOCB" mclr="11111111" por="11111111" />
+    <sfr address="0x0097" access="33333333" name="VRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009A" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x009B" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x009D" access="00033333" name="PSTRCON" mclr="00011112" por="00011112" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="30330000" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00022111" por="00022111" />
+    <sfr address="0x0107" access="31333033" name="CM1CON0" mclr="11110111" por="11110111" />
+    <sfr address="0x0108" access="31333033" name="CM2CON0" mclr="11110111" por="11110111" />
+    <sfr address="0x0109" access="11330033" name="CM2CON1" mclr="11111121" por="11111121" />
+    <sfr address="0x010C" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x010D" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00000000" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00000000" />
+    <sfr address="0x0185" access="33333303" name="SRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0187" access="21033033" name="BAUDCTL" mclr="12011011" por="12011011" />
+    <sfr address="0x0188" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x0189" access="00333333" name="ANSELH" mclr="00222222" por="00222222" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30003111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F913" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0008" start="0x0008" />
+    <unused end="0x001D" start="0x001B" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x009B" start="0x009A" />
+    <unused end="0x0112" start="0x0112" />
+    <unused end="0x0115" start="0x0115" />
+    <unused end="0x0118" start="0x0118" />
+    <unused end="0x011B" start="0x011B" />
+    <unused end="0x011F" start="0x011E" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018E" />
+    <unused end="0x01EF" start="0x0190" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33333333" name="PORTA" mclr="33333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00001000" name="PORTE" mclr="00003000" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111110" por="11111110" />
+    <sfr address="0x000C" access="33111333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="33330300" name="PIR2" mclr="11110100" por="11110100" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="00001000" name="TRISE" mclr="00002000" por="00002000" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="33330300" name="PIE2" mclr="11110100" por="11110100" />
+    <sfr address="0x008E" access="00030033" name="PCON" mclr="00030033" por="00020044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0091" access="00033333" name="ANSEL" mclr="00022222" por="00022222" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33330000" name="IOCB" mclr="11110000" por="11110000" />
+    <sfr address="0x0097" access="00000033" name="CMCON1" mclr="00000021" por="00000021" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="11333333" name="CMCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x009D" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0107" access="33533333" name="LCDCON" mclr="11121122" por="11121122" />
+    <sfr address="0x0108" access="31133333" name="LCDPS" mclr="11111111" por="11111111" />
+    <sfr address="0x0109" access="00130333" name="LVDCON" mclr="00110211" por="00110211" />
+    <sfr address="0x010C" access="33333333" name="EEDATL" mclr="33333333" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="EEADRL" mclr="33333333" por="11111111" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00111111" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00011111" />
+    <sfr address="0x0110" access="33333333" name="LCDDATA0" mclr="33333333" por="00000000" />
+    <sfr address="0x0111" access="33333333" name="LCDDATA1" mclr="33333333" por="00000000" />
+    <sfr address="0x0113" access="33333333" name="LCDDATA3" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="33333333" name="LCDDATA4" mclr="33333333" por="00000000" />
+    <sfr address="0x0116" access="33333333" name="LCDDATA6" mclr="33333333" por="00000000" />
+    <sfr address="0x0117" access="33333333" name="LCDDATA7" mclr="33333333" por="00000000" />
+    <sfr address="0x0119" access="33333333" name="LCDDATA9" mclr="33333333" por="00000000" />
+    <sfr address="0x011A" access="33333333" name="LCDDATA10" mclr="33333333" por="00000000" />
+    <sfr address="0x011C" access="33333333" name="LCDSE0" mclr="33333333" por="11111111" />
+    <sfr address="0x011D" access="33333333" name="LCDSE1" mclr="33333333" por="11111111" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30004111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F914" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x009B" start="0x009A" />
+    <unused end="0x011F" start="0x011F" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018E" />
+    <unused end="0x01EF" start="0x0190" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33333333" name="PORTA" mclr="33333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00001333" name="PORTE" mclr="00003333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111110" por="11111110" />
+    <sfr address="0x000C" access="33111333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="33330303" name="PIR2" mclr="11110101" por="11110101" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="00001333" name="TRISE" mclr="00002222" por="00002222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="33330303" name="PIE2" mclr="11110101" por="11110101" />
+    <sfr address="0x008E" access="00030033" name="PCON" mclr="00030033" por="00020044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0091" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33330000" name="IOCB" mclr="11110000" por="11110000" />
+    <sfr address="0x0097" access="00000033" name="CMCON1" mclr="00000021" por="00000021" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="11333333" name="CMCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x009D" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0107" access="33533333" name="LCDCON" mclr="11121122" por="11121122" />
+    <sfr address="0x0108" access="31133333" name="LCDPS" mclr="11111111" por="11111111" />
+    <sfr address="0x0109" access="00130333" name="LVDCON" mclr="00110211" por="00110211" />
+    <sfr address="0x010C" access="33333333" name="EEDATL" mclr="33333333" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="EEADRL" mclr="33333333" por="11111111" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00111111" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00011111" />
+    <sfr address="0x0110" access="33333333" name="LCDDATA0" mclr="33333333" por="00000000" />
+    <sfr address="0x0111" access="33333333" name="LCDDATA1" mclr="33333333" por="00000000" />
+    <sfr address="0x0112" access="33333333" name="LCDDATA2" mclr="33333333" por="00000000" />
+    <sfr address="0x0113" access="33333333" name="LCDDATA3" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="33333333" name="LCDDATA4" mclr="33333333" por="00000000" />
+    <sfr address="0x0115" access="33333333" name="LCDDATA5" mclr="33333333" por="00000000" />
+    <sfr address="0x0116" access="33333333" name="LCDDATA6" mclr="33333333" por="00000000" />
+    <sfr address="0x0117" access="33333333" name="LCDDATA7" mclr="33333333" por="00000000" />
+    <sfr address="0x0118" access="33333333" name="LCDDATA8" mclr="33333333" por="00000000" />
+    <sfr address="0x0119" access="33333333" name="LCDDATA9" mclr="33333333" por="00000000" />
+    <sfr address="0x011A" access="33333333" name="LCDDATA10" mclr="33333333" por="00000000" />
+    <sfr address="0x011B" access="33333333" name="LCDDATA11" mclr="33333333" por="00000000" />
+    <sfr address="0x011C" access="33333333" name="LCDSE0" mclr="33333333" por="11111111" />
+    <sfr address="0x011D" access="33333333" name="LCDSE1" mclr="33333333" por="11111111" />
+    <sfr address="0x011E" access="33333333" name="LCDSE2" mclr="33333333" por="11111111" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30004111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F916" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x0008" start="0x0008" />
+    <unused end="0x001D" start="0x001B" />
+    <unused end="0x0089" start="0x0088" />
+    <unused end="0x009B" start="0x009A" />
+    <unused end="0x0112" start="0x0112" />
+    <unused end="0x0115" start="0x0115" />
+    <unused end="0x0118" start="0x0118" />
+    <unused end="0x011B" start="0x011B" />
+    <unused end="0x011F" start="0x011E" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33333333" name="PORTA" mclr="33333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00001000" name="PORTE" mclr="00003000" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111110" por="11111110" />
+    <sfr address="0x000C" access="33111333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="33330300" name="PIR2" mclr="11110100" por="11110100" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="00001000" name="TRISE" mclr="00002000" por="00002000" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="33330300" name="PIE2" mclr="11110100" por="11110100" />
+    <sfr address="0x008E" access="00030033" name="PCON" mclr="00030033" por="00020044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0091" access="00033333" name="ANSEL" mclr="00022222" por="00022222" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33330000" name="IOCB" mclr="11110000" por="11110000" />
+    <sfr address="0x0097" access="00000033" name="CMCON1" mclr="00000021" por="00000021" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="11333333" name="CMCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x009D" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0107" access="33533333" name="LCDCON" mclr="11121122" por="11121122" />
+    <sfr address="0x0108" access="31133333" name="LCDPS" mclr="11111111" por="11111111" />
+    <sfr address="0x0109" access="00130333" name="LVDCON" mclr="00110211" por="00110211" />
+    <sfr address="0x010C" access="33333333" name="EEDATL" mclr="33333333" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="EEADRL" mclr="33333333" por="11111111" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00111111" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00011111" />
+    <sfr address="0x0110" access="33333333" name="LCDDATA0" mclr="33333333" por="00000000" />
+    <sfr address="0x0111" access="33333333" name="LCDDATA1" mclr="33333333" por="00000000" />
+    <sfr address="0x0113" access="33333333" name="LCDDATA3" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="33333333" name="LCDDATA4" mclr="33333333" por="00000000" />
+    <sfr address="0x0116" access="33333333" name="LCDDATA6" mclr="33333333" por="00000000" />
+    <sfr address="0x0117" access="33333333" name="LCDDATA7" mclr="33333333" por="00000000" />
+    <sfr address="0x0119" access="33333333" name="LCDDATA9" mclr="33333333" por="00000000" />
+    <sfr address="0x011A" access="33333333" name="LCDDATA10" mclr="33333333" por="00000000" />
+    <sfr address="0x011C" access="33333333" name="LCDSE0" mclr="33333333" por="11111111" />
+    <sfr address="0x011D" access="33333333" name="LCDSE1" mclr="33333333" por="11111111" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30004111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F917" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x009B" start="0x009A" />
+    <unused end="0x011F" start="0x011F" />
+    <unused end="0x0185" start="0x0185" />
+    <unused end="0x0189" start="0x0187" />
+    <unused end="0x018F" start="0x018E" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33333333" name="PORTA" mclr="33333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="00001333" name="PORTE" mclr="00003333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111110" por="11111110" />
+    <sfr address="0x000C" access="33111333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="33330303" name="PIR2" mclr="11110101" por="11110101" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="00001333" name="TRISE" mclr="00002222" por="00002222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="33330303" name="PIE2" mclr="11110101" por="11110101" />
+    <sfr address="0x008E" access="00030033" name="PCON" mclr="00030033" por="00020044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0091" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33330000" name="IOCB" mclr="11110000" por="11110000" />
+    <sfr address="0x0097" access="00000033" name="CMCON1" mclr="00000021" por="00000021" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="11333333" name="CMCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x009D" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0107" access="33533333" name="LCDCON" mclr="11121122" por="11121122" />
+    <sfr address="0x0108" access="31133333" name="LCDPS" mclr="11111111" por="11111111" />
+    <sfr address="0x0109" access="00130333" name="LVDCON" mclr="00110211" por="00110211" />
+    <sfr address="0x010C" access="33333333" name="EEDATL" mclr="33333333" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="EEADRL" mclr="33333333" por="11111111" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00111111" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00011111" />
+    <sfr address="0x0110" access="33333333" name="LCDDATA0" mclr="33333333" por="00000000" />
+    <sfr address="0x0111" access="33333333" name="LCDDATA1" mclr="33333333" por="00000000" />
+    <sfr address="0x0112" access="33333333" name="LCDDATA2" mclr="33333333" por="00000000" />
+    <sfr address="0x0113" access="33333333" name="LCDDATA3" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="33333333" name="LCDDATA4" mclr="33333333" por="00000000" />
+    <sfr address="0x0115" access="33333333" name="LCDDATA5" mclr="33333333" por="00000000" />
+    <sfr address="0x0116" access="33333333" name="LCDDATA6" mclr="33333333" por="00000000" />
+    <sfr address="0x0117" access="33333333" name="LCDDATA7" mclr="33333333" por="00000000" />
+    <sfr address="0x0118" access="33333333" name="LCDDATA8" mclr="33333333" por="00000000" />
+    <sfr address="0x0119" access="33333333" name="LCDDATA9" mclr="33333333" por="00000000" />
+    <sfr address="0x011A" access="33333333" name="LCDDATA10" mclr="33333333" por="00000000" />
+    <sfr address="0x011B" access="33333333" name="LCDDATA11" mclr="33333333" por="00000000" />
+    <sfr address="0x011C" access="33333333" name="LCDSE0" mclr="33333333" por="11111111" />
+    <sfr address="0x011D" access="33333333" name="LCDSE1" mclr="33333333" por="11111111" />
+    <sfr address="0x011E" access="33333333" name="LCDSE2" mclr="33333333" por="11111111" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30004111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="4" name="16F946" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+      <range end="0x0100" start="0x0100" />
+      <range end="0x0180" start="0x0180" />
+    </mirror>
+    <mirror>
+      <range end="0x0001" start="0x0001" />
+      <range end="0x0101" start="0x0101" />
+    </mirror>
+    <mirror>
+      <range end="0x0081" start="0x0081" />
+      <range end="0x0181" start="0x0181" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+      <range end="0x0104" start="0x0102" />
+      <range end="0x0184" start="0x0182" />
+    </mirror>
+    <mirror>
+      <range end="0x0006" start="0x0006" />
+      <range end="0x0106" start="0x0106" />
+    </mirror>
+    <mirror>
+      <range end="0x0086" start="0x0086" />
+      <range end="0x0186" start="0x0186" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+      <range end="0x010B" start="0x010A" />
+      <range end="0x018B" start="0x018A" />
+    </mirror>
+    <mirror>
+      <range end="0x007F" start="0x0070" />
+      <range end="0x00FF" start="0x00F0" />
+      <range end="0x017F" start="0x0170" />
+      <range end="0x01FF" start="0x01F0" />
+    </mirror>
+    <unused end="0x009B" start="0x009A" />
+    <unused end="0x011F" start="0x011F" />
+    <unused end="0x018F" start="0x018E" />
+    <unused end="0x019F" start="0x019F" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="33333333" name="PORTA" mclr="33333333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0007" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0008" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0009" access="33331333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111110" por="11111110" />
+    <sfr address="0x000C" access="33111333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x000D" access="33330303" name="PIR2" mclr="11110101" por="11110101" />
+    <combined address="0x000E" size="2" name="TMR1" />
+    <sfr address="0x000E" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x000F" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0010" access="33333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0011" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0012" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0013" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0014" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0015" size="2" name="CCPR1" />
+    <sfr address="0x0015" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0016" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0018" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0019" access="33333333" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x001A" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <combined address="0x001B" size="2" name="CCPR2" />
+    <sfr address="0x001B" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x001C" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x001D" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x001E" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x001F" access="33333333" name="ADCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0087" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0088" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0089" access="33331333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x008C" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x008D" access="33330303" name="PIE2" mclr="11110101" por="11110101" />
+    <sfr address="0x008E" access="00030033" name="PCON" mclr="00030033" por="00020044" />
+    <sfr address="0x008F" access="03331113" name="OSCCON" mclr="02210111" por="02210111" />
+    <sfr address="0x0090" access="00033333" name="OSCTUNE" mclr="00033333" por="00011111" />
+    <sfr address="0x0091" access="33333333" name="ANSEL" mclr="22222222" por="22222222" />
+    <sfr address="0x0092" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0093" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0094" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0095" access="33333333" name="WPUB" mclr="22222222" por="22222222" />
+    <sfr address="0x0096" access="33330000" name="IOCB" mclr="11110000" por="11110000" />
+    <sfr address="0x0097" access="00000033" name="CMCON1" mclr="00000021" por="00000021" />
+    <sfr address="0x0098" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0099" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x009C" access="11333333" name="CMCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x009D" access="30303333" name="VRCON" mclr="10101111" por="10101111" />
+    <sfr address="0x009E" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x009F" access="03330000" name="ADCON1" mclr="01110000" por="01110000" />
+    <sfr address="0x0105" access="00033333" name="WDTCON" mclr="00012111" por="00012111" />
+    <sfr address="0x0107" access="33533333" name="LCDCON" mclr="11121122" por="11121122" />
+    <sfr address="0x0108" access="31133333" name="LCDPS" mclr="11111111" por="11111111" />
+    <sfr address="0x0109" access="00130333" name="LVDCON" mclr="00110211" por="00110211" />
+    <sfr address="0x010C" access="33333333" name="EEDATL" mclr="33333333" por="11111111" />
+    <sfr address="0x010D" access="33333333" name="EEADRL" mclr="33333333" por="11111111" />
+    <sfr address="0x010E" access="00333333" name="EEDATH" mclr="00333333" por="00111111" />
+    <sfr address="0x010F" access="00033333" name="EEADRH" mclr="00033333" por="00011111" />
+    <sfr address="0x0110" access="33333333" name="LCDDATA0" mclr="33333333" por="00000000" />
+    <sfr address="0x0111" access="33333333" name="LCDDATA1" mclr="33333333" por="00000000" />
+    <sfr address="0x0112" access="33333333" name="LCDDATA2" mclr="33333333" por="00000000" />
+    <sfr address="0x0113" access="33333333" name="LCDDATA3" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="33333333" name="LCDDATA4" mclr="33333333" por="00000000" />
+    <sfr address="0x0115" access="33333333" name="LCDDATA5" mclr="33333333" por="00000000" />
+    <sfr address="0x0116" access="33333333" name="LCDDATA6" mclr="33333333" por="00000000" />
+    <sfr address="0x0117" access="33333333" name="LCDDATA7" mclr="33333333" por="00000000" />
+    <sfr address="0x0118" access="33333333" name="LCDDATA8" mclr="33333333" por="00000000" />
+    <sfr address="0x0119" access="33333333" name="LCDDATA9" mclr="33333333" por="00000000" />
+    <sfr address="0x011A" access="33333333" name="LCDDATA10" mclr="33333333" por="00000000" />
+    <sfr address="0x011B" access="33333333" name="LCDDATA11" mclr="33333333" por="00000000" />
+    <sfr address="0x011C" access="33333333" name="LCDSE0" mclr="33333333" por="11111111" />
+    <sfr address="0x011D" access="33333333" name="LCDSE1" mclr="33333333" por="11111111" />
+    <sfr address="0x011E" access="33333333" name="LCDSE2" mclr="33333333" por="11111111" />
+    <sfr address="0x0185" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0187" access="00333333" name="TRISG" mclr="11222222" por="11222222" />
+    <sfr address="0x0188" access="33333333" name="PORTF" mclr="33333333" por="00000000" />
+    <sfr address="0x0189" access="00333333" name="PORTG" mclr="00333333" por="00000000" />
+    <sfr address="0x018C" access="30003399" name="EECON1" mclr="30004111" por="00000111" />
+    <sfr address="0x018D" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0190" access="33333333" name="LCDDATA12" mclr="33333333" por="00000000" />
+    <sfr address="0x0191" access="33333333" name="LCDDATA13" mclr="33333333" por="00000000" />
+    <sfr address="0x0192" access="00000033" name="LCDDATA14" mclr="33333333" por="00000000" />
+    <sfr address="0x0193" access="33333333" name="LCDDATA15" mclr="33333333" por="00000000" />
+    <sfr address="0x0194" access="33333333" name="LCDDATA16" mclr="33333333" por="00000000" />
+    <sfr address="0x0195" access="00000033" name="LCDDATA17" mclr="33333333" por="00000000" />
+    <sfr address="0x0196" access="33333333" name="LCDDATA18" mclr="33333333" por="00000000" />
+    <sfr address="0x0197" access="33333333" name="LCDDATA19" mclr="33333333" por="00000000" />
+    <sfr address="0x0198" access="00000033" name="LCDDATA20" mclr="33333333" por="00000000" />
+    <sfr address="0x0199" access="33333333" name="LCDDATA21" mclr="33333333" por="00000000" />
+    <sfr address="0x019A" access="33333333" name="LCDDATA22" mclr="33333333" por="00000000" />
+    <sfr address="0x019B" access="00000033" name="LCDDATA23" mclr="33333333" por="00000000" />
+    <sfr address="0x019C" access="33333333" name="LCDSE3" mclr="33333333" por="11111111" />
+    <sfr address="0x019D" access="33333333" name="LCDSE4" mclr="33333333" por="11111111" />
+    <sfr address="0x019E" access="00000033" name="LCDSE5" mclr="33333333" por="11111111" />
+  </device>
+  <device nb_banks="1" name="16HV540" >
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="22222222" por="22222222" />
+    <sfr address="0x0003" access="33311333" name="STATUS" mclr="21144333" por="21122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="22233333" por="22200000" />
+    <sfr address="0x0005" access="00013333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0000" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="STKPTR" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00013333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0003" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0005" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0006" access="00333333" name="OPTION2" mclr="00222222" por="00222222" />
+  </device>
+  <device nb_banks="4" name="17C42" >
+    <unused end="0x010F" start="0x0100" />
+    <unused end="0x01FF" start="0x0118" />
+    <unused end="0x020F" start="0x0200" />
+    <unused end="0x02FF" start="0x0218" />
+    <unused end="0x030F" start="0x0300" />
+    <unused end="0x03FF" start="0x0318" />
+    <sfr address="0x0000" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="FSR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33333333" name="PCLATH" mclr="33333333" por="11111111" />
+    <sfr address="0x0004" access="33333333" name="ALUSTA" mclr="22223333" por="22220000" />
+    <sfr address="0x0005" access="33333330" name="T0STA" mclr="11111110" por="11111110" />
+    <sfr address="0x0006" access="00131100" name="CPUSTA" mclr="00224400" por="00222200" />
+    <sfr address="0x0007" access="13333333" name="INTSTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0008" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="FSR1" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <combined address="0x000B" size="2" name="TMR0" />
+    <sfr address="0x000B" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x000C" access="33333333" name="TMR0H" mclr="33333333" por="00000000" />
+    <combined address="0x000D" size="2" name="TBLPTR" />
+    <sfr address="0x000D" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x000E" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x000F" access="33333333" name="BSR" mclr="11111111" por="11111111" />
+    <sfr address="0x0010" access="30333311" name="PORTA" mclr="10333333" por="10000000" />
+    <sfr address="0x0011" access="33333333" name="DDRB" mclr="22222222" por="22222222" />
+    <sfr address="0x0012" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0013" access="33330111" name="RCSTA" mclr="11110113" por="11110110" />
+    <sfr address="0x0014" access="11111111" name="RCREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="33330013" name="TXSTA" mclr="11110023" por="11110020" />
+    <sfr address="0x0016" access="33333333" name="TXREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="SPBRG" mclr="33333333" por="00000000" />
+    <sfr address="0x0110" access="33333333" name="DDRC" mclr="22222222" por="22222222" />
+    <sfr address="0x0111" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0112" access="33333333" name="DDRD" mclr="22222222" por="22222222" />
+    <sfr address="0x0113" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="00000333" name="DDRE" mclr="00000222" por="00000222" />
+    <sfr address="0x0115" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x0116" access="33333311" name="PIR" mclr="11111121" por="11111121" />
+    <sfr address="0x0117" access="33333333" name="PIE" mclr="11111111" por="11111111" />
+    <sfr address="0x0210" access="33333333" name="TMR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0211" access="33333333" name="TMR2" mclr="33333333" por="00000000" />
+    <combined address="0x0212" size="2" name="TMR3" />
+    <sfr address="0x0212" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0213" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0214" access="33333333" name="PR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0215" access="33333333" name="PR2" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="PR3" />
+    <sfr address="0x0216" access="33333333" name="PR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="33333333" name="PR3H" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="CA1" />
+    <sfr address="0x0216" access="11111111" name="CA1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="11111111" name="CA1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0310" access="33000000" name="PW1DCL" mclr="33000000" por="00000000" />
+    <sfr address="0x0311" access="33300000" name="PW2DCL" mclr="33100000" por="00100000" />
+    <sfr address="0x0312" access="33333333" name="PW1DCH" mclr="33333333" por="00000000" />
+    <sfr address="0x0313" access="33333333" name="PW2DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0314" size="2" name="CA2" />
+    <sfr address="0x0314" access="11111111" name="CA2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0315" access="11111111" name="CA2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0316" access="33333333" name="TCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0317" access="11333333" name="TCON2" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="4" name="17C42A" >
+    <unused end="0x010F" start="0x0100" />
+    <unused end="0x011F" start="0x0118" />
+    <unused end="0x020F" start="0x0200" />
+    <unused end="0x02FF" start="0x0218" />
+    <unused end="0x030F" start="0x0300" />
+    <unused end="0x03FF" start="0x0318" />
+    <sfr address="0x0000" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="FSR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33333333" name="PCLATH" mclr="33333333" por="11111111" />
+    <sfr address="0x0004" access="33333333" name="ALUSTA" mclr="22223333" por="22220000" />
+    <sfr address="0x0005" access="33333330" name="T0STA" mclr="11111110" por="11111110" />
+    <sfr address="0x0006" access="00131100" name="CPUSTA" mclr="00224400" por="00222200" />
+    <sfr address="0x0007" access="13333333" name="INTSTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0008" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="FSR1" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <combined address="0x000B" size="2" name="TMR0" />
+    <sfr address="0x000B" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x000C" access="33333333" name="TMR0H" mclr="33333333" por="00000000" />
+    <combined address="0x000D" size="2" name="TBLPTR" />
+    <sfr address="0x000D" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x000E" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x000F" access="33333333" name="BSR" mclr="11111111" por="11111111" />
+    <sfr address="0x0010" access="30333311" name="PORTA" mclr="10333333" por="10000000" />
+    <sfr address="0x0011" access="33333333" name="DDRB" mclr="22222222" por="22222222" />
+    <sfr address="0x0012" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0013" access="33330111" name="RCSTA" mclr="11110113" por="11110110" />
+    <sfr address="0x0014" access="11111111" name="RCREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="33330013" name="TXSTA" mclr="11110023" por="11110020" />
+    <sfr address="0x0016" access="33333333" name="TXREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="SPBRG" mclr="33333333" por="00000000" />
+    <sfr address="0x0110" access="33333333" name="DDRC" mclr="22222222" por="22222222" />
+    <sfr address="0x0111" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0112" access="33333333" name="DDRD" mclr="22222222" por="22222222" />
+    <sfr address="0x0113" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="00000333" name="DDRE" mclr="00000222" por="00000222" />
+    <sfr address="0x0115" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x0116" access="33333311" name="PIR" mclr="11111121" por="11111121" />
+    <sfr address="0x0117" access="33333333" name="PIE" mclr="11111111" por="11111111" />
+    <sfr address="0x0210" access="33333333" name="TMR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0211" access="33333333" name="TMR2" mclr="33333333" por="00000000" />
+    <combined address="0x0212" size="2" name="TMR3" />
+    <sfr address="0x0212" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0213" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0214" access="33333333" name="PR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0215" access="33333333" name="PR2" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="PR3" />
+    <sfr address="0x0216" access="33333333" name="PR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="33333333" name="PR3H" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="CA1" />
+    <sfr address="0x0216" access="11111111" name="CA1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="11111111" name="CA1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0310" access="33000000" name="PW1DCL" mclr="33000000" por="00000000" />
+    <sfr address="0x0311" access="33300000" name="PW2DCL" mclr="33100000" por="00100000" />
+    <sfr address="0x0312" access="33333333" name="PW1DCH" mclr="33333333" por="00000000" />
+    <sfr address="0x0313" access="33333333" name="PW2DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0314" size="2" name="CA2" />
+    <sfr address="0x0314" access="11111111" name="CA2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0315" access="11111111" name="CA2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0316" access="33333333" name="TCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0317" access="11333333" name="TCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0018" size="2" name="PROD" />
+    <sfr address="0x0018" access="11111111" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0019" access="11111111" name="PRODH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="4" name="17C43" >
+    <unused end="0x010F" start="0x0100" />
+    <unused end="0x011F" start="0x0118" />
+    <unused end="0x020F" start="0x0200" />
+    <unused end="0x02FF" start="0x0218" />
+    <unused end="0x030F" start="0x0300" />
+    <unused end="0x03FF" start="0x0318" />
+    <sfr address="0x0000" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="FSR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33333333" name="PCLATH" mclr="33333333" por="11111111" />
+    <sfr address="0x0004" access="33333333" name="ALUSTA" mclr="22223333" por="22220000" />
+    <sfr address="0x0005" access="33333330" name="T0STA" mclr="11111110" por="11111110" />
+    <sfr address="0x0006" access="00131100" name="CPUSTA" mclr="00224400" por="00222200" />
+    <sfr address="0x0007" access="13333333" name="INTSTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0008" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="FSR1" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <combined address="0x000B" size="2" name="TMR0" />
+    <sfr address="0x000B" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x000C" access="33333333" name="TMR0H" mclr="33333333" por="00000000" />
+    <combined address="0x000D" size="2" name="TBLPTR" />
+    <sfr address="0x000D" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x000E" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x000F" access="33333333" name="BSR" mclr="11111111" por="11111111" />
+    <sfr address="0x0010" access="30333311" name="PORTA" mclr="10333333" por="10000000" />
+    <sfr address="0x0011" access="33333333" name="DDRB" mclr="22222222" por="22222222" />
+    <sfr address="0x0012" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0013" access="33330111" name="RCSTA" mclr="11110113" por="11110110" />
+    <sfr address="0x0014" access="11111111" name="RCREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="33330013" name="TXSTA" mclr="11110023" por="11110020" />
+    <sfr address="0x0016" access="33333333" name="TXREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="SPBRG" mclr="33333333" por="00000000" />
+    <sfr address="0x0110" access="33333333" name="DDRC" mclr="22222222" por="22222222" />
+    <sfr address="0x0111" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0112" access="33333333" name="DDRD" mclr="22222222" por="22222222" />
+    <sfr address="0x0113" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="00000333" name="DDRE" mclr="00000222" por="00000222" />
+    <sfr address="0x0115" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x0116" access="33333311" name="PIR" mclr="11111121" por="11111121" />
+    <sfr address="0x0117" access="33333333" name="PIE" mclr="11111111" por="11111111" />
+    <sfr address="0x0210" access="33333333" name="TMR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0211" access="33333333" name="TMR2" mclr="33333333" por="00000000" />
+    <combined address="0x0212" size="2" name="TMR3" />
+    <sfr address="0x0212" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0213" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0214" access="33333333" name="PR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0215" access="33333333" name="PR2" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="PR3" />
+    <sfr address="0x0216" access="33333333" name="PR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="33333333" name="PR3H" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="CA1" />
+    <sfr address="0x0216" access="11111111" name="CA1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="11111111" name="CA1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0310" access="33000000" name="PW1DCL" mclr="33000000" por="00000000" />
+    <sfr address="0x0311" access="33300000" name="PW2DCL" mclr="33100000" por="00100000" />
+    <sfr address="0x0312" access="33333333" name="PW1DCH" mclr="33333333" por="00000000" />
+    <sfr address="0x0313" access="33333333" name="PW2DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0314" size="2" name="CA2" />
+    <sfr address="0x0314" access="11111111" name="CA2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0315" access="11111111" name="CA2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0316" access="33333333" name="TCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0317" access="11333333" name="TCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0018" size="2" name="PROD" />
+    <sfr address="0x0018" access="11111111" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0019" access="11111111" name="PRODH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="4" name="17C44" >
+    <unused end="0x010F" start="0x0100" />
+    <unused end="0x011F" start="0x0118" />
+    <unused end="0x020F" start="0x0200" />
+    <unused end="0x02FF" start="0x0218" />
+    <unused end="0x030F" start="0x0300" />
+    <unused end="0x03FF" start="0x0318" />
+    <sfr address="0x0000" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="FSR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33333333" name="PCLATH" mclr="33333333" por="11111111" />
+    <sfr address="0x0004" access="33333333" name="ALUSTA" mclr="22223333" por="22220000" />
+    <sfr address="0x0005" access="33333330" name="T0STA" mclr="11111110" por="11111110" />
+    <sfr address="0x0006" access="00131100" name="CPUSTA" mclr="00224400" por="00222200" />
+    <sfr address="0x0007" access="13333333" name="INTSTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0008" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="FSR1" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <combined address="0x000B" size="2" name="TMR0" />
+    <sfr address="0x000B" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x000C" access="33333333" name="TMR0H" mclr="33333333" por="00000000" />
+    <combined address="0x000D" size="2" name="TBLPTR" />
+    <sfr address="0x000D" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x000E" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x000F" access="33333333" name="BSR" mclr="11111111" por="11111111" />
+    <sfr address="0x0010" access="30333311" name="PORTA" mclr="10333333" por="10000000" />
+    <sfr address="0x0011" access="33333333" name="DDRB" mclr="22222222" por="22222222" />
+    <sfr address="0x0012" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0013" access="33330111" name="RCSTA" mclr="11110113" por="11110110" />
+    <sfr address="0x0014" access="11111111" name="RCREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="33330013" name="TXSTA" mclr="11110023" por="11110020" />
+    <sfr address="0x0016" access="33333333" name="TXREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="SPBRG" mclr="33333333" por="00000000" />
+    <sfr address="0x0110" access="33333333" name="DDRC" mclr="22222222" por="22222222" />
+    <sfr address="0x0111" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0112" access="33333333" name="DDRD" mclr="22222222" por="22222222" />
+    <sfr address="0x0113" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="00000333" name="DDRE" mclr="00000222" por="00000222" />
+    <sfr address="0x0115" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x0116" access="33333311" name="PIR" mclr="11111121" por="11111121" />
+    <sfr address="0x0117" access="33333333" name="PIE" mclr="11111111" por="11111111" />
+    <sfr address="0x0210" access="33333333" name="TMR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0211" access="33333333" name="TMR2" mclr="33333333" por="00000000" />
+    <combined address="0x0212" size="2" name="TMR3" />
+    <sfr address="0x0212" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0213" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0214" access="33333333" name="PR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0215" access="33333333" name="PR2" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="PR3" />
+    <sfr address="0x0216" access="33333333" name="PR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="33333333" name="PR3H" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="CA1" />
+    <sfr address="0x0216" access="11111111" name="CA1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="11111111" name="CA1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0310" access="33000000" name="PW1DCL" mclr="33000000" por="00000000" />
+    <sfr address="0x0311" access="33300000" name="PW2DCL" mclr="33100000" por="00100000" />
+    <sfr address="0x0312" access="33333333" name="PW1DCH" mclr="33333333" por="00000000" />
+    <sfr address="0x0313" access="33333333" name="PW2DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0314" size="2" name="CA2" />
+    <sfr address="0x0314" access="11111111" name="CA2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0315" access="11111111" name="CA2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0316" access="33333333" name="TCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0317" access="11333333" name="TCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0018" size="2" name="PROD" />
+    <sfr address="0x0018" access="11111111" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0019" access="11111111" name="PRODH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="8" name="17C752" >
+    <unused end="0x0412" start="0x0412" />
+    <unused end="0x0617" start="0x0615" />
+    <unused end="0x0717" start="0x0717" />
+    <unused end="0x010F" start="0x0100" />
+    <unused end="0x011F" start="0x0118" />
+    <unused end="0x020F" start="0x0200" />
+    <unused end="0x021F" start="0x0218" />
+    <unused end="0x030F" start="0x0300" />
+    <unused end="0x03FF" start="0x0318" />
+    <unused end="0x040F" start="0x0400" />
+    <unused end="0x04FF" start="0x0418" />
+    <unused end="0x050F" start="0x0500" />
+    <unused end="0x05FF" start="0x0518" />
+    <unused end="0x060F" start="0x0600" />
+    <unused end="0x06FF" start="0x0618" />
+    <unused end="0x070F" start="0x0700" />
+    <unused end="0x07FF" start="0x0718" />
+    <sfr address="0x0000" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="FSR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33333333" name="PCLATH" mclr="33333333" por="11111111" />
+    <sfr address="0x0004" access="33333333" name="ALUSTA" mclr="22223333" por="22220000" />
+    <sfr address="0x0005" access="33333330" name="T0STA" mclr="11111110" por="11111110" />
+    <sfr address="0x0006" access="00131133" name="CPUSTA" mclr="00224433" por="00222244" />
+    <sfr address="0x0007" access="13333333" name="INTSTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0008" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="FSR1" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <combined address="0x000B" size="2" name="TMR0" />
+    <sfr address="0x000B" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x000C" access="33333333" name="TMR0H" mclr="33333333" por="00000000" />
+    <combined address="0x000D" size="2" name="TBLPTR" />
+    <sfr address="0x000D" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x000E" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x000F" access="33333333" name="BSR" mclr="11111111" por="11111111" />
+    <sfr address="0x0010" access="30113311" name="PORTA" mclr="10332233" por="10002200" />
+    <sfr address="0x0011" access="33333333" name="DDRB" mclr="22222222" por="22222222" />
+    <sfr address="0x0012" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0013" access="33330111" name="RCSTA1" mclr="11110113" por="11110110" />
+    <sfr address="0x0014" access="11111111" name="RCREG1" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="33330013" name="TXSTA1" mclr="11110023" por="11110020" />
+    <sfr address="0x0016" access="33333333" name="TXREG1" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0110" access="33333333" name="DDRC" mclr="22222222" por="22222222" />
+    <sfr address="0x0111" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0112" access="33333333" name="DDRD" mclr="22222222" por="22222222" />
+    <sfr address="0x0113" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="00003333" name="DDRE" mclr="00002222" por="00002222" />
+    <sfr address="0x0115" access="00003333" name="PORTE" mclr="00003333" por="00000000" />
+    <sfr address="0x0116" access="33333311" name="PIR1" mclr="31111121" por="01111121" />
+    <sfr address="0x0117" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0210" access="33333333" name="TMR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0211" access="33333333" name="TMR2" mclr="33333333" por="00000000" />
+    <combined address="0x0212" size="2" name="TMR3" />
+    <sfr address="0x0212" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0213" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0214" access="33333333" name="PR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0215" access="33333333" name="PR2" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="PR3" />
+    <sfr address="0x0216" access="33333333" name="PR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="33333333" name="PR3H" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="CA1" />
+    <sfr address="0x0216" access="11111111" name="CA1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="11111111" name="CA1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0310" access="33000000" name="PW1DCL" mclr="33000000" por="00000000" />
+    <sfr address="0x0311" access="33300000" name="PW2DCL" mclr="33100000" por="00100000" />
+    <sfr address="0x0312" access="33333333" name="PW1DCH" mclr="33333333" por="00000000" />
+    <sfr address="0x0313" access="33333333" name="PW2DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0314" size="2" name="CA2" />
+    <sfr address="0x0314" access="11111111" name="CA2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0315" access="11111111" name="CA2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0316" access="33333333" name="TCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0317" access="11333333" name="TCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0410" access="33303311" name="PIR2" mclr="11101121" por="11101121" />
+    <sfr address="0x0411" access="33303333" name="PIE2" mclr="11101111" por="11101111" />
+    <sfr address="0x0413" access="33330111" name="RCSTA2" mclr="11110113" por="11110110" />
+    <sfr address="0x0414" access="11111111" name="RCREG2" mclr="33333333" por="00000000" />
+    <sfr address="0x0415" access="33330013" name="TXSTA2" mclr="11110023" por="11110020" />
+    <sfr address="0x0416" access="33333333" name="TXREG2" mclr="33333333" por="00000000" />
+    <sfr address="0x0417" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0510" access="33333333" name="DDRF" mclr="22222222" por="22222222" />
+    <sfr address="0x0511" access="33333333" name="PORTF" mclr="11111111" por="11111111" />
+    <sfr address="0x0512" access="33333333" name="DDRG" mclr="22222222" por="22222222" />
+    <sfr address="0x0513" access="33333333" name="PORTG" mclr="33331111" por="00001111" />
+    <sfr address="0x0514" access="33330303" name="ADCON0" mclr="11110101" por="11110101" />
+    <sfr address="0x0515" access="33303333" name="ADCON1" mclr="11101111" por="11101111" />
+    <combined address="0x0516" size="2" name="ADRES" />
+    <sfr address="0x0516" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0517" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0610" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0611" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0612" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0613" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0614" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <combined address="0x0710" size="2" name="PW3DC" />
+    <sfr address="0x0710" access="33333333" name="PW3DCL" mclr="33100000" por="00100000" />
+    <sfr address="0x0711" access="33333333" name="PW3DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0712" size="2" name="CA3" />
+    <sfr address="0x0712" access="11111111" name="CA3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0713" access="11111111" name="CA3H" mclr="33333333" por="00000000" />
+    <combined address="0x0714" size="2" name="CA4" />
+    <sfr address="0x0714" access="11111111" name="CA4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0715" access="11111111" name="CA4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0716" access="01133333" name="TCON3" mclr="01111111" por="01111111" />
+    <combined address="0x0018" size="2" name="PROD" />
+    <sfr address="0x0018" access="11111111" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0019" access="11111111" name="PRODH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="8" name="17C756" >
+    <unused end="0x0412" start="0x0412" />
+    <unused end="0x0617" start="0x0615" />
+    <unused end="0x0717" start="0x0717" />
+    <unused end="0x010F" start="0x0100" />
+    <unused end="0x011F" start="0x0118" />
+    <unused end="0x020F" start="0x0200" />
+    <unused end="0x021F" start="0x0218" />
+    <unused end="0x030F" start="0x0300" />
+    <unused end="0x031F" start="0x0318" />
+    <unused end="0x040F" start="0x0400" />
+    <unused end="0x04FF" start="0x0418" />
+    <unused end="0x050F" start="0x0500" />
+    <unused end="0x05FF" start="0x0518" />
+    <unused end="0x060F" start="0x0600" />
+    <unused end="0x06FF" start="0x0618" />
+    <unused end="0x070F" start="0x0700" />
+    <unused end="0x07FF" start="0x0718" />
+    <sfr address="0x0000" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="FSR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33333333" name="PCLATH" mclr="33333333" por="11111111" />
+    <sfr address="0x0004" access="33333333" name="ALUSTA" mclr="22223333" por="22220000" />
+    <sfr address="0x0005" access="33333330" name="T0STA" mclr="11111110" por="11111110" />
+    <sfr address="0x0006" access="00131133" name="CPUSTA" mclr="00224433" por="00222244" />
+    <sfr address="0x0007" access="13333333" name="INTSTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0008" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="FSR1" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <combined address="0x000B" size="2" name="TMR0" />
+    <sfr address="0x000B" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x000C" access="33333333" name="TMR0H" mclr="33333333" por="00000000" />
+    <combined address="0x000D" size="2" name="TBLPTR" />
+    <sfr address="0x000D" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x000E" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x000F" access="33333333" name="BSR" mclr="11111111" por="11111111" />
+    <sfr address="0x0010" access="30113311" name="PORTA" mclr="10332233" por="10002200" />
+    <sfr address="0x0011" access="33333333" name="DDRB" mclr="22222222" por="22222222" />
+    <sfr address="0x0012" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0013" access="33330111" name="RCSTA1" mclr="11110113" por="11110110" />
+    <sfr address="0x0014" access="11111111" name="RCREG1" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="33330013" name="TXSTA1" mclr="11110023" por="11110020" />
+    <sfr address="0x0016" access="33333333" name="TXREG1" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0110" access="33333333" name="DDRC" mclr="22222222" por="22222222" />
+    <sfr address="0x0111" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0112" access="33333333" name="DDRD" mclr="22222222" por="22222222" />
+    <sfr address="0x0113" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="00003333" name="DDRE" mclr="00002222" por="00002222" />
+    <sfr address="0x0115" access="00003333" name="PORTE" mclr="00003333" por="00000000" />
+    <sfr address="0x0116" access="33333311" name="PIR1" mclr="31111121" por="01111121" />
+    <sfr address="0x0117" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0210" access="33333333" name="TMR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0211" access="33333333" name="TMR2" mclr="33333333" por="00000000" />
+    <combined address="0x0212" size="2" name="TMR3" />
+    <sfr address="0x0212" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0213" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0214" access="33333333" name="PR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0215" access="33333333" name="PR2" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="PR3" />
+    <sfr address="0x0216" access="33333333" name="PR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="33333333" name="PR3H" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="CA1" />
+    <sfr address="0x0216" access="11111111" name="CA1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="11111111" name="CA1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0310" access="33000000" name="PW1DCL" mclr="33000000" por="00000000" />
+    <sfr address="0x0311" access="33300000" name="PW2DCL" mclr="33100000" por="00100000" />
+    <sfr address="0x0312" access="33333333" name="PW1DCH" mclr="33333333" por="00000000" />
+    <sfr address="0x0313" access="33333333" name="PW2DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0314" size="2" name="CA2" />
+    <sfr address="0x0314" access="11111111" name="CA2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0315" access="11111111" name="CA2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0316" access="33333333" name="TCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0317" access="11333333" name="TCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0410" access="33303311" name="PIR2" mclr="11101121" por="11101121" />
+    <sfr address="0x0411" access="33303333" name="PIE2" mclr="11101111" por="11101111" />
+    <sfr address="0x0413" access="33330111" name="RCSTA2" mclr="11110113" por="11110110" />
+    <sfr address="0x0414" access="11111111" name="RCREG2" mclr="33333333" por="00000000" />
+    <sfr address="0x0415" access="33330013" name="TXSTA2" mclr="11110023" por="11110020" />
+    <sfr address="0x0416" access="33333333" name="TXREG2" mclr="33333333" por="00000000" />
+    <sfr address="0x0417" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0510" access="33333333" name="DDRF" mclr="22222222" por="22222222" />
+    <sfr address="0x0511" access="33333333" name="PORTF" mclr="11111111" por="11111111" />
+    <sfr address="0x0512" access="33333333" name="DDRG" mclr="22222222" por="22222222" />
+    <sfr address="0x0513" access="33333333" name="PORTG" mclr="33331111" por="00001111" />
+    <sfr address="0x0514" access="33330303" name="ADCON0" mclr="11110101" por="11110101" />
+    <sfr address="0x0515" access="33303333" name="ADCON1" mclr="11101111" por="11101111" />
+    <combined address="0x0516" size="2" name="ADRES" />
+    <sfr address="0x0516" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0517" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0610" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0611" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0612" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0613" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0614" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <combined address="0x0710" size="2" name="PW3DC" />
+    <sfr address="0x0710" access="33333333" name="PW3DCL" mclr="33100000" por="00100000" />
+    <sfr address="0x0711" access="33333333" name="PW3DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0712" size="2" name="CA3" />
+    <sfr address="0x0712" access="11111111" name="CA3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0713" access="11111111" name="CA3H" mclr="33333333" por="00000000" />
+    <combined address="0x0714" size="2" name="CA4" />
+    <sfr address="0x0714" access="11111111" name="CA4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0715" access="11111111" name="CA4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0716" access="01133333" name="TCON3" mclr="01111111" por="01111111" />
+    <combined address="0x0018" size="2" name="PROD" />
+    <sfr address="0x0018" access="11111111" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0019" access="11111111" name="PRODH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="8" name="17C756A" >
+    <unused end="0x0412" start="0x0412" />
+    <unused end="0x0617" start="0x0615" />
+    <unused end="0x0717" start="0x0717" />
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+    <unused end="0x07FF" start="0x0718" />
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+    <sfr address="0x0001" access="33333333" name="FSR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33333333" name="PCLATH" mclr="33333333" por="11111111" />
+    <sfr address="0x0004" access="33333333" name="ALUSTA" mclr="22223333" por="22220000" />
+    <sfr address="0x0005" access="33333330" name="T0STA" mclr="11111110" por="11111110" />
+    <sfr address="0x0006" access="00131133" name="CPUSTA" mclr="00224433" por="00222244" />
+    <sfr address="0x0007" access="13333333" name="INTSTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0008" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="FSR1" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <combined address="0x000B" size="2" name="TMR0" />
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+    <sfr address="0x000C" access="33333333" name="TMR0H" mclr="33333333" por="00000000" />
+    <combined address="0x000D" size="2" name="TBLPTR" />
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+    <sfr address="0x000E" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x000F" access="33333333" name="BSR" mclr="11111111" por="11111111" />
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+    <sfr address="0x0012" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
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+    <sfr address="0x0014" access="11111111" name="RCREG1" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="33330013" name="TXSTA1" mclr="11110023" por="11110020" />
+    <sfr address="0x0016" access="33333333" name="TXREG1" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0110" access="33333333" name="DDRC" mclr="22222222" por="22222222" />
+    <sfr address="0x0111" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
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+    <sfr address="0x0113" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
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+    <sfr address="0x0115" access="00003333" name="PORTE" mclr="00003333" por="00000000" />
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+    <sfr address="0x0211" access="33333333" name="TMR2" mclr="33333333" por="00000000" />
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+    <sfr address="0x0215" access="33333333" name="PR2" mclr="33333333" por="00000000" />
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+    <sfr address="0x0217" access="33333333" name="PR3H" mclr="33333333" por="00000000" />
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+    <sfr address="0x0313" access="33333333" name="PW2DCH" mclr="33333333" por="00000000" />
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+    <sfr address="0x0413" access="33330111" name="RCSTA2" mclr="11110113" por="11110110" />
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+    <sfr address="0x0416" access="33333333" name="TXREG2" mclr="33333333" por="00000000" />
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+    <sfr address="0x0511" access="33333333" name="PORTF" mclr="11111111" por="11111111" />
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+    <sfr address="0x0517" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
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+    <sfr address="0x0611" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0612" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0613" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0614" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <combined address="0x0710" size="2" name="PW3DC" />
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+    <sfr address="0x0711" access="33333333" name="PW3DCH" mclr="33333333" por="00000000" />
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+    <sfr address="0x0713" access="11111111" name="CA3H" mclr="33333333" por="00000000" />
+    <combined address="0x0714" size="2" name="CA4" />
+    <sfr address="0x0714" access="11111111" name="CA4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0715" access="11111111" name="CA4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0716" access="01133333" name="TCON3" mclr="01111111" por="01111111" />
+    <combined address="0x0018" size="2" name="PROD" />
+    <sfr address="0x0018" access="11111111" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0019" access="11111111" name="PRODH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="9" name="17C762" >
+    <unused end="0x0412" start="0x0412" />
+    <unused end="0x0617" start="0x0615" />
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+    <unused end="0x080F" start="0x0800" />
+    <unused end="0x08FF" start="0x0818" />
+    <sfr address="0x0000" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="FSR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33333333" name="PCLATH" mclr="33333333" por="11111111" />
+    <sfr address="0x0004" access="33333333" name="ALUSTA" mclr="22223333" por="22220000" />
+    <sfr address="0x0005" access="33333330" name="T0STA" mclr="11111110" por="11111110" />
+    <sfr address="0x0006" access="00131133" name="CPUSTA" mclr="00224433" por="00222244" />
+    <sfr address="0x0007" access="13333333" name="INTSTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0008" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="FSR1" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="33333333" name="WREG" mclr="33333333" por="00000000" />
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+    <sfr address="0x000C" access="33333333" name="TMR0H" mclr="33333333" por="00000000" />
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+    <sfr address="0x000E" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
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+    <sfr address="0x0012" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
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+    <sfr address="0x0014" access="11111111" name="RCREG1" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="33330013" name="TXSTA1" mclr="11110023" por="11110020" />
+    <sfr address="0x0016" access="33333333" name="TXREG1" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0110" access="33333333" name="DDRC" mclr="22222222" por="22222222" />
+    <sfr address="0x0111" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
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+    <sfr address="0x0113" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="00003333" name="DDRE" mclr="00002222" por="00002222" />
+    <sfr address="0x0115" access="00003333" name="PORTE" mclr="00003333" por="00000000" />
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+    <sfr address="0x0117" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0210" access="33333333" name="TMR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0211" access="33333333" name="TMR2" mclr="33333333" por="00000000" />
+    <combined address="0x0212" size="2" name="TMR3" />
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+    <sfr address="0x0217" access="33333333" name="PR3H" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="CA1" />
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+    <sfr address="0x0313" access="33333333" name="PW2DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0314" size="2" name="CA2" />
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+    <sfr address="0x0315" access="11111111" name="CA2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0316" access="33333333" name="TCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0317" access="11333333" name="TCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0410" access="33303311" name="PIR2" mclr="11101121" por="11101121" />
+    <sfr address="0x0411" access="33303333" name="PIE2" mclr="11101111" por="11101111" />
+    <sfr address="0x0413" access="33330111" name="RCSTA2" mclr="11110113" por="11110110" />
+    <sfr address="0x0414" access="11111111" name="RCREG2" mclr="33333333" por="00000000" />
+    <sfr address="0x0415" access="33330013" name="TXSTA2" mclr="11110023" por="11110020" />
+    <sfr address="0x0416" access="33333333" name="TXREG2" mclr="33333333" por="00000000" />
+    <sfr address="0x0417" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0510" access="33333333" name="DDRF" mclr="22222222" por="22222222" />
+    <sfr address="0x0511" access="33333333" name="PORTF" mclr="11111111" por="11111111" />
+    <sfr address="0x0512" access="33333333" name="DDRG" mclr="22222222" por="22222222" />
+    <sfr address="0x0513" access="33333333" name="PORTG" mclr="33331111" por="00001111" />
+    <sfr address="0x0514" access="33330303" name="ADCON0" mclr="11110101" por="11110101" />
+    <sfr address="0x0515" access="33303333" name="ADCON1" mclr="11101111" por="11101111" />
+    <combined address="0x0516" size="2" name="ADRES" />
+    <sfr address="0x0516" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0517" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0610" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0611" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0612" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0613" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0614" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <combined address="0x0710" size="2" name="PW3DC" />
+    <sfr address="0x0710" access="33333333" name="PW3DCL" mclr="33100000" por="00100000" />
+    <sfr address="0x0711" access="33333333" name="PW3DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0712" size="2" name="CA3" />
+    <sfr address="0x0712" access="11111111" name="CA3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0713" access="11111111" name="CA3H" mclr="33333333" por="00000000" />
+    <combined address="0x0714" size="2" name="CA4" />
+    <sfr address="0x0714" access="11111111" name="CA4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0715" access="11111111" name="CA4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0716" access="01133333" name="TCON3" mclr="01111111" por="01111111" />
+    <sfr address="0x0810" access="33333333" name="DDRH" mclr="22222222" por="22222222" />
+    <sfr address="0x0811" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0812" access="33333333" name="DDRJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0813" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <combined address="0x0018" size="2" name="PROD" />
+    <sfr address="0x0018" access="11111111" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0019" access="11111111" name="PRODH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="9" name="17C766" >
+    <unused end="0x0412" start="0x0412" />
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+    <unused end="0x080F" start="0x0800" />
+    <unused end="0x08FF" start="0x0818" />
+    <sfr address="0x0000" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="FSR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33333333" name="PCLATH" mclr="33333333" por="11111111" />
+    <sfr address="0x0004" access="33333333" name="ALUSTA" mclr="22223333" por="22220000" />
+    <sfr address="0x0005" access="33333330" name="T0STA" mclr="11111110" por="11111110" />
+    <sfr address="0x0006" access="00131133" name="CPUSTA" mclr="00224433" por="00222244" />
+    <sfr address="0x0007" access="13333333" name="INTSTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0008" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="FSR1" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <combined address="0x000B" size="2" name="TMR0" />
+    <sfr address="0x000B" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x000C" access="33333333" name="TMR0H" mclr="33333333" por="00000000" />
+    <combined address="0x000D" size="2" name="TBLPTR" />
+    <sfr address="0x000D" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x000E" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x000F" access="33333333" name="BSR" mclr="11111111" por="11111111" />
+    <sfr address="0x0010" access="30113311" name="PORTA" mclr="10332233" por="10002200" />
+    <sfr address="0x0011" access="33333333" name="DDRB" mclr="22222222" por="22222222" />
+    <sfr address="0x0012" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0013" access="33330111" name="RCSTA1" mclr="11110113" por="11110110" />
+    <sfr address="0x0014" access="11111111" name="RCREG1" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="33330013" name="TXSTA1" mclr="11110023" por="11110020" />
+    <sfr address="0x0016" access="33333333" name="TXREG1" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0110" access="33333333" name="DDRC" mclr="22222222" por="22222222" />
+    <sfr address="0x0111" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0112" access="33333333" name="DDRD" mclr="22222222" por="22222222" />
+    <sfr address="0x0113" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="00003333" name="DDRE" mclr="00002222" por="00002222" />
+    <sfr address="0x0115" access="00003333" name="PORTE" mclr="00003333" por="00000000" />
+    <sfr address="0x0116" access="33333311" name="PIR1" mclr="31111121" por="01111121" />
+    <sfr address="0x0117" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0210" access="33333333" name="TMR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0211" access="33333333" name="TMR2" mclr="33333333" por="00000000" />
+    <combined address="0x0212" size="2" name="TMR3" />
+    <sfr address="0x0212" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0213" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0214" access="33333333" name="PR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0215" access="33333333" name="PR2" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="PR3" />
+    <sfr address="0x0216" access="33333333" name="PR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="33333333" name="PR3H" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="CA1" />
+    <sfr address="0x0216" access="11111111" name="CA1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="11111111" name="CA1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0310" access="33000000" name="PW1DCL" mclr="33000000" por="00000000" />
+    <sfr address="0x0311" access="33300000" name="PW2DCL" mclr="33100000" por="00100000" />
+    <sfr address="0x0312" access="33333333" name="PW1DCH" mclr="33333333" por="00000000" />
+    <sfr address="0x0313" access="33333333" name="PW2DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0314" size="2" name="CA2" />
+    <sfr address="0x0314" access="11111111" name="CA2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0315" access="11111111" name="CA2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0316" access="33333333" name="TCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0317" access="11333333" name="TCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0410" access="33303311" name="PIR2" mclr="11101121" por="11101121" />
+    <sfr address="0x0411" access="33303333" name="PIE2" mclr="11101111" por="11101111" />
+    <sfr address="0x0413" access="33330111" name="RCSTA2" mclr="11110113" por="11110110" />
+    <sfr address="0x0414" access="11111111" name="RCREG2" mclr="33333333" por="00000000" />
+    <sfr address="0x0415" access="33330013" name="TXSTA2" mclr="11110023" por="11110020" />
+    <sfr address="0x0416" access="33333333" name="TXREG2" mclr="33333333" por="00000000" />
+    <sfr address="0x0417" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0510" access="33333333" name="DDRF" mclr="22222222" por="22222222" />
+    <sfr address="0x0511" access="33333333" name="PORTF" mclr="11111111" por="11111111" />
+    <sfr address="0x0512" access="33333333" name="DDRG" mclr="22222222" por="22222222" />
+    <sfr address="0x0513" access="33333333" name="PORTG" mclr="33331111" por="00001111" />
+    <sfr address="0x0514" access="33330303" name="ADCON0" mclr="11110101" por="11110101" />
+    <sfr address="0x0515" access="33303333" name="ADCON1" mclr="11101111" por="11101111" />
+    <combined address="0x0516" size="2" name="ADRES" />
+    <sfr address="0x0516" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0517" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0610" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0611" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0612" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0613" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0614" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <combined address="0x0710" size="2" name="PW3DC" />
+    <sfr address="0x0710" access="33333333" name="PW3DCL" mclr="33100000" por="00100000" />
+    <sfr address="0x0711" access="33333333" name="PW3DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0712" size="2" name="CA3" />
+    <sfr address="0x0712" access="11111111" name="CA3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0713" access="11111111" name="CA3H" mclr="33333333" por="00000000" />
+    <combined address="0x0714" size="2" name="CA4" />
+    <sfr address="0x0714" access="11111111" name="CA4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0715" access="11111111" name="CA4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0716" access="01133333" name="TCON3" mclr="01111111" por="01111111" />
+    <sfr address="0x0810" access="33333333" name="DDRH" mclr="22222222" por="22222222" />
+    <sfr address="0x0811" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0812" access="33333333" name="DDRJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0813" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <combined address="0x0018" size="2" name="PROD" />
+    <sfr address="0x0018" access="11111111" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0019" access="11111111" name="PRODH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="4" name="17CR42" >
+    <unused end="0x010F" start="0x0100" />
+    <unused end="0x011F" start="0x0118" />
+    <unused end="0x020F" start="0x0200" />
+    <unused end="0x02FF" start="0x0218" />
+    <unused end="0x030F" start="0x0300" />
+    <unused end="0x03FF" start="0x0318" />
+    <sfr address="0x0000" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="FSR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33333333" name="PCLATH" mclr="33333333" por="11111111" />
+    <sfr address="0x0004" access="33333333" name="ALUSTA" mclr="22223333" por="22220000" />
+    <sfr address="0x0005" access="33333330" name="T0STA" mclr="11111110" por="11111110" />
+    <sfr address="0x0006" access="00131100" name="CPUSTA" mclr="00224400" por="00222200" />
+    <sfr address="0x0007" access="13333333" name="INTSTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0008" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="FSR1" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <combined address="0x000B" size="2" name="TMR0" />
+    <sfr address="0x000B" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x000C" access="33333333" name="TMR0H" mclr="33333333" por="00000000" />
+    <combined address="0x000D" size="2" name="TBLPTR" />
+    <sfr address="0x000D" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x000E" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x000F" access="33333333" name="BSR" mclr="11111111" por="11111111" />
+    <sfr address="0x0010" access="30333311" name="PORTA" mclr="10333333" por="10000000" />
+    <sfr address="0x0011" access="33333333" name="DDRB" mclr="22222222" por="22222222" />
+    <sfr address="0x0012" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0013" access="33330111" name="RCSTA" mclr="11110113" por="11110110" />
+    <sfr address="0x0014" access="11111111" name="RCREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="33330013" name="TXSTA" mclr="11110023" por="11110020" />
+    <sfr address="0x0016" access="33333333" name="TXREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="SPBRG" mclr="33333333" por="00000000" />
+    <sfr address="0x0110" access="33333333" name="DDRC" mclr="22222222" por="22222222" />
+    <sfr address="0x0111" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0112" access="33333333" name="DDRD" mclr="22222222" por="22222222" />
+    <sfr address="0x0113" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="00000333" name="DDRE" mclr="00000222" por="00000222" />
+    <sfr address="0x0115" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x0116" access="33333311" name="PIR" mclr="11111121" por="11111121" />
+    <sfr address="0x0117" access="33333333" name="PIE" mclr="11111111" por="11111111" />
+    <sfr address="0x0210" access="33333333" name="TMR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0211" access="33333333" name="TMR2" mclr="33333333" por="00000000" />
+    <combined address="0x0212" size="2" name="TMR3" />
+    <sfr address="0x0212" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0213" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0214" access="33333333" name="PR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0215" access="33333333" name="PR2" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="PR3" />
+    <sfr address="0x0216" access="33333333" name="PR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="33333333" name="PR3H" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="CA1" />
+    <sfr address="0x0216" access="11111111" name="CA1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="11111111" name="CA1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0310" access="33000000" name="PW1DCL" mclr="33000000" por="00000000" />
+    <sfr address="0x0311" access="33300000" name="PW2DCL" mclr="33100000" por="00100000" />
+    <sfr address="0x0312" access="33333333" name="PW1DCH" mclr="33333333" por="00000000" />
+    <sfr address="0x0313" access="33333333" name="PW2DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0314" size="2" name="CA2" />
+    <sfr address="0x0314" access="11111111" name="CA2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0315" access="11111111" name="CA2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0316" access="33333333" name="TCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0317" access="11333333" name="TCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0018" size="2" name="PROD" />
+    <sfr address="0x0018" access="11111111" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0019" access="11111111" name="PRODH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="4" name="17CR43" >
+    <unused end="0x010F" start="0x0100" />
+    <unused end="0x011F" start="0x0118" />
+    <unused end="0x020F" start="0x0200" />
+    <unused end="0x02FF" start="0x0218" />
+    <unused end="0x030F" start="0x0300" />
+    <unused end="0x03FF" start="0x0318" />
+    <sfr address="0x0000" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="FSR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33333333" name="PCLATH" mclr="33333333" por="11111111" />
+    <sfr address="0x0004" access="33333333" name="ALUSTA" mclr="22223333" por="22220000" />
+    <sfr address="0x0005" access="33333330" name="T0STA" mclr="11111110" por="11111110" />
+    <sfr address="0x0006" access="00131100" name="CPUSTA" mclr="00224400" por="00222200" />
+    <sfr address="0x0007" access="13333333" name="INTSTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0008" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0009" access="33333333" name="FSR1" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <combined address="0x000B" size="2" name="TMR0" />
+    <sfr address="0x000B" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x000C" access="33333333" name="TMR0H" mclr="33333333" por="00000000" />
+    <combined address="0x000D" size="2" name="TBLPTR" />
+    <sfr address="0x000D" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x000E" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x000F" access="33333333" name="BSR" mclr="11111111" por="11111111" />
+    <sfr address="0x0010" access="30333311" name="PORTA" mclr="10333333" por="10000000" />
+    <sfr address="0x0011" access="33333333" name="DDRB" mclr="22222222" por="22222222" />
+    <sfr address="0x0012" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0013" access="33330111" name="RCSTA" mclr="11110113" por="11110110" />
+    <sfr address="0x0014" access="11111111" name="RCREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0015" access="33330013" name="TXSTA" mclr="11110023" por="11110020" />
+    <sfr address="0x0016" access="33333333" name="TXREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0017" access="33333333" name="SPBRG" mclr="33333333" por="00000000" />
+    <sfr address="0x0110" access="33333333" name="DDRC" mclr="22222222" por="22222222" />
+    <sfr address="0x0111" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0112" access="33333333" name="DDRD" mclr="22222222" por="22222222" />
+    <sfr address="0x0113" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0114" access="00000333" name="DDRE" mclr="00000222" por="00000222" />
+    <sfr address="0x0115" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x0116" access="33333311" name="PIR" mclr="11111121" por="11111121" />
+    <sfr address="0x0117" access="33333333" name="PIE" mclr="11111111" por="11111111" />
+    <sfr address="0x0210" access="33333333" name="TMR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0211" access="33333333" name="TMR2" mclr="33333333" por="00000000" />
+    <combined address="0x0212" size="2" name="TMR3" />
+    <sfr address="0x0212" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0213" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0214" access="33333333" name="PR1" mclr="33333333" por="00000000" />
+    <sfr address="0x0215" access="33333333" name="PR2" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="PR3" />
+    <sfr address="0x0216" access="33333333" name="PR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="33333333" name="PR3H" mclr="33333333" por="00000000" />
+    <combined address="0x0216" size="2" name="CA1" />
+    <sfr address="0x0216" access="11111111" name="CA1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0217" access="11111111" name="CA1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0310" access="33000000" name="PW1DCL" mclr="33000000" por="00000000" />
+    <sfr address="0x0311" access="33300000" name="PW2DCL" mclr="33100000" por="00100000" />
+    <sfr address="0x0312" access="33333333" name="PW1DCH" mclr="33333333" por="00000000" />
+    <sfr address="0x0313" access="33333333" name="PW2DCH" mclr="33333333" por="00000000" />
+    <combined address="0x0314" size="2" name="CA2" />
+    <sfr address="0x0314" access="11111111" name="CA2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0315" access="11111111" name="CA2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0316" access="33333333" name="TCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0317" access="11333333" name="TCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0018" size="2" name="PROD" />
+    <sfr address="0x0018" access="11111111" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0019" access="11111111" name="PRODH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18C242" unused_bank_mask="0x7FFC" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F83" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9C" start="0x0F95" />
+    <unused end="0x0FAA" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="11024433" por="11022211" />
+    <sfr address="0x0FA2" access="00003333" name="IPR2" mclr="00002222" por="00002222" />
+    <sfr address="0x0FA1" access="00003333" name="PIR2" mclr="00001111" por="00001111" />
+    <sfr address="0x0FA0" access="00003333" name="PIE2" mclr="00001111" por="00001111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18C252" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F83" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9C" start="0x0F95" />
+    <unused end="0x0FAA" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="11024433" por="11022211" />
+    <sfr address="0x0FA2" access="00003333" name="IPR2" mclr="00002222" por="00002222" />
+    <sfr address="0x0FA1" access="00003333" name="PIR2" mclr="00001111" por="00001111" />
+    <sfr address="0x0FA0" access="00003333" name="PIE2" mclr="00001111" por="00001111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18C442" unused_bank_mask="0x7FFC" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9C" start="0x0F97" />
+    <unused end="0x0FAA" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="11024433" por="11022211" />
+    <sfr address="0x0FA2" access="00003333" name="IPR2" mclr="00002222" por="00002222" />
+    <sfr address="0x0FA1" access="00003333" name="PIR2" mclr="00001111" por="00001111" />
+    <sfr address="0x0FA0" access="00003333" name="PIE2" mclr="00001111" por="00001111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00000333" name="PORTE" mclr="00000111" por="00000111" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18C452" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9C" start="0x0F97" />
+    <unused end="0x0FAA" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="11024433" por="11022211" />
+    <sfr address="0x0FA2" access="00003333" name="IPR2" mclr="00002222" por="00002222" />
+    <sfr address="0x0FA1" access="00003333" name="PIR2" mclr="00001111" por="00001111" />
+    <sfr address="0x0FA0" access="00003333" name="PIE2" mclr="00001111" por="00001111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00000333" name="PORTE" mclr="00000111" por="00000111" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="11330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18C601" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9B" start="0x0F99" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FB5" start="0x0FB4" />
+    <unused end="0x0FB9" start="0x0FB6" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00003333" name="OSCCON" mclr="00003331" por="00001111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00003333" name="WDTCON" mclr="00000000" por="00001111" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10022211" />
+    <sfr address="0x0FA7" access="33333333" name="CSEL2" mclr="33333333" por="22222222" />
+    <sfr address="0x0FA6" access="33333333" name="CSELIO" mclr="33333333" por="22222222" />
+    <sfr address="0x0FA2" access="00003333" name="IPR2" mclr="00002222" por="00002222" />
+    <sfr address="0x0FA1" access="00003333" name="PIR2" mclr="00001111" por="00001111" />
+    <sfr address="0x0FA0" access="00003333" name="PIE2" mclr="00001111" por="00001111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9C" access="33330033" name="MEMCON" mclr="11110011" por="11110011" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00033333" name="PORTG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30000333" name="ADCON2" mclr="10000111" por="10000111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="00000022" name="PSPCON" mclr="00000011" por="00000011" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18C658" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F2F" start="0x0F2F" />
+    <unused end="0x0F3F" start="0x0F3F" />
+    <unused end="0x0F4F" start="0x0F4F" />
+    <unused end="0x0F5F" start="0x0F5F" />
+    <unused end="0x0F7F" start="0x0F77" />
+    <unused end="0x0F9B" start="0x0F9B" />
+    <unused end="0x0FAA" start="0x0FA6" />
+    <unused end="0x0FB9" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="11044433" por="11022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33333333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="03003333" name="IPR2" mclr="02002222" por="02002222" />
+    <sfr address="0x0FA1" access="03003333" name="PIR2" mclr="01001111" por="01001111" />
+    <sfr address="0x0FA0" access="03003333" name="PIE2" mclr="01001111" por="01001111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00033333" name="PORTG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30000333" name="ADCON2" mclr="10000111" por="10000111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0F76" access="11111111" name="TXERRCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F75" access="11111111" name="RXERRCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F74" access="55111111" name="COMSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F73" access="33330000" name="CIOCON" mclr="21110000" por="21110000" />
+    <sfr address="0x0F72" access="03000333" name="BRGCON3" mclr="01000111" por="01000111" />
+    <sfr address="0x0F71" access="33333333" name="BRGCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F70" access="33333333" name="BRGCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333330" name="CANCON" mclr="33333330" por="00000000" />
+    <sfr address="0x0F6E" access="11101110" name="CANSTAT" mclr="33333330" por="00000000" />
+    <sfr address="0x0F6D" access="33333333" name="RXB0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6C" access="33333333" name="RXB0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6B" access="33333333" name="RXB0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="RXB0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F69" access="33333333" name="RXB0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="RXB0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="RXB0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="RXB0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="03333333" name="RXB0DLC" mclr="13333333" por="10000000" />
+    <sfr address="0x0F64" access="33333333" name="RXB0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F63" access="33333333" name="RXB0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F62" access="33333033" name="RXB0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0F61" access="33333333" name="RXB0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F60" access="53301313" name="RXB0CON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F5E" access="11101110" name="CANSTATRO0" mclr="33303330" por="00000000" />
+    <sfr address="0x0F5D" access="33333333" name="RXB1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5C" access="33333333" name="RXB1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5B" access="33333333" name="RXB1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5A" access="33333333" name="RXB1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F59" access="33333333" name="RXB1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F58" access="33333333" name="RXB1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F57" access="33333333" name="RXB1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F56" access="33333333" name="RXB1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F55" access="03333333" name="RXB1DLC" mclr="13333333" por="10000000" />
+    <sfr address="0x0F54" access="33333333" name="RXB1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F53" access="33333333" name="RXB1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F52" access="33333033" name="RXB1SIDL" mclr="33333133" por="00000100" />
+    <sfr address="0x0F51" access="33333333" name="RXB1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F50" access="53301111" name="RXB1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F4E" access="11101110" name="CANSTATRO1" mclr="33303330" por="00000000" />
+    <sfr address="0x0F4D" access="33333333" name="TXB0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F4C" access="33333333" name="TXB0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F4B" access="33333333" name="TXB0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F4A" access="33333333" name="TXB0D4" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F48" access="33333333" name="TXB0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F47" access="33333333" name="TXB0D1" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F45" access="03003333" name="TXB0DLC" mclr="13113333" por="10110000" />
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+    <sfr address="0x0F42" access="33333333" name="TXB0SIDL" mclr="33313133" por="00010100" />
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+    <sfr address="0x0F40" access="01113033" name="TXB0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F3E" access="11101110" name="CANSTATRO2" mclr="33303330" por="00000000" />
+    <sfr address="0x0F3D" access="33333333" name="TXB1D7" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F3A" access="33333333" name="TXB1D4" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F38" access="33333333" name="TXB1D2" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F34" access="33333333" name="TXB1EIDL" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F32" access="33333333" name="TXB1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F31" access="33333333" name="TXB1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F30" access="01113033" name="TXB1CON" mclr="03333033" por="01111011" />
+    <sfr address="0x0F2E" access="11101110" name="CANSTATRO3" mclr="33303330" por="00000000" />
+    <sfr address="0x0F2D" access="33333333" name="TXB2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2C" access="33333333" name="TXB2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2B" access="33333333" name="TXB2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2A" access="33333333" name="TXB2D4" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F1F" access="33333333" name="RXM1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1E" access="33333333" name="RXM1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1D" access="33300033" name="RXM1SIDL" mclr="33300033" por="00000000" />
+    <sfr address="0x0F1C" access="33333333" name="RXM1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1B" access="33333333" name="RXM0EIDL" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F19" access="33300033" name="RXM0SIDL" mclr="33300033" por="00000000" />
+    <sfr address="0x0F18" access="33333333" name="RXM0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F17" access="33333333" name="RXF5EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F16" access="33333333" name="RXF5EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F15" access="33303033" name="RXF5SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F14" access="33333333" name="RXF5SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F13" access="33333333" name="RXF4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F12" access="33333333" name="RXF4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F11" access="33303033" name="RXF4SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F10" access="33333333" name="RXF4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0F" access="33333333" name="RXF3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0E" access="33333333" name="RXF3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0D" access="33303033" name="RXF3SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F0C" access="33333333" name="RXF3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0B" access="33333333" name="RXF2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0A" access="33333333" name="RXF2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F09" access="33303033" name="RXF2SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F08" access="33333333" name="RXF2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F07" access="33333333" name="RXF1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F06" access="33333333" name="RXF1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F05" access="33303033" name="RXF1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F04" access="33333333" name="RXF1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F03" access="33333333" name="RXF0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F02" access="33333333" name="RXF0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F01" access="33303033" name="RXF0SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F00" access="33333333" name="RXF0SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18C801" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F9B" start="0x0F9B" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
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+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
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+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00003333" name="OSCCON" mclr="00003331" por="00001111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00003333" name="WDTCON" mclr="00000000" por="00001111" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10022211" />
+    <sfr address="0x0FA7" access="33333333" name="CSEL2" mclr="33333333" por="22222222" />
+    <sfr address="0x0FA6" access="33333333" name="CSELIO" mclr="33333333" por="22222222" />
+    <sfr address="0x0FA2" access="00003333" name="IPR2" mclr="00002222" por="00002222" />
+    <sfr address="0x0FA1" access="00003333" name="PIR2" mclr="00001111" por="00001111" />
+    <sfr address="0x0FA0" access="00003333" name="PIE2" mclr="00001111" por="00001111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9C" access="33330033" name="MEMCON" mclr="11110011" por="11110011" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00033333" name="PORTG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="11113333" por="11110000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30000333" name="ADCON2" mclr="10000111" por="10000111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="00000022" name="PSPCON" mclr="00000011" por="00000011" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18C858" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F2F" start="0x0F2F" />
+    <unused end="0x0F3F" start="0x0F3F" />
+    <unused end="0x0F4F" start="0x0F4F" />
+    <unused end="0x0F5F" start="0x0F5F" />
+    <unused end="0x0F7C" start="0x0F77" />
+    <unused end="0x0F9B" start="0x0F9B" />
+    <unused end="0x0FAA" start="0x0FA6" />
+    <unused end="0x0FB9" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="11044433" por="11022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33333333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="03003333" name="IPR2" mclr="02002222" por="02002222" />
+    <sfr address="0x0FA1" access="03003333" name="PIR2" mclr="01001111" por="01001111" />
+    <sfr address="0x0FA0" access="03003333" name="PIE2" mclr="01001111" por="01001111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00033333" name="PORTG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="11113333" por="11110000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7D" access="33333333" name="PORTK" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7F" access="33333333" name="TRISK" mclr="22222222" por="22222222" />
+    <sfr address="0x0F7E" access="33333333" name="LATK" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30000333" name="ADCON2" mclr="10000111" por="10000111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0F76" access="11111111" name="TXERRCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F75" access="11111111" name="RXERRCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F74" access="55111111" name="COMSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F73" access="33330000" name="CIOCON" mclr="21110000" por="21110000" />
+    <sfr address="0x0F72" access="03000333" name="BRGCON3" mclr="01000111" por="01000111" />
+    <sfr address="0x0F71" access="33333333" name="BRGCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F70" access="33333333" name="BRGCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333330" name="CANCON" mclr="33333330" por="00000000" />
+    <sfr address="0x0F6E" access="11101110" name="CANSTAT" mclr="33333330" por="00000000" />
+    <sfr address="0x0F6D" access="33333333" name="RXB0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6C" access="33333333" name="RXB0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6B" access="33333333" name="RXB0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="RXB0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F69" access="33333333" name="RXB0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="RXB0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="RXB0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="RXB0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="03333333" name="RXB0DLC" mclr="13333333" por="10000000" />
+    <sfr address="0x0F64" access="33333333" name="RXB0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F63" access="33333333" name="RXB0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F62" access="33333033" name="RXB0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0F61" access="33333333" name="RXB0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F60" access="53301313" name="RXB0CON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F5E" access="11101110" name="CANSTATRO0" mclr="33303330" por="00000000" />
+    <sfr address="0x0F5D" access="33333333" name="RXB1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5C" access="33333333" name="RXB1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5B" access="33333333" name="RXB1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5A" access="33333333" name="RXB1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F59" access="33333333" name="RXB1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F58" access="33333333" name="RXB1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F57" access="33333333" name="RXB1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F56" access="33333333" name="RXB1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F55" access="03333333" name="RXB1DLC" mclr="13333333" por="10000000" />
+    <sfr address="0x0F54" access="33333333" name="RXB1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F53" access="33333333" name="RXB1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F52" access="33333033" name="RXB1SIDL" mclr="33333133" por="00000100" />
+    <sfr address="0x0F51" access="33333333" name="RXB1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F50" access="53301111" name="RXB1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F4E" access="11101110" name="CANSTATRO1" mclr="33303330" por="00000000" />
+    <sfr address="0x0F4D" access="33333333" name="TXB0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F4C" access="33333333" name="TXB0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F4B" access="33333333" name="TXB0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F4A" access="33333333" name="TXB0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F49" access="33333333" name="TXB0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F48" access="33333333" name="TXB0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F47" access="33333333" name="TXB0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F46" access="33333333" name="TXB0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F45" access="03003333" name="TXB0DLC" mclr="13113333" por="10110000" />
+    <sfr address="0x0F44" access="33333333" name="TXB0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F43" access="33333333" name="TXB0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F42" access="33333333" name="TXB0SIDL" mclr="33313133" por="00010100" />
+    <sfr address="0x0F41" access="33333333" name="TXB0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F40" access="01113033" name="TXB0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F3E" access="11101110" name="CANSTATRO2" mclr="33303330" por="00000000" />
+    <sfr address="0x0F3D" access="33333333" name="TXB1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F3C" access="33333333" name="TXB1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F3B" access="33333333" name="TXB1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F3A" access="33333333" name="TXB1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F39" access="33333333" name="TXB1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F38" access="33333333" name="TXB1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F37" access="33333333" name="TXB1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F36" access="33333333" name="TXB1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F35" access="03003333" name="TXB1DLC" mclr="03003333" por="00000000" />
+    <sfr address="0x0F34" access="33333333" name="TXB1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F33" access="33333333" name="TXB1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F32" access="33333333" name="TXB1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F31" access="33333333" name="TXB1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F30" access="01113033" name="TXB1CON" mclr="03333033" por="01111011" />
+    <sfr address="0x0F2E" access="11101110" name="CANSTATRO3" mclr="33303330" por="00000000" />
+    <sfr address="0x0F2D" access="33333333" name="TXB2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2C" access="33333333" name="TXB2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2B" access="33333333" name="TXB2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2A" access="33333333" name="TXB2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F29" access="33333333" name="TXB2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F28" access="33333333" name="TXB2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F27" access="33333333" name="TXB2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F26" access="33333333" name="TXB2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F25" access="03003333" name="TXB2DLC" mclr="03003333" por="00000000" />
+    <sfr address="0x0F24" access="33333333" name="TXB2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F23" access="33333333" name="TXB2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F22" access="33333333" name="TXB2SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F21" access="33333333" name="TXB2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F20" access="01113033" name="TXB2CON" mclr="01111011" por="01111011" />
+    <sfr address="0x0F1F" access="33333333" name="RXM1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1E" access="33333333" name="RXM1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1D" access="33300033" name="RXM1SIDL" mclr="33300033" por="00000000" />
+    <sfr address="0x0F1C" access="33333333" name="RXM1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1B" access="33333333" name="RXM0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1A" access="33333333" name="RXM0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F19" access="33300033" name="RXM0SIDL" mclr="33300033" por="00000000" />
+    <sfr address="0x0F18" access="33333333" name="RXM0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F17" access="33333333" name="RXF5EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F16" access="33333333" name="RXF5EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F15" access="33303033" name="RXF5SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F14" access="33333333" name="RXF5SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F13" access="33333333" name="RXF4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F12" access="33333333" name="RXF4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F11" access="33303033" name="RXF4SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F10" access="33333333" name="RXF4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0F" access="33333333" name="RXF3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0E" access="33333333" name="RXF3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0D" access="33303033" name="RXF3SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F0C" access="33333333" name="RXF3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0B" access="33333333" name="RXF2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0A" access="33333333" name="RXF2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F09" access="33303033" name="RXF2SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F08" access="33333333" name="RXF2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F07" access="33333333" name="RXF1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F06" access="33333333" name="RXF1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F05" access="33303033" name="RXF1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F04" access="33333333" name="RXF1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F03" access="33333333" name="RXF0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F02" access="33333333" name="RXF0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F01" access="33303033" name="RXF0SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F00" access="33333333" name="RXF0SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F1220" unused_bank_mask="0x7FFE" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F82" />
+    <unused end="0x0F91" start="0x0F8B" />
+    <unused end="0x0F9A" start="0x0F94" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FB5" start="0x0FB4" />
+    <unused end="0x0FBC" start="0x0FB8" />
+    <unused end="0x0FC9" start="0x0FC5" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11111141" por="11114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="30030330" name="IPR2" mclr="20020220" por="20020220" />
+    <sfr address="0x0FA1" access="30030330" name="PIR2" mclr="10010110" por="10010110" />
+    <sfr address="0x0FA0" access="30030330" name="PIE2" mclr="10010110" por="10010110" />
+    <sfr address="0x0F9F" access="03330333" name="IPR1" mclr="02220222" por="02220222" />
+    <sfr address="0x0F9E" access="03110333" name="PIR1" mclr="01110111" por="01110111" />
+    <sfr address="0x0F9D" access="03330333" name="PIE1" mclr="01110111" por="01110111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33133333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33033333" name="LATA" mclr="33033333" por="00000000" />
+    <sfr address="0x0F92" access="33033333" name="TRISA" mclr="22022222" por="22022222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33033333" name="ADCON0" mclr="11011111" por="11011111" />
+    <sfr address="0x0FC1" access="03333333" name="ADCON1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0FAA" access="01033033" name="BAUDCTL" mclr="02021011" por="02021011" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F1230" unused_bank_mask="0x7FFE" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0FBF" start="0x0FBA" />
+    <unused end="0x0FCC" start="0x0FC5" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="12114111" por="12114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FB8" access="33033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB5" access="30333333" name="CVRCON" mclr="20222222" por="20222222" />
+    <sfr address="0x0FB4" access="33300333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA5" access="00030000" name="IPR3" mclr="00020000" por="00020000" />
+    <sfr address="0x0FA4" access="00030000" name="PIR3" mclr="00010000" por="00010000" />
+    <sfr address="0x0FA3" access="00030000" name="PIE3" mclr="00010000" por="00010000" />
+    <sfr address="0x0FA2" access="30030300" name="IPR2" mclr="20020200" por="20020200" />
+    <sfr address="0x0FA1" access="30030330" name="PIR2" mclr="10010110" por="10010110" />
+    <sfr address="0x0FA0" access="30030330" name="PIE2" mclr="10010110" por="10010110" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="12222222" por="12222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9A" access="33333333" name="PTCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0F99" access="33000000" name="PTCON1" mclr="11000000" por="11000000" />
+    <sfr address="0x0F98" access="33333333" name="PTMRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F97" access="00003333" name="PTMRH" mclr="00001111" por="00001111" />
+    <sfr address="0x0F96" access="33333333" name="PTPERL" mclr="22222222" por="22222222" />
+    <sfr address="0x0F95" access="00003333" name="PTPERH" mclr="00002222" por="00002222" />
+    <sfr address="0x0F91" access="33333333" name="PDC0L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F90" access="00333333" name="PDC0H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F8F" access="33333333" name="PDC1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F8E" access="00333333" name="PDC1H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F8D" access="33333333" name="PDC2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F8C" access="00333333" name="PDC2H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F8B" access="30000333" name="FLTCONFIG" mclr="10000111" por="10000111" />
+    <sfr address="0x0F88" access="33333333" name="SEVTCMPL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F87" access="00003333" name="SEVTCMPH" mclr="00001111" por="00001111" />
+    <sfr address="0x0F86" access="03330333" name="PWMCON0" mclr="02110111" por="02110111" />
+    <sfr address="0x0F85" access="33333033" name="PWMCON1" mclr="11111011" por="11111011" />
+    <sfr address="0x0F84" access="33333333" name="DTCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F83" access="00333333" name="OVDCOND" mclr="00222222" por="00222222" />
+    <sfr address="0x0F82" access="00333333" name="OVDCONS" mclr="00111111" por="00111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33133333" name="PORTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0F89" access="33033333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33033333" name="TRISA" mclr="22022222" por="22022222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="30003333" name="ADCON0" mclr="10001111" por="10001111" />
+    <sfr address="0x0FC1" access="00033333" name="ADCON1" mclr="11112222" por="11112222" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F1320" unused_bank_mask="0x7FFE" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F82" />
+    <unused end="0x0F91" start="0x0F8B" />
+    <unused end="0x0F9A" start="0x0F94" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FB5" start="0x0FB4" />
+    <unused end="0x0FBC" start="0x0FB8" />
+    <unused end="0x0FC9" start="0x0FC5" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11111141" por="11114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="30030330" name="IPR2" mclr="20020220" por="20020220" />
+    <sfr address="0x0FA1" access="30030330" name="PIR2" mclr="10010110" por="10010110" />
+    <sfr address="0x0FA0" access="30030330" name="PIE2" mclr="10010110" por="10010110" />
+    <sfr address="0x0F9F" access="03330333" name="IPR1" mclr="02220222" por="02220222" />
+    <sfr address="0x0F9E" access="03110333" name="PIR1" mclr="01110111" por="01110111" />
+    <sfr address="0x0F9D" access="03330333" name="PIE1" mclr="01110111" por="01110111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33133333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33033333" name="LATA" mclr="33033333" por="00000000" />
+    <sfr address="0x0F92" access="33033333" name="TRISA" mclr="22022222" por="22022222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33033333" name="ADCON0" mclr="11011111" por="11011111" />
+    <sfr address="0x0FC1" access="03333333" name="ADCON1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0FAA" access="01033033" name="BAUDCTL" mclr="02021011" por="02021011" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F1330" unused_bank_mask="0x7FFE" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0FBF" start="0x0FBA" />
+    <unused end="0x0FCC" start="0x0FC5" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="12114111" por="12114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FB8" access="33033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB5" access="30333333" name="CVRCON" mclr="20222222" por="20222222" />
+    <sfr address="0x0FB4" access="33300333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA5" access="00030000" name="IPR3" mclr="00020000" por="00020000" />
+    <sfr address="0x0FA4" access="00030000" name="PIR3" mclr="00010000" por="00010000" />
+    <sfr address="0x0FA3" access="00030000" name="PIE3" mclr="00010000" por="00010000" />
+    <sfr address="0x0FA2" access="30030300" name="IPR2" mclr="20020200" por="20020200" />
+    <sfr address="0x0FA1" access="30030330" name="PIR2" mclr="10010110" por="10010110" />
+    <sfr address="0x0FA0" access="30030330" name="PIE2" mclr="10010110" por="10010110" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="12222222" por="12222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9A" access="33333333" name="PTCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0F99" access="33000000" name="PTCON1" mclr="11000000" por="11000000" />
+    <sfr address="0x0F98" access="33333333" name="PTMRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F97" access="00003333" name="PTMRH" mclr="00001111" por="00001111" />
+    <sfr address="0x0F96" access="33333333" name="PTPERL" mclr="22222222" por="22222222" />
+    <sfr address="0x0F95" access="00003333" name="PTPERH" mclr="00002222" por="00002222" />
+    <sfr address="0x0F91" access="33333333" name="PDC0L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F90" access="00333333" name="PDC0H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F8F" access="33333333" name="PDC1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F8E" access="00333333" name="PDC1H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F8D" access="33333333" name="PDC2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F8C" access="00333333" name="PDC2H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F8B" access="30000333" name="FLTCONFIG" mclr="10000111" por="10000111" />
+    <sfr address="0x0F88" access="33333333" name="SEVTCMPL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F87" access="00003333" name="SEVTCMPH" mclr="00001111" por="00001111" />
+    <sfr address="0x0F86" access="03330333" name="PWMCON0" mclr="02110111" por="02110111" />
+    <sfr address="0x0F85" access="33333033" name="PWMCON1" mclr="11111011" por="11111011" />
+    <sfr address="0x0F84" access="33333333" name="DTCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F83" access="00333333" name="OVDCOND" mclr="00222222" por="00222222" />
+    <sfr address="0x0F82" access="00333333" name="OVDCONS" mclr="00111111" por="00111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33133333" name="PORTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0F89" access="33033333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33033333" name="TRISA" mclr="22022222" por="22022222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="30003333" name="ADCON0" mclr="10001111" por="10001111" />
+    <sfr address="0x0FC1" access="00033333" name="ADCON1" mclr="11112222" por="11112222" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2220" unused_bank_mask="0x7FFC" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F83" start="0x0F83" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9A" start="0x0F95" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11111141" por="11114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2221" unused_bank_mask="0x7FFC" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11111141" por="11114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCPAS1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="ECCP1DEL" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0FB8" access="31333033" name="BAUDCON" mclr="12111011" por="12111011" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2320" unused_bank_mask="0x7FFC" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F83" start="0x0F83" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9A" start="0x0F95" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11111141" por="11114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2321" unused_bank_mask="0x7FFC" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11111141" por="11114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCPAS1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="ECCP1DEL" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0FB8" access="31333033" name="BAUDCON" mclr="12111011" por="12111011" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F2331" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F86" start="0x0F84" />
+    <unused end="0x0F8F" start="0x0F8E" />
+    <unused end="0x0F98" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB5" start="0x0FB1" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FC5" start="0x0FC5" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="11111113" name="WDTCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10022244" />
+    <sfr address="0x0FA5" access="00033333" name="IPR3" mclr="00022222" por="00022222" />
+    <sfr address="0x0FA4" access="00033333" name="PIR3" mclr="00011111" por="00011111" />
+    <sfr address="0x0FA3" access="00033333" name="PIE3" mclr="00011111" por="00011111" />
+    <sfr address="0x0FA2" access="30030303" name="IPR2" mclr="20020202" por="20020202" />
+    <sfr address="0x0FA1" access="30030303" name="PIR2" mclr="10010101" por="10010101" />
+    <sfr address="0x0FA0" access="30030303" name="PIE2" mclr="10010101" por="10010101" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33111111" por="00111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="33031111" name="ADCON1" mclr="11011111" por="11011111" />
+    <sfr address="0x0FC0" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9A" access="33033333" name="ADCON3" mclr="11011111" por="11011111" />
+    <sfr address="0x0F99" access="33333333" name="ADCHS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB8" access="00033333" name="ANSEL0" mclr="00022222" por="00022222" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="33331133" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB7" access="33333333" name="T5CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F90" size="2" name="PR5" />
+    <sfr address="0x0F91" access="33333333" name="PR5H" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="PR5L" mclr="22222222" por="22222222" />
+    <combined address="0x0F87" size="2" name="TMR5" />
+    <sfr address="0x0F88" access="33333333" name="TMR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="TMR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0FAA" access="01033033" name="BAUDCTL" mclr="02021011" por="02021011" />
+    <sfr address="0x0F7F" access="33333333" name="PTCON0" mclr="33333333" por="11111111" />
+    <sfr address="0x0F7E" access="31000000" name="PTCON1" mclr="11000000" por="11000000" />
+    <sfr address="0x0F7D" access="33333333" name="PTMRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F7C" access="00003333" name="PTMRH" mclr="00001111" por="00001111" />
+    <sfr address="0x0F7B" access="33333333" name="PTPERL" mclr="22222222" por="22222222" />
+    <sfr address="0x0F7A" access="00003333" name="PTPERH" mclr="00002222" por="00002222" />
+    <sfr address="0x0F79" access="33333333" name="PDC0L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F78" access="00333333" name="PDC0H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F77" access="33333333" name="PDC1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F76" access="00333333" name="PDC1H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F75" access="33333333" name="PDC2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F74" access="00333333" name="PDC2H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F73" access="33333333" name="PDC3L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F72" access="00333333" name="PDC3H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F71" access="33333333" name="SEVTCMPL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F70" access="00003333" name="SEVTCMPH" mclr="00001111" por="00001111" />
+    <sfr address="0x0F6F" access="03333333" name="PWMCON0" mclr="02121111" por="02121111" />
+    <sfr address="0x0F6E" access="33333033" name="PWMCON1" mclr="11111011" por="11111011" />
+    <sfr address="0x0F6D" access="33333333" name="DTCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="03333333" name="FLTCONFIG" mclr="01111111" por="01111111" />
+    <sfr address="0x0F6B" access="33333333" name="OVDCOND" mclr="22222222" por="22222222" />
+    <sfr address="0x0F6A" access="33333333" name="OVDCONS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="03303333" name="CAP1CON" mclr="02101111" por="02101111" />
+    <sfr address="0x0F62" access="03303333" name="CAP2CON" mclr="02101111" por="02101111" />
+    <sfr address="0x0F61" access="03303333" name="CAP3CON" mclr="02101111" por="02101111" />
+    <sfr address="0x0FB6" access="30333333" name="QEICON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F60" access="03333333" name="DFLTCON" mclr="01111111" por="01111111" />
+    <sfr address="0x0F69" access="33333333" name="CAP1BUFH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F69" access="33333333" name="VELRH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="CAP1BUFL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="VELRL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CAP2BUFH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="POSCNTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="CAP2BUFL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="POSCNTL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="CAP3BUFH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="MAXCNTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F64" access="33333333" name="CAP3BUFL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F64" access="33333333" name="MAXCNTL" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2410" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001000" name="PORTE" mclr="00000000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCP1AS" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="PWM1CON" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F242" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F83" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9C" start="0x0F95" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10042211" />
+    <sfr address="0x0FA2" access="00033333" name="IPR2" mclr="00022222" por="00022222" />
+    <sfr address="0x0FA1" access="00033333" name="PIR2" mclr="00011111" por="00011111" />
+    <sfr address="0x0FA0" access="00033333" name="PIE2" mclr="00011111" por="00011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2420" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FD3" access="33330100" name="OSCCON" mclr="11110100" por="12110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001000" name="PORTE" mclr="00000000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCP1AS" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="PWM1CON" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2423" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03330303" name="INTCON2" mclr="02220202" por="02220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001000" name="PORTE" mclr="00000000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCP1AS" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="PWM1CON" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F2431" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F86" start="0x0F84" />
+    <unused end="0x0F8F" start="0x0F8E" />
+    <unused end="0x0F98" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB5" start="0x0FB1" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FC5" start="0x0FC5" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="11111113" name="WDTCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10022244" />
+    <sfr address="0x0FA5" access="00033333" name="IPR3" mclr="00022222" por="00022222" />
+    <sfr address="0x0FA4" access="00033333" name="PIR3" mclr="00011111" por="00011111" />
+    <sfr address="0x0FA3" access="00033333" name="PIE3" mclr="00011111" por="00011111" />
+    <sfr address="0x0FA2" access="30030303" name="IPR2" mclr="20020202" por="20020202" />
+    <sfr address="0x0FA1" access="30030303" name="PIR2" mclr="10010101" por="10010101" />
+    <sfr address="0x0FA0" access="30030303" name="PIE2" mclr="10010101" por="10010101" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33111111" por="00111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="33031111" name="ADCON1" mclr="11011111" por="11011111" />
+    <sfr address="0x0FC0" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9A" access="33033333" name="ADCON3" mclr="11011111" por="11011111" />
+    <sfr address="0x0F99" access="33333333" name="ADCHS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB8" access="00033333" name="ANSEL0" mclr="00022222" por="00022222" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="33331133" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB7" access="33333333" name="T5CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F90" size="2" name="PR5" />
+    <sfr address="0x0F91" access="33333333" name="PR5H" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="PR5L" mclr="22222222" por="22222222" />
+    <combined address="0x0F87" size="2" name="TMR5" />
+    <sfr address="0x0F88" access="33333333" name="TMR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="TMR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0FAA" access="01033033" name="BAUDCTL" mclr="02021011" por="02021011" />
+    <sfr address="0x0F7F" access="33333333" name="PTCON0" mclr="33333333" por="11111111" />
+    <sfr address="0x0F7E" access="31000000" name="PTCON1" mclr="11000000" por="11000000" />
+    <sfr address="0x0F7D" access="33333333" name="PTMRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F7C" access="00003333" name="PTMRH" mclr="00001111" por="00001111" />
+    <sfr address="0x0F7B" access="33333333" name="PTPERL" mclr="22222222" por="22222222" />
+    <sfr address="0x0F7A" access="00003333" name="PTPERH" mclr="00002222" por="00002222" />
+    <sfr address="0x0F79" access="33333333" name="PDC0L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F78" access="00333333" name="PDC0H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F77" access="33333333" name="PDC1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F76" access="00333333" name="PDC1H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F75" access="33333333" name="PDC2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F74" access="00333333" name="PDC2H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F73" access="33333333" name="PDC3L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F72" access="00333333" name="PDC3H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F71" access="33333333" name="SEVTCMPL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F70" access="00003333" name="SEVTCMPH" mclr="00001111" por="00001111" />
+    <sfr address="0x0F6F" access="03333333" name="PWMCON0" mclr="02121111" por="02121111" />
+    <sfr address="0x0F6E" access="33333033" name="PWMCON1" mclr="11111011" por="11111011" />
+    <sfr address="0x0F6D" access="33333333" name="DTCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="03333333" name="FLTCONFIG" mclr="01111111" por="01111111" />
+    <sfr address="0x0F6B" access="33333333" name="OVDCOND" mclr="22222222" por="22222222" />
+    <sfr address="0x0F6A" access="33333333" name="OVDCONS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="03303333" name="CAP1CON" mclr="02101111" por="02101111" />
+    <sfr address="0x0F62" access="03303333" name="CAP2CON" mclr="02101111" por="02101111" />
+    <sfr address="0x0F61" access="03303333" name="CAP3CON" mclr="02101111" por="02101111" />
+    <sfr address="0x0FB6" access="30333333" name="QEICON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F60" access="03333333" name="DFLTCON" mclr="01111111" por="01111111" />
+    <sfr address="0x0F69" access="33333333" name="CAP1BUFH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F69" access="33333333" name="VELRH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="CAP1BUFL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="VELRL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CAP2BUFH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="POSCNTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="CAP2BUFL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="POSCNTL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="CAP3BUFH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="MAXCNTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F64" access="33333333" name="CAP3BUFL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F64" access="33333333" name="MAXCNTL" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2439" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F83" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9C" start="0x0F95" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="00033330" name="IPR2" mclr="00022220" por="00022220" />
+    <sfr address="0x0FA1" access="00033330" name="PIR2" mclr="00011110" por="00011110" />
+    <sfr address="0x0FA0" access="00033330" name="PIE2" mclr="00011110" por="00011110" />
+    <sfr address="0x0F9F" access="03333033" name="IPR1" mclr="02222022" por="02222022" />
+    <sfr address="0x0F9E" access="03113033" name="PIR1" mclr="01111011" por="01111011" />
+    <sfr address="0x0F9D" access="03333033" name="PIE1" mclr="01111011" por="01111011" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30330333" name="T1CON" mclr="30330333" por="10110111" />
+    <sfr address="0x0FCC" access="11111111" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="11111111" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="11111111" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="30330333" name="T3CON" mclr="30330333" por="10110111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2450" unused_bank_mask="0x7FEC" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F83" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9C" start="0x0F95" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FB5" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FC5" start="0x0FC9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03330303" name="INTCON2" mclr="02220202" por="02220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="30300300" name="IPR2" mclr="20200200" por="20200200" />
+    <sfr address="0x0FA1" access="30300300" name="PIR2" mclr="10100100" por="10100100" />
+    <sfr address="0x0FA0" access="30300300" name="PIE2" mclr="10100100" por="10100100" />
+    <sfr address="0x0F9F" access="03330333" name="IPR1" mclr="02220222" por="02220222" />
+    <sfr address="0x0F9E" access="03110333" name="PIR1" mclr="01110111" por="01110111" />
+    <sfr address="0x0F9D" access="03330333" name="PIE1" mclr="01110111" por="01110111" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON1" mclr="12111011" por="12011011" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7F" access="00033333" name="UEP15" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7E" access="00033333" name="UEP14" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7D" access="00033333" name="UEP13" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7C" access="00033333" name="UEP12" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7B" access="00033333" name="UEP11" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7A" access="00033333" name="UEP10" mclr="00011111" por="00011111" />
+    <sfr address="0x0F79" access="00033333" name="UEP9" mclr="00011111" por="00011111" />
+    <sfr address="0x0F78" access="00033333" name="UEP8" mclr="00011111" por="00011111" />
+    <sfr address="0x0F77" access="00033333" name="UEP7" mclr="00011111" por="00011111" />
+    <sfr address="0x0F76" access="00033333" name="UEP6" mclr="00011111" por="00011111" />
+    <sfr address="0x0F75" access="00033333" name="UEP5" mclr="00011111" por="00011111" />
+    <sfr address="0x0F74" access="00033333" name="UEP4" mclr="00011111" por="00011111" />
+    <sfr address="0x0F73" access="00033333" name="UEP3" mclr="00011111" por="00011111" />
+    <sfr address="0x0F72" access="00033333" name="UEP2" mclr="00011111" por="00011111" />
+    <sfr address="0x0F71" access="00033333" name="UEP1" mclr="00011111" por="00011111" />
+    <sfr address="0x0F70" access="00033333" name="UEP0" mclr="00011111" por="00011111" />
+    <sfr address="0x0F6F" access="33033333" name="UCFG" mclr="11011111" por="11011111" />
+    <sfr address="0x0F6E" access="03333333" name="UADDR" mclr="01111111" por="01111111" />
+    <sfr address="0x0F6D" access="03153330" name="UCON" mclr="01011110" por="01011110" />
+    <sfr address="0x0F6C" access="01111110" name="USTAT" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6B" access="30033333" name="UEIE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F6A" access="50055555" name="UEIR" mclr="10011111" por="10011111" />
+    <sfr address="0x0F69" access="03333333" name="UIE" mclr="01111111" por="01111111" />
+    <sfr address="0x0F68" access="03333313" name="UIR" mclr="01111111" por="01111111" />
+    <combined address="0x0F66" size="2" name="UFRM" />
+    <sfr address="0x0F67" access="00000111" name="UFRMH" mclr="00000000" por="00000000" />
+    <sfr address="0x0F66" access="11111111" name="UFRML" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="03033390" name="EECON1" mclr="03013110" por="00010110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F2455" unused_bank_mask="0x7F00" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F83" start="0x0F83" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F8D" start="0x0F8C" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F96" start="0x0F95" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="30133333" name="HLVDCON" mclr="10111212" por="10111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="30033333" name="OSCTUNE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33330333" name="PORTC" mclr="33330333" por="00000000" />
+    <sfr address="0x0F8B" access="33000333" name="LATC" mclr="33000333" por="00000000" />
+    <sfr address="0x0F94" access="33000333" name="TRISC" mclr="22000222" por="22000222" />
+    <sfr address="0x0F84" access="00001000" name="PORTE" mclr="00000000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCP1AS" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="ECCP1DEL" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="00000333" name="SPPCON" mclr="00000111" por="00000111" />
+    <sfr address="0x0F64" access="33033333" name="SPPEPS" mclr="11011111" por="11011111" />
+    <sfr address="0x0F63" access="33333333" name="SPPCFG" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SPPDATA" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7F" access="00033333" name="UEP15" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7E" access="00033333" name="UEP14" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7D" access="00033333" name="UEP13" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7C" access="00033333" name="UEP12" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7B" access="00033333" name="UEP11" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7A" access="00033333" name="UEP10" mclr="00011111" por="00011111" />
+    <sfr address="0x0F79" access="00033333" name="UEP9" mclr="00011111" por="00011111" />
+    <sfr address="0x0F78" access="00033333" name="UEP8" mclr="00011111" por="00011111" />
+    <sfr address="0x0F77" access="00033333" name="UEP7" mclr="00011111" por="00011111" />
+    <sfr address="0x0F76" access="00033333" name="UEP6" mclr="00011111" por="00011111" />
+    <sfr address="0x0F75" access="00033333" name="UEP5" mclr="00011111" por="00011111" />
+    <sfr address="0x0F74" access="00033333" name="UEP4" mclr="00011111" por="00011111" />
+    <sfr address="0x0F73" access="00033333" name="UEP3" mclr="00011111" por="00011111" />
+    <sfr address="0x0F72" access="00033333" name="UEP2" mclr="00011111" por="00011111" />
+    <sfr address="0x0F71" access="00033333" name="UEP1" mclr="00011111" por="00011111" />
+    <sfr address="0x0F70" access="00033333" name="UEP0" mclr="00011111" por="00011111" />
+    <sfr address="0x0F6F" access="33033333" name="UCFG" mclr="11011111" por="11011111" />
+    <sfr address="0x0F6E" access="03333333" name="UADDR" mclr="01111111" por="01111111" />
+    <sfr address="0x0F6D" access="03153330" name="UCON" mclr="01011110" por="01011110" />
+    <sfr address="0x0F6C" access="01111110" name="USTAT" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6B" access="30033333" name="UEIE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F6A" access="50055555" name="UEIR" mclr="10011111" por="10011111" />
+    <sfr address="0x0F69" access="03333333" name="UIE" mclr="01111111" por="01111111" />
+    <sfr address="0x0F68" access="03333313" name="UIR" mclr="01111111" por="01111111" />
+    <combined address="0x0F66" size="2" name="UFRM" />
+    <sfr address="0x0F67" access="00000111" name="UFRMH" mclr="00000000" por="00000000" />
+    <sfr address="0x0F66" access="11111111" name="UFRML" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F248" unused_bank_mask="0x7FF8" >
+    <mirror>
+      <range end="0x0F2E" start="0x0F2E" />
+      <range end="0x0F3E" start="0x0F3E" />
+      <range end="0x0F4E" start="0x0F4E" />
+      <range end="0x0F5E" start="0x0F5E" />
+    </mirror>
+    <unused end="0x0F2F" start="0x0F2F" />
+    <unused end="0x0F3F" start="0x0F3F" />
+    <unused end="0x0F4F" start="0x0F4F" />
+    <unused end="0x0F5F" start="0x0F5F" />
+    <unused end="0x0F7F" start="0x0F77" />
+    <unused end="0x0F88" start="0x0F83" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9C" start="0x0F95" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FBC" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33333333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0F76" access="11111111" name="TXERRCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F75" access="11111111" name="RXERRCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F74" access="55111111" name="COMSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F73" access="00330000" name="CIOCON" mclr="00110000" por="00110000" />
+    <sfr address="0x0F72" access="03000333" name="BRGCON3" mclr="01000111" por="01000111" />
+    <sfr address="0x0F71" access="33333333" name="BRGCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F70" access="33333333" name="BRGCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333330" name="CANCON" mclr="21111110" por="21111110" />
+    <sfr address="0x0F6E" access="11101110" name="CANSTAT" mclr="21101110" por="21101110" />
+    <sfr address="0x0F6D" access="33333333" name="RXB0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6C" access="33333333" name="RXB0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6B" access="33333333" name="RXB0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="RXB0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F69" access="33333333" name="RXB0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="RXB0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="RXB0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="RXB0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="03333333" name="RXB0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0F64" access="33333333" name="RXB0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F63" access="33333333" name="RXB0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F62" access="33333033" name="RXB0SIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F61" access="33333333" name="RXB0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F60" access="53301313" name="RXB0CON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F5E" access="11101110" name="CANSTATRO1" mclr="00000000" por="00000000" />
+    <sfr address="0x0F5D" access="33333333" name="RXB1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5C" access="33333333" name="RXB1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5B" access="33333333" name="RXB1D5" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F57" access="33333333" name="RXB1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F56" access="33333333" name="RXB1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F55" access="03333333" name="RXB1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0F54" access="33333333" name="RXB1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F53" access="33333333" name="RXB1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F52" access="33333033" name="RXB1SIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F51" access="33333333" name="RXB1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F50" access="53301111" name="RXB1CON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F4E" access="11101110" name="CANSTATRO2" mclr="33303330" por="00000000" />
+    <sfr address="0x0F4D" access="33333333" name="TXB0D7" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F4B" access="33333333" name="TXB0D5" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F11" access="33303033" name="RXF4SIDL" mclr="33303033" por="00000000" />
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+    <sfr address="0x0F0F" access="33333333" name="RXF3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0E" access="33333333" name="RXF3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0D" access="33303033" name="RXF3SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F0C" access="33333333" name="RXF3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0B" access="33333333" name="RXF2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0A" access="33333333" name="RXF2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F09" access="33303033" name="RXF2SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F08" access="33333333" name="RXF2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F07" access="33333333" name="RXF1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F06" access="33333333" name="RXF1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F05" access="33303033" name="RXF1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F04" access="33333333" name="RXF1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F03" access="33333333" name="RXF0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F02" access="33333333" name="RXF0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F01" access="33303033" name="RXF0SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F00" access="33333333" name="RXF0SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F2480" unused_bank_mask="0x1FF8" >
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
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+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
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+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="33011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
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+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
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+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
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+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
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+    <sfr address="0x0E7B" access="33333333" name="RXB7D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E7A" access="33333333" name="RXB7D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E79" access="33333333" name="RXB7D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E78" access="33333333" name="RXB7D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E77" access="33333333" name="RXB7D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E76" access="33333333" name="RXB7D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E75" access="03333333" name="RXB7DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E73" size="2" name="RXB7EID" />
+    <sfr address="0x0E74" access="33333333" name="RXB7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E73" access="33333333" name="RXB7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E72" access="33303033" name="RXB7SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E71" access="33333333" name="RXB7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E70" access="33333333" name="RXB7CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6D" access="33333333" name="RXB6D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6C" access="33333333" name="RXB6D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6B" access="33333333" name="RXB6D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6A" access="33333333" name="RXB6D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E69" access="33333333" name="RXB6D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E68" access="33333333" name="RXB6D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E67" access="33333333" name="RXB6D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E66" access="33333333" name="RXB6D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E65" access="03333333" name="RXB6DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E63" size="2" name="RXB6EID" />
+    <sfr address="0x0E64" access="33333333" name="RXB6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E63" access="33333333" name="RXB6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E62" access="33303033" name="RXB6SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E61" access="33333333" name="RXB6SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E60" access="33333333" name="RXB6CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5D" access="33333333" name="RXB5D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5C" access="33333333" name="RXB5D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5B" access="33333333" name="RXB5D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5A" access="33333333" name="RXB5D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E59" access="33333333" name="RXB5D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E58" access="33333333" name="RXB5D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E57" access="33333333" name="RXB5D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E56" access="33333333" name="RXB5D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03333333" name="RXB5DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E53" size="2" name="RXB5EID" />
+    <sfr address="0x0E54" access="33333333" name="RXB5EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="RXB5EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33303033" name="RXB5SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="RXB5SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33333333" name="RXB5CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4D" access="33333333" name="RXB4D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="RXB4D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="RXB4D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="RXB4D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="RXB4D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="RXB4D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="RXB4D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="RXB4D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03333333" name="RXB4DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E43" size="2" name="RXB4EID" />
+    <sfr address="0x0E44" access="33333333" name="RXB4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="RXB4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33303033" name="RXB4SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="RXB4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33333333" name="RXB4CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3D" access="33333333" name="RXB3D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="RXB3D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="RXB3D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="RXB3D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="RXB3D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="RXB3D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="RXB3D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="RXB3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03333333" name="RXB3DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E33" size="2" name="RXB3EID" />
+    <sfr address="0x0E34" access="33333333" name="RXB3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="RXB3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33303033" name="RXB3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="RXB3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33333333" name="RXB3CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2D" access="33333333" name="RXB2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="RXB2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="RXB2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="RXB2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="RXB2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="RXB2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="RXB2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="RXB2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03333333" name="RXB2DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E23" size="2" name="RXB2EID" />
+    <sfr address="0x0E24" access="33333333" name="RXB2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="RXB2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33303033" name="RXB2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="RXB2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33333333" name="RXB2CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0DFC" access="00033300" name="TX_BUFINTEN" mclr="00033300" por="00000000" />
+    <sfr address="0x0DFA" access="33333333" name="BUF_INT_EN0" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF8" access="33333300" name="RX_TX_SEL0" mclr="33333300" por="00000000" />
+    <sfr address="0x0DF3" access="33333333" name="MSK_SEL3" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF2" access="33333333" name="MSK_SEL2" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF1" access="33333333" name="MSK_SEL1" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF0" access="33333333" name="MSK_SEL0" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE7" access="33333333" name="BUFPNT1514" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE6" access="33333333" name="BUFPNT1312" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE5" access="33333333" name="BUFPNT1110" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE4" access="33333333" name="BUFPNT98" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE3" access="33333333" name="BUFPNT76" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE2" access="33333333" name="BUFPNT54" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE1" access="33333333" name="BUFPNT32" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE0" access="33333333" name="BUFPNT10" mclr="33333333" por="00000000" />
+    <sfr address="0x0DD8" access="00033333" name="DEV_NET_CT" mclr="00033333" por="00000000" />
+    <sfr address="0x0DD5" access="33333333" name="FER1" mclr="33333333" por="00000000" />
+    <sfr address="0x0DD4" access="33333333" name="FER0" mclr="33333333" por="00000000" />
+    <combined address="0x0D92" size="2" name="RXF15EID" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33303033" name="RXF15SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D8A" size="2" name="RXF14EID" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33303033" name="RXF14SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D86" size="2" name="RXF13EID" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33303033" name="RXF13SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D82" size="2" name="RXF12EID" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33303033" name="RXF12SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D7A" size="2" name="RXF11EID" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33303033" name="RXF11SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D76" size="2" name="RXF10EID" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33303033" name="RXF10SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D72" size="2" name="RXF9EID" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33303033" name="RXF9SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D6A" size="2" name="RXF8EID" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33303033" name="RXF8SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D66" size="2" name="RXF7EID" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33303033" name="RXF7SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D62" size="2" name="RXF6EID" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33303033" name="RXF6SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F24J10" unused_bank_mask="0x7FF0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="12034433" por="10022211" />
+    <sfr address="0x0FA5" access="03000000" name="IPR3" mclr="02000000" por="02000000" />
+    <sfr address="0x0FA4" access="03000000" name="PIR3" mclr="01000000" por="01000000" />
+    <sfr address="0x0FA3" access="03000000" name="PIE3" mclr="01000000" por="01000000" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002002" por="22002002" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001001" por="11001001" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001001" por="11001001" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="00303333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="00303333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="00303333" name="TRISA" mclr="00202222" por="00202222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCP1AS" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="PWM1CON" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2510" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F83" start="0x0F83" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F8D" start="0x0F8C" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F96" start="0x0F95" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FA9" start="0x0FA6" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001000" name="PORTE" mclr="00000000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCPAS1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="PWM1CON" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2515" unused_bank_mask="0x0000" >
+    <unused end="0x0F83" start="0x0F83" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9A" start="0x0F95" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001111" por="11001111" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9B" access="30033333" name="OSCTUNE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001000" name="PORTE" mclr="00003000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCPAS1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="PWM1CON" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F252" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F83" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9C" start="0x0F95" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10042211" />
+    <sfr address="0x0FA2" access="00033333" name="IPR2" mclr="00022222" por="00022222" />
+    <sfr address="0x0FA1" access="00033333" name="PIR2" mclr="00011111" por="00011111" />
+    <sfr address="0x0FA0" access="00033333" name="PIE2" mclr="00011111" por="00011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2520" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F83" start="0x0F83" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F8D" start="0x0F8C" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F96" start="0x0F95" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FD3" access="33330100" name="OSCCON" mclr="11110100" por="12110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001000" name="PORTE" mclr="00000000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCPAS1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="PWM1CON" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2523" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F83" start="0x0F83" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F8D" start="0x0F8C" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F96" start="0x0F95" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03330303" name="INTCON2" mclr="02220202" por="02220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001000" name="PORTE" mclr="00000000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCPAS1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="PWM1CON" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2525" unused_bank_mask="0x0000" >
+    <unused end="0x0F83" start="0x0F83" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9A" start="0x0F95" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="12114111" por="12114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="10011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001000" name="PORTE" mclr="00003000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCPAS1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="PWM1CON" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2539" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F83" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9C" start="0x0F95" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="00033330" name="IPR2" mclr="00022220" por="00022220" />
+    <sfr address="0x0FA1" access="00033330" name="PIR2" mclr="00011110" por="00011110" />
+    <sfr address="0x0FA0" access="00033330" name="PIE2" mclr="00011110" por="00011110" />
+    <sfr address="0x0F9F" access="03333033" name="IPR1" mclr="02222022" por="02222022" />
+    <sfr address="0x0F9E" access="03113033" name="PIR1" mclr="01111011" por="01111011" />
+    <sfr address="0x0F9D" access="03333033" name="PIE1" mclr="01111011" por="01111011" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30330333" name="T1CON" mclr="30330333" por="10110111" />
+    <sfr address="0x0FCC" access="11111111" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="11111111" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="11111111" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="30330333" name="T3CON" mclr="30330333" por="10110111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F2550" unused_bank_mask="0x7F00" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F83" start="0x0F83" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F8D" start="0x0F8C" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F96" start="0x0F95" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="30133333" name="HLVDCON" mclr="10111212" por="10111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="30033333" name="OSCTUNE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33330333" name="PORTC" mclr="33330333" por="00000000" />
+    <sfr address="0x0F8B" access="33000333" name="LATC" mclr="33000333" por="00000000" />
+    <sfr address="0x0F94" access="33000333" name="TRISC" mclr="22000222" por="22000222" />
+    <sfr address="0x0F84" access="00001000" name="PORTE" mclr="00000000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCP1AS" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="ECCP1DEL" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="00000333" name="SPPCON" mclr="00000111" por="00000111" />
+    <sfr address="0x0F64" access="33033333" name="SPPEPS" mclr="11011111" por="11011111" />
+    <sfr address="0x0F63" access="33333333" name="SPPCFG" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SPPDATA" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7F" access="00033333" name="UEP15" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7E" access="00033333" name="UEP14" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7D" access="00033333" name="UEP13" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7C" access="00033333" name="UEP12" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7B" access="00033333" name="UEP11" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7A" access="00033333" name="UEP10" mclr="00011111" por="00011111" />
+    <sfr address="0x0F79" access="00033333" name="UEP9" mclr="00011111" por="00011111" />
+    <sfr address="0x0F78" access="00033333" name="UEP8" mclr="00011111" por="00011111" />
+    <sfr address="0x0F77" access="00033333" name="UEP7" mclr="00011111" por="00011111" />
+    <sfr address="0x0F76" access="00033333" name="UEP6" mclr="00011111" por="00011111" />
+    <sfr address="0x0F75" access="00033333" name="UEP5" mclr="00011111" por="00011111" />
+    <sfr address="0x0F74" access="00033333" name="UEP4" mclr="00011111" por="00011111" />
+    <sfr address="0x0F73" access="00033333" name="UEP3" mclr="00011111" por="00011111" />
+    <sfr address="0x0F72" access="00033333" name="UEP2" mclr="00011111" por="00011111" />
+    <sfr address="0x0F71" access="00033333" name="UEP1" mclr="00011111" por="00011111" />
+    <sfr address="0x0F70" access="00033333" name="UEP0" mclr="00011111" por="00011111" />
+    <sfr address="0x0F6F" access="33033333" name="UCFG" mclr="11011111" por="11011111" />
+    <sfr address="0x0F6E" access="03333333" name="UADDR" mclr="01111111" por="01111111" />
+    <sfr address="0x0F6D" access="03153330" name="UCON" mclr="01011110" por="01011110" />
+    <sfr address="0x0F6C" access="01111110" name="USTAT" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6B" access="30033333" name="UEIE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F6A" access="50055555" name="UEIR" mclr="10011111" por="10011111" />
+    <sfr address="0x0F69" access="03333333" name="UIE" mclr="01111111" por="01111111" />
+    <sfr address="0x0F68" access="03333313" name="UIR" mclr="01111111" por="01111111" />
+    <combined address="0x0F66" size="2" name="UFRM" />
+    <sfr address="0x0F67" access="00000111" name="UFRMH" mclr="00000000" por="00000000" />
+    <sfr address="0x0F66" access="11111111" name="UFRML" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F258" unused_bank_mask="0x7FC0" >
+    <mirror>
+      <range end="0x0F2E" start="0x0F2E" />
+      <range end="0x0F3E" start="0x0F3E" />
+      <range end="0x0F4E" start="0x0F4E" />
+      <range end="0x0F5E" start="0x0F5E" />
+    </mirror>
+    <unused end="0x0F2F" start="0x0F2F" />
+    <unused end="0x0F3F" start="0x0F3F" />
+    <unused end="0x0F4F" start="0x0F4F" />
+    <unused end="0x0F5F" start="0x0F5F" />
+    <unused end="0x0F7F" start="0x0F77" />
+    <unused end="0x0F88" start="0x0F83" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9C" start="0x0F95" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FBC" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
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+    <sfr address="0x0F0D" access="33303033" name="RXF3SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F0C" access="33333333" name="RXF3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0B" access="33333333" name="RXF2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0A" access="33333333" name="RXF2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F09" access="33303033" name="RXF2SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F08" access="33333333" name="RXF2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F07" access="33333333" name="RXF1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F06" access="33333333" name="RXF1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F05" access="33303033" name="RXF1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F04" access="33333333" name="RXF1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F03" access="33333333" name="RXF0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F02" access="33333333" name="RXF0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F01" access="33303033" name="RXF0SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F00" access="33333333" name="RXF0SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F2580" unused_bank_mask="0x1FC0" >
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
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+    <unused end="0x0FD4" start="0x0FD4" />
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+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
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+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
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+    <sfr address="0x0F31" access="33333333" name="TXB1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F30" access="33333033" name="TXB1CON" mclr="33333033" por="00000000" />
+    <sfr address="0x0F2D" access="33333333" name="TXB2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2C" access="33333333" name="TXB2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2B" access="33333333" name="TXB2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2A" access="33333333" name="TXB2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F29" access="33333333" name="TXB2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F28" access="33333333" name="TXB2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F27" access="33333333" name="TXB2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F26" access="33333333" name="TXB2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F25" access="03003333" name="TXB2DLC" mclr="03003333" por="00000000" />
+    <combined address="0x0F23" size="2" name="TXB2EID" />
+    <sfr address="0x0F24" access="33333333" name="TXB2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F23" access="33333333" name="TXB2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F22" access="33303033" name="TXB2SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F21" access="33333333" name="TXB2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F20" access="33333033" name="TXB2CON" mclr="33333033" por="00000000" />
+    <combined address="0x0F1E" size="2" name="RXM1EID" />
+    <sfr address="0x0F1F" access="33333333" name="RXM1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1E" access="33333333" name="RXM1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1D" access="33303033" name="RXM1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F1C" access="33333333" name="RXM1SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F1A" size="2" name="RXM0EID" />
+    <sfr address="0x0F1B" access="33333333" name="RXM0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1A" access="33333333" name="RXM0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F19" access="33303033" name="RXM0SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F18" access="33333333" name="RXM0SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F16" size="2" name="RXF5EID" />
+    <sfr address="0x0F17" access="33333333" name="RXF5EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F16" access="33333333" name="RXF5EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F15" access="33303033" name="RXF5SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F14" access="33333333" name="RXF5SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F12" size="2" name="RXF4EID" />
+    <sfr address="0x0F13" access="33333333" name="RXF4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F12" access="33333333" name="RXF4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F11" access="33303033" name="RXF4SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F10" access="33333333" name="RXF4SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F0E" size="2" name="RXF3EID" />
+    <sfr address="0x0F0F" access="33333333" name="RXF3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0E" access="33333333" name="RXF3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0D" access="33303033" name="RXF3SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F0C" access="33333333" name="RXF3SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F0A" size="2" name="RXF2EID" />
+    <sfr address="0x0F0B" access="33333333" name="RXF2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0A" access="33333333" name="RXF2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F09" access="33303033" name="RXF2SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F08" access="33333333" name="RXF2SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F06" size="2" name="RXF1EID" />
+    <sfr address="0x0F07" access="33333333" name="RXF1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F06" access="33333333" name="RXF1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F05" access="33303033" name="RXF1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F04" access="33333333" name="RXF1SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F02" size="2" name="RXF0EID" />
+    <sfr address="0x0F03" access="33333333" name="RXF0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F02" access="33333333" name="RXF0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F01" access="33303033" name="RXF0SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F00" access="33333333" name="RXF0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E7D" access="33333333" name="RXB7D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E7C" access="33333333" name="RXB7D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E7B" access="33333333" name="RXB7D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E7A" access="33333333" name="RXB7D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E79" access="33333333" name="RXB7D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E78" access="33333333" name="RXB7D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E77" access="33333333" name="RXB7D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E76" access="33333333" name="RXB7D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E75" access="03333333" name="RXB7DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E73" size="2" name="RXB7EID" />
+    <sfr address="0x0E74" access="33333333" name="RXB7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E73" access="33333333" name="RXB7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E72" access="33303033" name="RXB7SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E71" access="33333333" name="RXB7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E70" access="33333333" name="RXB7CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6D" access="33333333" name="RXB6D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6C" access="33333333" name="RXB6D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6B" access="33333333" name="RXB6D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6A" access="33333333" name="RXB6D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E69" access="33333333" name="RXB6D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E68" access="33333333" name="RXB6D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E67" access="33333333" name="RXB6D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E66" access="33333333" name="RXB6D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E65" access="03333333" name="RXB6DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E63" size="2" name="RXB6EID" />
+    <sfr address="0x0E64" access="33333333" name="RXB6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E63" access="33333333" name="RXB6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E62" access="33303033" name="RXB6SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E61" access="33333333" name="RXB6SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E60" access="33333333" name="RXB6CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5D" access="33333333" name="RXB5D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5C" access="33333333" name="RXB5D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5B" access="33333333" name="RXB5D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5A" access="33333333" name="RXB5D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E59" access="33333333" name="RXB5D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E58" access="33333333" name="RXB5D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E57" access="33333333" name="RXB5D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E56" access="33333333" name="RXB5D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03333333" name="RXB5DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E53" size="2" name="RXB5EID" />
+    <sfr address="0x0E54" access="33333333" name="RXB5EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="RXB5EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33303033" name="RXB5SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="RXB5SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33333333" name="RXB5CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4D" access="33333333" name="RXB4D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="RXB4D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="RXB4D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="RXB4D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="RXB4D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="RXB4D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="RXB4D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="RXB4D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03333333" name="RXB4DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E43" size="2" name="RXB4EID" />
+    <sfr address="0x0E44" access="33333333" name="RXB4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="RXB4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33303033" name="RXB4SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="RXB4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33333333" name="RXB4CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3D" access="33333333" name="RXB3D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="RXB3D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="RXB3D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="RXB3D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="RXB3D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="RXB3D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="RXB3D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="RXB3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03333333" name="RXB3DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E33" size="2" name="RXB3EID" />
+    <sfr address="0x0E34" access="33333333" name="RXB3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="RXB3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33303033" name="RXB3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="RXB3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33333333" name="RXB3CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2D" access="33333333" name="RXB2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="RXB2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="RXB2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="RXB2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="RXB2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="RXB2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="RXB2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="RXB2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03333333" name="RXB2DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E23" size="2" name="RXB2EID" />
+    <sfr address="0x0E24" access="33333333" name="RXB2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="RXB2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33303033" name="RXB2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="RXB2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33333333" name="RXB2CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0DFC" access="00033300" name="TX_BUFINTEN" mclr="00033300" por="00000000" />
+    <sfr address="0x0DFA" access="33333333" name="BUF_INT_EN0" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF8" access="33333300" name="RX_TX_SEL0" mclr="33333300" por="00000000" />
+    <sfr address="0x0DF3" access="33333333" name="MSK_SEL3" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF2" access="33333333" name="MSK_SEL2" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF1" access="33333333" name="MSK_SEL1" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF0" access="33333333" name="MSK_SEL0" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE7" access="33333333" name="BUFPNT1514" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE6" access="33333333" name="BUFPNT1312" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE5" access="33333333" name="BUFPNT1110" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE4" access="33333333" name="BUFPNT98" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE3" access="33333333" name="BUFPNT76" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE2" access="33333333" name="BUFPNT54" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE1" access="33333333" name="BUFPNT32" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE0" access="33333333" name="BUFPNT10" mclr="33333333" por="00000000" />
+    <sfr address="0x0DD8" access="00033333" name="DEV_NET_CT" mclr="00033333" por="00000000" />
+    <sfr address="0x0DD5" access="33333333" name="FER1" mclr="33333333" por="00000000" />
+    <sfr address="0x0DD4" access="33333333" name="FER0" mclr="33333333" por="00000000" />
+    <combined address="0x0D92" size="2" name="RXF15EID" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33303033" name="RXF15SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D8A" size="2" name="RXF14EID" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33303033" name="RXF14SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D86" size="2" name="RXF13EID" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33303033" name="RXF13SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D82" size="2" name="RXF12EID" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33303033" name="RXF12SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D7A" size="2" name="RXF11EID" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33303033" name="RXF11SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D76" size="2" name="RXF10EID" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33303033" name="RXF10SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D72" size="2" name="RXF9EID" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33303033" name="RXF9SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D6A" size="2" name="RXF8EID" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33303033" name="RXF8SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D66" size="2" name="RXF7EID" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33303033" name="RXF7SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D62" size="2" name="RXF6EID" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33303033" name="RXF6SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F2585" unused_bank_mask="0x0000" >
+    <unused end="0x0D59" start="0x0D00" />
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
+    <unused end="0x0D8F" start="0x0D8C" />
+    <unused end="0x0DD3" start="0x0D94" />
+    <unused end="0x0DD7" start="0x0DD6" />
+    <unused end="0x0DDF" start="0x0DD9" />
+    <unused end="0x0DEF" start="0x0DE8" />
+    <unused end="0x0DF7" start="0x0DF4" />
+    <unused end="0x0DF9" start="0x0DF9" />
+    <unused end="0x0DFB" start="0x0DFB" />
+    <unused end="0x0DFF" start="0x0DFD" />
+    <unused end="0x0E1F" start="0x0E00" />
+    <unused end="0x0EFF" start="0x0E80" />
+    <unused end="0x0F7F" start="0x0F78" />
+    <unused end="0x0F88" start="0x0F83" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9A" start="0x0F95" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB7" start="0x0FB6" />
+    <unused end="0x0FBC" start="0x0FBA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
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+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
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+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="12113111" por="12113111" />
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+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
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+    <sfr address="0x0FA4" access="33333333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="30033333" name="IPR2" mclr="20022222" por="20022222" />
+    <sfr address="0x0FA1" access="30033333" name="PIR2" mclr="10011111" por="10011111" />
+    <sfr address="0x0FA0" access="30033333" name="PIE2" mclr="10011111" por="10011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9B" access="30033333" name="OSCTUNE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
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+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
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+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
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+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
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+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
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+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
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+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30330333" name="T1CON" mclr="30330333" por="10110111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
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+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
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+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0F77" access="33333333" name="ECANCON" mclr="11121111" por="11121111" />
+    <sfr address="0x0F76" access="11111111" name="TXERRCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F75" access="11111111" name="RXERRCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F74" access="55111111" name="COMSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F73" access="00330000" name="CIOCON" mclr="00110000" por="00110000" />
+    <sfr address="0x0F72" access="33000333" name="BRGCON3" mclr="11000111" por="11000111" />
+    <sfr address="0x0F71" access="33333333" name="BRGCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F70" access="33333333" name="BRGCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33393331" name="CANCON" mclr="21111111" por="21111111" />
+    <sfr address="0x0F6E" access="11111111" name="CANSTAT" mclr="21111111" por="21111111" />
+    <sfr address="0x0F6D" access="11111111" name="RXB0D7" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F6B" access="11111111" name="RXB0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6A" access="11111111" name="RXB0D4" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F66" access="11111111" name="RXB0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="01111111" name="RXB0DLC" mclr="13333333" por="10000000" />
+    <sfr address="0x0F64" access="11111111" name="RXB0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F63" access="11111111" name="RXB0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F62" access="11111011" name="RXB0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0F61" access="11111111" name="RXB0SIDH" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F5F" access="33393331" name="CANCON_RO0" mclr="21111111" por="21111111" />
+    <sfr address="0x0F5E" access="11111111" name="CANSTAT_RO0" mclr="21111111" por="21111111" />
+    <sfr address="0x0F5D" access="11111111" name="RXB1D7" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F58" access="11111111" name="RXB1D2" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F56" access="11111111" name="RXB1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F55" access="01111111" name="RXB1DLC" mclr="13333333" por="10000000" />
+    <sfr address="0x0F54" access="11111111" name="RXB1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F53" access="11111111" name="RXB1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F52" access="11111011" name="RXB1SIDL" mclr="33333133" por="00000100" />
+    <sfr address="0x0F51" access="11111111" name="RXB1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F50" access="53311311" name="RXB1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F4F" access="33393331" name="CANCON_RO1" mclr="21111111" por="21111111" />
+    <sfr address="0x0F4E" access="11111111" name="CANSTAT_RO1" mclr="21111111" por="21111111" />
+    <sfr address="0x0F4D" access="33333333" name="TXB0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F4C" access="33333333" name="TXB0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F4B" access="33333333" name="TXB0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F4A" access="33333333" name="TXB0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F49" access="33333333" name="TXB0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F48" access="33333333" name="TXB0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F47" access="33333333" name="TXB0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F46" access="33333333" name="TXB0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F45" access="03003333" name="TXB0DLC" mclr="13113333" por="10110000" />
+    <sfr address="0x0F44" access="33333333" name="TXB0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F43" access="33333333" name="TXB0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F42" access="33303033" name="TXB0SIDL" mclr="33303033" por="00000000" />
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+    <sfr address="0x0F40" access="51113033" name="TXB0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F3F" access="33393331" name="CANCON_RO2" mclr="21111111" por="21111111" />
+    <sfr address="0x0F3E" access="11111111" name="CANSTAT_RO2" mclr="21111111" por="21111111" />
+    <sfr address="0x0F3D" access="33333333" name="TXB1D7" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F3A" access="33333333" name="TXB1D4" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F36" access="33333333" name="TXB1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F35" access="03003333" name="TXB1DLC" mclr="03003333" por="00000000" />
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+    <sfr address="0x0F33" access="33333333" name="TXB1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F32" access="33303033" name="TXB1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F31" access="33333333" name="TXB1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F30" access="51113033" name="TXB1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F2F" access="33393331" name="CANCON_RO3" mclr="21111111" por="21111111" />
+    <sfr address="0x0F2E" access="11111111" name="CANSTAT_RO3" mclr="21111111" por="21111111" />
+    <sfr address="0x0F2D" access="33333333" name="TXB2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2C" access="33333333" name="TXB2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2B" access="33333333" name="TXB2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2A" access="33333333" name="TXB2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F29" access="33333333" name="TXB2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F28" access="33333333" name="TXB2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F27" access="33333333" name="TXB2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F26" access="33333333" name="TXB2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F25" access="03003333" name="TXB2DLC" mclr="03003333" por="00000000" />
+    <sfr address="0x0F24" access="33333333" name="TXB2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F23" access="33333333" name="TXB2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F22" access="33333333" name="TXB2SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F21" access="33333333" name="TXB2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F20" access="51113033" name="TXB2CON" mclr="11111011" por="11111011" />
+    <sfr address="0x0F1F" access="33333333" name="RXM1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1E" access="33333333" name="RXM1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1D" access="33303033" name="RXM1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F1C" access="33333333" name="RXM1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1B" access="33333333" name="RXM0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1A" access="33333333" name="RXM0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F19" access="33303033" name="RXM0SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F18" access="33333333" name="RXM0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F17" access="33333333" name="RXF5EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F16" access="33333333" name="RXF5EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F15" access="33303033" name="RXF5SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F14" access="33333333" name="RXF5SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F13" access="33333333" name="RXF4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F12" access="33333333" name="RXF4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F11" access="33303033" name="RXF4SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F10" access="33333333" name="RXF4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0F" access="33333333" name="RXF3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0E" access="33333333" name="RXF3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0D" access="33303033" name="RXF3SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F0C" access="33333333" name="RXF3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0B" access="33333333" name="RXF2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0A" access="33333333" name="RXF2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F09" access="33303033" name="RXF2SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F08" access="33333333" name="RXF2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F07" access="33333333" name="RXF1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F06" access="33333333" name="RXF1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F05" access="33303033" name="RXF1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F04" access="33333333" name="RXF1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F03" access="33333333" name="RXF0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F02" access="33333333" name="RXF0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F01" access="33303033" name="RXF0SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F00" access="33333333" name="RXF0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E7F" access="33393331" name="CANCON_RO4" mclr="21111111" por="21111111" />
+    <sfr address="0x0E7E" access="11111111" name="CANSTAT_RO4" mclr="21111111" por="21111111" />
+    <sfr address="0x0E7D" access="33333333" name="B5D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E7C" access="33333333" name="B5D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E7B" access="33333333" name="B5D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E7A" access="33333333" name="B5D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E79" access="33333333" name="B5D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E78" access="33333333" name="B5D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E77" access="33333333" name="B5D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E76" access="33333333" name="B5D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E75" access="03113333" name="B5DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E74" access="33333333" name="B5EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E73" access="33333333" name="B5EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E72" access="33333033" name="B5SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E71" access="33333333" name="B5SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E70" access="33113333" name="B5CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E6F" access="33393331" name="CANCON_RO5" mclr="21111111" por="21111111" />
+    <sfr address="0x0E6E" access="11111111" name="CANSTAT_RO5" mclr="21111111" por="21111111" />
+    <sfr address="0x0E6D" access="33333333" name="B4D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6C" access="33333333" name="B4D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6B" access="33333333" name="B4D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6A" access="33333333" name="B4D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E69" access="33333333" name="B4D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E68" access="33333333" name="B4D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E67" access="33333333" name="B4D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E66" access="33333333" name="B4D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E65" access="03113333" name="B4DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E64" access="33333333" name="B4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E63" access="33333333" name="B4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E62" access="33333033" name="B4SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E61" access="33333333" name="B4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E60" access="33113333" name="B4CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E5F" access="33393331" name="CANCON_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5E" access="11111111" name="CANSTAT_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5D" access="33333333" name="B3D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5C" access="33333333" name="B3D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5B" access="33333333" name="B3D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5A" access="33333333" name="B3D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E59" access="33333333" name="B3D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E58" access="33333333" name="B3D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E57" access="33333333" name="B3D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E56" access="33333333" name="B3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03113333" name="B3DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E54" access="33333333" name="B3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="B3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33333033" name="B3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="B3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33113333" name="B3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E4F" access="33393331" name="CANCON_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4E" access="11111111" name="CANSTAT_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4D" access="33333333" name="B2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="B2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="B2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="B2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="B2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="B2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="B2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="B2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03113333" name="B2DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E44" access="33333333" name="B2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="B2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33333033" name="B2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="B2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33113333" name="B2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E3F" access="33393331" name="CANCON_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3E" access="11111111" name="CANSTAT_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3D" access="33333333" name="B1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="B1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="B1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="B1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="B1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="B1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="B1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="B1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03113333" name="B1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E34" access="33333333" name="B1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="B1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33333033" name="B1SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="B1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33113333" name="B1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E2F" access="33393331" name="CANCON_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2E" access="11111111" name="CANSTAT_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2D" access="33333333" name="B0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="B0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="B0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="B0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="B0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="B0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="B0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="B0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03113333" name="B0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E24" access="33333333" name="B0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="B0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33333033" name="B0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="B0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33113333" name="B0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0DFC" access="00033300" name="TXBIE" mclr="00033300" por="00011100" />
+    <sfr address="0x0DFA" access="33333333" name="BIE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF8" access="33333300" name="BSEL0" mclr="11111100" por="11111100" />
+    <sfr address="0x0DF3" access="33333333" name="MSEL3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF2" access="33333333" name="MSEL2" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF1" access="33333333" name="MSEL1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF0" access="33333333" name="MSEL0" mclr="12121111" por="12121111" />
+    <sfr address="0x0DE7" access="33333333" name="RXFBCON7" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE6" access="33333333" name="RXFBCON6" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE5" access="33333333" name="RXFBCON5" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE4" access="33333333" name="RXFBCON4" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE3" access="33333333" name="RXFBCON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE2" access="33333333" name="RXFBCON2" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE1" access="33333333" name="RXFBCON1" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE0" access="33333333" name="RXFBCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD8" access="00033333" name="SDFLC" mclr="00011111" por="00011111" />
+    <sfr address="0x0DD5" access="33333333" name="RXFCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD4" access="33333333" name="RXFCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33303033" name="RXF15SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33303033" name="RXF14SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33303033" name="RXF13SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33303033" name="RXF12SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33303033" name="RXF11SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33303033" name="RXF10SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33303033" name="RXF9SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33303033" name="RXF8SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33303033" name="RXF7SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33303033" name="RXF6SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F25J10" unused_bank_mask="0x7FF0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="12034433" por="10022211" />
+    <sfr address="0x0FA5" access="03000000" name="IPR3" mclr="02000000" por="02000000" />
+    <sfr address="0x0FA4" access="03000000" name="PIR3" mclr="01000000" por="01000000" />
+    <sfr address="0x0FA3" access="03000000" name="PIE3" mclr="01000000" por="01000000" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002002" por="22002002" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001001" por="11001001" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001001" por="11001001" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="00303333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="00303333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="00303333" name="TRISA" mclr="00202222" por="00202222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCP1AS" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="PWM1CON" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2610" unused_bank_mask="0x0000" >
+    <unused end="0x0F83" start="0x0F83" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9A" start="0x0F95" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001111" por="11001111" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9B" access="30033333" name="OSCTUNE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001000" name="PORTE" mclr="00003000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCPAS1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="PWM1CON" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F2620" unused_bank_mask="0x0000" >
+    <unused end="0x0F83" start="0x0F83" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9A" start="0x0F95" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="12114111" por="12114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="10011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001000" name="PORTE" mclr="00003000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FB6" access="33333300" name="ECCPAS1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FB7" access="30000000" name="PWM1CON" mclr="10000000" por="10000000" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F2680" unused_bank_mask="0x0000" >
+    <unused end="0x0D59" start="0x0D00" />
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
+    <unused end="0x0D8F" start="0x0D8C" />
+    <unused end="0x0DD3" start="0x0D94" />
+    <unused end="0x0DD7" start="0x0DD6" />
+    <unused end="0x0DDF" start="0x0DD9" />
+    <unused end="0x0DEF" start="0x0DE8" />
+    <unused end="0x0DF7" start="0x0DF4" />
+    <unused end="0x0DF9" start="0x0DF9" />
+    <unused end="0x0DFB" start="0x0DFB" />
+    <unused end="0x0DFF" start="0x0DFD" />
+    <unused end="0x0E1F" start="0x0E00" />
+    <unused end="0x0EFF" start="0x0E80" />
+    <unused end="0x0F7F" start="0x0F78" />
+    <unused end="0x0F88" start="0x0F83" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9A" start="0x0F95" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB7" start="0x0FB6" />
+    <unused end="0x0FBC" start="0x0FBA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
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+    <sfr address="0x0E71" access="33333333" name="B5SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E70" access="33113333" name="B5CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E6F" access="33393331" name="CANCON_RO5" mclr="21111111" por="21111111" />
+    <sfr address="0x0E6E" access="11111111" name="CANSTAT_RO5" mclr="21111111" por="21111111" />
+    <sfr address="0x0E6D" access="33333333" name="B4D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6C" access="33333333" name="B4D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6B" access="33333333" name="B4D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6A" access="33333333" name="B4D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E69" access="33333333" name="B4D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E68" access="33333333" name="B4D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E67" access="33333333" name="B4D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E66" access="33333333" name="B4D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E65" access="03113333" name="B4DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E64" access="33333333" name="B4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E63" access="33333333" name="B4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E62" access="33333033" name="B4SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E61" access="33333333" name="B4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E60" access="33113333" name="B4CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E5F" access="33393331" name="CANCON_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5E" access="11111111" name="CANSTAT_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5D" access="33333333" name="B3D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5C" access="33333333" name="B3D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5B" access="33333333" name="B3D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5A" access="33333333" name="B3D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E59" access="33333333" name="B3D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E58" access="33333333" name="B3D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E57" access="33333333" name="B3D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E56" access="33333333" name="B3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03113333" name="B3DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E54" access="33333333" name="B3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="B3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33333033" name="B3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="B3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33113333" name="B3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E4F" access="33393331" name="CANCON_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4E" access="11111111" name="CANSTAT_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4D" access="33333333" name="B2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="B2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="B2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="B2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="B2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="B2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="B2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="B2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03113333" name="B2DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E44" access="33333333" name="B2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="B2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33333033" name="B2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="B2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33113333" name="B2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E3F" access="33393331" name="CANCON_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3E" access="11111111" name="CANSTAT_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3D" access="33333333" name="B1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="B1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="B1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="B1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="B1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="B1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="B1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="B1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03113333" name="B1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E34" access="33333333" name="B1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="B1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33333033" name="B1SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="B1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33113333" name="B1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E2F" access="33393331" name="CANCON_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2E" access="11111111" name="CANSTAT_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2D" access="33333333" name="B0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="B0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="B0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="B0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="B0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="B0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="B0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="B0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03113333" name="B0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E24" access="33333333" name="B0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="B0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33333033" name="B0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="B0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33113333" name="B0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0DFC" access="00033300" name="TXBIE" mclr="00033300" por="00011100" />
+    <sfr address="0x0DFA" access="33333333" name="BIE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF8" access="33333300" name="BSEL0" mclr="11111100" por="11111100" />
+    <sfr address="0x0DF3" access="33333333" name="MSEL3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF2" access="33333333" name="MSEL2" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF1" access="33333333" name="MSEL1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF0" access="33333333" name="MSEL0" mclr="12121111" por="12121111" />
+    <sfr address="0x0DE7" access="33333333" name="RXFBCON7" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE6" access="33333333" name="RXFBCON6" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE5" access="33333333" name="RXFBCON5" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE4" access="33333333" name="RXFBCON4" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE3" access="33333333" name="RXFBCON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE2" access="33333333" name="RXFBCON2" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE1" access="33333333" name="RXFBCON1" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE0" access="33333333" name="RXFBCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD8" access="00033333" name="SDFLC" mclr="00011111" por="00011111" />
+    <sfr address="0x0DD5" access="33333333" name="RXFCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD4" access="33333333" name="RXFCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33303033" name="RXF15SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33303033" name="RXF14SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33303033" name="RXF13SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33303033" name="RXF12SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33303033" name="RXF11SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33303033" name="RXF10SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33303033" name="RXF9SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33303033" name="RXF8SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33303033" name="RXF7SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33303033" name="RXF6SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F2682" unused_bank_mask="0x0000" >
+    <unused end="0x0D59" start="0x0D00" />
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
+    <unused end="0x0D8F" start="0x0D8C" />
+    <unused end="0x0DD3" start="0x0D94" />
+    <unused end="0x0DD7" start="0x0DD6" />
+    <unused end="0x0DDF" start="0x0DD9" />
+    <unused end="0x0DEF" start="0x0DE8" />
+    <unused end="0x0DF7" start="0x0DF4" />
+    <unused end="0x0DF9" start="0x0DF9" />
+    <unused end="0x0DFB" start="0x0DFB" />
+    <unused end="0x0DFF" start="0x0DFD" />
+    <unused end="0x0E1F" start="0x0E00" />
+    <unused end="0x0EFF" start="0x0E80" />
+    <unused end="0x0F7F" start="0x0F78" />
+    <unused end="0x0F88" start="0x0F83" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9A" start="0x0F95" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB7" start="0x0FB6" />
+    <unused end="0x0FBC" start="0x0FBA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="12113111" por="12113111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
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+    <sfr address="0x0E6D" access="33333333" name="B4D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6C" access="33333333" name="B4D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6B" access="33333333" name="B4D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6A" access="33333333" name="B4D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E69" access="33333333" name="B4D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E68" access="33333333" name="B4D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E67" access="33333333" name="B4D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E66" access="33333333" name="B4D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E65" access="03113333" name="B4DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E64" access="33333333" name="B4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E63" access="33333333" name="B4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E62" access="33333033" name="B4SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E61" access="33333333" name="B4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E60" access="33113333" name="B4CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E5F" access="33393331" name="CANCON_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5E" access="11111111" name="CANSTAT_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5D" access="33333333" name="B3D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5C" access="33333333" name="B3D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5B" access="33333333" name="B3D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5A" access="33333333" name="B3D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E59" access="33333333" name="B3D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E58" access="33333333" name="B3D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E57" access="33333333" name="B3D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E56" access="33333333" name="B3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03113333" name="B3DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E54" access="33333333" name="B3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="B3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33333033" name="B3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="B3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33113333" name="B3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E4F" access="33393331" name="CANCON_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4E" access="11111111" name="CANSTAT_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4D" access="33333333" name="B2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="B2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="B2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="B2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="B2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="B2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="B2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="B2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03113333" name="B2DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E44" access="33333333" name="B2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="B2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33333033" name="B2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="B2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33113333" name="B2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E3F" access="33393331" name="CANCON_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3E" access="11111111" name="CANSTAT_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3D" access="33333333" name="B1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="B1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="B1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="B1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="B1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="B1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="B1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="B1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03113333" name="B1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E34" access="33333333" name="B1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="B1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33333033" name="B1SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="B1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33113333" name="B1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E2F" access="33393331" name="CANCON_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2E" access="11111111" name="CANSTAT_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2D" access="33333333" name="B0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="B0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="B0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="B0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="B0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="B0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="B0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="B0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03113333" name="B0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E24" access="33333333" name="B0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="B0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33333033" name="B0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="B0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33113333" name="B0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0DFC" access="00033300" name="TXBIE" mclr="00033300" por="00011100" />
+    <sfr address="0x0DFA" access="33333333" name="BIE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF8" access="33333300" name="BSEL0" mclr="11111100" por="11111100" />
+    <sfr address="0x0DF3" access="33333333" name="MSEL3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF2" access="33333333" name="MSEL2" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF1" access="33333333" name="MSEL1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF0" access="33333333" name="MSEL0" mclr="12121111" por="12121111" />
+    <sfr address="0x0DE7" access="33333333" name="RXFBCON7" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE6" access="33333333" name="RXFBCON6" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE5" access="33333333" name="RXFBCON5" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE4" access="33333333" name="RXFBCON4" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE3" access="33333333" name="RXFBCON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE2" access="33333333" name="RXFBCON2" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE1" access="33333333" name="RXFBCON1" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE0" access="33333333" name="RXFBCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD8" access="00033333" name="SDFLC" mclr="00011111" por="00011111" />
+    <sfr address="0x0DD5" access="33333333" name="RXFCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD4" access="33333333" name="RXFCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33303033" name="RXF15SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33303033" name="RXF14SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33303033" name="RXF13SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33303033" name="RXF12SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33303033" name="RXF11SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33303033" name="RXF10SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33303033" name="RXF9SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33303033" name="RXF8SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33303033" name="RXF7SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33303033" name="RXF6SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F2685" unused_bank_mask="0x0000" >
+    <unused end="0x0D59" start="0x0D00" />
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
+    <unused end="0x0D8F" start="0x0D8C" />
+    <unused end="0x0DD3" start="0x0D94" />
+    <unused end="0x0DD7" start="0x0DD6" />
+    <unused end="0x0DDF" start="0x0DD9" />
+    <unused end="0x0DEF" start="0x0DE8" />
+    <unused end="0x0DF7" start="0x0DF4" />
+    <unused end="0x0DF9" start="0x0DF9" />
+    <unused end="0x0DFB" start="0x0DFB" />
+    <unused end="0x0DFF" start="0x0DFD" />
+    <unused end="0x0E1F" start="0x0E00" />
+    <unused end="0x0EFF" start="0x0E80" />
+    <unused end="0x0F7F" start="0x0F78" />
+    <unused end="0x0F88" start="0x0F83" />
+    <unused end="0x0F91" start="0x0F8C" />
+    <unused end="0x0F9A" start="0x0F95" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB7" start="0x0FB6" />
+    <unused end="0x0FBC" start="0x0FBA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="12113111" por="12113111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33333333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
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+    <sfr address="0x0E69" access="33333333" name="B4D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E68" access="33333333" name="B4D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E67" access="33333333" name="B4D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E66" access="33333333" name="B4D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E65" access="03113333" name="B4DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E64" access="33333333" name="B4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E63" access="33333333" name="B4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E62" access="33333033" name="B4SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E61" access="33333333" name="B4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E60" access="33113333" name="B4CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E5F" access="33393331" name="CANCON_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5E" access="11111111" name="CANSTAT_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5D" access="33333333" name="B3D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5C" access="33333333" name="B3D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5B" access="33333333" name="B3D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5A" access="33333333" name="B3D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E59" access="33333333" name="B3D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E58" access="33333333" name="B3D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E57" access="33333333" name="B3D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E56" access="33333333" name="B3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03113333" name="B3DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E54" access="33333333" name="B3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="B3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33333033" name="B3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="B3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33113333" name="B3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E4F" access="33393331" name="CANCON_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4E" access="11111111" name="CANSTAT_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4D" access="33333333" name="B2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="B2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="B2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="B2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="B2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="B2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="B2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="B2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03113333" name="B2DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E44" access="33333333" name="B2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="B2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33333033" name="B2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="B2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33113333" name="B2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E3F" access="33393331" name="CANCON_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3E" access="11111111" name="CANSTAT_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3D" access="33333333" name="B1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="B1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="B1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="B1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="B1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="B1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="B1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="B1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03113333" name="B1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E34" access="33333333" name="B1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="B1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33333033" name="B1SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="B1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33113333" name="B1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E2F" access="33393331" name="CANCON_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2E" access="11111111" name="CANSTAT_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2D" access="33333333" name="B0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="B0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="B0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="B0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="B0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="B0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="B0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="B0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03113333" name="B0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E24" access="33333333" name="B0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="B0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33333033" name="B0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="B0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33113333" name="B0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0DFC" access="00033300" name="TXBIE" mclr="00033300" por="00011100" />
+    <sfr address="0x0DFA" access="33333333" name="BIE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF8" access="33333300" name="BSEL0" mclr="11111100" por="11111100" />
+    <sfr address="0x0DF3" access="33333333" name="MSEL3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF2" access="33333333" name="MSEL2" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF1" access="33333333" name="MSEL1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF0" access="33333333" name="MSEL0" mclr="12121111" por="12121111" />
+    <sfr address="0x0DE7" access="33333333" name="RXFBCON7" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE6" access="33333333" name="RXFBCON6" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE5" access="33333333" name="RXFBCON5" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE4" access="33333333" name="RXFBCON4" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE3" access="33333333" name="RXFBCON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE2" access="33333333" name="RXFBCON2" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE1" access="33333333" name="RXFBCON1" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE0" access="33333333" name="RXFBCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD8" access="00033333" name="SDFLC" mclr="00011111" por="00011111" />
+    <sfr address="0x0DD5" access="33333333" name="RXFCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD4" access="33333333" name="RXFCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33303033" name="RXF15SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33303033" name="RXF14SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33303033" name="RXF13SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33303033" name="RXF12SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33303033" name="RXF11SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33303033" name="RXF10SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33303033" name="RXF9SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33303033" name="RXF8SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33303033" name="RXF7SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33303033" name="RXF6SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4220" unused_bank_mask="0x7FFC" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB8" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11111141" por="11114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4221" unused_bank_mask="0x7FFC" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11111141" por="11114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0FB8" access="31333033" name="BAUDCON" mclr="12111011" por="12111011" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4320" unused_bank_mask="0x7FFC" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB8" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11111141" por="11114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4321" unused_bank_mask="0x7FFC" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11114111" por="11114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0FB8" access="31333033" name="BAUDCON" mclr="12111011" por="12111011" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F4331" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F86" start="0x0F85" />
+    <unused end="0x0F8F" start="0x0F8E" />
+    <unused end="0x0F98" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB5" start="0x0FB1" />
+    <unused end="0x0FC5" start="0x0FC5" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="11111113" name="WDTCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10022244" />
+    <sfr address="0x0FA5" access="00033333" name="IPR3" mclr="00022222" por="00022222" />
+    <sfr address="0x0FA4" access="00033333" name="PIR3" mclr="00011111" por="00011111" />
+    <sfr address="0x0FA3" access="00033333" name="PIE3" mclr="00011111" por="00011111" />
+    <sfr address="0x0FA2" access="30030303" name="IPR2" mclr="20020202" por="20020202" />
+    <sfr address="0x0FA1" access="30030303" name="PIR2" mclr="10010101" por="10010101" />
+    <sfr address="0x0FA0" access="30030303" name="PIE2" mclr="10010101" por="10010101" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33111111" por="00111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00003111" por="00000111" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="00000333" name="TRISE" mclr="00000222" por="00000222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="33031111" name="ADCON1" mclr="11011111" por="11011111" />
+    <sfr address="0x0FC0" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9A" access="33033333" name="ADCON3" mclr="11011111" por="11011111" />
+    <sfr address="0x0F99" access="33333333" name="ADCHS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="00000003" name="ANSEL1" mclr="00000002" por="00000002" />
+    <sfr address="0x0FB8" access="33333333" name="ANSEL0" mclr="22222222" por="22222222" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="33331133" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB7" access="33333333" name="T5CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F90" size="2" name="PR5" />
+    <sfr address="0x0F91" access="33333333" name="PR5H" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="PR5L" mclr="22222222" por="22222222" />
+    <combined address="0x0F87" size="2" name="TMR5" />
+    <sfr address="0x0F88" access="33333333" name="TMR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="TMR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0FAA" access="01033033" name="BAUDCTL" mclr="02021011" por="02021011" />
+    <sfr address="0x0F7F" access="33333333" name="PTCON0" mclr="33333333" por="11111111" />
+    <sfr address="0x0F7E" access="31000000" name="PTCON1" mclr="11000000" por="11000000" />
+    <sfr address="0x0F7D" access="33333333" name="PTMRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F7C" access="00003333" name="PTMRH" mclr="00001111" por="00001111" />
+    <sfr address="0x0F7B" access="33333333" name="PTPERL" mclr="22222222" por="22222222" />
+    <sfr address="0x0F7A" access="00003333" name="PTPERH" mclr="00002222" por="00002222" />
+    <sfr address="0x0F79" access="33333333" name="PDC0L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F78" access="00333333" name="PDC0H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F77" access="33333333" name="PDC1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F76" access="00333333" name="PDC1H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F75" access="33333333" name="PDC2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F74" access="00333333" name="PDC2H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F73" access="33333333" name="PDC3L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F72" access="00333333" name="PDC3H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F71" access="33333333" name="SEVTCMPL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F70" access="00003333" name="SEVTCMPH" mclr="00001111" por="00001111" />
+    <sfr address="0x0F6F" access="03333333" name="PWMCON0" mclr="02121111" por="02121111" />
+    <sfr address="0x0F6E" access="33333033" name="PWMCON1" mclr="11111011" por="11111011" />
+    <sfr address="0x0F6D" access="33333333" name="DTCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="03333333" name="FLTCONFIG" mclr="01111111" por="01111111" />
+    <sfr address="0x0F6B" access="33333333" name="OVDCOND" mclr="22222222" por="22222222" />
+    <sfr address="0x0F6A" access="33333333" name="OVDCONS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="03303333" name="CAP1CON" mclr="02101111" por="02101111" />
+    <sfr address="0x0F62" access="03303333" name="CAP2CON" mclr="02101111" por="02101111" />
+    <sfr address="0x0F61" access="03303333" name="CAP3CON" mclr="02101111" por="02101111" />
+    <sfr address="0x0FB6" access="30333333" name="QEICON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F60" access="03333333" name="DFLTCON" mclr="01111111" por="01111111" />
+    <sfr address="0x0F69" access="33333333" name="CAP1BUFH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F69" access="33333333" name="VELRH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="CAP1BUFL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="VELRL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CAP2BUFH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="POSCNTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="CAP2BUFL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="POSCNTL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="CAP3BUFH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="MAXCNTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F64" access="33333333" name="CAP3BUFL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F64" access="33333333" name="MAXCNTL" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4410" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F442" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9C" start="0x0F97" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10042211" />
+    <sfr address="0x0FA2" access="00033333" name="IPR2" mclr="00022222" por="00022222" />
+    <sfr address="0x0FA1" access="00033333" name="PIR2" mclr="00011111" por="00011111" />
+    <sfr address="0x0FA0" access="00033333" name="PIE2" mclr="00011111" por="00011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4420" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD3" access="33330100" name="OSCCON" mclr="11110100" por="12110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
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+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4423" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
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+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
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+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
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+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03330303" name="INTCON2" mclr="02220202" por="02220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
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+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
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+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
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+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
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+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F4431" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F86" start="0x0F85" />
+    <unused end="0x0F8F" start="0x0F8E" />
+    <unused end="0x0F98" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB5" start="0x0FB1" />
+    <unused end="0x0FC5" start="0x0FC5" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="11111113" name="WDTCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10022244" />
+    <sfr address="0x0FA5" access="00033333" name="IPR3" mclr="00022222" por="00022222" />
+    <sfr address="0x0FA4" access="00033333" name="PIR3" mclr="00011111" por="00011111" />
+    <sfr address="0x0FA3" access="00033333" name="PIE3" mclr="00011111" por="00011111" />
+    <sfr address="0x0FA2" access="30030303" name="IPR2" mclr="20020202" por="20020202" />
+    <sfr address="0x0FA1" access="30030303" name="PIR2" mclr="10010101" por="10010101" />
+    <sfr address="0x0FA0" access="30030303" name="PIE2" mclr="10010101" por="10010101" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33111111" por="00111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00003111" por="00000111" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="00000333" name="TRISE" mclr="00000222" por="00000222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="33031111" name="ADCON1" mclr="11011111" por="11011111" />
+    <sfr address="0x0FC0" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9A" access="33033333" name="ADCON3" mclr="11011111" por="11011111" />
+    <sfr address="0x0F99" access="33333333" name="ADCHS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="00000003" name="ANSEL1" mclr="00000002" por="00000002" />
+    <sfr address="0x0FB8" access="33333333" name="ANSEL0" mclr="22222222" por="22222222" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="33331133" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB7" access="33333333" name="T5CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F90" size="2" name="PR5" />
+    <sfr address="0x0F91" access="33333333" name="PR5H" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="PR5L" mclr="22222222" por="22222222" />
+    <combined address="0x0F87" size="2" name="TMR5" />
+    <sfr address="0x0F88" access="33333333" name="TMR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="TMR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="33333333" por="00000000" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0FAA" access="01033033" name="BAUDCTL" mclr="02021011" por="02021011" />
+    <sfr address="0x0F7F" access="33333333" name="PTCON0" mclr="33333333" por="11111111" />
+    <sfr address="0x0F7E" access="31000000" name="PTCON1" mclr="11000000" por="11000000" />
+    <sfr address="0x0F7D" access="33333333" name="PTMRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F7C" access="00003333" name="PTMRH" mclr="00001111" por="00001111" />
+    <sfr address="0x0F7B" access="33333333" name="PTPERL" mclr="22222222" por="22222222" />
+    <sfr address="0x0F7A" access="00003333" name="PTPERH" mclr="00002222" por="00002222" />
+    <sfr address="0x0F79" access="33333333" name="PDC0L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F78" access="00333333" name="PDC0H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F77" access="33333333" name="PDC1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F76" access="00333333" name="PDC1H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F75" access="33333333" name="PDC2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F74" access="00333333" name="PDC2H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F73" access="33333333" name="PDC3L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F72" access="00333333" name="PDC3H" mclr="00111111" por="00111111" />
+    <sfr address="0x0F71" access="33333333" name="SEVTCMPL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F70" access="00003333" name="SEVTCMPH" mclr="00001111" por="00001111" />
+    <sfr address="0x0F6F" access="03333333" name="PWMCON0" mclr="02121111" por="02121111" />
+    <sfr address="0x0F6E" access="33333033" name="PWMCON1" mclr="11111011" por="11111011" />
+    <sfr address="0x0F6D" access="33333333" name="DTCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="03333333" name="FLTCONFIG" mclr="01111111" por="01111111" />
+    <sfr address="0x0F6B" access="33333333" name="OVDCOND" mclr="22222222" por="22222222" />
+    <sfr address="0x0F6A" access="33333333" name="OVDCONS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="03303333" name="CAP1CON" mclr="02101111" por="02101111" />
+    <sfr address="0x0F62" access="03303333" name="CAP2CON" mclr="02101111" por="02101111" />
+    <sfr address="0x0F61" access="03303333" name="CAP3CON" mclr="02101111" por="02101111" />
+    <sfr address="0x0FB6" access="30333333" name="QEICON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F60" access="03333333" name="DFLTCON" mclr="01111111" por="01111111" />
+    <sfr address="0x0F69" access="33333333" name="CAP1BUFH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F69" access="33333333" name="VELRH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="CAP1BUFL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="VELRL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CAP2BUFH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="POSCNTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="CAP2BUFL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="POSCNTL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="CAP3BUFH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="MAXCNTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F64" access="33333333" name="CAP3BUFL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F64" access="33333333" name="MAXCNTL" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4439" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9C" start="0x0F97" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="00033330" name="IPR2" mclr="00022220" por="00022220" />
+    <sfr address="0x0FA1" access="00033330" name="PIR2" mclr="00011110" por="00011110" />
+    <sfr address="0x0FA0" access="00033330" name="PIE2" mclr="00011110" por="00011110" />
+    <sfr address="0x0F9F" access="33333033" name="IPR1" mclr="22222022" por="22222022" />
+    <sfr address="0x0F9E" access="33113033" name="PIR1" mclr="11111011" por="11111011" />
+    <sfr address="0x0F9D" access="33333033" name="PIE1" mclr="11111011" por="11111011" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30330333" name="T1CON" mclr="30330333" por="10110111" />
+    <sfr address="0x0FCC" access="11111111" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="11111111" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="11111111" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="30330333" name="T3CON" mclr="30330333" por="10110111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4450" unused_bank_mask="0x7FEC" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9C" start="0x0F97" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FB5" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FC5" start="0x0FC9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03330303" name="INTCON2" mclr="02220202" por="02220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
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+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="30300300" name="IPR2" mclr="20200200" por="20200200" />
+    <sfr address="0x0FA1" access="30300300" name="PIR2" mclr="10100100" por="10100100" />
+    <sfr address="0x0FA0" access="30300300" name="PIE2" mclr="10100100" por="10100100" />
+    <sfr address="0x0F9F" access="03330333" name="IPR1" mclr="02220222" por="02220222" />
+    <sfr address="0x0F9E" access="03110333" name="PIR1" mclr="01110111" por="01110111" />
+    <sfr address="0x0F9D" access="03330333" name="PIE1" mclr="01110111" por="01110111" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON1" mclr="12111011" por="12011011" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7F" access="00033333" name="UEP15" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7E" access="00033333" name="UEP14" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7D" access="00033333" name="UEP13" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7C" access="00033333" name="UEP12" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7B" access="00033333" name="UEP11" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7A" access="00033333" name="UEP10" mclr="00011111" por="00011111" />
+    <sfr address="0x0F79" access="00033333" name="UEP9" mclr="00011111" por="00011111" />
+    <sfr address="0x0F78" access="00033333" name="UEP8" mclr="00011111" por="00011111" />
+    <sfr address="0x0F77" access="00033333" name="UEP7" mclr="00011111" por="00011111" />
+    <sfr address="0x0F76" access="00033333" name="UEP6" mclr="00011111" por="00011111" />
+    <sfr address="0x0F75" access="00033333" name="UEP5" mclr="00011111" por="00011111" />
+    <sfr address="0x0F74" access="00033333" name="UEP4" mclr="00011111" por="00011111" />
+    <sfr address="0x0F73" access="00033333" name="UEP3" mclr="00011111" por="00011111" />
+    <sfr address="0x0F72" access="00033333" name="UEP2" mclr="00011111" por="00011111" />
+    <sfr address="0x0F71" access="00033333" name="UEP1" mclr="00011111" por="00011111" />
+    <sfr address="0x0F70" access="00033333" name="UEP0" mclr="00011111" por="00011111" />
+    <sfr address="0x0F6F" access="33033333" name="UCFG" mclr="11011111" por="11011111" />
+    <sfr address="0x0F6E" access="03333333" name="UADDR" mclr="01111111" por="01111111" />
+    <sfr address="0x0F6D" access="03153330" name="UCON" mclr="01011110" por="01011110" />
+    <sfr address="0x0F6C" access="01111110" name="USTAT" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6B" access="30033333" name="UEIE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F6A" access="50055555" name="UEIR" mclr="10011111" por="10011111" />
+    <sfr address="0x0F69" access="03333333" name="UIE" mclr="01111111" por="01111111" />
+    <sfr address="0x0F68" access="03333313" name="UIR" mclr="01111111" por="01111111" />
+    <combined address="0x0F66" size="2" name="UFRM" />
+    <sfr address="0x0F67" access="00000111" name="UFRMH" mclr="00000000" por="00000000" />
+    <sfr address="0x0F66" access="11111111" name="UFRML" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="03033390" name="EECON1" mclr="03013110" por="00010110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F4455" unused_bank_mask="0x7F00" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="30133333" name="HLVDCON" mclr="10111212" por="10111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="30033333" name="OSCTUNE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33330333" name="PORTC" mclr="33330333" por="00000000" />
+    <sfr address="0x0F8B" access="33000333" name="LATC" mclr="33000333" por="00000000" />
+    <sfr address="0x0F94" access="33000333" name="TRISC" mclr="22000222" por="22000222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="30001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="00000333" name="TRISE" mclr="00000222" por="00000222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="00000033" name="SPPCON" mclr="00000011" por="00000011" />
+    <sfr address="0x0F64" access="33033333" name="SPPEPS" mclr="11011111" por="11011111" />
+    <sfr address="0x0F63" access="33333333" name="SPPCFG" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SPPDATA" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7F" access="00033333" name="UEP15" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7E" access="00033333" name="UEP14" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7D" access="00033333" name="UEP13" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7C" access="00033333" name="UEP12" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7B" access="00033333" name="UEP11" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7A" access="00033333" name="UEP10" mclr="00011111" por="00011111" />
+    <sfr address="0x0F79" access="00033333" name="UEP9" mclr="00011111" por="00011111" />
+    <sfr address="0x0F78" access="00033333" name="UEP8" mclr="00011111" por="00011111" />
+    <sfr address="0x0F77" access="00033333" name="UEP7" mclr="00011111" por="00011111" />
+    <sfr address="0x0F76" access="00033333" name="UEP6" mclr="00011111" por="00011111" />
+    <sfr address="0x0F75" access="00033333" name="UEP5" mclr="00011111" por="00011111" />
+    <sfr address="0x0F74" access="00033333" name="UEP4" mclr="00011111" por="00011111" />
+    <sfr address="0x0F73" access="00033333" name="UEP3" mclr="00011111" por="00011111" />
+    <sfr address="0x0F72" access="00033333" name="UEP2" mclr="00011111" por="00011111" />
+    <sfr address="0x0F71" access="00033333" name="UEP1" mclr="00011111" por="00011111" />
+    <sfr address="0x0F70" access="00033333" name="UEP0" mclr="00011111" por="00011111" />
+    <sfr address="0x0F6F" access="33033333" name="UCFG" mclr="11011111" por="11011111" />
+    <sfr address="0x0F6E" access="03333333" name="UADDR" mclr="01111111" por="01111111" />
+    <sfr address="0x0F6D" access="03153330" name="UCON" mclr="01011110" por="01011110" />
+    <sfr address="0x0F6C" access="01111110" name="USTAT" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6B" access="30033333" name="UEIE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F6A" access="50055555" name="UEIR" mclr="10011111" por="10011111" />
+    <sfr address="0x0F69" access="03333333" name="UIE" mclr="01111111" por="01111111" />
+    <sfr address="0x0F68" access="03333313" name="UIR" mclr="01111111" por="01111111" />
+    <combined address="0x0F66" size="2" name="UFRM" />
+    <sfr address="0x0F67" access="00000111" name="UFRMH" mclr="00000000" por="00000000" />
+    <sfr address="0x0F66" access="11111111" name="UFRML" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F448" unused_bank_mask="0x7FF8" >
+    <mirror>
+      <range end="0x0F2E" start="0x0F2E" />
+      <range end="0x0F3E" start="0x0F3E" />
+      <range end="0x0F4E" start="0x0F4E" />
+      <range end="0x0F5E" start="0x0F5E" />
+    </mirror>
+    <unused end="0x0F2F" start="0x0F2F" />
+    <unused end="0x0F3F" start="0x0F3F" />
+    <unused end="0x0F4F" start="0x0F4F" />
+    <unused end="0x0F5F" start="0x0F5F" />
+    <unused end="0x0F7F" start="0x0F77" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9C" start="0x0F97" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB8" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
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+    <sfr address="0x0F0D" access="33303033" name="RXF3SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F0C" access="33333333" name="RXF3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0B" access="33333333" name="RXF2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0A" access="33333333" name="RXF2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F09" access="33303033" name="RXF2SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F08" access="33333333" name="RXF2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F07" access="33333333" name="RXF1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F06" access="33333333" name="RXF1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F05" access="33303033" name="RXF1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F04" access="33333333" name="RXF1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F03" access="33333333" name="RXF0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F02" access="33333333" name="RXF0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F01" access="33303033" name="RXF0SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F00" access="33333333" name="RXF0SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F4480" unused_bank_mask="0x1FF8" >
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
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+    <unused end="0x0FD4" start="0x0FD4" />
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+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
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+    <sfr address="0x0F3C" access="33333333" name="TXB1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F3B" access="33333333" name="TXB1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F3A" access="33333333" name="TXB1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F39" access="33333333" name="TXB1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F38" access="33333333" name="TXB1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F37" access="33333333" name="TXB1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F36" access="33333333" name="TXB1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F35" access="03003333" name="TXB1DLC" mclr="03003333" por="00000000" />
+    <combined address="0x0F33" size="2" name="TXB1EID" />
+    <sfr address="0x0F34" access="33333333" name="TXB1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F33" access="33333333" name="TXB1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F32" access="33303033" name="TXB1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F31" access="33333333" name="TXB1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F30" access="33333033" name="TXB1CON" mclr="33333033" por="00000000" />
+    <sfr address="0x0F2D" access="33333333" name="TXB2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2C" access="33333333" name="TXB2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2B" access="33333333" name="TXB2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F2A" access="33333333" name="TXB2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F29" access="33333333" name="TXB2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F28" access="33333333" name="TXB2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F27" access="33333333" name="TXB2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F26" access="33333333" name="TXB2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F25" access="03003333" name="TXB2DLC" mclr="03003333" por="00000000" />
+    <combined address="0x0F23" size="2" name="TXB2EID" />
+    <sfr address="0x0F24" access="33333333" name="TXB2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F23" access="33333333" name="TXB2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F22" access="33303033" name="TXB2SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F21" access="33333333" name="TXB2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F20" access="33333033" name="TXB2CON" mclr="33333033" por="00000000" />
+    <combined address="0x0F1E" size="2" name="RXM1EID" />
+    <sfr address="0x0F1F" access="33333333" name="RXM1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1E" access="33333333" name="RXM1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1D" access="33303033" name="RXM1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F1C" access="33333333" name="RXM1SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F1A" size="2" name="RXM0EID" />
+    <sfr address="0x0F1B" access="33333333" name="RXM0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F1A" access="33333333" name="RXM0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F19" access="33303033" name="RXM0SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F18" access="33333333" name="RXM0SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F16" size="2" name="RXF5EID" />
+    <sfr address="0x0F17" access="33333333" name="RXF5EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F16" access="33333333" name="RXF5EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F15" access="33303033" name="RXF5SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F14" access="33333333" name="RXF5SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F12" size="2" name="RXF4EID" />
+    <sfr address="0x0F13" access="33333333" name="RXF4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F12" access="33333333" name="RXF4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F11" access="33303033" name="RXF4SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F10" access="33333333" name="RXF4SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F0E" size="2" name="RXF3EID" />
+    <sfr address="0x0F0F" access="33333333" name="RXF3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0E" access="33333333" name="RXF3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0D" access="33303033" name="RXF3SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F0C" access="33333333" name="RXF3SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F0A" size="2" name="RXF2EID" />
+    <sfr address="0x0F0B" access="33333333" name="RXF2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0A" access="33333333" name="RXF2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F09" access="33303033" name="RXF2SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F08" access="33333333" name="RXF2SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F06" size="2" name="RXF1EID" />
+    <sfr address="0x0F07" access="33333333" name="RXF1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F06" access="33333333" name="RXF1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F05" access="33303033" name="RXF1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F04" access="33333333" name="RXF1SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0F02" size="2" name="RXF0EID" />
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+    <sfr address="0x0F02" access="33333333" name="RXF0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F01" access="33303033" name="RXF0SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F00" access="33333333" name="RXF0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E7D" access="33333333" name="RXB7D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E7C" access="33333333" name="RXB7D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E7B" access="33333333" name="RXB7D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E7A" access="33333333" name="RXB7D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E79" access="33333333" name="RXB7D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E78" access="33333333" name="RXB7D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E77" access="33333333" name="RXB7D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E76" access="33333333" name="RXB7D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E75" access="03333333" name="RXB7DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E73" size="2" name="RXB7EID" />
+    <sfr address="0x0E74" access="33333333" name="RXB7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E73" access="33333333" name="RXB7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E72" access="33303033" name="RXB7SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E71" access="33333333" name="RXB7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E70" access="33333333" name="RXB7CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6D" access="33333333" name="RXB6D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6C" access="33333333" name="RXB6D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6B" access="33333333" name="RXB6D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6A" access="33333333" name="RXB6D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E69" access="33333333" name="RXB6D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E68" access="33333333" name="RXB6D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E67" access="33333333" name="RXB6D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E66" access="33333333" name="RXB6D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E65" access="03333333" name="RXB6DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E63" size="2" name="RXB6EID" />
+    <sfr address="0x0E64" access="33333333" name="RXB6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E63" access="33333333" name="RXB6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E62" access="33303033" name="RXB6SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E61" access="33333333" name="RXB6SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E60" access="33333333" name="RXB6CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5D" access="33333333" name="RXB5D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5C" access="33333333" name="RXB5D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5B" access="33333333" name="RXB5D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5A" access="33333333" name="RXB5D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E59" access="33333333" name="RXB5D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E58" access="33333333" name="RXB5D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E57" access="33333333" name="RXB5D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E56" access="33333333" name="RXB5D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03333333" name="RXB5DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E53" size="2" name="RXB5EID" />
+    <sfr address="0x0E54" access="33333333" name="RXB5EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="RXB5EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33303033" name="RXB5SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="RXB5SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33333333" name="RXB5CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4D" access="33333333" name="RXB4D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="RXB4D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="RXB4D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="RXB4D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="RXB4D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="RXB4D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="RXB4D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="RXB4D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03333333" name="RXB4DLC" mclr="03333333" por="00000000" />
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+    <sfr address="0x0E44" access="33333333" name="RXB4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="RXB4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33303033" name="RXB4SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="RXB4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33333333" name="RXB4CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3D" access="33333333" name="RXB3D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="RXB3D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="RXB3D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="RXB3D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="RXB3D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="RXB3D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="RXB3D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="RXB3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03333333" name="RXB3DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E33" size="2" name="RXB3EID" />
+    <sfr address="0x0E34" access="33333333" name="RXB3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="RXB3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33303033" name="RXB3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="RXB3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33333333" name="RXB3CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2D" access="33333333" name="RXB2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="RXB2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="RXB2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="RXB2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="RXB2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="RXB2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="RXB2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="RXB2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03333333" name="RXB2DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E23" size="2" name="RXB2EID" />
+    <sfr address="0x0E24" access="33333333" name="RXB2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="RXB2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33303033" name="RXB2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="RXB2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33333333" name="RXB2CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0DFC" access="00033300" name="TX_BUFINTEN" mclr="00033300" por="00000000" />
+    <sfr address="0x0DFA" access="33333333" name="BUF_INT_EN0" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF8" access="33333300" name="RX_TX_SEL0" mclr="33333300" por="00000000" />
+    <sfr address="0x0DF3" access="33333333" name="MSK_SEL3" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF2" access="33333333" name="MSK_SEL2" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF1" access="33333333" name="MSK_SEL1" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF0" access="33333333" name="MSK_SEL0" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE7" access="33333333" name="BUFPNT1514" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE6" access="33333333" name="BUFPNT1312" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE5" access="33333333" name="BUFPNT1110" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE4" access="33333333" name="BUFPNT98" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE3" access="33333333" name="BUFPNT76" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE2" access="33333333" name="BUFPNT54" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE1" access="33333333" name="BUFPNT32" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE0" access="33333333" name="BUFPNT10" mclr="33333333" por="00000000" />
+    <sfr address="0x0DD8" access="00033333" name="DEV_NET_CT" mclr="00033333" por="00000000" />
+    <sfr address="0x0DD5" access="33333333" name="FER1" mclr="33333333" por="00000000" />
+    <sfr address="0x0DD4" access="33333333" name="FER0" mclr="33333333" por="00000000" />
+    <combined address="0x0D92" size="2" name="RXF15EID" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33303033" name="RXF15SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D8A" size="2" name="RXF14EID" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33303033" name="RXF14SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D86" size="2" name="RXF13EID" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33303033" name="RXF13SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D82" size="2" name="RXF12EID" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33303033" name="RXF12SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D7A" size="2" name="RXF11EID" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33303033" name="RXF11SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D76" size="2" name="RXF10EID" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33303033" name="RXF10SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D72" size="2" name="RXF9EID" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33303033" name="RXF9SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D6A" size="2" name="RXF8EID" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33303033" name="RXF8SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D66" size="2" name="RXF7EID" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33303033" name="RXF7SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D62" size="2" name="RXF6EID" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33303033" name="RXF6SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F44J10" unused_bank_mask="0x7FF0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F91" start="0x0F8F" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FB3" start="0x0FB1" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="12034433" por="10022211" />
+    <sfr address="0x0FA5" access="33000000" name="IPR3" mclr="22000000" por="22000000" />
+    <sfr address="0x0FA4" access="33000000" name="PIR3" mclr="11000000" por="11000000" />
+    <sfr address="0x0FA3" access="33000000" name="PIE3" mclr="11000000" por="11000000" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002002" por="22002002" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001001" por="11001001" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001001" por="11001001" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="00303333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="00303333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="00303333" name="TRISA" mclr="00202222" por="00202222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00000333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F8E" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F87" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F86" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F85" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4510" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FA9" start="0x0FA6" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4515" unused_bank_mask="0x0000" >
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001111" por="11001111" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9B" access="30033333" name="OSCTUNE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="ECCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="ECCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="ECCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F452" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9C" start="0x0F97" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10042211" />
+    <sfr address="0x0FA2" access="00033333" name="IPR2" mclr="00022222" por="00022222" />
+    <sfr address="0x0FA1" access="00033333" name="PIR2" mclr="00011111" por="00011111" />
+    <sfr address="0x0FA0" access="00033333" name="PIE2" mclr="00011111" por="00011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4520" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD3" access="33330100" name="OSCCON" mclr="11110100" por="12110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4523" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03330303" name="INTCON2" mclr="02220202" por="02220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4525" unused_bank_mask="0x0000" >
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="12114111" por="12114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="10011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="ECCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="ECCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="ECCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4539" unused_bank_mask="0x7FC0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9C" start="0x0F97" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB4" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA2" access="00033330" name="IPR2" mclr="00022220" por="00022220" />
+    <sfr address="0x0FA1" access="00033330" name="PIR2" mclr="00011110" por="00011110" />
+    <sfr address="0x0FA0" access="00033330" name="PIE2" mclr="00011110" por="00011110" />
+    <sfr address="0x0F9F" access="33333033" name="IPR1" mclr="22222022" por="22222022" />
+    <sfr address="0x0F9E" access="33113033" name="PIR1" mclr="11111011" por="11111011" />
+    <sfr address="0x0F9D" access="33333033" name="PIE1" mclr="11111011" por="11111011" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30330333" name="T1CON" mclr="30330333" por="10110111" />
+    <sfr address="0x0FCC" access="11111111" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="11111111" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="11111111" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="30330333" name="T3CON" mclr="30330333" por="10110111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F4550" unused_bank_mask="0x7F00" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="30133333" name="HLVDCON" mclr="10111212" por="10111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="30033333" name="OSCTUNE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33330333" name="PORTC" mclr="33330333" por="00000000" />
+    <sfr address="0x0F8B" access="33000333" name="LATC" mclr="33000333" por="00000000" />
+    <sfr address="0x0F94" access="33000333" name="TRISC" mclr="22000222" por="22000222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="30001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="00000333" name="TRISE" mclr="00000222" por="00000222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="00000033" name="SPPCON" mclr="00000011" por="00000011" />
+    <sfr address="0x0F64" access="33033333" name="SPPEPS" mclr="11011111" por="11011111" />
+    <sfr address="0x0F63" access="33333333" name="SPPCFG" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SPPDATA" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7F" access="00033333" name="UEP15" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7E" access="00033333" name="UEP14" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7D" access="00033333" name="UEP13" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7C" access="00033333" name="UEP12" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7B" access="00033333" name="UEP11" mclr="00011111" por="00011111" />
+    <sfr address="0x0F7A" access="00033333" name="UEP10" mclr="00011111" por="00011111" />
+    <sfr address="0x0F79" access="00033333" name="UEP9" mclr="00011111" por="00011111" />
+    <sfr address="0x0F78" access="00033333" name="UEP8" mclr="00011111" por="00011111" />
+    <sfr address="0x0F77" access="00033333" name="UEP7" mclr="00011111" por="00011111" />
+    <sfr address="0x0F76" access="00033333" name="UEP6" mclr="00011111" por="00011111" />
+    <sfr address="0x0F75" access="00033333" name="UEP5" mclr="00011111" por="00011111" />
+    <sfr address="0x0F74" access="00033333" name="UEP4" mclr="00011111" por="00011111" />
+    <sfr address="0x0F73" access="00033333" name="UEP3" mclr="00011111" por="00011111" />
+    <sfr address="0x0F72" access="00033333" name="UEP2" mclr="00011111" por="00011111" />
+    <sfr address="0x0F71" access="00033333" name="UEP1" mclr="00011111" por="00011111" />
+    <sfr address="0x0F70" access="00033333" name="UEP0" mclr="00011111" por="00011111" />
+    <sfr address="0x0F6F" access="33033333" name="UCFG" mclr="11011111" por="11011111" />
+    <sfr address="0x0F6E" access="03333333" name="UADDR" mclr="01111111" por="01111111" />
+    <sfr address="0x0F6D" access="03153330" name="UCON" mclr="01011110" por="01011110" />
+    <sfr address="0x0F6C" access="01111110" name="USTAT" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6B" access="30033333" name="UEIE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F6A" access="50055555" name="UEIR" mclr="10011111" por="10011111" />
+    <sfr address="0x0F69" access="03333333" name="UIE" mclr="01111111" por="01111111" />
+    <sfr address="0x0F68" access="03333313" name="UIR" mclr="01111111" por="01111111" />
+    <combined address="0x0F66" size="2" name="UFRM" />
+    <sfr address="0x0F67" access="00000111" name="UFRMH" mclr="00000000" por="00000000" />
+    <sfr address="0x0F66" access="11111111" name="UFRML" mclr="00000000" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F458" unused_bank_mask="0x7FC0" >
+    <mirror>
+      <range end="0x0F2E" start="0x0F2E" />
+      <range end="0x0F3E" start="0x0F3E" />
+      <range end="0x0F4E" start="0x0F4E" />
+      <range end="0x0F5E" start="0x0F5E" />
+    </mirror>
+    <unused end="0x0F2F" start="0x0F2F" />
+    <unused end="0x0F3F" start="0x0F3F" />
+    <unused end="0x0F4F" start="0x0F4F" />
+    <unused end="0x0F5F" start="0x0F5F" />
+    <unused end="0x0F7F" start="0x0F77" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9C" start="0x0F97" />
+    <unused end="0x0FAA" start="0x0FAA" />
+    <unused end="0x0FB9" start="0x0FB8" />
+    <unused end="0x0FC0" start="0x0FC0" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33333333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00000333" name="PORTE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="00000333" name="TRISE" mclr="00000222" por="00000222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333303" name="ADCON0" mclr="11111101" por="11111101" />
+    <sfr address="0x0FC1" access="33003333" name="ADCON1" mclr="11001111" por="11001111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="ECCPR1" />
+    <sfr address="0x0FBC" access="33333333" name="ECCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+    <sfr address="0x0F76" access="11111111" name="TXERRCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F75" access="11111111" name="RXERRCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F74" access="55111111" name="COMSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F73" access="00330000" name="CIOCON" mclr="00110000" por="00110000" />
+    <sfr address="0x0F72" access="03000333" name="BRGCON3" mclr="01000111" por="01000111" />
+    <sfr address="0x0F71" access="33333333" name="BRGCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F70" access="33333333" name="BRGCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333330" name="CANCON" mclr="21111110" por="21111110" />
+    <sfr address="0x0F6E" access="11101110" name="CANSTAT" mclr="21101110" por="21101110" />
+    <sfr address="0x0F6D" access="33333333" name="RXB0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6C" access="33333333" name="RXB0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6B" access="33333333" name="RXB0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="RXB0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F69" access="33333333" name="RXB0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="RXB0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="RXB0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="RXB0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="03333333" name="RXB0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0F64" access="33333333" name="RXB0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F63" access="33333333" name="RXB0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F62" access="33333033" name="RXB0SIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F61" access="33333333" name="RXB0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F60" access="53301313" name="RXB0CON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F5E" access="11101110" name="CANSTATRO1" mclr="00000000" por="00000000" />
+    <sfr address="0x0F5D" access="33333333" name="RXB1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5C" access="33333333" name="RXB1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5B" access="33333333" name="RXB1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5A" access="33333333" name="RXB1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F59" access="33333333" name="RXB1D3" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F56" access="33333333" name="RXB1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F55" access="03333333" name="RXB1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0F54" access="33333333" name="RXB1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F53" access="33333333" name="RXB1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F52" access="33333033" name="RXB1SIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F51" access="33333333" name="RXB1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F50" access="53301111" name="RXB1CON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F4E" access="11101110" name="CANSTATRO2" mclr="33303330" por="00000000" />
+    <sfr address="0x0F4D" access="33333333" name="TXB0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F4C" access="33333333" name="TXB0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F4B" access="33333333" name="TXB0D5" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F48" access="33333333" name="TXB0D2" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F42" access="33333333" name="TXB0SIDL" mclr="33303033" por="00000000" />
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+    <sfr address="0x0F3E" access="11101110" name="CANSTATRO3" mclr="33303330" por="00000000" />
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+    <sfr address="0x0F10" access="33333333" name="RXF4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0F" access="33333333" name="RXF3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0E" access="33333333" name="RXF3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0D" access="33303033" name="RXF3SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F0C" access="33333333" name="RXF3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0B" access="33333333" name="RXF2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0F0A" access="33333333" name="RXF2EIDH" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F07" access="33333333" name="RXF1EIDL" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F05" access="33303033" name="RXF1SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0F04" access="33333333" name="RXF1SIDH" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F02" access="33333333" name="RXF0EIDH" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F00" access="33333333" name="RXF0SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F4580" unused_bank_mask="0x1FC0" >
+    <unused end="0x0D6F" start="0x0D6C" />
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+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
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+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
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+    <sfr address="0x0E70" access="33333333" name="RXB7CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6D" access="33333333" name="RXB6D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6C" access="33333333" name="RXB6D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6B" access="33333333" name="RXB6D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6A" access="33333333" name="RXB6D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E69" access="33333333" name="RXB6D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E68" access="33333333" name="RXB6D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E67" access="33333333" name="RXB6D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E66" access="33333333" name="RXB6D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E65" access="03333333" name="RXB6DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E63" size="2" name="RXB6EID" />
+    <sfr address="0x0E64" access="33333333" name="RXB6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E63" access="33333333" name="RXB6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E62" access="33303033" name="RXB6SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E61" access="33333333" name="RXB6SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E60" access="33333333" name="RXB6CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5D" access="33333333" name="RXB5D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5C" access="33333333" name="RXB5D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5B" access="33333333" name="RXB5D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5A" access="33333333" name="RXB5D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E59" access="33333333" name="RXB5D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E58" access="33333333" name="RXB5D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E57" access="33333333" name="RXB5D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E56" access="33333333" name="RXB5D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03333333" name="RXB5DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E53" size="2" name="RXB5EID" />
+    <sfr address="0x0E54" access="33333333" name="RXB5EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="RXB5EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33303033" name="RXB5SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="RXB5SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33333333" name="RXB5CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4D" access="33333333" name="RXB4D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="RXB4D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="RXB4D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="RXB4D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="RXB4D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="RXB4D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="RXB4D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="RXB4D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03333333" name="RXB4DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E43" size="2" name="RXB4EID" />
+    <sfr address="0x0E44" access="33333333" name="RXB4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="RXB4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33303033" name="RXB4SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="RXB4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33333333" name="RXB4CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3D" access="33333333" name="RXB3D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="RXB3D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="RXB3D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="RXB3D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="RXB3D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="RXB3D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="RXB3D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="RXB3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03333333" name="RXB3DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E33" size="2" name="RXB3EID" />
+    <sfr address="0x0E34" access="33333333" name="RXB3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="RXB3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33303033" name="RXB3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="RXB3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33333333" name="RXB3CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2D" access="33333333" name="RXB2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="RXB2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="RXB2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="RXB2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="RXB2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="RXB2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="RXB2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="RXB2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03333333" name="RXB2DLC" mclr="03333333" por="00000000" />
+    <combined address="0x0E23" size="2" name="RXB2EID" />
+    <sfr address="0x0E24" access="33333333" name="RXB2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="RXB2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33303033" name="RXB2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="RXB2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33333333" name="RXB2CON" mclr="33333333" por="00000000" />
+    <sfr address="0x0DFC" access="00033300" name="TX_BUFINTEN" mclr="00033300" por="00000000" />
+    <sfr address="0x0DFA" access="33333333" name="BUF_INT_EN0" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF8" access="33333300" name="RX_TX_SEL0" mclr="33333300" por="00000000" />
+    <sfr address="0x0DF3" access="33333333" name="MSK_SEL3" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF2" access="33333333" name="MSK_SEL2" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF1" access="33333333" name="MSK_SEL1" mclr="33333333" por="00000000" />
+    <sfr address="0x0DF0" access="33333333" name="MSK_SEL0" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE7" access="33333333" name="BUFPNT1514" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE6" access="33333333" name="BUFPNT1312" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE5" access="33333333" name="BUFPNT1110" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE4" access="33333333" name="BUFPNT98" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE3" access="33333333" name="BUFPNT76" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE2" access="33333333" name="BUFPNT54" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE1" access="33333333" name="BUFPNT32" mclr="33333333" por="00000000" />
+    <sfr address="0x0DE0" access="33333333" name="BUFPNT10" mclr="33333333" por="00000000" />
+    <sfr address="0x0DD8" access="00033333" name="DEV_NET_CT" mclr="00033333" por="00000000" />
+    <sfr address="0x0DD5" access="33333333" name="FER1" mclr="33333333" por="00000000" />
+    <sfr address="0x0DD4" access="33333333" name="FER0" mclr="33333333" por="00000000" />
+    <combined address="0x0D92" size="2" name="RXF15EID" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33303033" name="RXF15SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D8A" size="2" name="RXF14EID" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33303033" name="RXF14SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D86" size="2" name="RXF13EID" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33303033" name="RXF13SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D82" size="2" name="RXF12EID" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33303033" name="RXF12SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D7A" size="2" name="RXF11EID" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33303033" name="RXF11SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D76" size="2" name="RXF10EID" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33303033" name="RXF10SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D72" size="2" name="RXF9EID" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33303033" name="RXF9SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D6A" size="2" name="RXF8EID" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33303033" name="RXF8SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D66" size="2" name="RXF7EID" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33303033" name="RXF7SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <combined address="0x0D62" size="2" name="RXF6EID" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33303033" name="RXF6SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F4585" unused_bank_mask="0x0000" >
+    <unused end="0x0D59" start="0x0D00" />
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
+    <unused end="0x0D8F" start="0x0D8C" />
+    <unused end="0x0DD3" start="0x0D94" />
+    <unused end="0x0DD7" start="0x0DD6" />
+    <unused end="0x0DDF" start="0x0DD9" />
+    <unused end="0x0DEF" start="0x0DE8" />
+    <unused end="0x0DF7" start="0x0DF4" />
+    <unused end="0x0DF9" start="0x0DF9" />
+    <unused end="0x0DFB" start="0x0DFB" />
+    <unused end="0x0DFF" start="0x0DFD" />
+    <unused end="0x0E1F" start="0x0E00" />
+    <unused end="0x0EFF" start="0x0E80" />
+    <unused end="0x0F7F" start="0x0F78" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="12113111" por="12113111" />
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+    <sfr address="0x0E79" access="33333333" name="B5D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E78" access="33333333" name="B5D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E77" access="33333333" name="B5D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E76" access="33333333" name="B5D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E75" access="03113333" name="B5DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E74" access="33333333" name="B5EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E73" access="33333333" name="B5EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E72" access="33333033" name="B5SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E71" access="33333333" name="B5SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E70" access="33113333" name="B5CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E6F" access="33393331" name="CANCON_RO5" mclr="21111111" por="21111111" />
+    <sfr address="0x0E6E" access="11111111" name="CANSTAT_RO5" mclr="21111111" por="21111111" />
+    <sfr address="0x0E6D" access="33333333" name="B4D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6C" access="33333333" name="B4D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6B" access="33333333" name="B4D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E6A" access="33333333" name="B4D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E69" access="33333333" name="B4D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E68" access="33333333" name="B4D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E67" access="33333333" name="B4D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E66" access="33333333" name="B4D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E65" access="03113333" name="B4DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E64" access="33333333" name="B4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E63" access="33333333" name="B4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E62" access="33333033" name="B4SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E61" access="33333333" name="B4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E60" access="33113333" name="B4CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E5F" access="33393331" name="CANCON_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5E" access="11111111" name="CANSTAT_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5D" access="33333333" name="B3D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5C" access="33333333" name="B3D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5B" access="33333333" name="B3D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5A" access="33333333" name="B3D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E59" access="33333333" name="B3D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E58" access="33333333" name="B3D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E57" access="33333333" name="B3D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E56" access="33333333" name="B3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03113333" name="B3DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E54" access="33333333" name="B3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="B3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33333033" name="B3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="B3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33113333" name="B3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E4F" access="33393331" name="CANCON_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4E" access="11111111" name="CANSTAT_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4D" access="33333333" name="B2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="B2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="B2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="B2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="B2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="B2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="B2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="B2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03113333" name="B2DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E44" access="33333333" name="B2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="B2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33333033" name="B2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="B2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33113333" name="B2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E3F" access="33393331" name="CANCON_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3E" access="11111111" name="CANSTAT_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3D" access="33333333" name="B1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="B1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="B1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="B1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="B1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="B1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="B1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="B1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03113333" name="B1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E34" access="33333333" name="B1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="B1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33333033" name="B1SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="B1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33113333" name="B1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E2F" access="33393331" name="CANCON_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2E" access="11111111" name="CANSTAT_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2D" access="33333333" name="B0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="B0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="B0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="B0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="B0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="B0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="B0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="B0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03113333" name="B0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E24" access="33333333" name="B0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="B0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33333033" name="B0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="B0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33113333" name="B0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0DFC" access="00033300" name="TXBIE" mclr="00033300" por="00011100" />
+    <sfr address="0x0DFA" access="33333333" name="BIE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF8" access="33333300" name="BSEL0" mclr="11111100" por="11111100" />
+    <sfr address="0x0DF3" access="33333333" name="MSEL3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF2" access="33333333" name="MSEL2" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF1" access="33333333" name="MSEL1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF0" access="33333333" name="MSEL0" mclr="12121111" por="12121111" />
+    <sfr address="0x0DE7" access="33333333" name="RXFBCON7" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE6" access="33333333" name="RXFBCON6" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE5" access="33333333" name="RXFBCON5" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE4" access="33333333" name="RXFBCON4" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE3" access="33333333" name="RXFBCON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE2" access="33333333" name="RXFBCON2" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE1" access="33333333" name="RXFBCON1" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE0" access="33333333" name="RXFBCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD8" access="00033333" name="SDFLC" mclr="00011111" por="00011111" />
+    <sfr address="0x0DD5" access="33333333" name="RXFCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD4" access="33333333" name="RXFCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33303033" name="RXF15SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33303033" name="RXF14SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33303033" name="RXF13SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33303033" name="RXF12SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33303033" name="RXF11SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33303033" name="RXF10SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33303033" name="RXF9SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33303033" name="RXF8SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33303033" name="RXF7SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33303033" name="RXF6SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F45J10" unused_bank_mask="0x7FF0" >
+    <unused end="0x0F7F" start="0x0F00" />
+    <unused end="0x0F91" start="0x0F8F" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FB3" start="0x0FB1" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="12034433" por="10022211" />
+    <sfr address="0x0FA5" access="33000000" name="IPR3" mclr="22000000" por="22000000" />
+    <sfr address="0x0FA4" access="33000000" name="PIR3" mclr="11000000" por="11000000" />
+    <sfr address="0x0FA3" access="33000000" name="PIE3" mclr="11000000" por="11000000" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002002" por="22002002" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001001" por="11001001" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001001" por="11001001" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="00303333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="00303333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="00303333" name="TRISA" mclr="00202222" por="00202222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00000333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F8E" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F87" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F86" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F85" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4610" unused_bank_mask="0x0000" >
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="01110100" por="01110100" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001111" por="11001111" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9B" access="30033333" name="OSCTUNE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="ECCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="ECCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="ECCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x80" name="18F4620" unused_bank_mask="0x0000" >
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FA5" start="0x0FA3" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="12114111" por="12114111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="10011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="ECCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="ECCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="ECCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FB8" access="51033033" name="BAUDCON" mclr="12011011" por="12011011" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRGH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F4680" unused_bank_mask="0x0000" >
+    <unused end="0x0D59" start="0x0D00" />
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
+    <unused end="0x0D8F" start="0x0D8C" />
+    <unused end="0x0DD3" start="0x0D94" />
+    <unused end="0x0DD7" start="0x0DD6" />
+    <unused end="0x0DDF" start="0x0DD9" />
+    <unused end="0x0DEF" start="0x0DE8" />
+    <unused end="0x0DF7" start="0x0DF4" />
+    <unused end="0x0DF9" start="0x0DF9" />
+    <unused end="0x0DFB" start="0x0DFB" />
+    <unused end="0x0DFF" start="0x0DFD" />
+    <unused end="0x0E1F" start="0x0E00" />
+    <unused end="0x0EFF" start="0x0E80" />
+    <unused end="0x0F7F" start="0x0F78" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
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+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="12113111" por="12113111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33333333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9B" access="30033333" name="OSCTUNE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="ECCPR1" />
+    <sfr address="0x0FBC" access="33333333" name="ECCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
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+    <sfr address="0x0E51" access="33333333" name="B3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33113333" name="B3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E4F" access="33393331" name="CANCON_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4E" access="11111111" name="CANSTAT_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4D" access="33333333" name="B2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="B2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="B2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="B2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="B2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="B2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="B2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="B2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03113333" name="B2DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E44" access="33333333" name="B2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="B2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33333033" name="B2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="B2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33113333" name="B2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E3F" access="33393331" name="CANCON_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3E" access="11111111" name="CANSTAT_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3D" access="33333333" name="B1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="B1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="B1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="B1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="B1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="B1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="B1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="B1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03113333" name="B1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E34" access="33333333" name="B1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="B1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33333033" name="B1SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="B1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33113333" name="B1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E2F" access="33393331" name="CANCON_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2E" access="11111111" name="CANSTAT_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2D" access="33333333" name="B0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="B0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="B0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="B0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="B0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="B0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="B0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="B0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03113333" name="B0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E24" access="33333333" name="B0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="B0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33333033" name="B0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="B0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33113333" name="B0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0DFC" access="00033300" name="TXBIE" mclr="00033300" por="00011100" />
+    <sfr address="0x0DFA" access="33333333" name="BIE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF8" access="33333300" name="BSEL0" mclr="11111100" por="11111100" />
+    <sfr address="0x0DF3" access="33333333" name="MSEL3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF2" access="33333333" name="MSEL2" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF1" access="33333333" name="MSEL1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF0" access="33333333" name="MSEL0" mclr="12121111" por="12121111" />
+    <sfr address="0x0DE7" access="33333333" name="RXFBCON7" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE6" access="33333333" name="RXFBCON6" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE5" access="33333333" name="RXFBCON5" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE4" access="33333333" name="RXFBCON4" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE3" access="33333333" name="RXFBCON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE2" access="33333333" name="RXFBCON2" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE1" access="33333333" name="RXFBCON1" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE0" access="33333333" name="RXFBCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD8" access="00033333" name="SDFLC" mclr="00011111" por="00011111" />
+    <sfr address="0x0DD5" access="33333333" name="RXFCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD4" access="33333333" name="RXFCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33303033" name="RXF15SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33303033" name="RXF14SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33303033" name="RXF13SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33303033" name="RXF12SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33303033" name="RXF11SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33303033" name="RXF10SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33303033" name="RXF9SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33303033" name="RXF8SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33303033" name="RXF7SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33303033" name="RXF6SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F4682" unused_bank_mask="0x0000" >
+    <unused end="0x0D59" start="0x0D00" />
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
+    <unused end="0x0D8F" start="0x0D8C" />
+    <unused end="0x0DD3" start="0x0D94" />
+    <unused end="0x0DD7" start="0x0DD6" />
+    <unused end="0x0DDF" start="0x0DD9" />
+    <unused end="0x0DEF" start="0x0DE8" />
+    <unused end="0x0DF7" start="0x0DF4" />
+    <unused end="0x0DF9" start="0x0DF9" />
+    <unused end="0x0DFB" start="0x0DFB" />
+    <unused end="0x0DFF" start="0x0DFD" />
+    <unused end="0x0E1F" start="0x0E00" />
+    <unused end="0x0EFF" start="0x0E80" />
+    <unused end="0x0F7F" start="0x0F78" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="12113111" por="12113111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33333333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9B" access="30033333" name="OSCTUNE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
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+    <sfr address="0x0E56" access="33333333" name="B3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03113333" name="B3DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E54" access="33333333" name="B3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="B3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33333033" name="B3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="B3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33113333" name="B3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E4F" access="33393331" name="CANCON_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4E" access="11111111" name="CANSTAT_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4D" access="33333333" name="B2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="B2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="B2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="B2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="B2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="B2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="B2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="B2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03113333" name="B2DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E44" access="33333333" name="B2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="B2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33333033" name="B2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="B2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33113333" name="B2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E3F" access="33393331" name="CANCON_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3E" access="11111111" name="CANSTAT_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3D" access="33333333" name="B1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="B1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="B1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="B1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="B1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="B1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="B1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="B1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03113333" name="B1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E34" access="33333333" name="B1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="B1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33333033" name="B1SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="B1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33113333" name="B1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E2F" access="33393331" name="CANCON_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2E" access="11111111" name="CANSTAT_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2D" access="33333333" name="B0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="B0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="B0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="B0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="B0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="B0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="B0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="B0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03113333" name="B0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E24" access="33333333" name="B0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="B0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33333033" name="B0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="B0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33113333" name="B0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0DFC" access="00033300" name="TXBIE" mclr="00033300" por="00011100" />
+    <sfr address="0x0DFA" access="33333333" name="BIE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF8" access="33333300" name="BSEL0" mclr="11111100" por="11111100" />
+    <sfr address="0x0DF3" access="33333333" name="MSEL3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF2" access="33333333" name="MSEL2" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF1" access="33333333" name="MSEL1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF0" access="33333333" name="MSEL0" mclr="12121111" por="12121111" />
+    <sfr address="0x0DE7" access="33333333" name="RXFBCON7" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE6" access="33333333" name="RXFBCON6" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE5" access="33333333" name="RXFBCON5" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE4" access="33333333" name="RXFBCON4" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE3" access="33333333" name="RXFBCON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE2" access="33333333" name="RXFBCON2" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE1" access="33333333" name="RXFBCON1" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE0" access="33333333" name="RXFBCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD8" access="00033333" name="SDFLC" mclr="00011111" por="00011111" />
+    <sfr address="0x0DD5" access="33333333" name="RXFCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD4" access="33333333" name="RXFCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33303033" name="RXF15SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33303033" name="RXF14SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33303033" name="RXF13SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33303033" name="RXF12SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33303033" name="RXF11SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33303033" name="RXF10SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33303033" name="RXF9SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33303033" name="RXF8SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33303033" name="RXF7SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33303033" name="RXF6SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F4685" unused_bank_mask="0x0000" >
+    <unused end="0x0D59" start="0x0D00" />
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
+    <unused end="0x0D8F" start="0x0D8C" />
+    <unused end="0x0DD3" start="0x0D94" />
+    <unused end="0x0DD7" start="0x0DD6" />
+    <unused end="0x0DDF" start="0x0DD9" />
+    <unused end="0x0DEF" start="0x0DE8" />
+    <unused end="0x0DF7" start="0x0DF4" />
+    <unused end="0x0DF9" start="0x0DF9" />
+    <unused end="0x0DFB" start="0x0DFB" />
+    <unused end="0x0DFF" start="0x0DFD" />
+    <unused end="0x0E1F" start="0x0E00" />
+    <unused end="0x0EFF" start="0x0E80" />
+    <unused end="0x0F7F" start="0x0F78" />
+    <unused end="0x0F88" start="0x0F85" />
+    <unused end="0x0F91" start="0x0F8E" />
+    <unused end="0x0F9A" start="0x0F97" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB9" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33330303" name="INTCON2" mclr="22220202" por="22220202" />
+    <sfr address="0x0FF0" access="33033033" name="INTCON3" mclr="22011011" por="22011011" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="33331133" name="OSCCON" mclr="12113111" por="12113111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33333333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9B" access="30033333" name="OSCTUNE" mclr="10011111" por="10011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="00001333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="00000333" name="LATE" mclr="00000333" por="00000000" />
+    <sfr address="0x0F96" access="33330333" name="TRISE" mclr="11110222" por="11110222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
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+    <sfr address="0x0E5E" access="11111111" name="CANSTAT_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5D" access="33333333" name="B3D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5C" access="33333333" name="B3D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5B" access="33333333" name="B3D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5A" access="33333333" name="B3D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E59" access="33333333" name="B3D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E58" access="33333333" name="B3D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E57" access="33333333" name="B3D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E56" access="33333333" name="B3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03113333" name="B3DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E54" access="33333333" name="B3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="B3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33333033" name="B3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="B3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33113333" name="B3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E4F" access="33393331" name="CANCON_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4E" access="11111111" name="CANSTAT_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4D" access="33333333" name="B2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="B2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="B2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="B2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="B2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="B2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="B2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="B2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03113333" name="B2DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E44" access="33333333" name="B2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="B2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33333033" name="B2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="B2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33113333" name="B2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E3F" access="33393331" name="CANCON_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3E" access="11111111" name="CANSTAT_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3D" access="33333333" name="B1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="B1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="B1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="B1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="B1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="B1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="B1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="B1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03113333" name="B1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E34" access="33333333" name="B1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="B1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33333033" name="B1SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="B1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33113333" name="B1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E2F" access="33393331" name="CANCON_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2E" access="11111111" name="CANSTAT_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2D" access="33333333" name="B0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="B0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="B0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="B0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="B0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="B0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="B0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="B0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03113333" name="B0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E24" access="33333333" name="B0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="B0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33333033" name="B0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="B0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33113333" name="B0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0DFC" access="00033300" name="TXBIE" mclr="00033300" por="00011100" />
+    <sfr address="0x0DFA" access="33333333" name="BIE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF8" access="33333300" name="BSEL0" mclr="11111100" por="11111100" />
+    <sfr address="0x0DF3" access="33333333" name="MSEL3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF2" access="33333333" name="MSEL2" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF1" access="33333333" name="MSEL1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF0" access="33333333" name="MSEL0" mclr="12121111" por="12121111" />
+    <sfr address="0x0DE7" access="33333333" name="RXFBCON7" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE6" access="33333333" name="RXFBCON6" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE5" access="33333333" name="RXFBCON5" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE4" access="33333333" name="RXFBCON4" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE3" access="33333333" name="RXFBCON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE2" access="33333333" name="RXFBCON2" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE1" access="33333333" name="RXFBCON1" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE0" access="33333333" name="RXFBCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD8" access="00033333" name="SDFLC" mclr="00011111" por="00011111" />
+    <sfr address="0x0DD5" access="33333333" name="RXFCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD4" access="33333333" name="RXFCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33303033" name="RXF15SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33303033" name="RXF14SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33303033" name="RXF13SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33303033" name="RXF12SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33303033" name="RXF11SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33303033" name="RXF10SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33303033" name="RXF9SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33303033" name="RXF8SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33303033" name="RXF7SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33303033" name="RXF6SIDL" mclr="33303033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6310" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F6A" start="0x0F40" />
+    <unused end="0x0F7C" start="0x0F70" />
+    <unused end="0x0F7D" start="0x0F7D" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FAA" start="0x0FA6" />
+    <unused end="0x0FB6" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="HLVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="00330003" name="IPR3" mclr="00220002" por="00220002" />
+    <sfr address="0x0FA4" access="00110003" name="PIR3" mclr="00110001" por="00110001" />
+    <sfr address="0x0FA3" access="00330003" name="PIE3" mclr="00110001" por="00110001" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001111" por="11001111" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00333333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="31033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6390" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F57" start="0x0F40" />
+    <unused end="0x0F5F" start="0x0F5E" />
+    <unused end="0x0F7D" start="0x0F7D" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FAA" start="0x0FA6" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="HLVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="03330000" name="IPR3" mclr="02220000" por="02220000" />
+    <sfr address="0x0FA4" access="03110000" name="PIR3" mclr="01110000" por="01110000" />
+    <sfr address="0x0FA3" access="03330000" name="PIE3" mclr="01110000" por="01110000" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001111" por="11001111" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33330000" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33330000" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33330000" name="TRISE" mclr="22220000" por="22220000" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00333333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="31033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="33333333" name="LCDD23" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7B" access="33333333" name="LCDD22" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="LCDD21" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="LCDD20" mclr="33333333" por="00000000" />
+    <sfr address="0x0F78" access="33333333" name="LCDD19" mclr="33333333" por="00000000" />
+    <sfr address="0x0F77" access="33333333" name="LCDD18" mclr="33333333" por="00000000" />
+    <sfr address="0x0F76" access="33333333" name="LCDD17" mclr="33333333" por="00000000" />
+    <sfr address="0x0F75" access="33333333" name="LCDD16" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="LCDD15" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="33333333" name="LCDD14" mclr="33333333" por="00000000" />
+    <sfr address="0x0F72" access="33333333" name="LCDD13" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="LCDD12" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="33333333" name="LCDD11" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="LCDD10" mclr="33333333" por="00000000" />
+    <sfr address="0x0F69" access="33333333" name="LCDD9" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="LCDD8" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="LCDD7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="LCDD6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="LCDD5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F64" access="33333333" name="LCDD4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F63" access="33333333" name="LCDD3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F62" access="33333333" name="LCDD2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F61" access="33333333" name="LCDD1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F60" access="33333333" name="LCDD0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5D" access="33333333" name="LCDSE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="LCDSE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="33333333" name="LCDSE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5A" access="33333333" name="LCDSE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0F59" access="33303333" name="LCDCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F58" access="33333333" name="LCDPS" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F63J11" unused_bank_mask="0x7FF0" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0FBF" start="0x0F6B" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03333333" name="INTCON2" mclr="02222222" por="02222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="03333333" name="VREG_CNTL" mclr="01222111" por="01222111" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="00330330" name="IPR3" mclr="10221221" por="10221221" />
+    <sfr address="0x0FA4" access="00330330" name="PIR3" mclr="10111111" por="10111111" />
+    <sfr address="0x0FA3" access="00330330" name="PIE3" mclr="10111111" por="10111111" />
+    <sfr address="0x0FA2" access="33003330" name="IPR2" mclr="22112221" por="22112221" />
+    <sfr address="0x0FA1" access="33003330" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33003330" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333033" name="IPR1" mclr="22222122" por="22222122" />
+    <sfr address="0x0F9E" access="33113033" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333033" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="02110100" por="02110100" />
+    <sfr address="0x0F9B" access="30333333" name="OSCTUNE" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <sfr address="0x0F68" access="00333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="CCPR1L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="CCPR1H" mclr="00000000" por="00000000" />
+    <sfr address="0x0F65" access="00333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="CCPR2L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CCPR2H" mclr="00000000" por="00000000" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F64" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F60" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F63J90" unused_bank_mask="0x7FF0" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03333333" name="INTCON2" mclr="02222222" por="02222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="03333333" name="VREG_CNTL" mclr="01222111" por="01222111" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="03330330" name="IPR3" mclr="12221221" por="12221221" />
+    <sfr address="0x0FA4" access="03330330" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="03330330" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003330" name="IPR2" mclr="22112221" por="22112221" />
+    <sfr address="0x0FA1" access="33003330" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33003330" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="03333033" name="IPR1" mclr="02222122" por="02222122" />
+    <sfr address="0x0F9E" access="03113033" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333033" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="02110100" por="02110100" />
+    <sfr address="0x0F9B" access="30333333" name="OSCTUNE" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <sfr address="0x0F68" access="00333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="CCPR1L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="CCPR1H" mclr="00000000" por="00000000" />
+    <sfr address="0x0F65" access="00333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="CCPR2L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CCPR2H" mclr="00000000" por="00000000" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F64" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F60" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+    <sfr address="0x0FBF" access="33333333" name="LCDD4" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="LCDD3" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="LCDD2" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="LCDD1" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="LCDD0" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="LCDSE5" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="LCDSE4" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB8" access="33333333" name="LCDSE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="LCDSE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="LCDSE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="33333333" name="LCDPS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="LCDSE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33303333" name="LCDCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F7D" access="33333333" name="LCDD23" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7C" access="33333333" name="LCDD22" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7B" access="33333333" name="LCDD21" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="LCDD20" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="LCDD19" mclr="33333333" por="00000000" />
+    <sfr address="0x0F78" access="33333333" name="LCDD18" mclr="33333333" por="00000000" />
+    <sfr address="0x0F77" access="33333333" name="LCDD17" mclr="33333333" por="00000000" />
+    <sfr address="0x0F76" access="33333333" name="LCDD16" mclr="33333333" por="00000000" />
+    <sfr address="0x0F75" access="33333333" name="LCDD15" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="LCDD14" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="33333333" name="LCDD13" mclr="33333333" por="00000000" />
+    <sfr address="0x0F72" access="33333333" name="LCDD12" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="LCDD11" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="33333333" name="LCDD10" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6F" access="33333333" name="LCDD9" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="LCDD8" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6D" access="33333333" name="LCDD7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6C" access="33333333" name="LCDD6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6B" access="33333333" name="LCDD5" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6410" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F6A" start="0x0F00" />
+    <unused end="0x0F7C" start="0x0F70" />
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+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FAA" start="0x0FA6" />
+    <unused end="0x0FB6" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
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+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
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+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
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+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="HLVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="00330003" name="IPR3" mclr="00220002" por="00220002" />
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+    <sfr address="0x0FA3" access="00330003" name="PIE3" mclr="00110001" por="00110001" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
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+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00333333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
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+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
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+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="31033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6490" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F57" start="0x0F40" />
+    <unused end="0x0F5F" start="0x0F5E" />
+    <unused end="0x0F7D" start="0x0F7D" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FAA" start="0x0FA6" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="HLVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="03330000" name="IPR3" mclr="02220000" por="02220000" />
+    <sfr address="0x0FA4" access="03110000" name="PIR3" mclr="01110000" por="01110000" />
+    <sfr address="0x0FA3" access="03330000" name="PIE3" mclr="01110000" por="01110000" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001111" por="11001111" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33330000" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33330000" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33330000" name="TRISE" mclr="22220000" por="22220000" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00333333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="31033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="33333333" name="LCDD23" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7B" access="33333333" name="LCDD22" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="LCDD21" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="LCDD20" mclr="33333333" por="00000000" />
+    <sfr address="0x0F78" access="33333333" name="LCDD19" mclr="33333333" por="00000000" />
+    <sfr address="0x0F77" access="33333333" name="LCDD18" mclr="33333333" por="00000000" />
+    <sfr address="0x0F76" access="33333333" name="LCDD17" mclr="33333333" por="00000000" />
+    <sfr address="0x0F75" access="33333333" name="LCDD16" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="LCDD15" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="33333333" name="LCDD14" mclr="33333333" por="00000000" />
+    <sfr address="0x0F72" access="33333333" name="LCDD13" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="LCDD12" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="33333333" name="LCDD11" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="LCDD10" mclr="33333333" por="00000000" />
+    <sfr address="0x0F69" access="33333333" name="LCDD9" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="LCDD8" mclr="33333333" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="LCDD7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F66" access="33333333" name="LCDD6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="LCDD5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F64" access="33333333" name="LCDD4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F63" access="33333333" name="LCDD3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F62" access="33333333" name="LCDD2" mclr="33333333" por="00000000" />
+    <sfr address="0x0F61" access="33333333" name="LCDD1" mclr="33333333" por="00000000" />
+    <sfr address="0x0F60" access="33333333" name="LCDD0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5D" access="33333333" name="LCDSE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="LCDSE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="33333333" name="LCDSE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5A" access="33333333" name="LCDSE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0F59" access="33303333" name="LCDCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F58" access="33333333" name="LCDPS" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F64J11" unused_bank_mask="0x7FF0" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0FBF" start="0x0F6B" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03333333" name="INTCON2" mclr="02222222" por="02222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="03333333" name="VREG_CNTL" mclr="01222111" por="01222111" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="00330330" name="IPR3" mclr="10221221" por="10221221" />
+    <sfr address="0x0FA4" access="00330330" name="PIR3" mclr="10111111" por="10111111" />
+    <sfr address="0x0FA3" access="00330330" name="PIE3" mclr="10111111" por="10111111" />
+    <sfr address="0x0FA2" access="33003330" name="IPR2" mclr="22112221" por="22112221" />
+    <sfr address="0x0FA1" access="33003330" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33003330" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333033" name="IPR1" mclr="22222122" por="22222122" />
+    <sfr address="0x0F9E" access="33113033" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333033" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="02110100" por="02110100" />
+    <sfr address="0x0F9B" access="30333333" name="OSCTUNE" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <sfr address="0x0F68" access="00333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="CCPR1L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="CCPR1H" mclr="00000000" por="00000000" />
+    <sfr address="0x0F65" access="00333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="CCPR2L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CCPR2H" mclr="00000000" por="00000000" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F64" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F60" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F64J90" unused_bank_mask="0x7FF0" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03333333" name="INTCON2" mclr="02222222" por="02222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="03333333" name="VREG_CNTL" mclr="01222111" por="01222111" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="03330330" name="IPR3" mclr="12221221" por="12221221" />
+    <sfr address="0x0FA4" access="03330330" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="03330330" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003330" name="IPR2" mclr="22112221" por="22112221" />
+    <sfr address="0x0FA1" access="33003330" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33003330" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="03333033" name="IPR1" mclr="02222122" por="02222122" />
+    <sfr address="0x0F9E" access="03113033" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333033" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="02110100" por="02110100" />
+    <sfr address="0x0F9B" access="30333333" name="OSCTUNE" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <sfr address="0x0F68" access="00333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="CCPR1L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="CCPR1H" mclr="00000000" por="00000000" />
+    <sfr address="0x0F65" access="00333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="CCPR2L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CCPR2H" mclr="00000000" por="00000000" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F64" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F60" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+    <sfr address="0x0FBF" access="33333333" name="LCDD4" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="LCDD3" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="LCDD2" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="LCDD1" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="LCDD0" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="LCDSE5" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="LCDSE4" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB8" access="33333333" name="LCDSE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="LCDSE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="LCDSE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="33333333" name="LCDPS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="LCDSE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33303333" name="LCDCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F7D" access="33333333" name="LCDD23" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7C" access="33333333" name="LCDD22" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7B" access="33333333" name="LCDD21" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="LCDD20" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="LCDD19" mclr="33333333" por="00000000" />
+    <sfr address="0x0F78" access="33333333" name="LCDD18" mclr="33333333" por="00000000" />
+    <sfr address="0x0F77" access="33333333" name="LCDD17" mclr="33333333" por="00000000" />
+    <sfr address="0x0F76" access="33333333" name="LCDD16" mclr="33333333" por="00000000" />
+    <sfr address="0x0F75" access="33333333" name="LCDD15" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="LCDD14" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="33333333" name="LCDD13" mclr="33333333" por="00000000" />
+    <sfr address="0x0F72" access="33333333" name="LCDD12" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="LCDD11" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="33333333" name="LCDD10" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6F" access="33333333" name="LCDD9" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="LCDD8" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6D" access="33333333" name="LCDD7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6C" access="33333333" name="LCDD6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6B" access="33333333" name="LCDD5" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6520" unused_bank_mask="0x7F00" >
+    <unused end="0x0F6A" start="0x0F00" />
+    <unused end="0x0F7F" start="0x0F79" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F9B" start="0x0F9B" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB6" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
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+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
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+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
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+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
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+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="00333333" name="IPR3" mclr="00222222" por="00222222" />
+    <sfr address="0x0FA4" access="00113333" name="PIR3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA3" access="00333333" name="PIE3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
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+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30000333" name="ADCON2" mclr="10000111" por="10000111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
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+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
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+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6525" unused_bank_mask="0x0000" >
+    <unused end="0x0F66" start="0x0F00" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9C" start="0x0F99" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00003333" name="OSCCON" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10022211" />
+    <sfr address="0x0FA5" access="00333333" name="IPR3" mclr="00222222" por="00222222" />
+    <sfr address="0x0FA4" access="00113333" name="PIR3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA3" access="00333333" name="PIE3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00333333" por="00000000" />
+    <sfr address="0x0F98" access="00133333" name="TRISG" mclr="00222222" por="00222222" />
+    <sfr address="0x0F8F" access="00133333" name="LATG" mclr="00333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCON1" mclr="02021011" por="02021011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCON2" mclr="02021011" por="02021011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6527" unused_bank_mask="0x0000" >
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="11222222" por="11222222" />
+    <sfr address="0x0FA4" access="33113333" name="PIR3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33333399" name="EECON1" mclr="33313111" por="00010111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCTL1" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCTL2" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6585" unused_bank_mask="0x0000" >
+    <unused end="0x0D5F" start="0x0D00" />
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
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+    <unused end="0x0DD3" start="0x0D94" />
+    <unused end="0x0DD7" start="0x0DD6" />
+    <unused end="0x0DDF" start="0x0DD9" />
+    <unused end="0x0DEF" start="0x0DE8" />
+    <unused end="0x0DF7" start="0x0DF4" />
+    <unused end="0x0DF9" start="0x0DF9" />
+    <unused end="0x0DFB" start="0x0DFB" />
+    <unused end="0x0E1F" start="0x0DFD" />
+    <unused end="0x0EFF" start="0x0E80" />
+    <unused end="0x0F78" start="0x0F78" />
+    <unused end="0x0F7D" start="0x0F7A" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9C" start="0x0F99" />
+    <unused end="0x0FB9" start="0x0FB7" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
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+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00001133" name="OSCCON" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33333333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
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+    <sfr address="0x0E66" access="33333333" name="B4D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E65" access="03113333" name="B4DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E64" access="33333333" name="B4EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E63" access="33333333" name="B4EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E62" access="33333033" name="B4SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E61" access="33333333" name="B4SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E60" access="33113333" name="B4CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E5F" access="33393331" name="CANCON_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5E" access="11111111" name="CANSTAT_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5D" access="33333333" name="B3D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5C" access="33333333" name="B3D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5B" access="33333333" name="B3D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5A" access="33333333" name="B3D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E59" access="33333333" name="B3D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E58" access="33333333" name="B3D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E57" access="33333333" name="B3D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E56" access="33333333" name="B3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03113333" name="B3DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E54" access="33333333" name="B3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="B3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33333033" name="B3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="B3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33113333" name="B3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E4F" access="33393331" name="CANCON_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4E" access="11111111" name="CANSTAT_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4D" access="33333333" name="B2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="B2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="B2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="B2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="B2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="B2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="B2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="B2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03113333" name="B2DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E44" access="33333333" name="B2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="B2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33333033" name="B2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="B2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33113333" name="B2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E3F" access="33393331" name="CANCON_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3E" access="11111111" name="CANSTAT_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3D" access="33333333" name="B1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="B1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="B1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="B1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="B1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="B1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="B1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="B1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03113333" name="B1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E34" access="33333333" name="B1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="B1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33333033" name="B1SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="B1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33113333" name="B1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E2F" access="33393331" name="CANCON_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2E" access="11111111" name="CANSTAT_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2D" access="33333333" name="B0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="B0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="B0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="B0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="B0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="B0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="B0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="B0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03113333" name="B0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E24" access="33333333" name="B0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="B0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33333033" name="B0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="B0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33113333" name="B0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0DFC" access="00033300" name="TXBIE" mclr="00033300" por="00011100" />
+    <sfr address="0x0DFA" access="33333333" name="BIE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF8" access="33333300" name="BSEL0" mclr="11111100" por="11111100" />
+    <sfr address="0x0DF3" access="33333333" name="MSEL3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF2" access="33333333" name="MSEL2" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF1" access="33333333" name="MSEL1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF0" access="33333333" name="MSEL0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE7" access="33333333" name="RXFBCON7" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE6" access="33333333" name="RXFBCON6" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE5" access="33333333" name="RXFBCON5" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE4" access="33333333" name="RXFBCON4" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE3" access="33333333" name="RXFBCON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE2" access="33333333" name="RXFBCON2" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE1" access="33333333" name="RXFBCON1" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE0" access="33333333" name="RXFBCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD8" access="00033333" name="SDFLC" mclr="00011111" por="00011111" />
+    <sfr address="0x0DD5" access="33333333" name="RXFCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD4" access="33333333" name="RXFCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33333033" name="RXF15SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33333033" name="RXF14SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33333033" name="RXF13SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33333033" name="RXF12SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33333033" name="RXF11SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33333033" name="RXF10SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33333033" name="RXF9SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33333033" name="RXF8SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33333033" name="RXF7SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33333033" name="RXF6SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F65J10" unused_bank_mask="0x7F00" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FD2" start="0x0FD2" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003033" name="IPR2" mclr="22002022" por="22002022" />
+    <sfr address="0x0FA1" access="33003033" name="PIR2" mclr="11001011" por="11001011" />
+    <sfr address="0x0FA0" access="33003033" name="PIE2" mclr="11001011" por="11001011" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="10001011" por="10001011" />
+    <sfr address="0x0F9B" access="03000000" name="OSCTUNE" mclr="01000000" por="01000000" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51033033" name="BAUDCON2" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F65J11" unused_bank_mask="0x7F00" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0FBF" start="0x0F6B" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03333333" name="INTCON2" mclr="02222222" por="02222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="03333333" name="VREG_CNTL" mclr="01222111" por="01222111" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="00330330" name="IPR3" mclr="10221221" por="10221221" />
+    <sfr address="0x0FA4" access="00330330" name="PIR3" mclr="10111111" por="10111111" />
+    <sfr address="0x0FA3" access="00330330" name="PIE3" mclr="10111111" por="10111111" />
+    <sfr address="0x0FA2" access="33003330" name="IPR2" mclr="22112221" por="22112221" />
+    <sfr address="0x0FA1" access="33003330" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33003330" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333033" name="IPR1" mclr="22222122" por="22222122" />
+    <sfr address="0x0F9E" access="33113033" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333033" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="02110100" por="02110100" />
+    <sfr address="0x0F9B" access="30333333" name="OSCTUNE" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <sfr address="0x0F68" access="00333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="CCPR1L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="CCPR1H" mclr="00000000" por="00000000" />
+    <sfr address="0x0F65" access="00333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="CCPR2L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CCPR2H" mclr="00000000" por="00000000" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F64" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F60" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F65J15" unused_bank_mask="0x7F00" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FD2" start="0x0FD2" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003033" name="IPR2" mclr="22002022" por="22002022" />
+    <sfr address="0x0FA1" access="33003033" name="PIR2" mclr="11001011" por="11001011" />
+    <sfr address="0x0FA0" access="33003033" name="PIE2" mclr="11001011" por="11001011" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="10001011" por="10001011" />
+    <sfr address="0x0F9B" access="03000000" name="OSCTUNE" mclr="01000000" por="01000000" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51033033" name="BAUDCON2" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F65J50" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD0" access="30333333" name="RCON" mclr="10334433" por="10222211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333300" name="PORTF" mclr="31111100" por="01111100" />
+    <sfr address="0x0F8E" access="33333300" name="LATF" mclr="33333300" por="00000000" />
+    <sfr address="0x0F97" access="33333300" name="TRISF" mclr="22222200" por="22222200" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00003300" name="ANCON1" mclr="00001100" por="00001100" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="30033333" name="ANCON2" mclr="10011111" por="10011111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
+    <sfr address="0x0FBD" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F65J90" unused_bank_mask="0x7F00" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03333333" name="INTCON2" mclr="02222222" por="02222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="03333333" name="VREG_CNTL" mclr="01222111" por="01222111" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="03330330" name="IPR3" mclr="12221221" por="12221221" />
+    <sfr address="0x0FA4" access="03330330" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="03330330" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003330" name="IPR2" mclr="22112221" por="22112221" />
+    <sfr address="0x0FA1" access="33003330" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33003330" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="03333033" name="IPR1" mclr="02222122" por="02222122" />
+    <sfr address="0x0F9E" access="03113033" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333033" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="02110100" por="02110100" />
+    <sfr address="0x0F9B" access="30333333" name="OSCTUNE" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <sfr address="0x0F68" access="00333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="CCPR1L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="CCPR1H" mclr="00000000" por="00000000" />
+    <sfr address="0x0F65" access="00333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="CCPR2L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CCPR2H" mclr="00000000" por="00000000" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F64" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F60" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+    <sfr address="0x0FBF" access="33333333" name="LCDD4" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="LCDD3" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="LCDD2" mclr="33333333" por="00000000" />
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+    <sfr address="0x0FBA" access="33333333" name="LCDSE5" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="LCDSE4" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB8" access="33333333" name="LCDSE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="LCDSE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="LCDSE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="33333333" name="LCDPS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="LCDSE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33303333" name="LCDCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F7D" access="33333333" name="LCDD23" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7C" access="33333333" name="LCDD22" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7B" access="33333333" name="LCDD21" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="LCDD20" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="LCDD19" mclr="33333333" por="00000000" />
+    <sfr address="0x0F78" access="33333333" name="LCDD18" mclr="33333333" por="00000000" />
+    <sfr address="0x0F77" access="33333333" name="LCDD17" mclr="33333333" por="00000000" />
+    <sfr address="0x0F76" access="33333333" name="LCDD16" mclr="33333333" por="00000000" />
+    <sfr address="0x0F75" access="33333333" name="LCDD15" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="LCDD14" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="33333333" name="LCDD13" mclr="33333333" por="00000000" />
+    <sfr address="0x0F72" access="33333333" name="LCDD12" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="LCDD11" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="33333333" name="LCDD10" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6F" access="33333333" name="LCDD9" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="LCDD8" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6D" access="33333333" name="LCDD7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6C" access="33333333" name="LCDD6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6B" access="33333333" name="LCDD5" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6620" unused_bank_mask="0x0000" >
+    <unused end="0x0F6A" start="0x0F00" />
+    <unused end="0x0F7F" start="0x0F79" />
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+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F9B" start="0x0F9B" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB6" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
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+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
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+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
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+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
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+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="00333333" name="IPR3" mclr="00222222" por="00222222" />
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+    <sfr address="0x0FA3" access="00333333" name="PIE3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
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+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
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+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30000333" name="ADCON2" mclr="10000111" por="10000111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
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+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
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+    <sfr address="0x0FB7" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
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+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6621" unused_bank_mask="0x0000" >
+    <unused end="0x0F66" start="0x0F00" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9C" start="0x0F99" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00003333" name="OSCCON" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10022211" />
+    <sfr address="0x0FA5" access="00333333" name="IPR3" mclr="00222222" por="00222222" />
+    <sfr address="0x0FA4" access="00113333" name="PIR3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA3" access="00333333" name="PIE3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00333333" por="00000000" />
+    <sfr address="0x0F98" access="00133333" name="TRISG" mclr="00222222" por="00222222" />
+    <sfr address="0x0F8F" access="00133333" name="LATG" mclr="00333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCON1" mclr="02021011" por="02021011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCON2" mclr="02021011" por="02021011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6622" unused_bank_mask="0x0000" >
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="11222222" por="11222222" />
+    <sfr address="0x0FA4" access="33113333" name="PIR3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33333399" name="EECON1" mclr="33313111" por="00010111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCTL1" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCTL2" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6627" unused_bank_mask="0x0000" >
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="11222222" por="11222222" />
+    <sfr address="0x0FA4" access="33113333" name="PIR3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33333399" name="EECON1" mclr="33313111" por="00010111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCTL1" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCTL2" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6680" unused_bank_mask="0x0000" >
+    <unused end="0x0D5F" start="0x0D00" />
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
+    <unused end="0x0D8F" start="0x0D8C" />
+    <unused end="0x0DD3" start="0x0D94" />
+    <unused end="0x0DD7" start="0x0DD6" />
+    <unused end="0x0DDF" start="0x0DD9" />
+    <unused end="0x0DEF" start="0x0DE8" />
+    <unused end="0x0DF7" start="0x0DF4" />
+    <unused end="0x0DF9" start="0x0DF9" />
+    <unused end="0x0DFB" start="0x0DFB" />
+    <unused end="0x0E1F" start="0x0DFD" />
+    <unused end="0x0EFF" start="0x0E80" />
+    <unused end="0x0F78" start="0x0F78" />
+    <unused end="0x0F7D" start="0x0F7A" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9C" start="0x0F99" />
+    <unused end="0x0FB9" start="0x0FB7" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00001133" name="OSCCON" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33333333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
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+    <sfr address="0x0E5F" access="33393331" name="CANCON_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5E" access="11111111" name="CANSTAT_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5D" access="33333333" name="B3D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5C" access="33333333" name="B3D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5B" access="33333333" name="B3D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5A" access="33333333" name="B3D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E59" access="33333333" name="B3D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E58" access="33333333" name="B3D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E57" access="33333333" name="B3D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E56" access="33333333" name="B3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03113333" name="B3DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E54" access="33333333" name="B3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="B3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33333033" name="B3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="B3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33113333" name="B3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E4F" access="33393331" name="CANCON_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4E" access="11111111" name="CANSTAT_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4D" access="33333333" name="B2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="B2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="B2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="B2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="B2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="B2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="B2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="B2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03113333" name="B2DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E44" access="33333333" name="B2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="B2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33333033" name="B2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="B2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33113333" name="B2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E3F" access="33393331" name="CANCON_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3E" access="11111111" name="CANSTAT_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3D" access="33333333" name="B1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="B1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="B1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="B1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="B1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="B1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="B1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="B1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03113333" name="B1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E34" access="33333333" name="B1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="B1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33333033" name="B1SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="B1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33113333" name="B1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E2F" access="33393331" name="CANCON_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2E" access="11111111" name="CANSTAT_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2D" access="33333333" name="B0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="B0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="B0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="B0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="B0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="B0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="B0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="B0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03113333" name="B0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E24" access="33333333" name="B0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="B0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33333033" name="B0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="B0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33113333" name="B0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0DFC" access="00033300" name="TXBIE" mclr="00033300" por="00011100" />
+    <sfr address="0x0DFA" access="33333333" name="BIE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF8" access="33333300" name="BSEL0" mclr="11111100" por="11111100" />
+    <sfr address="0x0DF3" access="33333333" name="MSEL3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF2" access="33333333" name="MSEL2" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF1" access="33333333" name="MSEL1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF0" access="33333333" name="MSEL0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE7" access="33333333" name="RXFBCON7" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE6" access="33333333" name="RXFBCON6" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE5" access="33333333" name="RXFBCON5" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE4" access="33333333" name="RXFBCON4" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE3" access="33333333" name="RXFBCON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE2" access="33333333" name="RXFBCON2" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE1" access="33333333" name="RXFBCON1" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE0" access="33333333" name="RXFBCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD8" access="00033333" name="SDFLC" mclr="00011111" por="00011111" />
+    <sfr address="0x0DD5" access="33333333" name="RXFCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD4" access="33333333" name="RXFCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33333033" name="RXF15SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33333033" name="RXF14SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33333033" name="RXF13SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33333033" name="RXF12SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33333033" name="RXF11SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33333033" name="RXF10SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33333033" name="RXF9SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33333033" name="RXF8SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33333033" name="RXF7SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33333033" name="RXF6SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F66J10" unused_bank_mask="0x7F00" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FD2" start="0x0FD2" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003033" name="IPR2" mclr="22002022" por="22002022" />
+    <sfr address="0x0FA1" access="33003033" name="PIR2" mclr="11001011" por="11001011" />
+    <sfr address="0x0FA0" access="33003033" name="PIE2" mclr="11001011" por="11001011" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="10001011" por="10001011" />
+    <sfr address="0x0F9B" access="03000000" name="OSCTUNE" mclr="01000000" por="01000000" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51033033" name="BAUDCON2" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F66J11" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
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+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD0" access="30333333" name="RCON" mclr="10334433" por="10222211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0000" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00003333" name="ANCON1" mclr="00001111" por="00001111" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33033333" name="ANCON2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
+    <sfr address="0x0FBD" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F66J15" unused_bank_mask="0x0000" >
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FD2" start="0x0FD2" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003033" name="IPR2" mclr="22002022" por="22002022" />
+    <sfr address="0x0FA1" access="33003033" name="PIR2" mclr="11001011" por="11001011" />
+    <sfr address="0x0FA0" access="33003033" name="PIE2" mclr="11001011" por="11001011" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="10001011" por="10001011" />
+    <sfr address="0x0F9B" access="03000000" name="OSCTUNE" mclr="01000000" por="01000000" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51033033" name="BAUDCON2" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F66J16" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD0" access="30333333" name="RCON" mclr="10334433" por="10222211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0000" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00003333" name="ANCON1" mclr="00001111" por="00001111" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33033333" name="ANCON2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
+    <sfr address="0x0FBD" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F66J50" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD0" access="30333333" name="RCON" mclr="10334433" por="10222211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0000" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333300" name="PORTF" mclr="31111100" por="01111100" />
+    <sfr address="0x0F8E" access="33333300" name="LATF" mclr="33333300" por="00000000" />
+    <sfr address="0x0F97" access="33333300" name="TRISF" mclr="22222200" por="22222200" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="33333300" name="ANCON1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="30033333" name="ANCON2" mclr="10011111" por="10011111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
+    <sfr address="0x0FBD" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F66J55" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD0" access="30333333" name="RCON" mclr="10334433" por="10222211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0000" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333300" name="PORTF" mclr="31111100" por="01111100" />
+    <sfr address="0x0F8E" access="33333300" name="LATF" mclr="33333300" por="00000000" />
+    <sfr address="0x0F97" access="33333300" name="TRISF" mclr="22222200" por="22222200" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="33333300" name="ANCON1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="30033333" name="ANCON2" mclr="10011111" por="10011111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
+    <sfr address="0x0FBD" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F66J60" unused_bank_mask="0x0000" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0EFF" start="0x0EFF" />
+    <unused end="0x0EFC" start="0x0EFC" />
+    <unused end="0x0EFA" start="0x0EF8" />
+    <unused end="0x0EE1" start="0x0EDA" />
+    <unused end="0x0ED7" start="0x0ED6" />
+    <unused end="0x0ED3" start="0x0ED2" />
+    <unused end="0x0EBF" start="0x0EBA" />
+    <unused end="0x0EB5" start="0x0EB5" />
+    <unused end="0x0EB3" start="0x0EB3" />
+    <unused end="0x0EB0" start="0x0EAC" />
+    <unused end="0x0EA5" start="0x0EA5" />
+    <unused end="0x0EA1" start="0x0EA1" />
+    <unused end="0x0E9F" start="0x0E9A" />
+    <unused end="0x0E96" start="0x0E8B" />
+    <unused end="0x0E89" start="0x0E86" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F66" start="0x0F62" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0F7D" start="0x0F7C" />
+    <unused end="0x0F6F" start="0x0F6B" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FA5" access="03003333" name="IPR3" mclr="02002222" por="02002222" />
+    <sfr address="0x0FA4" access="03003333" name="PIR3" mclr="01001111" por="01001111" />
+    <sfr address="0x0FA3" access="03003333" name="PIE3" mclr="01001111" por="01001111" />
+    <sfr address="0x0FA2" access="33333033" name="IPR2" mclr="22222022" por="22222022" />
+    <sfr address="0x0FA1" access="33333033" name="PIR2" mclr="11111011" por="11111011" />
+    <sfr address="0x0FA0" access="33333033" name="PIE2" mclr="11111011" por="11111011" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="10001011" por="10001011" />
+    <sfr address="0x0F9B" access="33330000" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="00000333" name="PORTD" mclr="00000333" por="00000000" />
+    <sfr address="0x0F8C" access="00000333" name="LATD" mclr="00000333" por="00000000" />
+    <sfr address="0x0F95" access="00000333" name="TRISD" mclr="00000222" por="00000222" />
+    <sfr address="0x0F84" access="00333333" name="PORTE" mclr="00333333" por="00000000" />
+    <sfr address="0x0F8D" access="00333333" name="LATE" mclr="00333333" por="00000000" />
+    <sfr address="0x0F96" access="00333333" name="TRISE" mclr="00222222" por="00222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="11111110" por="11111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="00030000" name="PORTG" mclr="00030000" por="00000000" />
+    <sfr address="0x0F98" access="00030000" name="TRISG" mclr="00020000" por="00020000" />
+    <sfr address="0x0F8F" access="00030000" name="LATG" mclr="00030000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
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+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCON1" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0FD2" access="33333300" name="ECON1" mclr="11111100" por="11111100" />
+    <sfr address="0x0F7B" access="00033333" name="ERDPTH" mclr="33311212" por="00011212" />
+    <sfr address="0x0F7A" access="33333333" name="ERDPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="00000000" name="EDATA" mclr="00000000" por="00000000" />
+    <sfr address="0x0F60" access="01515055" name="EIR" mclr="01111011" por="01111011" />
+    <sfr address="0x0EFE" access="33300000" name="ECON2" mclr="21100000" por="21100000" />
+    <sfr address="0x0EFD" access="05050153" name="ESTAT" mclr="01010111" por="01010111" />
+    <sfr address="0x0EFB" access="03333033" name="EIE" mclr="01111011" por="01111011" />
+    <sfr address="0x0EF7" access="11111111" name="EDMASCH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF6" access="11111111" name="EDMASCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF5" access="00033333" name="EDMADSTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EF4" access="33333333" name="EDMADSTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF3" access="00033333" name="EDMANDH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EF2" access="33333333" name="EDMANDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF1" access="00033333" name="EDMASTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EF0" access="33333333" name="EDMASTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EEF" access="00033333" name="ERXWRPTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EEE" access="33333333" name="ERXWRPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EED" access="00033333" name="ERXRDPTH" mclr="00011212" por="00011212" />
+    <sfr address="0x0EEC" access="33333333" name="ERXRDPTL" mclr="22222121" por="22222121" />
+    <sfr address="0x0EEB" access="00033333" name="ERXNDH" mclr="00022222" por="00022222" />
+    <sfr address="0x0EEA" access="33333333" name="ERXNDL" mclr="22222222" por="22222222" />
+    <sfr address="0x0EE9" access="00033333" name="ERXSTH" mclr="00011212" por="00011212" />
+    <sfr address="0x0EE8" access="33333333" name="ERXSTL" mclr="22222121" por="22222121" />
+    <sfr address="0x0EE7" access="00033333" name="ETXNDH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE6" access="33333333" name="ETXNDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EE5" access="00033333" name="ETXSTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE4" access="33333333" name="ETXSTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EE3" access="00033333" name="EWRPTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE2" access="33333333" name="EWRPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED9" access="11111111" name="EPKTCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED8" access="33333333" name="ERXFCON" mclr="21211112" por="21211112" />
+    <sfr address="0x0ED5" access="00033333" name="EPMOH" mclr="00011111" por="00011111" />
+    <sfr address="0x0ED4" access="33333333" name="EPMOL" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED1" access="33333333" name="EPMCSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED0" access="33333333" name="EPMCSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECF" access="33333333" name="EPMM7" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECE" access="33333333" name="EPMM6" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECD" access="33333333" name="EPMM5" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECC" access="33333333" name="EPMM4" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECB" access="33333333" name="EPMM3" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECA" access="33333333" name="EPMM2" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC9" access="33333333" name="EPMM1" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC8" access="33333333" name="EPMM0" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC7" access="33333333" name="EHT7" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC6" access="33333333" name="EHT6" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC5" access="33333333" name="EHT5" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC4" access="33333333" name="EHT4" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC3" access="33333333" name="EHT3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC2" access="33333333" name="EHT2" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC1" access="33333333" name="EHT1" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC0" access="33333333" name="EHT0" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB9" access="11111111" name="MIRDH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB8" access="11111111" name="MIRDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB7" access="22222222" name="MIWDH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB6" access="22222222" name="MIWDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB4" access="00033333" name="MIREGADR" mclr="00011111" por="00011111" />
+    <sfr address="0x0EB2" access="00000033" name="MICMD" mclr="00000011" por="00000011" />
+    <sfr address="0x0EB1" access="30000000" name="MICON" mclr="10000000" por="10000000" />
+    <sfr address="0x0EAB" access="33333333" name="MAMXFLH" mclr="11111221" por="11111221" />
+    <sfr address="0x0EAA" access="33333333" name="MAMXFLL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA9" access="00333333" name="MACLCON2" mclr="00221222" por="00221222" />
+    <sfr address="0x0EA8" access="00003333" name="MACLCON1" mclr="00002222" por="00002222" />
+    <sfr address="0x0EA7" access="03333333" name="MAIPGH" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA6" access="03333333" name="MAIPGL" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA4" access="03333333" name="MABBIPG" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA3" access="03330000" name="MACON4" mclr="01110011" por="01110011" />
+    <sfr address="0x0EA2" access="33333333" name="MACON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA0" access="00003333" name="MACON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0E99" access="33333333" name="EPAUSH" mclr="11121111" por="11121111" />
+    <sfr address="0x0E98" access="33333333" name="EPAUSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0E97" access="00000133" name="EFLOCON" mclr="00000111" por="00000111" />
+    <sfr address="0x0E8A" access="00001111" name="MISTAT" mclr="00001111" por="00001111" />
+    <sfr address="0x0E85" access="33333333" name="MAADR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0E84" access="33333333" name="MAADR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0E83" access="33333333" name="MAADR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0E82" access="33333333" name="MAADR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0E81" access="33333333" name="MAADR6" mclr="11111111" por="11111111" />
+    <sfr address="0x0E80" access="33333333" name="MAADR5" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F66J65" unused_bank_mask="0x0000" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0FAA" start="0x0FA8" />
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+    <unused end="0x0EB3" start="0x0EB3" />
+    <unused end="0x0EB0" start="0x0EAC" />
+    <unused end="0x0EA5" start="0x0EA5" />
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+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F66" start="0x0F62" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0F7D" start="0x0F7C" />
+    <unused end="0x0F6F" start="0x0F6B" />
+    <combined address="0x0FFD" size="3" name="TOS" />
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+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
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+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
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+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
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+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
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+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
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+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
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+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FA5" access="03003333" name="IPR3" mclr="02002222" por="02002222" />
+    <sfr address="0x0FA4" access="03003333" name="PIR3" mclr="01001111" por="01001111" />
+    <sfr address="0x0FA3" access="03003333" name="PIE3" mclr="01001111" por="01001111" />
+    <sfr address="0x0FA2" access="33333033" name="IPR2" mclr="22222022" por="22222022" />
+    <sfr address="0x0FA1" access="33333033" name="PIR2" mclr="11111011" por="11111011" />
+    <sfr address="0x0FA0" access="33333033" name="PIE2" mclr="11111011" por="11111011" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
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+    <sfr address="0x0F9B" access="33330000" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F83" access="00000333" name="PORTD" mclr="00000333" por="00000000" />
+    <sfr address="0x0F8C" access="00000333" name="LATD" mclr="00000333" por="00000000" />
+    <sfr address="0x0F95" access="00000333" name="TRISD" mclr="00000222" por="00000222" />
+    <sfr address="0x0F84" access="00333333" name="PORTE" mclr="00333333" por="00000000" />
+    <sfr address="0x0F8D" access="00333333" name="LATE" mclr="00333333" por="00000000" />
+    <sfr address="0x0F96" access="00333333" name="TRISE" mclr="00222222" por="00222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="11111110" por="11111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="00030000" name="PORTG" mclr="00030000" por="00000000" />
+    <sfr address="0x0F98" access="00030000" name="TRISG" mclr="00020000" por="00020000" />
+    <sfr address="0x0F8F" access="00030000" name="LATG" mclr="00030000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
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+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
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+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
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+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
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+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCON1" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0FD2" access="33333300" name="ECON1" mclr="11111100" por="11111100" />
+    <sfr address="0x0F7B" access="00033333" name="ERDPTH" mclr="33311212" por="00011212" />
+    <sfr address="0x0F7A" access="33333333" name="ERDPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="00000000" name="EDATA" mclr="00000000" por="00000000" />
+    <sfr address="0x0F60" access="01515055" name="EIR" mclr="01111011" por="01111011" />
+    <sfr address="0x0EFE" access="33300000" name="ECON2" mclr="21100000" por="21100000" />
+    <sfr address="0x0EFD" access="05050153" name="ESTAT" mclr="01010111" por="01010111" />
+    <sfr address="0x0EFB" access="03333033" name="EIE" mclr="01111011" por="01111011" />
+    <sfr address="0x0EF7" access="11111111" name="EDMASCH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF6" access="11111111" name="EDMASCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF5" access="00033333" name="EDMADSTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EF4" access="33333333" name="EDMADSTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF3" access="00033333" name="EDMANDH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EF2" access="33333333" name="EDMANDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF1" access="00033333" name="EDMASTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EF0" access="33333333" name="EDMASTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EEF" access="00033333" name="ERXWRPTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EEE" access="33333333" name="ERXWRPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EED" access="00033333" name="ERXRDPTH" mclr="00011212" por="00011212" />
+    <sfr address="0x0EEC" access="33333333" name="ERXRDPTL" mclr="22222121" por="22222121" />
+    <sfr address="0x0EEB" access="00033333" name="ERXNDH" mclr="00022222" por="00022222" />
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+    <sfr address="0x0EE9" access="00033333" name="ERXSTH" mclr="00011212" por="00011212" />
+    <sfr address="0x0EE8" access="33333333" name="ERXSTL" mclr="22222121" por="22222121" />
+    <sfr address="0x0EE7" access="00033333" name="ETXNDH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE6" access="33333333" name="ETXNDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EE5" access="00033333" name="ETXSTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE4" access="33333333" name="ETXSTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EE3" access="00033333" name="EWRPTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE2" access="33333333" name="EWRPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED9" access="11111111" name="EPKTCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED8" access="33333333" name="ERXFCON" mclr="21211112" por="21211112" />
+    <sfr address="0x0ED5" access="00033333" name="EPMOH" mclr="00011111" por="00011111" />
+    <sfr address="0x0ED4" access="33333333" name="EPMOL" mclr="11111111" por="11111111" />
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+    <sfr address="0x0ED0" access="33333333" name="EPMCSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECF" access="33333333" name="EPMM7" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECE" access="33333333" name="EPMM6" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECD" access="33333333" name="EPMM5" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECC" access="33333333" name="EPMM4" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECB" access="33333333" name="EPMM3" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECA" access="33333333" name="EPMM2" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC9" access="33333333" name="EPMM1" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC8" access="33333333" name="EPMM0" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC7" access="33333333" name="EHT7" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC6" access="33333333" name="EHT6" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC5" access="33333333" name="EHT5" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC4" access="33333333" name="EHT4" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC3" access="33333333" name="EHT3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC2" access="33333333" name="EHT2" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC1" access="33333333" name="EHT1" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC0" access="33333333" name="EHT0" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB9" access="11111111" name="MIRDH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB8" access="11111111" name="MIRDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB7" access="22222222" name="MIWDH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB6" access="22222222" name="MIWDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB4" access="00033333" name="MIREGADR" mclr="00011111" por="00011111" />
+    <sfr address="0x0EB2" access="00000033" name="MICMD" mclr="00000011" por="00000011" />
+    <sfr address="0x0EB1" access="30000000" name="MICON" mclr="10000000" por="10000000" />
+    <sfr address="0x0EAB" access="33333333" name="MAMXFLH" mclr="11111221" por="11111221" />
+    <sfr address="0x0EAA" access="33333333" name="MAMXFLL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA9" access="00333333" name="MACLCON2" mclr="00221222" por="00221222" />
+    <sfr address="0x0EA8" access="00003333" name="MACLCON1" mclr="00002222" por="00002222" />
+    <sfr address="0x0EA7" access="03333333" name="MAIPGH" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA6" access="03333333" name="MAIPGL" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA4" access="03333333" name="MABBIPG" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA3" access="03330000" name="MACON4" mclr="01110011" por="01110011" />
+    <sfr address="0x0EA2" access="33333333" name="MACON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA0" access="00003333" name="MACON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0E99" access="33333333" name="EPAUSH" mclr="11121111" por="11121111" />
+    <sfr address="0x0E98" access="33333333" name="EPAUSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0E97" access="00000133" name="EFLOCON" mclr="00000111" por="00000111" />
+    <sfr address="0x0E8A" access="00001111" name="MISTAT" mclr="00001111" por="00001111" />
+    <sfr address="0x0E85" access="33333333" name="MAADR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0E84" access="33333333" name="MAADR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0E83" access="33333333" name="MAADR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0E82" access="33333333" name="MAADR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0E81" access="33333333" name="MAADR6" mclr="11111111" por="11111111" />
+    <sfr address="0x0E80" access="33333333" name="MAADR5" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6720" unused_bank_mask="0x0000" >
+    <unused end="0x0F6A" start="0x0F00" />
+    <unused end="0x0F7F" start="0x0F79" />
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+    <unused end="0x0F9A" start="0x0F99" />
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+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FB6" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
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+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="00333333" name="IPR3" mclr="00222222" por="00222222" />
+    <sfr address="0x0FA4" access="00113333" name="PIR3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA3" access="00333333" name="PIE3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00033333" name="PORTG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30000333" name="ADCON2" mclr="10000111" por="10000111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
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+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F6722" unused_bank_mask="0x0000" >
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
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+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
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+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
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+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="11222222" por="11222222" />
+    <sfr address="0x0FA4" access="33113333" name="PIR3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11011111" por="11011111" />
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+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33333399" name="EECON1" mclr="33313111" por="00010111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCTL1" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCTL2" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F67J10" unused_bank_mask="0x0000" >
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0F88" start="0x0F87" />
+    <unused end="0x0F91" start="0x0F90" />
+    <unused end="0x0F9A" start="0x0F99" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FD2" start="0x0FD2" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003033" name="IPR2" mclr="22002022" por="22002022" />
+    <sfr address="0x0FA1" access="33003033" name="PIR2" mclr="11001011" por="11001011" />
+    <sfr address="0x0FA0" access="33003033" name="PIE2" mclr="11001011" por="11001011" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="10001011" por="10001011" />
+    <sfr address="0x0F9B" access="03000000" name="OSCTUNE" mclr="01000000" por="01000000" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51033033" name="BAUDCON2" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F67J11" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD0" access="30333333" name="RCON" mclr="10334433" por="10222211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0000" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="00003333" name="ANCON1" mclr="00001111" por="00001111" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33033333" name="ANCON2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
+    <sfr address="0x0FBD" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F67J50" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD0" access="30333333" name="RCON" mclr="10334433" por="10222211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0000" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333300" name="PORTF" mclr="31111100" por="01111100" />
+    <sfr address="0x0F8E" access="33333300" name="LATF" mclr="33333300" por="00000000" />
+    <sfr address="0x0F97" access="33333300" name="TRISF" mclr="22222200" por="22222200" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="33333300" name="ANCON1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="30033333" name="ANCON2" mclr="10011111" por="10011111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
+    <sfr address="0x0FBD" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F67J60" unused_bank_mask="0x0000" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0EFF" start="0x0EFF" />
+    <unused end="0x0EFC" start="0x0EFC" />
+    <unused end="0x0EFA" start="0x0EF8" />
+    <unused end="0x0EE1" start="0x0EDA" />
+    <unused end="0x0ED7" start="0x0ED6" />
+    <unused end="0x0ED3" start="0x0ED2" />
+    <unused end="0x0EBF" start="0x0EBA" />
+    <unused end="0x0EB5" start="0x0EB5" />
+    <unused end="0x0EB3" start="0x0EB3" />
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+    <sfr address="0x0EB4" access="00033333" name="MIREGADR" mclr="00011111" por="00011111" />
+    <sfr address="0x0EB2" access="00000033" name="MICMD" mclr="00000011" por="00000011" />
+    <sfr address="0x0EB1" access="30000000" name="MICON" mclr="10000000" por="10000000" />
+    <sfr address="0x0EAB" access="33333333" name="MAMXFLH" mclr="11111221" por="11111221" />
+    <sfr address="0x0EAA" access="33333333" name="MAMXFLL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA9" access="00333333" name="MACLCON2" mclr="00221222" por="00221222" />
+    <sfr address="0x0EA8" access="00003333" name="MACLCON1" mclr="00002222" por="00002222" />
+    <sfr address="0x0EA7" access="03333333" name="MAIPGH" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA6" access="03333333" name="MAIPGL" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA4" access="03333333" name="MABBIPG" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA3" access="03330000" name="MACON4" mclr="01110011" por="01110011" />
+    <sfr address="0x0EA2" access="33333333" name="MACON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA0" access="00003333" name="MACON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0E99" access="33333333" name="EPAUSH" mclr="11121111" por="11121111" />
+    <sfr address="0x0E98" access="33333333" name="EPAUSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0E97" access="00000133" name="EFLOCON" mclr="00000111" por="00000111" />
+    <sfr address="0x0E8A" access="00001111" name="MISTAT" mclr="00001111" por="00001111" />
+    <sfr address="0x0E85" access="33333333" name="MAADR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0E84" access="33333333" name="MAADR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0E83" access="33333333" name="MAADR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0E82" access="33333333" name="MAADR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0E81" access="33333333" name="MAADR6" mclr="11111111" por="11111111" />
+    <sfr address="0x0E80" access="33333333" name="MAADR5" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x40" name="18F8310" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F57" start="0x0F00" />
+    <unused end="0x0F7C" start="0x0F70" />
+    <unused end="0x0F7D" start="0x0F7D" />
+    <unused end="0x0FAA" start="0x0FA6" />
+    <unused end="0x0FB6" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="HLVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="00330003" name="IPR3" mclr="00220002" por="00220002" />
+    <sfr address="0x0FA4" access="00110003" name="PIR3" mclr="00110001" por="00110001" />
+    <sfr address="0x0FA3" access="00330003" name="PIE3" mclr="00110001" por="00110001" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001111" por="11001111" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00333333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="11113333" por="11110000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="31033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8390" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F57" start="0x0F40" />
+    <unused end="0x0F7D" start="0x0F7D" />
+    <unused end="0x0FAA" start="0x0FA6" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="HLVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="03330000" name="IPR3" mclr="02220000" por="02220000" />
+    <sfr address="0x0FA4" access="03110000" name="PIR3" mclr="01110000" por="01110000" />
+    <sfr address="0x0FA3" access="03330000" name="PIE3" mclr="01110000" por="01110000" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001111" por="11001111" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
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+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="11113333" por="11110000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
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+    <combined address="0x0FC3" size="2" name="ADRES" />
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+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
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+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
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+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
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+    <combined address="0x0FCE" size="2" name="TMR1" />
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+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
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+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
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+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
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+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
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+    <sfr address="0x0F5F" access="33333333" name="LCDSE5" mclr="11111111" por="11111111" />
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+    <sfr address="0x0F5C" access="33333333" name="LCDSE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="33333333" name="LCDSE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5A" access="33333333" name="LCDSE0" mclr="11111111" por="11111111" />
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+    <sfr address="0x0F58" access="33333333" name="LCDPS" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F83J11" unused_bank_mask="0x7FF0" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0FBF" start="0x0F6B" />
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+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
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+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <sfr address="0x0F68" access="00333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="CCPR1L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="CCPR1H" mclr="00000000" por="00000000" />
+    <sfr address="0x0F65" access="00333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="CCPR2L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CCPR2H" mclr="00000000" por="00000000" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F64" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F60" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F83J90" unused_bank_mask="0x7FF0" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03333333" name="INTCON2" mclr="02222222" por="02222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="03333333" name="VREG_CNTL" mclr="01222111" por="01222111" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="03330330" name="IPR3" mclr="12221221" por="12221221" />
+    <sfr address="0x0FA4" access="03330330" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="03330330" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003330" name="IPR2" mclr="22112221" por="22112221" />
+    <sfr address="0x0FA1" access="33003330" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33003330" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="03333033" name="IPR1" mclr="02222122" por="02222122" />
+    <sfr address="0x0F9E" access="03113033" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333033" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="02110100" por="02110100" />
+    <sfr address="0x0F9B" access="30333333" name="OSCTUNE" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <sfr address="0x0F68" access="00333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="CCPR1L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="CCPR1H" mclr="00000000" por="00000000" />
+    <sfr address="0x0F65" access="00333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="CCPR2L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CCPR2H" mclr="00000000" por="00000000" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F64" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F60" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+    <sfr address="0x0FBF" access="33333333" name="LCDD4" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="LCDD3" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="LCDD2" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="LCDD1" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="LCDD0" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="LCDSE5" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="LCDSE4" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB8" access="33333333" name="LCDSE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="LCDSE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="LCDSE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="33333333" name="LCDPS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="LCDSE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33303333" name="LCDCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F7D" access="33333333" name="LCDD23" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7C" access="33333333" name="LCDD22" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7B" access="33333333" name="LCDD21" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="LCDD20" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="LCDD19" mclr="33333333" por="00000000" />
+    <sfr address="0x0F78" access="33333333" name="LCDD18" mclr="33333333" por="00000000" />
+    <sfr address="0x0F77" access="33333333" name="LCDD17" mclr="33333333" por="00000000" />
+    <sfr address="0x0F76" access="33333333" name="LCDD16" mclr="33333333" por="00000000" />
+    <sfr address="0x0F75" access="33333333" name="LCDD15" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="LCDD14" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="33333333" name="LCDD13" mclr="33333333" por="00000000" />
+    <sfr address="0x0F72" access="33333333" name="LCDD12" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="LCDD11" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="33333333" name="LCDD10" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6F" access="33333333" name="LCDD9" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="LCDD8" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6D" access="33333333" name="LCDD7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6C" access="33333333" name="LCDD6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6B" access="33333333" name="LCDD5" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8410" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F6A" start="0x0F00" />
+    <unused end="0x0F7C" start="0x0F70" />
+    <unused end="0x0F7D" start="0x0F7D" />
+    <unused end="0x0FAA" start="0x0FA6" />
+    <unused end="0x0FB6" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="HLVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="00330003" name="IPR3" mclr="00220002" por="00220002" />
+    <sfr address="0x0FA4" access="00110003" name="PIR3" mclr="00110001" por="00110001" />
+    <sfr address="0x0FA3" access="00330003" name="PIE3" mclr="00110001" por="00110001" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001111" por="11001111" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00333333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="11113333" por="11110000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="31033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8490" unused_bank_mask="0x7FF8" >
+    <unused end="0x0F57" start="0x0F40" />
+    <unused end="0x0F7D" start="0x0F7D" />
+    <unused end="0x0FAA" start="0x0FA6" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <unused end="0x0FB9" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="HLVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="03330000" name="IPR3" mclr="02220000" por="02220000" />
+    <sfr address="0x0FA4" access="03110000" name="PIR3" mclr="01110000" por="01110000" />
+    <sfr address="0x0FA3" access="03330000" name="PIE3" mclr="01110000" por="01110000" />
+    <sfr address="0x0FA2" access="33003333" name="IPR2" mclr="22002222" por="22002222" />
+    <sfr address="0x0FA1" access="33003333" name="PIR2" mclr="11001111" por="11001111" />
+    <sfr address="0x0FA0" access="33003333" name="PIE2" mclr="11001111" por="11001111" />
+    <sfr address="0x0F9F" access="03333333" name="IPR1" mclr="02222222" por="02222222" />
+    <sfr address="0x0F9E" access="03113333" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333333" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="00333333" name="OSCTUNE" mclr="00111111" por="00111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33330000" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33330000" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33330000" name="TRISE" mclr="22220000" por="22220000" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00333333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="11113333" por="11110000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="31033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="33333333" name="LCDD23" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7B" access="33333333" name="LCDD22" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F74" access="33333333" name="LCDD15" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F72" access="33333333" name="LCDD13" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F70" access="33333333" name="LCDD11" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F69" access="33333333" name="LCDD9" mclr="33333333" por="00000000" />
+    <sfr address="0x0F68" access="33333333" name="LCDD8" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F66" access="33333333" name="LCDD6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="LCDD5" mclr="33333333" por="00000000" />
+    <sfr address="0x0F64" access="33333333" name="LCDD4" mclr="33333333" por="00000000" />
+    <sfr address="0x0F63" access="33333333" name="LCDD3" mclr="33333333" por="00000000" />
+    <sfr address="0x0F62" access="33333333" name="LCDD2" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F60" access="33333333" name="LCDD0" mclr="33333333" por="00000000" />
+    <sfr address="0x0F5F" access="33333333" name="LCDSE5" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="LCDSE4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="LCDSE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="LCDSE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="33333333" name="LCDSE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5A" access="33333333" name="LCDSE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0F59" access="33303333" name="LCDCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F58" access="33333333" name="LCDPS" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F84J11" unused_bank_mask="0x7FF0" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0FBF" start="0x0F6B" />
+    <combined address="0x0FFD" size="3" name="TOS" />
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+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
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+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
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+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
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+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
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+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
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+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="03333333" name="VREG_CNTL" mclr="01222111" por="01222111" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
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+    <sfr address="0x0FA2" access="33003330" name="IPR2" mclr="22112221" por="22112221" />
+    <sfr address="0x0FA1" access="33003330" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33003330" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333033" name="IPR1" mclr="22222122" por="22222122" />
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+    <sfr address="0x0F9D" access="33333033" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="02110100" por="02110100" />
+    <sfr address="0x0F9B" access="30333333" name="OSCTUNE" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
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+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
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+    <combined address="0x0FC3" size="2" name="ADRES" />
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+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <sfr address="0x0F68" access="00333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="CCPR1L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="CCPR1H" mclr="00000000" por="00000000" />
+    <sfr address="0x0F65" access="00333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="CCPR2L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CCPR2H" mclr="00000000" por="00000000" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F64" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F60" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F84J90" unused_bank_mask="0x7FF0" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03333333" name="INTCON2" mclr="02222222" por="02222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="03333333" name="VREG_CNTL" mclr="01222111" por="01222111" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="03330330" name="IPR3" mclr="12221221" por="12221221" />
+    <sfr address="0x0FA4" access="03330330" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="03330330" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003330" name="IPR2" mclr="22112221" por="22112221" />
+    <sfr address="0x0FA1" access="33003330" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33003330" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="03333033" name="IPR1" mclr="02222122" por="02222122" />
+    <sfr address="0x0F9E" access="03113033" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333033" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="02110100" por="02110100" />
+    <sfr address="0x0F9B" access="30333333" name="OSCTUNE" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <sfr address="0x0F68" access="00333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="CCPR1L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="CCPR1H" mclr="00000000" por="00000000" />
+    <sfr address="0x0F65" access="00333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="CCPR2L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CCPR2H" mclr="00000000" por="00000000" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F64" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F60" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+    <sfr address="0x0FBF" access="33333333" name="LCDD4" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="LCDD3" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="LCDD2" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="LCDD1" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="LCDD0" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="LCDSE5" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="LCDSE4" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB8" access="33333333" name="LCDSE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="LCDSE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="LCDSE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="33333333" name="LCDPS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="LCDSE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33303333" name="LCDCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F7D" access="33333333" name="LCDD23" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7C" access="33333333" name="LCDD22" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7B" access="33333333" name="LCDD21" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="LCDD20" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="LCDD19" mclr="33333333" por="00000000" />
+    <sfr address="0x0F78" access="33333333" name="LCDD18" mclr="33333333" por="00000000" />
+    <sfr address="0x0F77" access="33333333" name="LCDD17" mclr="33333333" por="00000000" />
+    <sfr address="0x0F76" access="33333333" name="LCDD16" mclr="33333333" por="00000000" />
+    <sfr address="0x0F75" access="33333333" name="LCDD15" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="LCDD14" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="33333333" name="LCDD13" mclr="33333333" por="00000000" />
+    <sfr address="0x0F72" access="33333333" name="LCDD12" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="LCDD11" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="33333333" name="LCDD10" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6F" access="33333333" name="LCDD9" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="LCDD8" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6D" access="33333333" name="LCDD7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6C" access="33333333" name="LCDD6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6B" access="33333333" name="LCDD5" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8520" unused_bank_mask="0x7F00" >
+    <unused end="0x0F6A" start="0x0F00" />
+    <unused end="0x0F7F" start="0x0F79" />
+    <unused end="0x0F9B" start="0x0F9B" />
+    <unused end="0x0FB6" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="00333333" name="IPR3" mclr="00222222" por="00222222" />
+    <sfr address="0x0FA4" access="00113333" name="PIR3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA3" access="00333333" name="PIE3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00033333" name="PORTG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30000333" name="ADCON2" mclr="10000111" por="10000111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8525" unused_bank_mask="0x0000" >
+    <unused end="0x0F66" start="0x0F00" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0F9B" start="0x0F9B" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00003333" name="OSCCON" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10022211" />
+    <sfr address="0x0FA5" access="00333333" name="IPR3" mclr="00222222" por="00222222" />
+    <sfr address="0x0FA4" access="00113333" name="PIR3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA3" access="00333333" name="PIE3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00333333" por="00000000" />
+    <sfr address="0x0F98" access="00133333" name="TRISG" mclr="00222222" por="00222222" />
+    <sfr address="0x0F8F" access="00133333" name="LATG" mclr="00333333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="11113333" por="11110000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCON1" mclr="02021011" por="02021011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCON2" mclr="02021011" por="02021011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8527" unused_bank_mask="0x0000" >
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="11222222" por="11222222" />
+    <sfr address="0x0FA4" access="33113333" name="PIR3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="00000000" por="00000000" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="00000000" por="00000000" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33333399" name="EECON1" mclr="33313111" por="00010111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCTL1" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCTL2" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8585" unused_bank_mask="0x0000" >
+    <unused end="0x0D5F" start="0x0D00" />
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
+    <unused end="0x0D8F" start="0x0D8C" />
+    <unused end="0x0DD3" start="0x0D94" />
+    <unused end="0x0DD7" start="0x0DD6" />
+    <unused end="0x0DDF" start="0x0DD9" />
+    <unused end="0x0DEF" start="0x0DE8" />
+    <unused end="0x0DF7" start="0x0DF4" />
+    <unused end="0x0DF9" start="0x0DF9" />
+    <unused end="0x0DFB" start="0x0DFB" />
+    <unused end="0x0E1F" start="0x0DFD" />
+    <unused end="0x0EFF" start="0x0E80" />
+    <unused end="0x0F78" start="0x0F78" />
+    <unused end="0x0F7D" start="0x0F7A" />
+    <unused end="0x0F9B" start="0x0F9B" />
+    <unused end="0x0FB9" start="0x0FB7" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00001133" name="OSCCON" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33333333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="11113333" por="11110000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCPAS1" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
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+    <sfr address="0x0E3B" access="33333333" name="B1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="B1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="B1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="B1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="B1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="B1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03113333" name="B1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E34" access="33333333" name="B1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="B1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33333033" name="B1SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="B1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33113333" name="B1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E2F" access="33393331" name="CANCON_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2E" access="11111111" name="CANSTAT_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2D" access="33333333" name="B0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="B0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="B0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="B0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="B0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="B0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="B0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="B0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03113333" name="B0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E24" access="33333333" name="B0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="B0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33333033" name="B0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="B0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33113333" name="B0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0DFC" access="00033300" name="TXBIE" mclr="00033300" por="00011100" />
+    <sfr address="0x0DFA" access="33333333" name="BIE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF8" access="33333300" name="BSEL0" mclr="11111100" por="11111100" />
+    <sfr address="0x0DF3" access="33333333" name="MSEL3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF2" access="33333333" name="MSEL2" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF1" access="33333333" name="MSEL1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF0" access="33333333" name="MSEL0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE7" access="33333333" name="RXFBCON7" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE6" access="33333333" name="RXFBCON6" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE5" access="33333333" name="RXFBCON5" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE4" access="33333333" name="RXFBCON4" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE3" access="33333333" name="RXFBCON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE2" access="33333333" name="RXFBCON2" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE1" access="33333333" name="RXFBCON1" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE0" access="33333333" name="RXFBCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD8" access="00033333" name="SDFLC" mclr="00011111" por="00011111" />
+    <sfr address="0x0DD5" access="33333333" name="RXFCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD4" access="33333333" name="RXFCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33333033" name="RXF15SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33333033" name="RXF14SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33333033" name="RXF13SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33333033" name="RXF12SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33333033" name="RXF11SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33333033" name="RXF10SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33333033" name="RXF9SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33333033" name="RXF8SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33333033" name="RXF7SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33333033" name="RXF6SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F85J10" unused_bank_mask="0x7F00" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FD2" start="0x0FD2" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003033" name="IPR2" mclr="22002022" por="22002022" />
+    <sfr address="0x0FA1" access="33003033" name="PIR2" mclr="11001011" por="11001011" />
+    <sfr address="0x0FA0" access="33003033" name="PIE2" mclr="11001011" por="11001011" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="10001011" por="10001011" />
+    <sfr address="0x0F9B" access="03000000" name="OSCTUNE" mclr="01000000" por="01000000" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51033033" name="BAUDCON2" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F85J11" unused_bank_mask="0x7F00" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0FBF" start="0x0F6B" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03333333" name="INTCON2" mclr="02222222" por="02222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="03333333" name="VREG_CNTL" mclr="01222111" por="01222111" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="00330330" name="IPR3" mclr="10221221" por="10221221" />
+    <sfr address="0x0FA4" access="00330330" name="PIR3" mclr="10111111" por="10111111" />
+    <sfr address="0x0FA3" access="00330330" name="PIE3" mclr="10111111" por="10111111" />
+    <sfr address="0x0FA2" access="33003330" name="IPR2" mclr="22112221" por="22112221" />
+    <sfr address="0x0FA1" access="33003330" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33003330" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333033" name="IPR1" mclr="22222122" por="22222122" />
+    <sfr address="0x0F9E" access="33113033" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333033" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="02110100" por="02110100" />
+    <sfr address="0x0F9B" access="30333333" name="OSCTUNE" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <sfr address="0x0F68" access="00333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="CCPR1L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="CCPR1H" mclr="00000000" por="00000000" />
+    <sfr address="0x0F65" access="00333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="CCPR2L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CCPR2H" mclr="00000000" por="00000000" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F64" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F60" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F85J15" unused_bank_mask="0x7F00" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FD2" start="0x0FD2" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003033" name="IPR2" mclr="22002022" por="22002022" />
+    <sfr address="0x0FA1" access="33003033" name="PIR2" mclr="11001011" por="11001011" />
+    <sfr address="0x0FA0" access="33003033" name="PIE2" mclr="11001011" por="11001011" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="10001011" por="10001011" />
+    <sfr address="0x0F9B" access="03000000" name="OSCTUNE" mclr="01000000" por="01000000" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
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+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
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+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
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+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
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+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
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+    <sfr address="0x0FB7" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
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+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
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+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
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+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
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+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51033033" name="BAUDCON2" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F85J50" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
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+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
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+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
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+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
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+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
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+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
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+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
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+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
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+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0000" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333300" name="PORTF" mclr="31111100" por="01111100" />
+    <sfr address="0x0F8E" access="33333300" name="LATF" mclr="33333300" por="00000000" />
+    <sfr address="0x0F97" access="33333300" name="TRISF" mclr="22222200" por="22222200" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="33333300" name="ANCON1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="30033333" name="ANCON2" mclr="10011111" por="10011111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
+    <sfr address="0x0FBD" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F85J90" unused_bank_mask="0x7F00" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="03333333" name="INTCON2" mclr="02222222" por="02222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="03333333" name="LCDREG" mclr="01222111" por="01222111" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="00010110" por="00010110" />
+    <sfr address="0x0FA5" access="03330330" name="IPR3" mclr="12221221" por="12221221" />
+    <sfr address="0x0FA4" access="03330330" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="03330330" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003330" name="IPR2" mclr="22112221" por="22112221" />
+    <sfr address="0x0FA1" access="33003330" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33003330" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="03333033" name="IPR1" mclr="02222122" por="02222122" />
+    <sfr address="0x0F9E" access="03113033" name="PIR1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9D" access="03333033" name="PIE1" mclr="01111111" por="01111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="03330100" name="OSCCON" mclr="02110100" por="02110100" />
+    <sfr address="0x0F9B" access="30333333" name="OSCTUNE" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="11111111" por="11111111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <sfr address="0x0F68" access="00333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="CCPR1L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F6A" access="33333333" name="CCPR1H" mclr="00000000" por="00000000" />
+    <sfr address="0x0F65" access="00333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="CCPR2L" mclr="00000000" por="00000000" />
+    <sfr address="0x0F67" access="33333333" name="CCPR2H" mclr="00000000" por="00000000" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F64" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F60" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+    <sfr address="0x0FBF" access="33333333" name="LCDDATA4" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="LCDDATA3" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="LCDDATA2" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="LCDDATA1" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="LCDDATA0" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="LCDSE5" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="LCDSE4" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB8" access="33333333" name="LCDSE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB7" access="33333333" name="LCDSE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="LCDSE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="33333333" name="LCDPS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="33333333" name="LCDSE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33303333" name="LCDCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0F7D" access="33333333" name="LCDDATA23" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7C" access="33333333" name="LCDDATA22" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7B" access="33333333" name="LCDDATA21" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="LCDDATA20" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="LCDDATA19" mclr="33333333" por="00000000" />
+    <sfr address="0x0F78" access="33333333" name="LCDDATA18" mclr="33333333" por="00000000" />
+    <sfr address="0x0F77" access="33333333" name="LCDDATA17" mclr="33333333" por="00000000" />
+    <sfr address="0x0F76" access="33333333" name="LCDDATA16" mclr="33333333" por="00000000" />
+    <sfr address="0x0F75" access="33333333" name="LCDDATA15" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="LCDDATA14" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="33333333" name="LCDDATA13" mclr="33333333" por="00000000" />
+    <sfr address="0x0F72" access="33333333" name="LCDDATA12" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="LCDDATA11" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="33333333" name="LCDDATA10" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6F" access="33333333" name="LCDDATA9" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="LCDDATA8" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6D" access="33333333" name="LCDDATA7" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6C" access="33333333" name="LCDDATA6" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6B" access="33333333" name="LCDDATA5" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8620" unused_bank_mask="0x0000" >
+    <unused end="0x0F6A" start="0x0F00" />
+    <unused end="0x0F7F" start="0x0F79" />
+    <unused end="0x0F9B" start="0x0F9B" />
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+    <unused end="0x0FD4" start="0x0FD4" />
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+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
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+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
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+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
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+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
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+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
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+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
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+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
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+    <combined address="0x0FBE" size="2" name="CCPR1" />
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+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
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+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
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+    <sfr address="0x0FB7" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
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+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
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+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
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+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8621" unused_bank_mask="0x0000" >
+    <unused end="0x0F66" start="0x0F00" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0F9B" start="0x0F9B" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00003333" name="OSCCON" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10044433" por="10022211" />
+    <sfr address="0x0FA5" access="00333333" name="IPR3" mclr="00222222" por="00222222" />
+    <sfr address="0x0FA4" access="00113333" name="PIR3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA3" access="00333333" name="PIE3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00333333" por="00000000" />
+    <sfr address="0x0F98" access="00133333" name="TRISG" mclr="00222222" por="00222222" />
+    <sfr address="0x0F8F" access="00133333" name="LATG" mclr="00333333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="11113333" por="11110000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33303333" name="CVRCON" mclr="11101111" por="11101111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCON1" mclr="02021011" por="02021011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCON2" mclr="02021011" por="02021011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8622" unused_bank_mask="0x0000" >
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33113333" name="PIR3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="00000000" por="00000000" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="00000000" por="00000000" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33313111" por="00010111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCTL1" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCTL2" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8627" unused_bank_mask="0x0000" >
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
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+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="11222222" por="11222222" />
+    <sfr address="0x0FA4" access="33113333" name="PIR3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
+    <sfr address="0x0F80" access="33333333" name="PORTA" mclr="33131111" por="00101111" />
+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="00000000" por="00000000" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="00000000" por="00000000" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="31333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33333399" name="EECON1" mclr="33313111" por="00010111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCTL1" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCTL2" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8680" unused_bank_mask="0x0000" >
+    <unused end="0x0D5F" start="0x0D00" />
+    <unused end="0x0D6F" start="0x0D6C" />
+    <unused end="0x0D7F" start="0x0D7C" />
+    <unused end="0x0D8F" start="0x0D8C" />
+    <unused end="0x0DD3" start="0x0D94" />
+    <unused end="0x0DD7" start="0x0DD6" />
+    <unused end="0x0DDF" start="0x0DD9" />
+    <unused end="0x0DEF" start="0x0DE8" />
+    <unused end="0x0DF7" start="0x0DF4" />
+    <unused end="0x0DF9" start="0x0DF9" />
+    <unused end="0x0DFB" start="0x0DFB" />
+    <unused end="0x0E1F" start="0x0DFD" />
+    <unused end="0x0EFF" start="0x0E80" />
+    <unused end="0x0F78" start="0x0F78" />
+    <unused end="0x0F7D" start="0x0F7A" />
+    <unused end="0x0F9B" start="0x0F9B" />
+    <unused end="0x0FB9" start="0x0FB7" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00001133" name="OSCCON" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33333333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="11113333" por="11110000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
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+    <sfr address="0x0E60" access="33113333" name="B4CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E5F" access="33393331" name="CANCON_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5E" access="11111111" name="CANSTAT_RO6" mclr="21111111" por="21111111" />
+    <sfr address="0x0E5D" access="33333333" name="B3D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5C" access="33333333" name="B3D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5B" access="33333333" name="B3D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E5A" access="33333333" name="B3D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E59" access="33333333" name="B3D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E58" access="33333333" name="B3D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E57" access="33333333" name="B3D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E56" access="33333333" name="B3D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E55" access="03113333" name="B3DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E54" access="33333333" name="B3EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E53" access="33333333" name="B3EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E52" access="33333033" name="B3SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E51" access="33333333" name="B3SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E50" access="33113333" name="B3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E4F" access="33393331" name="CANCON_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4E" access="11111111" name="CANSTAT_RO7" mclr="21111111" por="21111111" />
+    <sfr address="0x0E4D" access="33333333" name="B2D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4C" access="33333333" name="B2D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4B" access="33333333" name="B2D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E4A" access="33333333" name="B2D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E49" access="33333333" name="B2D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E48" access="33333333" name="B2D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E47" access="33333333" name="B2D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E46" access="33333333" name="B2D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E45" access="03113333" name="B2DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E44" access="33333333" name="B2EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E43" access="33333333" name="B2EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E42" access="33333033" name="B2SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E41" access="33333333" name="B2SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E40" access="33113333" name="B2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E3F" access="33393331" name="CANCON_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3E" access="11111111" name="CANSTAT_RO8" mclr="21111111" por="21111111" />
+    <sfr address="0x0E3D" access="33333333" name="B1D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3C" access="33333333" name="B1D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3B" access="33333333" name="B1D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E3A" access="33333333" name="B1D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E39" access="33333333" name="B1D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E38" access="33333333" name="B1D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E37" access="33333333" name="B1D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E36" access="33333333" name="B1D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E35" access="03113333" name="B1DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E34" access="33333333" name="B1EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E33" access="33333333" name="B1EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E32" access="33333033" name="B1SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E31" access="33333333" name="B1SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E30" access="33113333" name="B1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0E2F" access="33393331" name="CANCON_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2E" access="11111111" name="CANSTAT_RO9" mclr="21111111" por="21111111" />
+    <sfr address="0x0E2D" access="33333333" name="B0D7" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2C" access="33333333" name="B0D6" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2B" access="33333333" name="B0D5" mclr="33333333" por="00000000" />
+    <sfr address="0x0E2A" access="33333333" name="B0D4" mclr="33333333" por="00000000" />
+    <sfr address="0x0E29" access="33333333" name="B0D3" mclr="33333333" por="00000000" />
+    <sfr address="0x0E28" access="33333333" name="B0D2" mclr="33333333" por="00000000" />
+    <sfr address="0x0E27" access="33333333" name="B0D1" mclr="33333333" por="00000000" />
+    <sfr address="0x0E26" access="33333333" name="B0D0" mclr="33333333" por="00000000" />
+    <sfr address="0x0E25" access="03113333" name="B0DLC" mclr="03333333" por="00000000" />
+    <sfr address="0x0E24" access="33333333" name="B0EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0E23" access="33333333" name="B0EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E22" access="33333033" name="B0SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0E21" access="33333333" name="B0SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0E20" access="33113333" name="B0CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0DFC" access="00033300" name="TXBIE" mclr="00033300" por="00011100" />
+    <sfr address="0x0DFA" access="33333333" name="BIE0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF8" access="33333300" name="BSEL0" mclr="11111100" por="11111100" />
+    <sfr address="0x0DF3" access="33333333" name="MSEL3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF2" access="33333333" name="MSEL2" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF1" access="33333333" name="MSEL1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DF0" access="33333333" name="MSEL0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE7" access="33333333" name="RXFBCON7" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE6" access="33333333" name="RXFBCON6" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE5" access="33333333" name="RXFBCON5" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE4" access="33333333" name="RXFBCON4" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE3" access="33333333" name="RXFBCON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0DE2" access="33333333" name="RXFBCON2" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE1" access="33333333" name="RXFBCON1" mclr="11121112" por="11121112" />
+    <sfr address="0x0DE0" access="33333333" name="RXFBCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD8" access="00033333" name="SDFLC" mclr="00011111" por="00011111" />
+    <sfr address="0x0DD5" access="33333333" name="RXFCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0DD4" access="33333333" name="RXFCON0" mclr="11111111" por="11111111" />
+    <sfr address="0x0D93" access="33333333" name="RXF15EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D92" access="33333333" name="RXF15EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D91" access="33333033" name="RXF15SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D90" access="33333333" name="RXF15SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8B" access="33333333" name="RXF14EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D8A" access="33333333" name="RXF14EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D89" access="33333033" name="RXF14SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D88" access="33333333" name="RXF14SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D87" access="33333333" name="RXF13EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D86" access="33333333" name="RXF13EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D85" access="33333033" name="RXF13SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D84" access="33333333" name="RXF13SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D83" access="33333333" name="RXF12EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D82" access="33333333" name="RXF12EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D81" access="33333033" name="RXF12SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D80" access="33333333" name="RXF12SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7B" access="33333333" name="RXF11EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D7A" access="33333333" name="RXF11EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D79" access="33333033" name="RXF11SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D78" access="33333333" name="RXF11SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D77" access="33333333" name="RXF10EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D76" access="33333333" name="RXF10EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D75" access="33333033" name="RXF10SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D74" access="33333333" name="RXF10SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D73" access="33333333" name="RXF9EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D72" access="33333333" name="RXF9EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D71" access="33333033" name="RXF9SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D70" access="33333333" name="RXF9SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6B" access="33333333" name="RXF8EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D6A" access="33333333" name="RXF8EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D69" access="33333033" name="RXF8SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D68" access="33333333" name="RXF8SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D67" access="33333333" name="RXF7EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D66" access="33333333" name="RXF7EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D65" access="33333033" name="RXF7SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D64" access="33333333" name="RXF7SIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D63" access="33333333" name="RXF6EIDL" mclr="33333333" por="00000000" />
+    <sfr address="0x0D62" access="33333333" name="RXF6EIDH" mclr="33333333" por="00000000" />
+    <sfr address="0x0D61" access="33333033" name="RXF6SIDL" mclr="33333033" por="00000000" />
+    <sfr address="0x0D60" access="33333333" name="RXF6SIDH" mclr="33333333" por="00000000" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F86J10" unused_bank_mask="0x7F00" >
+    <unused end="0x0F5F" start="0x0F00" />
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FD2" start="0x0FD2" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003033" name="IPR2" mclr="22002022" por="22002022" />
+    <sfr address="0x0FA1" access="33003033" name="PIR2" mclr="11001011" por="11001011" />
+    <sfr address="0x0FA0" access="33003033" name="PIE2" mclr="11001011" por="11001011" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="10001011" por="10001011" />
+    <sfr address="0x0F9B" access="03000000" name="OSCTUNE" mclr="01000000" por="01000000" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51033033" name="BAUDCON2" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F86J11" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
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+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
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+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD0" access="30333333" name="RCON" mclr="10334433" por="10222211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0000" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="33333333" name="ANCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33033333" name="ANCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
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+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F86J15" unused_bank_mask="0x0000" >
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0FD2" start="0x0FD2" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33003033" name="IPR2" mclr="22002022" por="22002022" />
+    <sfr address="0x0FA1" access="33003033" name="PIR2" mclr="11001011" por="11001011" />
+    <sfr address="0x0FA0" access="33003033" name="PIE2" mclr="11001011" por="11001011" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="10001011" por="10001011" />
+    <sfr address="0x0F9B" access="03000000" name="OSCTUNE" mclr="01000000" por="01000000" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51033033" name="BAUDCON2" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F86J16" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD0" access="30333333" name="RCON" mclr="10334433" por="10222211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0000" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="33333333" name="ANCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33033333" name="ANCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
+    <sfr address="0x0FBD" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F86J50" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD0" access="30333333" name="RCON" mclr="10334433" por="10222211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0000" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333300" name="PORTF" mclr="31111100" por="01111100" />
+    <sfr address="0x0F8E" access="33333300" name="LATF" mclr="33333300" por="00000000" />
+    <sfr address="0x0F97" access="33333300" name="TRISF" mclr="22222200" por="22222200" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="33333300" name="ANCON1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="30033333" name="ANCON2" mclr="10011111" por="10011111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
+    <sfr address="0x0FBD" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F86J55" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD0" access="30333333" name="RCON" mclr="10334433" por="10222211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0000" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333300" name="PORTF" mclr="31111100" por="01111100" />
+    <sfr address="0x0F8E" access="33333300" name="LATF" mclr="33333300" por="00000000" />
+    <sfr address="0x0F97" access="33333300" name="TRISF" mclr="22222200" por="22222200" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="33333300" name="ANCON1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="30033333" name="ANCON2" mclr="10011111" por="10011111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
+    <sfr address="0x0FBD" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F86J60" unused_bank_mask="0x0000" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0EFF" start="0x0EFF" />
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+    <unused end="0x0EFA" start="0x0EF8" />
+    <unused end="0x0EE1" start="0x0EDA" />
+    <unused end="0x0ED7" start="0x0ED6" />
+    <unused end="0x0ED3" start="0x0ED2" />
+    <unused end="0x0EBF" start="0x0EBA" />
+    <unused end="0x0EB5" start="0x0EB5" />
+    <unused end="0x0EB3" start="0x0EB3" />
+    <unused end="0x0EB0" start="0x0EAC" />
+    <unused end="0x0EA5" start="0x0EA5" />
+    <unused end="0x0EA1" start="0x0EA1" />
+    <unused end="0x0E9F" start="0x0E9A" />
+    <unused end="0x0E96" start="0x0E8B" />
+    <unused end="0x0E89" start="0x0E86" />
+    <unused end="0x0F66" start="0x0F62" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FA2" access="33333033" name="IPR2" mclr="22222022" por="22222022" />
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+    <sfr address="0x0F9B" access="33330000" name="OSCTUNE" mclr="11111111" por="11111111" />
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+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F91" access="00330000" name="LATJ" mclr="00330000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
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+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
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+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
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+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
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+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
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+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
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+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
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+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCON1" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
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+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+    <sfr address="0x0FD2" access="33333300" name="ECON1" mclr="11111100" por="11111100" />
+    <sfr address="0x0F7B" access="00033333" name="ERDPTH" mclr="33311212" por="00011212" />
+    <sfr address="0x0F7A" access="33333333" name="ERDPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="00000000" name="EDATA" mclr="00000000" por="00000000" />
+    <sfr address="0x0F60" access="01515055" name="EIR" mclr="01111011" por="01111011" />
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+    <sfr address="0x0EFB" access="03333033" name="EIE" mclr="01111011" por="01111011" />
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+    <sfr address="0x0EF5" access="00033333" name="EDMADSTH" mclr="00011111" por="00011111" />
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+    <sfr address="0x0EF2" access="33333333" name="EDMANDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF1" access="00033333" name="EDMASTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EF0" access="33333333" name="EDMASTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EEF" access="00033333" name="ERXWRPTH" mclr="00011111" por="00011111" />
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+    <sfr address="0x0EEC" access="33333333" name="ERXRDPTL" mclr="22222121" por="22222121" />
+    <sfr address="0x0EEB" access="00033333" name="ERXNDH" mclr="00022222" por="00022222" />
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+    <sfr address="0x0EE8" access="33333333" name="ERXSTL" mclr="22222121" por="22222121" />
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+    <sfr address="0x0EE6" access="33333333" name="ETXNDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EE5" access="00033333" name="ETXSTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE4" access="33333333" name="ETXSTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EE3" access="00033333" name="EWRPTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE2" access="33333333" name="EWRPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED9" access="11111111" name="EPKTCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED8" access="33333333" name="ERXFCON" mclr="21211112" por="21211112" />
+    <sfr address="0x0ED5" access="00033333" name="EPMOH" mclr="00011111" por="00011111" />
+    <sfr address="0x0ED4" access="33333333" name="EPMOL" mclr="11111111" por="11111111" />
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+    <sfr address="0x0ED0" access="33333333" name="EPMCSL" mclr="11111111" por="11111111" />
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+    <sfr address="0x0ECD" access="33333333" name="EPMM5" mclr="11111111" por="11111111" />
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+    <sfr address="0x0ECA" access="33333333" name="EPMM2" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC9" access="33333333" name="EPMM1" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC8" access="33333333" name="EPMM0" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC7" access="33333333" name="EHT7" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC6" access="33333333" name="EHT6" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC5" access="33333333" name="EHT5" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC4" access="33333333" name="EHT4" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC3" access="33333333" name="EHT3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC2" access="33333333" name="EHT2" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC1" access="33333333" name="EHT1" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC0" access="33333333" name="EHT0" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB9" access="11111111" name="MIRDH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB8" access="11111111" name="MIRDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB7" access="22222222" name="MIWDH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB6" access="22222222" name="MIWDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB4" access="00033333" name="MIREGADR" mclr="00011111" por="00011111" />
+    <sfr address="0x0EB2" access="00000033" name="MICMD" mclr="00000011" por="00000011" />
+    <sfr address="0x0EB1" access="30000000" name="MICON" mclr="10000000" por="10000000" />
+    <sfr address="0x0EAB" access="33333333" name="MAMXFLH" mclr="11111221" por="11111221" />
+    <sfr address="0x0EAA" access="33333333" name="MAMXFLL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA9" access="00333333" name="MACLCON2" mclr="00221222" por="00221222" />
+    <sfr address="0x0EA8" access="00003333" name="MACLCON1" mclr="00002222" por="00002222" />
+    <sfr address="0x0EA7" access="03333333" name="MAIPGH" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA6" access="03333333" name="MAIPGL" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA4" access="03333333" name="MABBIPG" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA3" access="03330000" name="MACON4" mclr="01110011" por="01110011" />
+    <sfr address="0x0EA2" access="33333333" name="MACON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA0" access="00003333" name="MACON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0E99" access="33333333" name="EPAUSH" mclr="11121111" por="11121111" />
+    <sfr address="0x0E98" access="33333333" name="EPAUSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0E97" access="00000133" name="EFLOCON" mclr="00000111" por="00000111" />
+    <sfr address="0x0E8A" access="00001111" name="MISTAT" mclr="00001111" por="00001111" />
+    <sfr address="0x0E85" access="33333333" name="MAADR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0E84" access="33333333" name="MAADR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0E83" access="33333333" name="MAADR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0E82" access="33333333" name="MAADR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0E81" access="33333333" name="MAADR6" mclr="11111111" por="11111111" />
+    <sfr address="0x0E80" access="33333333" name="MAADR5" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F86J65" unused_bank_mask="0x0000" >
+    <unused end="0x0FD4" start="0x0FD4" />
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+    <sfr address="0x0EC9" access="33333333" name="EPMM1" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC8" access="33333333" name="EPMM0" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC7" access="33333333" name="EHT7" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC6" access="33333333" name="EHT6" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC5" access="33333333" name="EHT5" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC4" access="33333333" name="EHT4" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC3" access="33333333" name="EHT3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC2" access="33333333" name="EHT2" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC1" access="33333333" name="EHT1" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC0" access="33333333" name="EHT0" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB9" access="11111111" name="MIRDH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB8" access="11111111" name="MIRDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB7" access="22222222" name="MIWDH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB6" access="22222222" name="MIWDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB4" access="00033333" name="MIREGADR" mclr="00011111" por="00011111" />
+    <sfr address="0x0EB2" access="00000033" name="MICMD" mclr="00000011" por="00000011" />
+    <sfr address="0x0EB1" access="30000000" name="MICON" mclr="10000000" por="10000000" />
+    <sfr address="0x0EAB" access="33333333" name="MAMXFLH" mclr="11111221" por="11111221" />
+    <sfr address="0x0EAA" access="33333333" name="MAMXFLL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA9" access="00333333" name="MACLCON2" mclr="00221222" por="00221222" />
+    <sfr address="0x0EA8" access="00003333" name="MACLCON1" mclr="00002222" por="00002222" />
+    <sfr address="0x0EA7" access="03333333" name="MAIPGH" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA6" access="03333333" name="MAIPGL" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA4" access="03333333" name="MABBIPG" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA3" access="03330000" name="MACON4" mclr="01110011" por="01110011" />
+    <sfr address="0x0EA2" access="33333333" name="MACON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA0" access="00003333" name="MACON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0E99" access="33333333" name="EPAUSH" mclr="11121111" por="11121111" />
+    <sfr address="0x0E98" access="33333333" name="EPAUSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0E97" access="00000133" name="EFLOCON" mclr="00000111" por="00000111" />
+    <sfr address="0x0E8A" access="00001111" name="MISTAT" mclr="00001111" por="00001111" />
+    <sfr address="0x0E85" access="33333333" name="MAADR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0E84" access="33333333" name="MAADR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0E83" access="33333333" name="MAADR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0E82" access="33333333" name="MAADR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0E81" access="33333333" name="MAADR6" mclr="11111111" por="11111111" />
+    <sfr address="0x0E80" access="33333333" name="MAADR5" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8720" unused_bank_mask="0x0000" >
+    <unused end="0x0F6A" start="0x0F00" />
+    <unused end="0x0F7F" start="0x0F79" />
+    <unused end="0x0F9B" start="0x0F9B" />
+    <unused end="0x0FB6" start="0x0FB6" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD3" access="00000003" name="OSCCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA5" access="00333333" name="IPR3" mclr="00222222" por="00222222" />
+    <sfr address="0x0FA4" access="00113333" name="PIR3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA3" access="00333333" name="PIE3" mclr="00111111" por="00111111" />
+    <sfr address="0x0FA2" access="03033333" name="IPR2" mclr="02022222" por="02022222" />
+    <sfr address="0x0FA1" access="03033333" name="PIR2" mclr="01011111" por="01011111" />
+    <sfr address="0x0FA0" access="03033333" name="PIE2" mclr="01011111" por="01011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0F80" access="03333333" name="PORTA" mclr="03131111" por="00101111" />
+    <sfr address="0x0F89" access="03333333" name="LATA" mclr="03333333" por="00000000" />
+    <sfr address="0x0F92" access="03333333" name="TRISA" mclr="02222222" por="02222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="31111111" por="01111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="00033333" name="PORTG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30000333" name="ADCON2" mclr="10000111" por="10000111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="00333333" name="CCP1CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="00333333" name="CCP2CON" mclr="00111111" por="00111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="00333333" name="CCP3CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSPBUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSPADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSPSTAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSPCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSPCON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="30333333" name="T1CON" mclr="30333333" por="10111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="00000033" name="EEADRH" mclr="00000011" por="00000011" />
+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33013111" por="00010111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F8722" unused_bank_mask="0x0000" >
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0F9C" start="0x0F9C" />
+    <unused end="0x0FD4" start="0x0FD4" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD2" access="00133333" name="LVDCON" mclr="00111212" por="00111212" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="33033333" name="RCON" mclr="12034433" por="12022211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33113333" name="PIR3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA2" access="33033333" name="IPR2" mclr="22022222" por="22022222" />
+    <sfr address="0x0FA1" access="33033333" name="PIR2" mclr="11011111" por="11011111" />
+    <sfr address="0x0FA0" access="33033333" name="PIE2" mclr="11011111" por="11011111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="33333133" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33033333" name="OSCTUNE" mclr="11011111" por="11011111" />
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+    <sfr address="0x0F89" access="33333333" name="LATA" mclr="33333333" por="00000000" />
+    <sfr address="0x0F92" access="33333333" name="TRISA" mclr="22222222" por="22222222" />
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+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F86" access="00133333" name="PORTG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00000000" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="00000000" por="00000000" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FB0" access="33330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
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+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
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+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
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+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
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+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
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+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
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+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
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+    <sfr address="0x0FA9" access="33333333" name="EEADR" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333333" name="EEDATA" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="33033399" name="EECON1" mclr="33313111" por="00010111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCON1" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCON2" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F87J10" unused_bank_mask="0x0000" >
+    <unused end="0x0F61" start="0x0F60" />
+    <unused end="0x0F7B" start="0x0F7A" />
+    <unused end="0x0FAA" start="0x0FA8" />
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+    <unused end="0x0FD4" start="0x0FD4" />
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+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
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+    <sfr address="0x0FA1" access="33003033" name="PIR2" mclr="11001011" por="11001011" />
+    <sfr address="0x0FA0" access="33003033" name="PIE2" mclr="11001011" por="11001011" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="10001011" por="10001011" />
+    <sfr address="0x0F9B" access="03000000" name="OSCTUNE" mclr="01000000" por="01000000" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111222" por="11111222" />
+    <sfr address="0x0F7E" access="51033033" name="BAUDCON1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51033033" name="BAUDCON2" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F87J11" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
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+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD0" access="30333333" name="RCON" mclr="10334433" por="10222211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0000" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="31111110" por="01111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="33033333" name="ANCON1" mclr="11011111" por="11011111" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="33333333" name="ANCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
+    <sfr address="0x0FBD" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F87J50" unused_bank_mask="0x0000" >
+    <unused end="0x0F59" start="0x0F40" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD0" access="30333333" name="RCON" mclr="10334433" por="10222211" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333333" name="IPR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA1" access="33333333" name="PIR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA0" access="33333333" name="PIE2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0000" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FC0" access="30030003" name="WDTCON" mclr="10010001" por="10010001" />
+    <sfr address="0x0FD4" access="33333333" name="OSCCON" mclr="12111111" por="12111111" />
+    <sfr address="0x0F9B" access="33333333" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0001" access="30333333" name="REFOCON" mclr="10111111" por="10111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333300" name="PORTF" mclr="31111100" por="01111100" />
+    <sfr address="0x0F8E" access="33333300" name="LATF" mclr="33333300" por="00000000" />
+    <sfr address="0x0F97" access="33333300" name="TRISF" mclr="22222200" por="22222200" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="22233333" por="22200000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="33333333" name="ADCON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0002" access="33333300" name="ANCON1" mclr="11111100" por="11111100" />
+    <sfr address="0x0FC1" access="33333333" name="ADCON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="30033333" name="ANCON2" mclr="10011111" por="10011111" />
+    <sfr address="0x0FBF" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBE" access="33333333" name="PWM1CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FBC" size="2" name="CCPR1" />
+    <sfr address="0x0FBD" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="ECCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FBA" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB9" access="33333333" name="PWM2CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB7" size="2" name="CCPR2" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB5" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="33333333" name="PWM3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0FB2" size="2" name="CCPR3" />
+    <sfr address="0x0FB3" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="ECCP3CON" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0004" access="00033333" name="ODCON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0005" access="00000033" name="ODCON2" mclr="00000011" por="00000011" />
+    <sfr address="0x0006" access="00000033" name="ODCON3" mclr="00000011" por="00000011" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F6E" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6B" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0F7A" size="2" name="TMR3" />
+    <sfr address="0x0F7B" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F7A" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F79" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0F69" access="33333333" name="PMPADDRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="PMPADDRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="PMPDATA1H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="PMPDATA1L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F65" access="30333333" name="PMPCONH" mclr="10111111" por="10111111" />
+    <sfr address="0x0F64" access="33333333" name="PMPCONL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="13333333" name="PMPMODEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="PMPMODEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="33333333" name="PMPDATAOUT2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F60" access="33333333" name="PMPDATAOUT2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5F" access="33333333" name="PMPDATA2H" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5E" access="33333333" name="PMPDATA2L" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5D" access="33333333" name="PMPPEH" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5C" access="33333333" name="PMPPEL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F5B" access="19001111" name="PMPSTATH" mclr="11001111" por="11001111" />
+    <sfr address="0x0F5A" access="19001111" name="PMPSTATL" mclr="21002222" por="21002222" />
+    <sfr address="0x0009" access="00000003" name="PADCFG1" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD3" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD2" access="33333333" name="CM1CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0FD1" access="33333333" name="CM2CON1" mclr="11122222" por="11122222" />
+    <sfr address="0x0F6A" access="00000011" name="CMSTAT" mclr="00000022" por="00000022" />
+    <sfr address="0x0F7E" access="51333033" name="BAUDCTL1" mclr="12011011" por="12011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB0" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="33333313" name="TXSTA1" mclr="11111121" por="11111121" />
+    <sfr address="0x0FAC" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="51333033" name="BAUDCTL2" mclr="12111011" por="12111011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAB" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAA" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA9" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA8" access="33333313" name="TXSTA2" mclr="11111121" por="11111121" />
+    <sfr address="0x0F9C" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F87J60" unused_bank_mask="0x0000" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0EFF" start="0x0EFF" />
+    <unused end="0x0EFC" start="0x0EFC" />
+    <unused end="0x0EFA" start="0x0EF8" />
+    <unused end="0x0EE1" start="0x0EDA" />
+    <unused end="0x0ED7" start="0x0ED6" />
+    <unused end="0x0ED3" start="0x0ED2" />
+    <unused end="0x0EBF" start="0x0EBA" />
+    <unused end="0x0EB5" start="0x0EB5" />
+    <unused end="0x0EB3" start="0x0EB3" />
+    <unused end="0x0EB0" start="0x0EAC" />
+    <unused end="0x0EA5" start="0x0EA5" />
+    <unused end="0x0EA1" start="0x0EA1" />
+    <unused end="0x0E9F" start="0x0E9A" />
+    <unused end="0x0E96" start="0x0E8B" />
+    <unused end="0x0E89" start="0x0E86" />
+    <unused end="0x0F66" start="0x0F62" />
+    <unused end="0x0FB0" start="0x0FB0" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FA5" access="03333333" name="IPR3" mclr="02222222" por="02222222" />
+    <sfr address="0x0FA4" access="03133333" name="PIR3" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA3" access="03333333" name="PIE3" mclr="01111111" por="01111111" />
+    <sfr address="0x0FA2" access="33333033" name="IPR2" mclr="22222022" por="22222022" />
+    <sfr address="0x0FA1" access="33333033" name="PIR2" mclr="11111011" por="11111011" />
+    <sfr address="0x0FA0" access="33333033" name="PIE2" mclr="11111011" por="11111011" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="10001011" por="10001011" />
+    <sfr address="0x0F9B" access="33330000" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="00000333" name="PORTD" mclr="00000333" por="00000000" />
+    <sfr address="0x0F8C" access="00000333" name="LATD" mclr="00000333" por="00000000" />
+    <sfr address="0x0F95" access="00000333" name="TRISD" mclr="00000222" por="00000222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333330" name="PORTF" mclr="11111110" por="11111110" />
+    <sfr address="0x0F8E" access="33333330" name="LATF" mclr="33333330" por="00000000" />
+    <sfr address="0x0F97" access="33333330" name="TRISF" mclr="22222220" por="22222220" />
+    <sfr address="0x0F86" access="00033333" name="PORTG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F98" access="00033333" name="TRISG" mclr="00022222" por="00022222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="00033333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="00330000" name="PORTJ" mclr="00330000" por="00000000" />
+    <sfr address="0x0F9A" access="00330000" name="TRISJ" mclr="00220000" por="00220000" />
+    <sfr address="0x0F91" access="00330000" name="LATJ" mclr="00330000" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCON1" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCON2" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+    <sfr address="0x0FD2" access="33333300" name="ECON1" mclr="11111100" por="11111100" />
+    <sfr address="0x0F7B" access="00033333" name="ERDPTH" mclr="33311212" por="00011212" />
+    <sfr address="0x0F7A" access="33333333" name="ERDPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="00000000" name="EDATA" mclr="00000000" por="00000000" />
+    <sfr address="0x0F60" access="01515055" name="EIR" mclr="01111011" por="01111011" />
+    <sfr address="0x0EFE" access="33300000" name="ECON2" mclr="21100000" por="21100000" />
+    <sfr address="0x0EFD" access="05050153" name="ESTAT" mclr="01010111" por="01010111" />
+    <sfr address="0x0EFB" access="03333033" name="EIE" mclr="01111011" por="01111011" />
+    <sfr address="0x0EF7" access="11111111" name="EDMASCH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF6" access="11111111" name="EDMASCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF5" access="00033333" name="EDMADSTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EF4" access="33333333" name="EDMADSTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF3" access="00033333" name="EDMANDH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EF2" access="33333333" name="EDMANDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF1" access="00033333" name="EDMASTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EF0" access="33333333" name="EDMASTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EEF" access="00033333" name="ERXWRPTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EEE" access="33333333" name="ERXWRPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EED" access="00033333" name="ERXRDPTH" mclr="00011212" por="00011212" />
+    <sfr address="0x0EEC" access="33333333" name="ERXRDPTL" mclr="22222121" por="22222121" />
+    <sfr address="0x0EEB" access="00033333" name="ERXNDH" mclr="00022222" por="00022222" />
+    <sfr address="0x0EEA" access="33333333" name="ERXNDL" mclr="22222222" por="22222222" />
+    <sfr address="0x0EE9" access="00033333" name="ERXSTH" mclr="00011212" por="00011212" />
+    <sfr address="0x0EE8" access="33333333" name="ERXSTL" mclr="22222121" por="22222121" />
+    <sfr address="0x0EE7" access="00033333" name="ETXNDH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE6" access="33333333" name="ETXNDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EE5" access="00033333" name="ETXSTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE4" access="33333333" name="ETXSTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EE3" access="00033333" name="EWRPTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE2" access="33333333" name="EWRPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED9" access="11111111" name="EPKTCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED8" access="33333333" name="ERXFCON" mclr="21211112" por="21211112" />
+    <sfr address="0x0ED5" access="00033333" name="EPMOH" mclr="00011111" por="00011111" />
+    <sfr address="0x0ED4" access="33333333" name="EPMOL" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED1" access="33333333" name="EPMCSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED0" access="33333333" name="EPMCSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECF" access="33333333" name="EPMM7" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECE" access="33333333" name="EPMM6" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECD" access="33333333" name="EPMM5" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECC" access="33333333" name="EPMM4" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECB" access="33333333" name="EPMM3" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECA" access="33333333" name="EPMM2" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC9" access="33333333" name="EPMM1" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC8" access="33333333" name="EPMM0" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC7" access="33333333" name="EHT7" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC6" access="33333333" name="EHT6" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC5" access="33333333" name="EHT5" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC4" access="33333333" name="EHT4" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC3" access="33333333" name="EHT3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC2" access="33333333" name="EHT2" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC1" access="33333333" name="EHT1" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC0" access="33333333" name="EHT0" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB9" access="11111111" name="MIRDH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB8" access="11111111" name="MIRDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB7" access="22222222" name="MIWDH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB6" access="22222222" name="MIWDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB4" access="00033333" name="MIREGADR" mclr="00011111" por="00011111" />
+    <sfr address="0x0EB2" access="00000033" name="MICMD" mclr="00000011" por="00000011" />
+    <sfr address="0x0EB1" access="30000000" name="MICON" mclr="10000000" por="10000000" />
+    <sfr address="0x0EAB" access="33333333" name="MAMXFLH" mclr="11111221" por="11111221" />
+    <sfr address="0x0EAA" access="33333333" name="MAMXFLL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA9" access="00333333" name="MACLCON2" mclr="00221222" por="00221222" />
+    <sfr address="0x0EA8" access="00003333" name="MACLCON1" mclr="00002222" por="00002222" />
+    <sfr address="0x0EA7" access="03333333" name="MAIPGH" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA6" access="03333333" name="MAIPGL" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA4" access="03333333" name="MABBIPG" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA3" access="03330000" name="MACON4" mclr="01110011" por="01110011" />
+    <sfr address="0x0EA2" access="33333333" name="MACON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA0" access="00003333" name="MACON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0E99" access="33333333" name="EPAUSH" mclr="11121111" por="11121111" />
+    <sfr address="0x0E98" access="33333333" name="EPAUSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0E97" access="00000133" name="EFLOCON" mclr="00000111" por="00000111" />
+    <sfr address="0x0E8A" access="00001111" name="MISTAT" mclr="00001111" por="00001111" />
+    <sfr address="0x0E85" access="33333333" name="MAADR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0E84" access="33333333" name="MAADR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0E83" access="33333333" name="MAADR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0E82" access="33333333" name="MAADR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0E81" access="33333333" name="MAADR6" mclr="11111111" por="11111111" />
+    <sfr address="0x0E80" access="33333333" name="MAADR5" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F96J60" unused_bank_mask="0x0000" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0EFF" start="0x0EFF" />
+    <unused end="0x0EFC" start="0x0EFC" />
+    <unused end="0x0EFA" start="0x0EF8" />
+    <unused end="0x0EE1" start="0x0EDA" />
+    <unused end="0x0ED7" start="0x0ED6" />
+    <unused end="0x0ED3" start="0x0ED2" />
+    <unused end="0x0EBF" start="0x0EBA" />
+    <unused end="0x0EB5" start="0x0EB5" />
+    <unused end="0x0EB3" start="0x0EB3" />
+    <unused end="0x0EB0" start="0x0EAC" />
+    <unused end="0x0EA5" start="0x0EA5" />
+    <unused end="0x0EA1" start="0x0EA1" />
+    <unused end="0x0E9F" start="0x0E9A" />
+    <unused end="0x0E96" start="0x0E8B" />
+    <unused end="0x0E89" start="0x0E86" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FA6" access="00033390" name="EECON1" mclr="11110111" por="11110111" />
+    <sfr address="0x0FA5" access="33333333" name="IPR3" mclr="22222222" por="22222222" />
+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA2" access="33333033" name="IPR2" mclr="22222022" por="22222022" />
+    <sfr address="0x0FA1" access="33333033" name="PIR2" mclr="11111011" por="11111011" />
+    <sfr address="0x0FA0" access="33333033" name="PIE2" mclr="11111011" por="11111011" />
+    <sfr address="0x0F9F" access="33333333" name="IPR1" mclr="22222222" por="22222222" />
+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9C" access="30330033" name="MEMCON" mclr="10110011" por="10110011" />
+    <sfr address="0x0FD3" access="30003033" name="OSCCON" mclr="10001011" por="10001011" />
+    <sfr address="0x0F9B" access="33330000" name="OSCTUNE" mclr="11111111" por="11111111" />
+    <sfr address="0x0F80" access="00333333" name="PORTA" mclr="00131111" por="00101111" />
+    <sfr address="0x0F89" access="00333333" name="LATA" mclr="00333333" por="00000000" />
+    <sfr address="0x0F92" access="00333333" name="TRISA" mclr="00222222" por="00222222" />
+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F93" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F94" access="33333333" name="TRISC" mclr="22222222" por="22222222" />
+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F95" access="33333333" name="TRISD" mclr="22222222" por="22222222" />
+    <sfr address="0x0F84" access="33333333" name="PORTE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
+    <sfr address="0x0F96" access="33333333" name="TRISE" mclr="22222222" por="22222222" />
+    <sfr address="0x0F85" access="33333333" name="PORTF" mclr="11111111" por="11111111" />
+    <sfr address="0x0F8E" access="33333333" name="LATF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F97" access="33333333" name="TRISF" mclr="22222222" por="22222222" />
+    <sfr address="0x0F86" access="33333333" name="PORTG" mclr="33333333" por="00000000" />
+    <sfr address="0x0F98" access="33333333" name="TRISG" mclr="22222222" por="22222222" />
+    <sfr address="0x0F8F" access="00033333" name="LATG" mclr="33333333" por="00000000" />
+    <sfr address="0x0F87" access="33333333" name="PORTH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F99" access="33333333" name="TRISH" mclr="22222222" por="22222222" />
+    <sfr address="0x0F90" access="33333333" name="LATH" mclr="33333333" por="00000000" />
+    <sfr address="0x0F88" access="33333333" name="PORTJ" mclr="33333333" por="00000000" />
+    <sfr address="0x0F9A" access="33333333" name="TRISJ" mclr="22222222" por="22222222" />
+    <sfr address="0x0F91" access="33333333" name="LATJ" mclr="33333333" por="00000000" />
+    <combined address="0x0FC3" size="2" name="ADRES" />
+    <sfr address="0x0FC4" access="33333333" name="ADRESH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC3" access="33333333" name="ADRESL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC2" access="00333333" name="ADCON0" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC1" access="00333333" name="ADCON1" mclr="00111111" por="00114444" />
+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
+    <sfr address="0x0FBF" access="33333333" name="CCPR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBE" access="33333333" name="CCPR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBB" access="33333333" name="CCPR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
+    <sfr address="0x0FB9" access="33333333" name="CCPR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB8" access="33333333" name="CCPR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F69" access="33333333" name="ECCP3DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0F74" size="2" name="CCPR4" />
+    <sfr address="0x0F75" access="33333333" name="CCPR4H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
+    <combined address="0x0F71" size="2" name="CCPR5" />
+    <sfr address="0x0F72" access="33333333" name="CCPR5H" mclr="33333333" por="00000000" />
+    <sfr address="0x0F71" access="33333333" name="CCPR5L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F70" access="00333333" name="CCP5CON" mclr="00111111" por="00111111" />
+    <sfr address="0x0FC9" access="33333333" name="SSP1BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0FC8" access="33333333" name="SSP1ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC7" access="33333333" name="SSP1STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC6" access="33333333" name="SSP1CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FC5" access="33333333" name="SSP1CON2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F66" access="33333333" name="SSP2BUF" mclr="33333333" por="00000000" />
+    <sfr address="0x0F65" access="33333333" name="SSP2ADD" mclr="11111111" por="11111111" />
+    <sfr address="0x0F64" access="33333333" name="SSP2STAT" mclr="11111111" por="11111111" />
+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F62" access="33333333" name="SSP2CON2" mclr="11111111" por="11111111" />
+    <combined address="0x0FD6" size="2" name="TMR0" />
+    <sfr address="0x0FD7" access="33333333" name="TMR0H" mclr="11111111" por="11111111" />
+    <sfr address="0x0FD6" access="33333333" name="TMR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD5" access="33333333" name="T0CON" mclr="22222222" por="22222222" />
+    <combined address="0x0FCE" size="2" name="TMR1" />
+    <sfr address="0x0FCF" access="33333333" name="TMR1H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCE" access="33333333" name="TMR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FCD" access="31333333" name="T1CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FCA" access="03333333" name="T2CON" mclr="01111111" por="01111111" />
+    <combined address="0x0FB2" size="2" name="TMR3" />
+    <sfr address="0x0FB3" access="33333333" name="TMR3H" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB2" access="33333333" name="TMR3L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FB1" access="33333333" name="T3CON" mclr="33333333" por="11111111" />
+    <sfr address="0x0F78" access="33333333" name="TMR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0F77" access="33333333" name="PR4" mclr="22222222" por="22222222" />
+    <sfr address="0x0F76" access="03333333" name="T4CON" mclr="01111111" por="01111111" />
+    <sfr address="0x0FB0" access="11330000" name="PSPCON" mclr="11110000" por="11110000" />
+    <sfr address="0x0FB5" access="33333333" name="CVRCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB4" access="11333333" name="CMCON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F7E" access="01033033" name="BAUDCON1" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7F" access="33333333" name="SPBRGH1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAF" access="33333333" name="SPBRG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAE" access="11111111" name="RCREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAD" access="22222222" name="TXREG1" mclr="11111111" por="11111111" />
+    <sfr address="0x0FAC" access="33330313" name="TXSTA1" mclr="11110121" por="11110121" />
+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
+    <sfr address="0x0F7C" access="01033033" name="BAUDCON2" mclr="02011011" por="02011011" />
+    <sfr address="0x0F7D" access="33333333" name="SPBRGH2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6F" access="33333333" name="SPBRG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6E" access="11111111" name="RCREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
+    <sfr address="0x0F6B" access="33333111" name="RCSTA2" mclr="11111110" por="11111110" />
+    <sfr address="0x0FD2" access="33333300" name="ECON1" mclr="11111100" por="11111100" />
+    <sfr address="0x0F7B" access="00033333" name="ERDPTH" mclr="33311212" por="00011212" />
+    <sfr address="0x0F7A" access="33333333" name="ERDPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0F61" access="00000000" name="EDATA" mclr="00000000" por="00000000" />
+    <sfr address="0x0F60" access="01515055" name="EIR" mclr="01111011" por="01111011" />
+    <sfr address="0x0EFE" access="33300000" name="ECON2" mclr="21100000" por="21100000" />
+    <sfr address="0x0EFD" access="05050153" name="ESTAT" mclr="01010111" por="01010111" />
+    <sfr address="0x0EFB" access="03333033" name="EIE" mclr="01111011" por="01111011" />
+    <sfr address="0x0EF7" access="11111111" name="EDMASCH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF6" access="11111111" name="EDMASCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF5" access="00033333" name="EDMADSTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EF4" access="33333333" name="EDMADSTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF3" access="00033333" name="EDMANDH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EF2" access="33333333" name="EDMANDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EF1" access="00033333" name="EDMASTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EF0" access="33333333" name="EDMASTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EEF" access="00033333" name="ERXWRPTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EEE" access="33333333" name="ERXWRPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EED" access="00033333" name="ERXRDPTH" mclr="00011212" por="00011212" />
+    <sfr address="0x0EEC" access="33333333" name="ERXRDPTL" mclr="22222121" por="22222121" />
+    <sfr address="0x0EEB" access="00033333" name="ERXNDH" mclr="00022222" por="00022222" />
+    <sfr address="0x0EEA" access="33333333" name="ERXNDL" mclr="22222222" por="22222222" />
+    <sfr address="0x0EE9" access="00033333" name="ERXSTH" mclr="00011212" por="00011212" />
+    <sfr address="0x0EE8" access="33333333" name="ERXSTL" mclr="22222121" por="22222121" />
+    <sfr address="0x0EE7" access="00033333" name="ETXNDH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE6" access="33333333" name="ETXNDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EE5" access="00033333" name="ETXSTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE4" access="33333333" name="ETXSTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EE3" access="00033333" name="EWRPTH" mclr="00011111" por="00011111" />
+    <sfr address="0x0EE2" access="33333333" name="EWRPTL" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED9" access="11111111" name="EPKTCNT" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED8" access="33333333" name="ERXFCON" mclr="21211112" por="21211112" />
+    <sfr address="0x0ED5" access="00033333" name="EPMOH" mclr="00011111" por="00011111" />
+    <sfr address="0x0ED4" access="33333333" name="EPMOL" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED1" access="33333333" name="EPMCSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0ED0" access="33333333" name="EPMCSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECF" access="33333333" name="EPMM7" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECE" access="33333333" name="EPMM6" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECD" access="33333333" name="EPMM5" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECC" access="33333333" name="EPMM4" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECB" access="33333333" name="EPMM3" mclr="11111111" por="11111111" />
+    <sfr address="0x0ECA" access="33333333" name="EPMM2" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC9" access="33333333" name="EPMM1" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC8" access="33333333" name="EPMM0" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC7" access="33333333" name="EHT7" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC6" access="33333333" name="EHT6" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC5" access="33333333" name="EHT5" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC4" access="33333333" name="EHT4" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC3" access="33333333" name="EHT3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC2" access="33333333" name="EHT2" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC1" access="33333333" name="EHT1" mclr="11111111" por="11111111" />
+    <sfr address="0x0EC0" access="33333333" name="EHT0" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB9" access="11111111" name="MIRDH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB8" access="11111111" name="MIRDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB7" access="22222222" name="MIWDH" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB6" access="22222222" name="MIWDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB4" access="00033333" name="MIREGADR" mclr="00011111" por="00011111" />
+    <sfr address="0x0EB2" access="00000033" name="MICMD" mclr="00000011" por="00000011" />
+    <sfr address="0x0EB1" access="30000000" name="MICON" mclr="10000000" por="10000000" />
+    <sfr address="0x0EAB" access="33333333" name="MAMXFLH" mclr="11111221" por="11111221" />
+    <sfr address="0x0EAA" access="33333333" name="MAMXFLL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA9" access="00333333" name="MACLCON2" mclr="00221222" por="00221222" />
+    <sfr address="0x0EA8" access="00003333" name="MACLCON1" mclr="00002222" por="00002222" />
+    <sfr address="0x0EA7" access="03333333" name="MAIPGH" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA6" access="03333333" name="MAIPGL" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA4" access="03333333" name="MABBIPG" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA3" access="03330000" name="MACON4" mclr="01110011" por="01110011" />
+    <sfr address="0x0EA2" access="33333333" name="MACON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA0" access="00003333" name="MACON1" mclr="00011111" por="00011111" />
+    <sfr address="0x0E99" access="33333333" name="EPAUSH" mclr="11121111" por="11121111" />
+    <sfr address="0x0E98" access="33333333" name="EPAUSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0E97" access="00000133" name="EFLOCON" mclr="00000111" por="00000111" />
+    <sfr address="0x0E8A" access="00001111" name="MISTAT" mclr="00001111" por="00001111" />
+    <sfr address="0x0E85" access="33333333" name="MAADR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0E84" access="33333333" name="MAADR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0E83" access="33333333" name="MAADR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0E82" access="33333333" name="MAADR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0E81" access="33333333" name="MAADR6" mclr="11111111" por="11111111" />
+    <sfr address="0x0E80" access="33333333" name="MAADR5" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F96J65" unused_bank_mask="0x0000" >
+    <unused end="0x0FD4" start="0x0FD4" />
+    <unused end="0x0FAA" start="0x0FA8" />
+    <unused end="0x0EFF" start="0x0EFF" />
+    <unused end="0x0EFC" start="0x0EFC" />
+    <unused end="0x0EFA" start="0x0EF8" />
+    <unused end="0x0EE1" start="0x0EDA" />
+    <unused end="0x0ED7" start="0x0ED6" />
+    <unused end="0x0ED3" start="0x0ED2" />
+    <unused end="0x0EBF" start="0x0EBA" />
+    <unused end="0x0EB5" start="0x0EB5" />
+    <unused end="0x0EB3" start="0x0EB3" />
+    <unused end="0x0EB0" start="0x0EAC" />
+    <unused end="0x0EA5" start="0x0EA5" />
+    <unused end="0x0EA1" start="0x0EA1" />
+    <unused end="0x0E9F" start="0x0E9A" />
+    <unused end="0x0E96" start="0x0E8B" />
+    <unused end="0x0E89" start="0x0E86" />
+    <combined address="0x0FFD" size="3" name="TOS" />
+    <sfr address="0x0FFF" access="00033333" name="TOSU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFE" access="33333333" name="TOSH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFD" access="33333333" name="TOSL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FFC" access="55033333" name="STKPTR" mclr="11011111" por="11011111" />
+    <combined address="0x0FF9" size="3" name="PCLAT" />
+    <sfr address="0x0FFB" access="00033333" name="PCLATU" mclr="00011111" por="00011111" />
+    <sfr address="0x0FFA" access="33333333" name="PCLATH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF9" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <combined address="0x0FF6" size="3" name="TBLPTR" />
+    <sfr address="0x0FF8" access="00333333" name="TBLPTRU" mclr="00111111" por="00111111" />
+    <sfr address="0x0FF7" access="33333333" name="TBLPTRH" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF6" access="33333333" name="TBLPTRL" mclr="11111111" por="11111111" />
+    <sfr address="0x0FF5" access="33333333" name="TABLAT" mclr="11111111" por="11111111" />
+    <combined address="0x0FF3" size="2" name="PROD" />
+    <sfr address="0x0FF4" access="33333333" name="PRODH" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF3" access="33333333" name="PRODL" mclr="33333333" por="00000000" />
+    <sfr address="0x0FF2" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0FF1" access="33333333" name="INTCON2" mclr="22222222" por="22222222" />
+    <sfr address="0x0FF0" access="33333333" name="INTCON3" mclr="22111111" por="22111111" />
+    <sfr address="0x0FEF" access="00000000" name="INDF0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEE" access="00000000" name="POSTINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FED" access="00000000" name="POSTDEC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEC" access="00000000" name="PREINC0" mclr="00000000" por="00000000" />
+    <sfr address="0x0FEB" access="00000000" name="PLUSW0" mclr="00000000" por="00000000" />
+    <combined address="0x0FE9" size="2" name="FSR0" />
+    <sfr address="0x0FEA" access="00003333" name="FSR0H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE9" access="33333333" name="FSR0L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE8" access="33333333" name="WREG" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE7" access="00000000" name="INDF1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE6" access="00000000" name="POSTINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE5" access="00000000" name="POSTDEC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE4" access="00000000" name="PREINC1" mclr="00000000" por="00000000" />
+    <sfr address="0x0FE3" access="00000000" name="PLUSW1" mclr="00000000" por="00000000" />
+    <combined address="0x0FE1" size="2" name="FSR1" />
+    <sfr address="0x0FE2" access="00003333" name="FSR1H" mclr="00003333" por="00001111" />
+    <sfr address="0x0FE1" access="33333333" name="FSR1L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FE0" access="00003333" name="BSR" mclr="00001111" por="00001111" />
+    <sfr address="0x0FDF" access="00000000" name="INDF2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDE" access="00000000" name="POSTINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDD" access="00000000" name="POSTDEC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDC" access="00000000" name="PREINC2" mclr="00000000" por="00000000" />
+    <sfr address="0x0FDB" access="00000000" name="PLUSW2" mclr="00000000" por="00000000" />
+    <combined address="0x0FD9" size="2" name="FSR2" />
+    <sfr address="0x0FDA" access="00003333" name="FSR2H" mclr="00001111" por="00001111" />
+    <sfr address="0x0FD9" access="33333333" name="FSR2L" mclr="33333333" por="00000000" />
+    <sfr address="0x0FD8" access="00033333" name="STATUS" mclr="00033333" por="00000000" />
+    <sfr address="0x0FD1" access="00000003" name="WDTCON" mclr="00000001" por="00000001" />
+    <sfr address="0x0FD0" access="30033333" name="RCON" mclr="10034433" por="10022211" />
+    <sfr address="0x0FA7" access="22222222" name="EECON2" mclr="00000000" por="00000000" />
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+    <sfr address="0x0FA4" access="33133333" name="PIR3" mclr="11111111" por="11111111" />
+    <sfr address="0x0FA3" access="33333333" name="PIE3" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FA1" access="33333033" name="PIR2" mclr="11111011" por="11111011" />
+    <sfr address="0x0FA0" access="33333033" name="PIE2" mclr="11111011" por="11111011" />
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+    <sfr address="0x0F9E" access="33113333" name="PIR1" mclr="11111111" por="11111111" />
+    <sfr address="0x0F9D" access="33333333" name="PIE1" mclr="11111111" por="11111111" />
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+    <sfr address="0x0F9B" access="33330000" name="OSCTUNE" mclr="11111111" por="11111111" />
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+    <sfr address="0x0F81" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F8A" access="33333333" name="LATB" mclr="33333333" por="00000000" />
+    <sfr address="0x0F82" access="33333333" name="PORTC" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8B" access="33333333" name="LATC" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F83" access="33333333" name="PORTD" mclr="33333333" por="00000000" />
+    <sfr address="0x0F8C" access="33333333" name="LATD" mclr="33333333" por="00000000" />
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+    <sfr address="0x0F8D" access="33333333" name="LATE" mclr="33333333" por="00000000" />
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+    <sfr address="0x0FC0" access="30333333" name="ADCON2" mclr="10111111" por="10111111" />
+    <combined address="0x0FBE" size="2" name="CCPR1" />
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+    <sfr address="0x0FBD" access="33333333" name="CCP1CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0FB6" access="33333333" name="ECCP1AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F79" access="33333333" name="ECCP1DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FBB" size="2" name="CCPR2" />
+    <sfr address="0x0FBC" access="33333333" name="CCPR2H" mclr="33333333" por="00000000" />
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+    <sfr address="0x0FBA" access="33333333" name="CCP2CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F68" access="33333333" name="ECCP2AS" mclr="11111111" por="11111111" />
+    <sfr address="0x0F67" access="33333333" name="ECCP2DEL" mclr="11111111" por="11111111" />
+    <combined address="0x0FB8" size="2" name="CCPR3" />
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+    <sfr address="0x0FB7" access="33333333" name="CCP3CON" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6A" access="33333333" name="ECCP3AS" mclr="11111111" por="11111111" />
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+    <sfr address="0x0F74" access="33333333" name="CCPR4L" mclr="33333333" por="00000000" />
+    <sfr address="0x0F73" access="00333333" name="CCP4CON" mclr="00111111" por="00111111" />
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+    <sfr address="0x0F63" access="33333333" name="SSP2CON1" mclr="11111111" por="11111111" />
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+    <sfr address="0x0FCC" access="33333333" name="TMR2" mclr="11111111" por="11111111" />
+    <sfr address="0x0FCB" access="33333333" name="PR2" mclr="22222222" por="22222222" />
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+    <sfr address="0x0FAB" access="33333111" name="RCSTA1" mclr="11111110" por="11111110" />
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+    <sfr address="0x0F6D" access="22222222" name="TXREG2" mclr="11111111" por="11111111" />
+    <sfr address="0x0F6C" access="33330313" name="TXSTA2" mclr="11110121" por="11110121" />
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+    <sfr address="0x0EEC" access="33333333" name="ERXRDPTL" mclr="22222121" por="22222121" />
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+    <sfr address="0x0EC3" access="33333333" name="EHT3" mclr="11111111" por="11111111" />
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+    <sfr address="0x0EB8" access="11111111" name="MIRDL" mclr="11111111" por="11111111" />
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+    <sfr address="0x0EB6" access="22222222" name="MIWDL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EB4" access="00033333" name="MIREGADR" mclr="00011111" por="00011111" />
+    <sfr address="0x0EB2" access="00000033" name="MICMD" mclr="00000011" por="00000011" />
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+    <sfr address="0x0EAB" access="33333333" name="MAMXFLH" mclr="11111221" por="11111221" />
+    <sfr address="0x0EAA" access="33333333" name="MAMXFLL" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA9" access="00333333" name="MACLCON2" mclr="00221222" por="00221222" />
+    <sfr address="0x0EA8" access="00003333" name="MACLCON1" mclr="00002222" por="00002222" />
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+    <sfr address="0x0EA4" access="03333333" name="MABBIPG" mclr="01111111" por="01111111" />
+    <sfr address="0x0EA3" access="03330000" name="MACON4" mclr="01110011" por="01110011" />
+    <sfr address="0x0EA2" access="33333333" name="MACON3" mclr="11111111" por="11111111" />
+    <sfr address="0x0EA0" access="00003333" name="MACON1" mclr="00011111" por="00011111" />
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+    <sfr address="0x0E97" access="00000133" name="EFLOCON" mclr="00000111" por="00000111" />
+    <sfr address="0x0E8A" access="00001111" name="MISTAT" mclr="00001111" por="00001111" />
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+    <sfr address="0x0E83" access="33333333" name="MAADR4" mclr="11111111" por="11111111" />
+    <sfr address="0x0E82" access="33333333" name="MAADR3" mclr="11111111" por="11111111" />
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+    <sfr address="0x0E80" access="33333333" name="MAADR5" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="16" access_bank_split_offset="0x60" name="18F97J60" unused_bank_mask="0x0000" >
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+    <sfr address="0x0E80" access="33333333" name="MAADR5" mclr="11111111" por="11111111" />
+  </device>
+  <device nb_banks="1" name="24FJ128GA006" >
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+  </device>
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+    <sfr address="0x02D6" access="0000333333333333" name="LATD" mclr="0000333333333333" por="0000111111111111" />
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+    <sfr address="0x039E" access="3333333333333333" name="DMA2STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A0" access="3333333333333333" name="DMA2PAD" mclr="1111111111111111" por="1111111111111111" />
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+    <sfr address="0x03B0" access="3333300000330033" name="DMA4CON" mclr="1111100000110011" por="1111100000110011" />
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+    <sfr address="0x03B4" access="3333333333333333" name="DMA4STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B6" access="3333333333333333" name="DMA4STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B8" access="3333333333333333" name="DMA4PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BA" access="0000003333333333" name="DMA4CNT" mclr="1111111111111111" por="1111111111111111" />
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+    <sfr address="0x03C0" access="3333333333333333" name="DMA5STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C2" access="3333333333333333" name="DMA5STB" mclr="1111111111111111" por="1111111111111111" />
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+    <sfr address="0x03CE" access="3333333333333333" name="DMA6STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D0" access="3333333333333333" name="DMA6PAD" mclr="1111111111111111" por="1111111111111111" />
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+    <sfr address="0x03D4" access="3333300000330033" name="DMA7CON" mclr="1111100000110011" por="1111100000110011" />
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+    <sfr address="0x03DA" access="3333333333333333" name="DMA7STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DC" access="3333333333333333" name="DMA7PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DE" access="0000003333333333" name="DMA7CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E0" access="1111111111111111" name="DMACS0" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E2" access="0000111111111111" name="DMACS1" mclr="0000111111111111" por="0000111111111111" />
+    <sfr address="0x03E4" access="1111111111111111" name="DSADR" mclr="1111111111111111" por="1111111111111111" />
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+    <sfr address="0x0602" access="3333333333333333" name="PMPMODE" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0604" access="3333333333333333" name="PMPADDR" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0606" access="3333333333333333" name="PMPDATA1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0608" access="3333333333333333" name="PMPDATA2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060A" access="3333333333333333" name="PMPPE1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060C" access="3333333333333333" name="PMPPE2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0620" access="3333333333333333" name="ALRMVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0622" access="3333333333333333" name="ALRMCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0624" access="3333333333333333" name="RTCVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0626" access="3333333333333333" name="RTCCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0630" access="3033333333333333" name="CMCON" mclr="3033333333333333" por="1011111111111111" />
+    <sfr address="0x0632" access="0000000033333333" name="CVRCON" mclr="0000000033333333" por="0000000011111111" />
+    <sfr address="0x0740" access="3300000033333333" name="RCON" mclr="3300000033333333" por="1100000011111122" />
+    <sfr address="0x0742" access="0333033330303033" name="OSCCON" mclr="0555055510001111" por="0555055510001111" />
+    <sfr address="0x0744" access="3333333333333333" name="CLKDIV" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0746" access="0000000333333333" name="PLLFBD" mclr="0000000333333333" por="0000000111111111" />
+    <sfr address="0x0748" access="0000000000333333" name="OSCTRIM" mclr="0000000000333333" por="0000000000111111" />
+    <sfr address="0x0760" access="9330000003003333" name="NVMCON" mclr="1110000001001111" por="1110000001001111" />
+    <sfr address="0x0766" access="0000000022222222" name="NVMKEY" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0770" access="3333300333333003" name="PMD1" mclr="1111100111111001" por="1111100111111111" />
+    <sfr address="0x0772" access="3333333333333333" name="PMD2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0774" access="0000033300000030" name="PMD3" mclr="0000011100000010" por="0000011100000010" />
+  </device>
+  <device nb_banks="1" name="24HJ128GP210" >
+    <unused end="0x002D" start="0x0022" />
+    <unused end="0x0041" start="0x0038" />
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+  </device>
+  <device nb_banks="1" name="24HJ128GP306" >
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+    <sfr address="0x03BE" access="9000000003333333" name="DMA5REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03C0" access="3333333333333333" name="DMA5STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C2" access="3333333333333333" name="DMA5STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C4" access="3333333333333333" name="DMA5PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C6" access="0000003333333333" name="DMA5CNT" mclr="1111111111111111" por="1111111111111111" />
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+    <sfr address="0x03CA" access="9000000003333333" name="DMA6REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03CC" access="3333333333333333" name="DMA6STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03CE" access="3333333333333333" name="DMA6STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D0" access="3333333333333333" name="DMA6PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D2" access="0000003333333333" name="DMA6CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D4" access="3333300000330033" name="DMA7CON" mclr="1111100000110011" por="1111100000110011" />
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+    <sfr address="0x03DA" access="3333333333333333" name="DMA7STB" mclr="1111111111111111" por="1111111111111111" />
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+    <sfr address="0x03DE" access="0000003333333333" name="DMA7CNT" mclr="1111111111111111" por="1111111111111111" />
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+  </device>
+  <device nb_banks="1" name="24HJ128GP310" >
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+    <sfr address="0x01A2" access="0030000000013333" name="OC6CON" mclr="0010000000011111" por="0010000000011111" />
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+    <sfr address="0x01A6" access="3333333333333333" name="OC7R" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x01A8" access="0030000000013333" name="OC7CON" mclr="0010000000011111" por="0010000000011111" />
+    <sfr address="0x01AA" access="3333333333333333" name="OC8RS" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x01AC" access="3333333333333333" name="OC8R" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x01AE" access="0030000000013333" name="OC8CON" mclr="0010000000011111" por="0010000000011111" />
+    <sfr address="0x0200" access="0000000011111111" name="I2C1RCV" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0202" access="0000000022222222" name="I2C1TRN" mclr="0000000022222222" por="0000000022222222" />
+    <sfr address="0x0204" access="0000000333333333" name="I2C1BRG" mclr="0000000111111111" por="0000000111111111" />
+    <sfr address="0x0206" access="3033303333333333" name="I2C1CON" mclr="1012101111111111" por="1012101111111111" />
+    <sfr address="0x0208" access="1100011155155111" name="I2C1STAT" mclr="1100011111111111" por="1100011111111111" />
+    <sfr address="0x020A" access="0000003333333333" name="I2C1ADD" mclr="0000001111111111" por="0000001111111111" />
+    <sfr address="0x020C" access="0000003333333333" name="I2C1MSK" mclr="0000001111111111" por="0000001111111111" />
+    <sfr address="0x0210" access="0000000011111111" name="I2C2RCV" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0212" access="0000000022222222" name="I2C2TRN" mclr="0000000022222222" por="0000000022222222" />
+    <sfr address="0x0214" access="0000000333333333" name="I2C2BRG" mclr="0000000111111111" por="0000000111111111" />
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+    <sfr address="0x021A" access="0000003333333333" name="I2C2ADD" mclr="0000001111111111" por="0000001111111111" />
+    <sfr address="0x021C" access="0000003333333333" name="I2C2MSK" mclr="0000001111111111" por="0000001111111111" />
+    <sfr address="0x0220" access="3033303333333333" name="U1MODE" mclr="1011101111111111" por="1011101111111111" />
+    <sfr address="0x0222" access="3330331133311151" name="U1STA" mclr="1110111211121111" por="1110111211121111" />
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+    <sfr address="0x0226" access="0000000111111111" name="U1RXREG" mclr="0000000111111111" por="0000000111111111" />
+    <sfr address="0x0228" access="3333333333333333" name="U1BRG" mclr="1111111111111111" por="1111111111111111" />
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+    <sfr address="0x0234" access="0000000222222222" name="U2TXREG" mclr="0000000111111111" por="0000000000000000" />
+    <sfr address="0x0236" access="0000000111111111" name="U2RXREG" mclr="0000000111111111" por="0000000111111111" />
+    <sfr address="0x0238" access="3333333333333333" name="U2BRG" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0240" access="3030033305000011" name="SPI1STAT" mclr="1010011101000011" por="1010011101000011" />
+    <sfr address="0x0242" access="0003333333333333" name="SPI1CON1" mclr="0001111111111111" por="0001111111111111" />
+    <sfr address="0x0244" access="3330000000000033" name="SPI1CON2" mclr="1110000000000011" por="1110000000000011" />
+    <sfr address="0x0248" access="3333333333333333" name="SPI1BUF" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0260" access="3030033305000011" name="SPI2STAT" mclr="1010011101000011" por="1010011101000011" />
+    <sfr address="0x0262" access="0003333333333333" name="SPI2CON1" mclr="0001111111111111" por="0001111111111111" />
+    <sfr address="0x0264" access="3330000000000033" name="SPI2CON2" mclr="1110000000000011" por="1110000000000011" />
+    <sfr address="0x0268" access="3333333333333333" name="SPI2BUF" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x02C0" access="3333033033333333" name="TRISA" mclr="2222022022222222" por="2222022022222222" />
+    <sfr address="0x02C2" access="3333033033333333" name="PORTA" mclr="3333033033333333" por="0000000000000000" />
+    <sfr address="0x02C4" access="3333033033333333" name="LATA" mclr="3333033033333333" por="1111011011111111" />
+    <sfr address="0x06C0" access="3333000000333333" name="ODCA" mclr="3333000000333333" por="1111000000111111" />
+    <sfr address="0x02C6" access="3333333333333333" name="TRISB" mclr="2222222222222222" por="2222222222222222" />
+    <sfr address="0x02C8" access="3333333333333333" name="PORTB" mclr="3333333333333333" por="0000000000000000" />
+    <sfr address="0x02CA" access="3333333333333333" name="LATB" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x02CC" access="3333000000033330" name="TRISC" mclr="2222000000022220" por="2222000000022220" />
+    <sfr address="0x02CE" access="3333000000033330" name="PORTC" mclr="3333000000033330" por="0000000000000000" />
+    <sfr address="0x02D0" access="3333000000033330" name="LATC" mclr="3333000000033330" por="1111000000011110" />
+    <sfr address="0x02D2" access="3333333333333333" name="TRISD" mclr="2222222222222222" por="2222222222222222" />
+    <sfr address="0x02D4" access="3333333333333333" name="PORTD" mclr="3333333333333333" por="0000000000000000" />
+    <sfr address="0x02D6" access="3333333333333333" name="LATD" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x06D2" access="3333333333333333" name="ODCD" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x02D8" access="0000000033333333" name="TRISE" mclr="0000000022222222" por="0000000022222222" />
+    <sfr address="0x02DA" access="0000000033333333" name="PORTE" mclr="0000000033333333" por="0000000000000000" />
+    <sfr address="0x02DC" access="0000000033333333" name="LATE" mclr="0000000033333333" por="0000000011111111" />
+    <sfr address="0x02DE" access="0033000333333333" name="TRISF" mclr="0022000222222222" por="0022000222222222" />
+    <sfr address="0x02E0" access="0033000333333333" name="PORTF" mclr="0033000333333333" por="0000000000000000" />
+    <sfr address="0x02E2" access="0033000333333333" name="LATF" mclr="0033000333333333" por="0011000111111111" />
+    <sfr address="0x06DE" access="0033000333333333" name="ODCF" mclr="0033000333333333" por="0011000111111111" />
+    <sfr address="0x02E4" access="3333003333003333" name="TRISG" mclr="2222002222002222" por="2222002222002222" />
+    <sfr address="0x02E6" access="3333003333003333" name="PORTG" mclr="3333003333003333" por="0000000000000000" />
+    <sfr address="0x02E8" access="3333003333003333" name="LATG" mclr="3333003333003333" por="1111001111001111" />
+    <sfr address="0x0300" access="0000111111111111" name="AD1BUF0" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0302" access="0000111111111111" name="AD1BUF1" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0304" access="0000111111111111" name="AD1BUF2" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0306" access="0000111111111111" name="AD1BUF3" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0308" access="0000111111111111" name="AD1BUF4" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x030A" access="0000111111111111" name="AD1BUF5" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x030C" access="0000111111111111" name="AD1BUF6" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x030E" access="0000111111111111" name="AD1BUF7" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0310" access="0000111111111111" name="AD1BUF8" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0312" access="0000111111111111" name="AD1BUF9" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0314" access="0000111111111111" name="AD1BUFA" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0316" access="0000111111111111" name="AD1BUFB" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0318" access="0000111111111111" name="AD1BUFC" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031A" access="0000111111111111" name="AD1BUFD" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031C" access="0000111111111111" name="AD1BUFE" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031E" access="0000111111111111" name="AD1BUFF" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0320" access="3030003333303335" name="AD1CON1" mclr="1010001111100111" por="1010001111100111" />
+    <sfr address="0x0322" access="3333033310333333" name="AD1CON2" mclr="1111011110111111" por="1111011110111111" />
+    <sfr address="0x0324" access="0003333330333333" name="AD1CON3" mclr="0001111110111111" por="0001111110111111" />
+    <sfr address="0x0332" access="0000000000000333" name="AD1CON4" mclr="0000000000000111" por="0000000000000111" />
+    <sfr address="0x0326" access="0000033300000333" name="AD1CHS123" mclr="0000011100000111" por="0000011100000111" />
+    <sfr address="0x0328" access="3000333330003333" name="AD1CHS0" mclr="1000111110001111" por="1000111110001111" />
+    <sfr address="0x032C" access="3333333333333333" name="AD1PCFGL" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0330" access="3333333333333333" name="AD1CSSL" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x032A" access="3333333333333333" name="AD1PCFGH" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x032E" access="3333333333333333" name="AD1CSSH" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0380" access="3333300000330033" name="DMA0CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x0382" access="9000000003333333" name="DMA0REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x0384" access="3333333333333333" name="DMA0STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0386" access="3333333333333333" name="DMA0STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0388" access="3333333333333333" name="DMA0PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x038A" access="0000003333333333" name="DMA0CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x038C" access="3333300000330033" name="DMA1CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x038E" access="9000000003333333" name="DMA1REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x0390" access="3333333333333333" name="DMA1STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0392" access="3333333333333333" name="DMA1STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0394" access="3333333333333333" name="DMA1PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0396" access="0000003333333333" name="DMA1CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0398" access="3333300000330033" name="DMA2CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x039A" access="9000000003333333" name="DMA2REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x039C" access="3333333333333333" name="DMA2STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x039E" access="3333333333333333" name="DMA2STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A0" access="3333333333333333" name="DMA2PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A2" access="0000003333333333" name="DMA2CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A4" access="3333300000330033" name="DMA3CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03A6" access="9000000003333333" name="DMA3REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03A8" access="3333333333333333" name="DMA3STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AA" access="3333333333333333" name="DMA3STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AC" access="3333333333333333" name="DMA3PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AE" access="0000003333333333" name="DMA3CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B0" access="3333300000330033" name="DMA4CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03B2" access="9000000003333333" name="DMA4REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03B4" access="3333333333333333" name="DMA4STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B6" access="3333333333333333" name="DMA4STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B8" access="3333333333333333" name="DMA4PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BA" access="0000003333333333" name="DMA4CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BC" access="3333300000330033" name="DMA5CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03BE" access="9000000003333333" name="DMA5REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03C0" access="3333333333333333" name="DMA5STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C2" access="3333333333333333" name="DMA5STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C4" access="3333333333333333" name="DMA5PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C6" access="0000003333333333" name="DMA5CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C8" access="3333300000330033" name="DMA6CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03CA" access="9000000003333333" name="DMA6REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03CC" access="3333333333333333" name="DMA6STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03CE" access="3333333333333333" name="DMA6STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D0" access="3333333333333333" name="DMA6PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D2" access="0000003333333333" name="DMA6CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D4" access="3333300000330033" name="DMA7CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03D6" access="9000000003333333" name="DMA7REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03D8" access="3333333333333333" name="DMA7STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DA" access="3333333333333333" name="DMA7STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DC" access="3333333333333333" name="DMA7PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DE" access="0000003333333333" name="DMA7CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E0" access="1111111111111111" name="DMACS0" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E2" access="0000111111111111" name="DMACS1" mclr="0000111111111111" por="0000111111111111" />
+    <sfr address="0x03E4" access="1111111111111111" name="DSADR" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0600" access="3033333333333333" name="PMPCON" mclr="1011111111111111" por="1011111111111111" />
+    <sfr address="0x0602" access="3333333333333333" name="PMPMODE" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0604" access="3333333333333333" name="PMPADDR" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0606" access="3333333333333333" name="PMPDATA1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0608" access="3333333333333333" name="PMPDATA2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060A" access="3333333333333333" name="PMPPE1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060C" access="3333333333333333" name="PMPPE2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0620" access="3333333333333333" name="ALRMVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0622" access="3333333333333333" name="ALRMCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0624" access="3333333333333333" name="RTCVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0626" access="3333333333333333" name="RTCCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0630" access="3033333333333333" name="CMCON" mclr="3033333333333333" por="1011111111111111" />
+    <sfr address="0x0632" access="0000000033333333" name="CVRCON" mclr="0000000033333333" por="0000000011111111" />
+    <sfr address="0x0740" access="3300000033333333" name="RCON" mclr="3300000033333333" por="1100000011111122" />
+    <sfr address="0x0742" access="0333033330303033" name="OSCCON" mclr="0555055510001111" por="0555055510001111" />
+    <sfr address="0x0744" access="3333333333333333" name="CLKDIV" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0746" access="0000000333333333" name="PLLFBD" mclr="0000000333333333" por="0000000111111111" />
+    <sfr address="0x0748" access="0000000000333333" name="OSCTRIM" mclr="0000000000333333" por="0000000000111111" />
+    <sfr address="0x0760" access="9330000003003333" name="NVMCON" mclr="1110000001001111" por="1110000001001111" />
+    <sfr address="0x0766" access="0000000022222222" name="NVMKEY" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0770" access="3333300333333003" name="PMD1" mclr="1111100111111001" por="1111100111111111" />
+    <sfr address="0x0772" access="3333333333333333" name="PMD2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0774" access="0000033300000030" name="PMD3" mclr="0000011100000010" por="0000011100000010" />
+  </device>
+  <device nb_banks="1" name="24HJ128GP506" >
+    <unused end="0x002D" start="0x0022" />
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+    <sfr address="0x0312" access="0000111111111111" name="AD1BUF9" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0314" access="0000111111111111" name="AD1BUFA" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0316" access="0000111111111111" name="AD1BUFB" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0318" access="0000111111111111" name="AD1BUFC" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031A" access="0000111111111111" name="AD1BUFD" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031C" access="0000111111111111" name="AD1BUFE" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031E" access="0000111111111111" name="AD1BUFF" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0320" access="3030003333303335" name="AD1CON1" mclr="1010001111100111" por="1010001111100111" />
+    <sfr address="0x0322" access="3333033310333333" name="AD1CON2" mclr="1111011110111111" por="1111011110111111" />
+    <sfr address="0x0324" access="0003333330333333" name="AD1CON3" mclr="0001111110111111" por="0001111110111111" />
+    <sfr address="0x0332" access="0000000000000333" name="AD1CON4" mclr="0000000000000111" por="0000000000000111" />
+    <sfr address="0x0326" access="0000033300000333" name="AD1CHS123" mclr="0000011100000111" por="0000011100000111" />
+    <sfr address="0x0328" access="3000333330003333" name="AD1CHS0" mclr="1000111110001111" por="1000111110001111" />
+    <sfr address="0x032C" access="3333333333333333" name="AD1PCFGL" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0330" access="3333333333333333" name="AD1CSSL" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x032A" access="0000000000000033" name="AD1PCFGH" mclr="0000000000000011" por="0000000000000011" />
+    <sfr address="0x032E" access="0000000000000033" name="AD1CSSH" mclr="0000000000000011" por="0000000000000011" />
+    <sfr address="0x0380" access="3333300000330033" name="DMA0CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x0382" access="9000000003333333" name="DMA0REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x0384" access="3333333333333333" name="DMA0STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0386" access="3333333333333333" name="DMA0STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0388" access="3333333333333333" name="DMA0PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x038A" access="0000003333333333" name="DMA0CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x038C" access="3333300000330033" name="DMA1CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x038E" access="9000000003333333" name="DMA1REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x0390" access="3333333333333333" name="DMA1STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0392" access="3333333333333333" name="DMA1STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0394" access="3333333333333333" name="DMA1PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0396" access="0000003333333333" name="DMA1CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0398" access="3333300000330033" name="DMA2CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x039A" access="9000000003333333" name="DMA2REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x039C" access="3333333333333333" name="DMA2STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x039E" access="3333333333333333" name="DMA2STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A0" access="3333333333333333" name="DMA2PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A2" access="0000003333333333" name="DMA2CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A4" access="3333300000330033" name="DMA3CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03A6" access="9000000003333333" name="DMA3REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03A8" access="3333333333333333" name="DMA3STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AA" access="3333333333333333" name="DMA3STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AC" access="3333333333333333" name="DMA3PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AE" access="0000003333333333" name="DMA3CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B0" access="3333300000330033" name="DMA4CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03B2" access="9000000003333333" name="DMA4REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03B4" access="3333333333333333" name="DMA4STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B6" access="3333333333333333" name="DMA4STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B8" access="3333333333333333" name="DMA4PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BA" access="0000003333333333" name="DMA4CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BC" access="3333300000330033" name="DMA5CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03BE" access="9000000003333333" name="DMA5REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03C0" access="3333333333333333" name="DMA5STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C2" access="3333333333333333" name="DMA5STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C4" access="3333333333333333" name="DMA5PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C6" access="0000003333333333" name="DMA5CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C8" access="3333300000330033" name="DMA6CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03CA" access="9000000003333333" name="DMA6REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03CC" access="3333333333333333" name="DMA6STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03CE" access="3333333333333333" name="DMA6STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D0" access="3333333333333333" name="DMA6PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D2" access="0000003333333333" name="DMA6CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D4" access="3333300000330033" name="DMA7CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03D6" access="9000000003333333" name="DMA7REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03D8" access="3333333333333333" name="DMA7STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DA" access="3333333333333333" name="DMA7STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DC" access="3333333333333333" name="DMA7PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DE" access="0000003333333333" name="DMA7CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E0" access="1111111111111111" name="DMACS0" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E2" access="0000111111111111" name="DMACS1" mclr="0000111111111111" por="0000111111111111" />
+    <sfr address="0x03E4" access="1111111111111111" name="DSADR" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0600" access="3033333333333333" name="PMPCON" mclr="1011111111111111" por="1011111111111111" />
+    <sfr address="0x0602" access="3333333333333333" name="PMPMODE" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0604" access="3333333333333333" name="PMPADDR" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0606" access="3333333333333333" name="PMPDATA1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0608" access="3333333333333333" name="PMPDATA2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060A" access="3333333333333333" name="PMPPE1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060C" access="3333333333333333" name="PMPPE2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0620" access="3333333333333333" name="ALRMVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0622" access="3333333333333333" name="ALRMCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0624" access="3333333333333333" name="RTCVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0626" access="3333333333333333" name="RTCCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0630" access="3033333333333333" name="CMCON" mclr="3033333333333333" por="1011111111111111" />
+    <sfr address="0x0632" access="0000000033333333" name="CVRCON" mclr="0000000033333333" por="0000000011111111" />
+    <sfr address="0x0740" access="3300000033333333" name="RCON" mclr="3300000033333333" por="1100000011111122" />
+    <sfr address="0x0742" access="0333033330303033" name="OSCCON" mclr="0555055510001111" por="0555055510001111" />
+    <sfr address="0x0744" access="3333333333333333" name="CLKDIV" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0746" access="0000000333333333" name="PLLFBD" mclr="0000000333333333" por="0000000111111111" />
+    <sfr address="0x0748" access="0000000000333333" name="OSCTRIM" mclr="0000000000333333" por="0000000000111111" />
+    <sfr address="0x0760" access="9330000003003333" name="NVMCON" mclr="1110000001001111" por="1110000001001111" />
+    <sfr address="0x0766" access="0000000022222222" name="NVMKEY" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0770" access="3333300333333033" name="PMD1" mclr="1111100111111011" por="1111100111111111" />
+    <sfr address="0x0772" access="3333333333333333" name="PMD2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0774" access="0000033300000000" name="PMD3" mclr="0000011100000000" por="0000011100000000" />
+  </device>
+  <device nb_banks="1" name="24HJ128GP510" >
+    <unused end="0x002D" start="0x0022" />
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+    <sfr address="0x0000" access="3333333333333333" name="WREG0" mclr="1111111111111111" por="1111111111111111" />
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+    <sfr address="0x0020" access="3333333333333331" name="SPLIM" mclr="1111111111111111" por="1111111111111111" />
+    <combined address="0x002E" size="3" name="PC" />
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+    <sfr address="0x03E0" access="1111111111111111" name="DMACS0" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E2" access="0000111111111111" name="DMACS1" mclr="0000111111111111" por="0000111111111111" />
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+    <sfr address="0x0602" access="3333333333333333" name="PMPMODE" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0604" access="3333333333333333" name="PMPADDR" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0606" access="3333333333333333" name="PMPDATA1" mclr="3333333333333333" por="1111111111111111" />
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+    <sfr address="0x0624" access="3333333333333333" name="RTCVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0626" access="3333333333333333" name="RTCCFG" mclr="3333333333333333" por="1111111111111111" />
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+    <sfr address="0x047E" access="3333333333333333" name="C1RXF15EID" mclr="0000000000000000" por="0000000000000000" />
+  </device>
+  <device nb_banks="1" name="24HJ12GP201" >
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+    <sfr address="0x0226" access="0000000111111111" name="U1RXREG" mclr="0000000111111111" por="0000000111111111" />
+    <sfr address="0x0228" access="3333333333333333" name="U1BRG" mclr="1111111111111111" por="1111111111111111" />
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+    <sfr address="0x0234" access="0000000222222222" name="U2TXREG" mclr="0000000111111111" por="0000000000000000" />
+    <sfr address="0x0236" access="0000000111111111" name="U2RXREG" mclr="0000000111111111" por="0000000111111111" />
+    <sfr address="0x0238" access="3333333333333333" name="U2BRG" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0240" access="3030033305000011" name="SPI1STAT" mclr="1010011101000011" por="1010011101000011" />
+    <sfr address="0x0242" access="0003333333333333" name="SPI1CON1" mclr="0001111111111111" por="0001111111111111" />
+    <sfr address="0x0244" access="3330000000000033" name="SPI1CON2" mclr="1110000000000011" por="1110000000000011" />
+    <sfr address="0x0248" access="3333333333333333" name="SPI1BUF" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0260" access="3030033305000011" name="SPI2STAT" mclr="1010011101000011" por="1010011101000011" />
+    <sfr address="0x0262" access="0003333333333333" name="SPI2CON1" mclr="0001111111111111" por="0001111111111111" />
+    <sfr address="0x0264" access="3330000000000033" name="SPI2CON2" mclr="1110000000000011" por="1110000000000011" />
+    <sfr address="0x0268" access="3333333333333333" name="SPI2BUF" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x02C6" access="3333333333333333" name="TRISB" mclr="2222222222222222" por="2222222222222222" />
+    <sfr address="0x02C8" access="3333333333333333" name="PORTB" mclr="3333333333333333" por="0000000000000000" />
+    <sfr address="0x02CA" access="3333333333333333" name="LATB" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x02CC" access="3333000000000330" name="TRISC" mclr="2222000000000220" por="2222000000000220" />
+    <sfr address="0x02CE" access="3333000000000330" name="PORTC" mclr="3333000000000330" por="0000000000000000" />
+    <sfr address="0x02D0" access="3333000000000330" name="LATC" mclr="3333000000000330" por="1111000000000110" />
+    <sfr address="0x02D2" access="0000333333333333" name="TRISD" mclr="0000222222222222" por="0000222222222222" />
+    <sfr address="0x02D4" access="0000333333333333" name="PORTD" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x02D6" access="0000333333333333" name="LATD" mclr="0000333333333333" por="0000111111111111" />
+    <sfr address="0x06D2" access="0000333333333333" name="ODCD" mclr="0000333333333333" por="0000111111111111" />
+    <sfr address="0x02DE" access="0000000003333333" name="TRISF" mclr="0000000002222222" por="0000000002222222" />
+    <sfr address="0x02E0" access="0000000003333333" name="PORTF" mclr="0000000003333333" por="0000000000000000" />
+    <sfr address="0x02E2" access="0000000003333333" name="LATF" mclr="0000000003333333" por="0000000001111111" />
+    <sfr address="0x06DE" access="0000000003333333" name="ODCF" mclr="0000000003333333" por="0000000001111111" />
+    <sfr address="0x02E4" access="3333003333003333" name="TRISG" mclr="2222002222002222" por="2222002222002222" />
+    <sfr address="0x02E6" access="3333003333003333" name="PORTG" mclr="3333003333003333" por="0000000000000000" />
+    <sfr address="0x02E8" access="3333003333003333" name="LATG" mclr="3333003333003333" por="1111001111001111" />
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+    <sfr address="0x0302" access="0000111111111111" name="AD1BUF1" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0304" access="0000111111111111" name="AD1BUF2" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0306" access="0000111111111111" name="AD1BUF3" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0308" access="0000111111111111" name="AD1BUF4" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x030A" access="0000111111111111" name="AD1BUF5" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x030C" access="0000111111111111" name="AD1BUF6" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x030E" access="0000111111111111" name="AD1BUF7" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0310" access="0000111111111111" name="AD1BUF8" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0312" access="0000111111111111" name="AD1BUF9" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0314" access="0000111111111111" name="AD1BUFA" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0316" access="0000111111111111" name="AD1BUFB" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0318" access="0000111111111111" name="AD1BUFC" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031A" access="0000111111111111" name="AD1BUFD" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031C" access="0000111111111111" name="AD1BUFE" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031E" access="0000111111111111" name="AD1BUFF" mclr="0000333333333333" por="0000000000000000" />
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+    <sfr address="0x0326" access="0000033300000333" name="AD1CHS123" mclr="0000011100000111" por="0000011100000111" />
+    <sfr address="0x0328" access="3000333330003333" name="AD1CHS0" mclr="1000111110001111" por="1000111110001111" />
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+    <sfr address="0x0330" access="3333333333333333" name="AD1CSSL" mclr="1111111111111111" por="1111111111111111" />
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+    <sfr address="0x032E" access="0000000000000033" name="AD1CSSH" mclr="0000000000000011" por="0000000000000011" />
+    <sfr address="0x0380" access="3333300000330033" name="DMA0CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x0382" access="9000000003333333" name="DMA0REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x0384" access="3333333333333333" name="DMA0STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0386" access="3333333333333333" name="DMA0STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0388" access="3333333333333333" name="DMA0PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x038A" access="0000003333333333" name="DMA0CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x038C" access="3333300000330033" name="DMA1CON" mclr="1111100000110011" por="1111100000110011" />
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+    <sfr address="0x0390" access="3333333333333333" name="DMA1STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0392" access="3333333333333333" name="DMA1STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0394" access="3333333333333333" name="DMA1PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0396" access="0000003333333333" name="DMA1CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0398" access="3333300000330033" name="DMA2CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x039A" access="9000000003333333" name="DMA2REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x039C" access="3333333333333333" name="DMA2STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x039E" access="3333333333333333" name="DMA2STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A0" access="3333333333333333" name="DMA2PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A2" access="0000003333333333" name="DMA2CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A4" access="3333300000330033" name="DMA3CON" mclr="1111100000110011" por="1111100000110011" />
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+    <sfr address="0x03A8" access="3333333333333333" name="DMA3STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AA" access="3333333333333333" name="DMA3STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AC" access="3333333333333333" name="DMA3PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AE" access="0000003333333333" name="DMA3CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B0" access="3333300000330033" name="DMA4CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03B2" access="9000000003333333" name="DMA4REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03B4" access="3333333333333333" name="DMA4STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B6" access="3333333333333333" name="DMA4STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B8" access="3333333333333333" name="DMA4PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BA" access="0000003333333333" name="DMA4CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BC" access="3333300000330033" name="DMA5CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03BE" access="9000000003333333" name="DMA5REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03C0" access="3333333333333333" name="DMA5STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C2" access="3333333333333333" name="DMA5STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C4" access="3333333333333333" name="DMA5PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C6" access="0000003333333333" name="DMA5CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C8" access="3333300000330033" name="DMA6CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03CA" access="9000000003333333" name="DMA6REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03CC" access="3333333333333333" name="DMA6STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03CE" access="3333333333333333" name="DMA6STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D0" access="3333333333333333" name="DMA6PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D2" access="0000003333333333" name="DMA6CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D4" access="3333300000330033" name="DMA7CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03D6" access="9000000003333333" name="DMA7REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03D8" access="3333333333333333" name="DMA7STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DA" access="3333333333333333" name="DMA7STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DC" access="3333333333333333" name="DMA7PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DE" access="0000003333333333" name="DMA7CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E0" access="1111111111111111" name="DMACS0" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E2" access="0000111111111111" name="DMACS1" mclr="0000111111111111" por="0000111111111111" />
+    <sfr address="0x03E4" access="1111111111111111" name="DSADR" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0600" access="3033333333333333" name="PMPCON" mclr="1011111111111111" por="1011111111111111" />
+    <sfr address="0x0602" access="3333333333333333" name="PMPMODE" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0604" access="3333333333333333" name="PMPADDR" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0606" access="3333333333333333" name="PMPDATA1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0608" access="3333333333333333" name="PMPDATA2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060A" access="3333333333333333" name="PMPPE1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060C" access="3333333333333333" name="PMPPE2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0620" access="3333333333333333" name="ALRMVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0622" access="3333333333333333" name="ALRMCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0624" access="3333333333333333" name="RTCVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0626" access="3333333333333333" name="RTCCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0630" access="3033333333333333" name="CMCON" mclr="3033333333333333" por="1011111111111111" />
+    <sfr address="0x0632" access="0000000033333333" name="CVRCON" mclr="0000000033333333" por="0000000011111111" />
+    <sfr address="0x0740" access="3300000033333333" name="RCON" mclr="3300000033333333" por="1100000011111122" />
+    <sfr address="0x0742" access="0333033330303033" name="OSCCON" mclr="0555055510001111" por="0555055510001111" />
+    <sfr address="0x0744" access="3333333333333333" name="CLKDIV" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0746" access="0000000333333333" name="PLLFBD" mclr="0000000333333333" por="0000000111111111" />
+    <sfr address="0x0748" access="0000000000333333" name="OSCTRIM" mclr="0000000000333333" por="0000000000111111" />
+    <sfr address="0x0760" access="9330000003003333" name="NVMCON" mclr="1110000001001111" por="1110000001001111" />
+    <sfr address="0x0766" access="0000000022222222" name="NVMKEY" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0770" access="3333300333333003" name="PMD1" mclr="1111100111111001" por="1111100111111111" />
+    <sfr address="0x0772" access="3333333333333333" name="PMD2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0774" access="0000033300000030" name="PMD3" mclr="0000011100000010" por="0000011100000010" />
+  </device>
+  <device nb_banks="1" name="24HJ256GP210" >
+    <unused end="0x002D" start="0x0022" />
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+    <sfr address="0x038C" access="3333300000330033" name="DMA1CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x038E" access="9000000003333333" name="DMA1REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x0390" access="3333333333333333" name="DMA1STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0392" access="3333333333333333" name="DMA1STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0394" access="3333333333333333" name="DMA1PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0396" access="0000003333333333" name="DMA1CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0398" access="3333300000330033" name="DMA2CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x039A" access="9000000003333333" name="DMA2REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x039C" access="3333333333333333" name="DMA2STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x039E" access="3333333333333333" name="DMA2STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A0" access="3333333333333333" name="DMA2PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A2" access="0000003333333333" name="DMA2CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A4" access="3333300000330033" name="DMA3CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03A6" access="9000000003333333" name="DMA3REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03A8" access="3333333333333333" name="DMA3STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AA" access="3333333333333333" name="DMA3STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AC" access="3333333333333333" name="DMA3PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AE" access="0000003333333333" name="DMA3CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B0" access="3333300000330033" name="DMA4CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03B2" access="9000000003333333" name="DMA4REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03B4" access="3333333333333333" name="DMA4STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B6" access="3333333333333333" name="DMA4STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B8" access="3333333333333333" name="DMA4PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BA" access="0000003333333333" name="DMA4CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BC" access="3333300000330033" name="DMA5CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03BE" access="9000000003333333" name="DMA5REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03C0" access="3333333333333333" name="DMA5STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C2" access="3333333333333333" name="DMA5STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C4" access="3333333333333333" name="DMA5PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C6" access="0000003333333333" name="DMA5CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C8" access="3333300000330033" name="DMA6CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03CA" access="9000000003333333" name="DMA6REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03CC" access="3333333333333333" name="DMA6STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03CE" access="3333333333333333" name="DMA6STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D0" access="3333333333333333" name="DMA6PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D2" access="0000003333333333" name="DMA6CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D4" access="3333300000330033" name="DMA7CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03D6" access="9000000003333333" name="DMA7REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03D8" access="3333333333333333" name="DMA7STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DA" access="3333333333333333" name="DMA7STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DC" access="3333333333333333" name="DMA7PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DE" access="0000003333333333" name="DMA7CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E0" access="1111111111111111" name="DMACS0" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E2" access="0000111111111111" name="DMACS1" mclr="0000111111111111" por="0000111111111111" />
+    <sfr address="0x03E4" access="1111111111111111" name="DSADR" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0600" access="3033333333333333" name="PMPCON" mclr="1011111111111111" por="1011111111111111" />
+    <sfr address="0x0602" access="3333333333333333" name="PMPMODE" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0604" access="3333333333333333" name="PMPADDR" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0606" access="3333333333333333" name="PMPDATA1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0608" access="3333333333333333" name="PMPDATA2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060A" access="3333333333333333" name="PMPPE1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060C" access="3333333333333333" name="PMPPE2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0620" access="3333333333333333" name="ALRMVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0622" access="3333333333333333" name="ALRMCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0624" access="3333333333333333" name="RTCVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0626" access="3333333333333333" name="RTCCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0630" access="3033333333333333" name="CMCON" mclr="3033333333333333" por="1011111111111111" />
+    <sfr address="0x0632" access="0000000033333333" name="CVRCON" mclr="0000000033333333" por="0000000011111111" />
+    <sfr address="0x0740" access="3300000033333333" name="RCON" mclr="3300000033333333" por="1100000011111122" />
+    <sfr address="0x0742" access="0333033330303033" name="OSCCON" mclr="0555055510001111" por="0555055510001111" />
+    <sfr address="0x0744" access="3333333333333333" name="CLKDIV" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0746" access="0000000333333333" name="PLLFBD" mclr="0000000333333333" por="0000000111111111" />
+    <sfr address="0x0748" access="0000000000333333" name="OSCTRIM" mclr="0000000000333333" por="0000000000111111" />
+    <sfr address="0x0760" access="9330000003003333" name="NVMCON" mclr="1110000001001111" por="1110000001001111" />
+    <sfr address="0x0766" access="0000000022222222" name="NVMKEY" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0770" access="3333300333333003" name="PMD1" mclr="1111100111111001" por="1111100111111111" />
+    <sfr address="0x0772" access="3333333333333333" name="PMD2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0774" access="0000033300000030" name="PMD3" mclr="0000011100000010" por="0000011100000010" />
+  </device>
+  <device nb_banks="1" name="24HJ256GP610" >
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+    <sfr address="0x03D6" access="9000000003333333" name="DMA7REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03D8" access="3333333333333333" name="DMA7STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DA" access="3333333333333333" name="DMA7STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DC" access="3333333333333333" name="DMA7PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DE" access="0000003333333333" name="DMA7CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E0" access="1111111111111111" name="DMACS0" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E2" access="0000111111111111" name="DMACS1" mclr="0000111111111111" por="0000111111111111" />
+    <sfr address="0x03E4" access="1111111111111111" name="DSADR" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0600" access="3033333333333333" name="PMPCON" mclr="1011111111111111" por="1011111111111111" />
+    <sfr address="0x0602" access="3333333333333333" name="PMPMODE" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0604" access="3333333333333333" name="PMPADDR" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0606" access="3333333333333333" name="PMPDATA1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0608" access="3333333333333333" name="PMPDATA2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060A" access="3333333333333333" name="PMPPE1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060C" access="3333333333333333" name="PMPPE2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0620" access="3333333333333333" name="ALRMVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0622" access="3333333333333333" name="ALRMCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0624" access="3333333333333333" name="RTCVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0626" access="3333333333333333" name="RTCCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0630" access="3033333333333333" name="CMCON" mclr="3033333333333333" por="1011111111111111" />
+    <sfr address="0x0632" access="0000000033333333" name="CVRCON" mclr="0000000033333333" por="0000000011111111" />
+    <sfr address="0x0740" access="3300000033333333" name="RCON" mclr="3300000033333333" por="1100000011111122" />
+    <sfr address="0x0742" access="0333033330303033" name="OSCCON" mclr="0555055510001111" por="0555055510001111" />
+    <sfr address="0x0744" access="3333333333333333" name="CLKDIV" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0746" access="0000000333333333" name="PLLFBD" mclr="0000000333333333" por="0000000111111111" />
+    <sfr address="0x0748" access="0000000000333333" name="OSCTRIM" mclr="0000000000333333" por="0000000000111111" />
+    <sfr address="0x0760" access="9330000003003333" name="NVMCON" mclr="1110000001001111" por="1110000001001111" />
+    <sfr address="0x0766" access="0000000022222222" name="NVMKEY" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0770" access="3333300333333333" name="PMD1" mclr="1111100111111111" por="1111100111111111" />
+    <sfr address="0x0772" access="3333333333333333" name="PMD2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0774" access="0000033300000033" name="PMD3" mclr="0000011100000011" por="0000011100000011" />
+    <sfr address="0x0400" access="0033333311103003" name="C1CTRL1" mclr="1111121121111111" por="1111121121111111" />
+    <sfr address="0x0402" access="0000000000011111" name="C1CTRL2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0404" access="0001111101111111" name="C1VEC" mclr="1111111112111111" por="1111111112111111" />
+    <sfr address="0x0406" access="3330000000033333" name="C1FCTRL" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0408" access="0011111100111111" name="C1FIFO" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x040A" access="0011111155505555" name="C1INTF" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x040C" access="0000000033333333" name="C1INTE" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0410" access="0000000033333333" name="C1CFG1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0412" access="0300033333333333" name="C1CFG2" mclr="1011100000000000" por="1011100000000000" />
+    <sfr address="0x0414" access="3333333333333333" name="C1FEN1" mclr="1111111111222222" por="1111111111222222" />
+    <sfr address="0x0418" access="3333333333333333" name="C1FMSKSEL1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x041A" access="3333333333333333" name="C1FMSKSEL2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0420" access="5555555555555555" name="C1RXFUL1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0422" access="5555555555555555" name="C1RXFUL2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0424" access="3333333333333333" name="C1BUFPNT3" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0426" access="3333333333333333" name="C1BUFPNT4" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0428" access="5555555555555555" name="C1RXOVF1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x042A" access="5555555555555555" name="C1RXOVF2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0430" access="3111333331113333" name="C1TR01CON" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0432" access="3111333331113333" name="C1TR23CON" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0434" access="3111333331113333" name="C1TR45CON" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0436" access="3111333331113333" name="C1TR67CON" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0438" access="3333333333303033" name="C1RXM2SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x043A" access="3333333333333333" name="C1RXM2EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0440" access="3333333333303033" name="C1RXF0SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0442" access="3333333333333333" name="C1RXF0EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0444" access="3333333333303033" name="C1RXF1SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0446" access="3333333333333333" name="C1RXF1EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0448" access="3333333333303033" name="C1RXF2SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x044A" access="3333333333333333" name="C1RXF2EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x044C" access="3333333333303033" name="C1RXF3SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x044E" access="3333333333333333" name="C1RXF3EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0450" access="3333333333303033" name="C1RXF4SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0452" access="3333333333333333" name="C1RXF4EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0454" access="3333333333303033" name="C1RXF5SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0456" access="3333333333333333" name="C1RXF5EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0458" access="3333333333303033" name="C1RXF6SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x045A" access="3333333333333333" name="C1RXF6EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x045C" access="3333333333303033" name="C1RXF7SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x045E" access="3333333333333333" name="C1RXF7EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0460" access="3333333333303033" name="C1RXF8SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0462" access="3333333333333333" name="C1RXF8EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0464" access="3333333333303033" name="C1RXF9SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0466" access="3333333333333333" name="C1RXF9EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0468" access="3333333333303033" name="C1RXF10SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x046A" access="3333333333333333" name="C1RXF10EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x046C" access="3333333333303033" name="C1RXF11SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x046E" access="3333333333333333" name="C1RXF11EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0470" access="3333333333303033" name="C1RXF12SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0472" access="3333333333333333" name="C1RXF12EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0474" access="3333333333303033" name="C1RXF13SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0476" access="3333333333333333" name="C1RXF13EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0478" access="3333333333303033" name="C1RXF14SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x047A" access="3333333333333333" name="C1RXF14EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x047C" access="3333333333303033" name="C1RXF15SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x047E" access="3333333333333333" name="C1RXF15EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0500" access="0033333311103003" name="C2CTRL1" mclr="1111121121111111" por="1111121121111111" />
+    <sfr address="0x0502" access="0000000000011111" name="C2CTRL2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0504" access="0001111101111111" name="C2VEC" mclr="1111111112111111" por="1111111112111111" />
+    <sfr address="0x0506" access="3330000000033333" name="C2FCTRL" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0508" access="0011111100111111" name="C2FIFO" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x050A" access="0011111155505555" name="C2INTF" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x050C" access="0000000033333333" name="C2INTE" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0510" access="0000000033333333" name="C2CFG1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0512" access="0300033333333333" name="C2CFG2" mclr="1011100000000000" por="1011100000000000" />
+    <sfr address="0x0514" access="3333333333333333" name="C2FEN1" mclr="1111111111222222" por="1111111111222222" />
+    <sfr address="0x0518" access="3333333333333333" name="C2FMSKSEL1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x051A" access="3333333333333333" name="C2FMSKSEL2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0520" access="5555555555555555" name="C2RXFUL1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0522" access="5555555555555555" name="C2RXFUL2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0524" access="3333333333333333" name="C2BUFPNT3" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0526" access="3333333333333333" name="C2BUFPNT4" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0528" access="5555555555555555" name="C2RXOVF1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x052A" access="5555555555555555" name="C2RXOVF2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0530" access="3111333331113333" name="C2TR01CON" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0532" access="3111333331113333" name="C2TR23CON" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0534" access="3111333331113333" name="C2TR45CON" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0536" access="3111333331113333" name="C2TR67CON" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0538" access="3333333333303033" name="C2RXM2SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x053A" access="3333333333333333" name="C2RXM2EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0540" access="3333333333303033" name="C2RXF0SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0542" access="3333333333333333" name="C2RXF0EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0544" access="3333333333303033" name="C2RXF1SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0546" access="3333333333333333" name="C2RXF1EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0548" access="3333333333303033" name="C2RXF2SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x054A" access="3333333333333333" name="C2RXF2EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x054C" access="3333333333303033" name="C2RXF3SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x054E" access="3333333333333333" name="C2RXF3EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0550" access="3333333333303033" name="C2RXF4SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0552" access="3333333333333333" name="C2RXF4EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0554" access="3333333333303033" name="C2RXF5SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0556" access="3333333333333333" name="C2RXF5EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0558" access="3333333333303033" name="C2RXF6SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x055A" access="3333333333333333" name="C2RXF6EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x055C" access="3333333333303033" name="C2RXF7SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x055E" access="3333333333333333" name="C2RXF7EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0560" access="3333333333303033" name="C2RXF8SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0562" access="3333333333333333" name="C2RXF8EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0564" access="3333333333303033" name="C2RXF9SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0566" access="3333333333333333" name="C2RXF9EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0568" access="3333333333303033" name="C2RXF10SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x056A" access="3333333333333333" name="C2RXF10EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x056C" access="3333333333303033" name="C2RXF11SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x056E" access="3333333333333333" name="C2RXF11EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0570" access="3333333333303033" name="C2RXF12SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0572" access="3333333333333333" name="C2RXF12EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0574" access="3333333333303033" name="C2RXF13SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0576" access="3333333333333333" name="C2RXF13EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0578" access="3333333333303033" name="C2RXF14SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x057A" access="3333333333333333" name="C2RXF14EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x057C" access="3333333333303033" name="C2RXF15SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x057E" access="3333333333333333" name="C2RXF15EID" mclr="0000000000000000" por="0000000000000000" />
+  </device>
+  <device nb_banks="1" name="24HJ64GP206" >
+    <unused end="0x002D" start="0x0022" />
+    <unused end="0x0041" start="0x0038" />
+    <unused end="0x0051" start="0x0046" />
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+    <unused end="0x0247" start="0x0246" />
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+    <unused end="0x02C5" start="0x02C0" />
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+    <unused end="0x05FF" start="0x0500" />
+    <sfr address="0x0000" access="3333333333333333" name="WREG0" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0002" access="3333333333333333" name="WREG1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0004" access="3333333333333333" name="WREG2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0006" access="3333333333333333" name="WREG3" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0008" access="3333333333333333" name="WREG4" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x000A" access="3333333333333333" name="WREG5" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x000C" access="3333333333333333" name="WREG6" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x000E" access="3333333333333333" name="WREG7" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0010" access="3333333333333333" name="WREG8" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0012" access="3333333333333333" name="WREG9" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0014" access="3333333333333333" name="WREG10" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0016" access="3333333333333333" name="WREG11" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0018" access="3333333333333333" name="WREG12" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x001A" access="3333333333333333" name="WREG13" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x001C" access="3333333333333333" name="WREG14" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x001E" access="3333333333333330" name="WREG15" mclr="1111211111111111" por="1111211111111111" />
+    <sfr address="0x0020" access="3333333333333331" name="SPLIM" mclr="1111111111111111" por="1111111111111111" />
+    <combined address="0x002E" size="3" name="PC" />
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+    <sfr address="0x038E" access="9000000003333333" name="DMA1REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x0390" access="3333333333333333" name="DMA1STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0392" access="3333333333333333" name="DMA1STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0394" access="3333333333333333" name="DMA1PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0396" access="0000003333333333" name="DMA1CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0398" access="3333300000330033" name="DMA2CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x039A" access="9000000003333333" name="DMA2REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x039C" access="3333333333333333" name="DMA2STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x039E" access="3333333333333333" name="DMA2STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A0" access="3333333333333333" name="DMA2PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A2" access="0000003333333333" name="DMA2CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A4" access="3333300000330033" name="DMA3CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03A6" access="9000000003333333" name="DMA3REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03A8" access="3333333333333333" name="DMA3STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AA" access="3333333333333333" name="DMA3STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AC" access="3333333333333333" name="DMA3PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AE" access="0000003333333333" name="DMA3CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B0" access="3333300000330033" name="DMA4CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03B2" access="9000000003333333" name="DMA4REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03B4" access="3333333333333333" name="DMA4STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B6" access="3333333333333333" name="DMA4STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B8" access="3333333333333333" name="DMA4PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BA" access="0000003333333333" name="DMA4CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BC" access="3333300000330033" name="DMA5CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03BE" access="9000000003333333" name="DMA5REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03C0" access="3333333333333333" name="DMA5STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C2" access="3333333333333333" name="DMA5STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C4" access="3333333333333333" name="DMA5PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C6" access="0000003333333333" name="DMA5CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C8" access="3333300000330033" name="DMA6CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03CA" access="9000000003333333" name="DMA6REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03CC" access="3333333333333333" name="DMA6STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03CE" access="3333333333333333" name="DMA6STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D0" access="3333333333333333" name="DMA6PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D2" access="0000003333333333" name="DMA6CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D4" access="3333300000330033" name="DMA7CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03D6" access="9000000003333333" name="DMA7REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03D8" access="3333333333333333" name="DMA7STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DA" access="3333333333333333" name="DMA7STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DC" access="3333333333333333" name="DMA7PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DE" access="0000003333333333" name="DMA7CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E0" access="1111111111111111" name="DMACS0" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E2" access="0000111111111111" name="DMACS1" mclr="0000111111111111" por="0000111111111111" />
+    <sfr address="0x03E4" access="1111111111111111" name="DSADR" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0600" access="3033333333333333" name="PMPCON" mclr="1011111111111111" por="1011111111111111" />
+    <sfr address="0x0602" access="3333333333333333" name="PMPMODE" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0604" access="3333333333333333" name="PMPADDR" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0606" access="3333333333333333" name="PMPDATA1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0608" access="3333333333333333" name="PMPDATA2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060A" access="3333333333333333" name="PMPPE1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060C" access="3333333333333333" name="PMPPE2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0620" access="3333333333333333" name="ALRMVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0622" access="3333333333333333" name="ALRMCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0624" access="3333333333333333" name="RTCVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0626" access="3333333333333333" name="RTCCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0630" access="3033333333333333" name="CMCON" mclr="3033333333333333" por="1011111111111111" />
+    <sfr address="0x0632" access="0000000033333333" name="CVRCON" mclr="0000000033333333" por="0000000011111111" />
+    <sfr address="0x0740" access="3300000033333333" name="RCON" mclr="3300000033333333" por="1100000011111122" />
+    <sfr address="0x0742" access="0333033330303033" name="OSCCON" mclr="0555055510001111" por="0555055510001111" />
+    <sfr address="0x0744" access="3333333333333333" name="CLKDIV" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0746" access="0000000333333333" name="PLLFBD" mclr="0000000333333333" por="0000000111111111" />
+    <sfr address="0x0748" access="0000000000333333" name="OSCTRIM" mclr="0000000000333333" por="0000000000111111" />
+    <sfr address="0x0760" access="9330000003003333" name="NVMCON" mclr="1110000001001111" por="1110000001001111" />
+    <sfr address="0x0766" access="0000000022222222" name="NVMKEY" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0770" access="3333300333333003" name="PMD1" mclr="1111100111111001" por="1111100111111111" />
+    <sfr address="0x0772" access="3333333333333333" name="PMD2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0774" access="0000033300000000" name="PMD3" mclr="0000011100000000" por="0000011100000000" />
+  </device>
+  <device nb_banks="1" name="24HJ64GP210" >
+    <unused end="0x002D" start="0x0022" />
+    <unused end="0x0041" start="0x0038" />
+    <unused end="0x0051" start="0x0046" />
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+    <unused end="0x05FF" start="0x0500" />
+    <sfr address="0x0000" access="3333333333333333" name="WREG0" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0002" access="3333333333333333" name="WREG1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0004" access="3333333333333333" name="WREG2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0006" access="3333333333333333" name="WREG3" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0008" access="3333333333333333" name="WREG4" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x000A" access="3333333333333333" name="WREG5" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x000C" access="3333333333333333" name="WREG6" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x000E" access="3333333333333333" name="WREG7" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0010" access="3333333333333333" name="WREG8" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0012" access="3333333333333333" name="WREG9" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0014" access="3333333333333333" name="WREG10" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0016" access="3333333333333333" name="WREG11" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0018" access="3333333333333333" name="WREG12" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x001A" access="3333333333333333" name="WREG13" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x001C" access="3333333333333333" name="WREG14" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x001E" access="3333333333333330" name="WREG15" mclr="1111211111111111" por="1111211111111111" />
+    <sfr address="0x0020" access="3333333333333331" name="SPLIM" mclr="1111111111111111" por="1111111111111111" />
+    <combined address="0x002E" size="3" name="PC" />
+    <sfr address="0x002E" access="1111111111111111" name="PCL" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0030" access="0000000001111111" name="PCH" mclr="0000000001111111" por="0000000001111111" />
+    <sfr address="0x0032" access="0000000033333333" name="TBLPAG" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0034" access="0000000033333333" name="PSVPAG" mclr="0000000011111111" por="0000000011111111" />
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+    <sfr address="0x0042" access="0000000333313333" name="SR" mclr="0000000111111111" por="0000000111111111" />
+    <sfr address="0x0044" access="0000000000005300" name="CORCON" mclr="0000000000001100" por="0000000000001100" />
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+    <sfr address="0x0244" access="3330000000000033" name="SPI1CON2" mclr="1110000000000011" por="1110000000000011" />
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+    <sfr address="0x0262" access="0003333333333333" name="SPI2CON1" mclr="0001111111111111" por="0001111111111111" />
+    <sfr address="0x0264" access="3330000000000033" name="SPI2CON2" mclr="1110000000000011" por="1110000000000011" />
+    <sfr address="0x0268" access="3333333333333333" name="SPI2BUF" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x02C0" access="3333033033333333" name="TRISA" mclr="2222022022222222" por="2222022022222222" />
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+    <sfr address="0x02C8" access="3333333333333333" name="PORTB" mclr="3333333333333333" por="0000000000000000" />
+    <sfr address="0x02CA" access="3333333333333333" name="LATB" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x02CC" access="3333000000033330" name="TRISC" mclr="2222000000022220" por="2222000000022220" />
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+    <sfr address="0x02D0" access="3333000000033330" name="LATC" mclr="3333000000033330" por="1111000000011110" />
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+    <sfr address="0x02D4" access="3333333333333333" name="PORTD" mclr="3333333333333333" por="0000000000000000" />
+    <sfr address="0x02D6" access="3333333333333333" name="LATD" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x06D2" access="3333333333333333" name="ODCD" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x02D8" access="0000000033333333" name="TRISE" mclr="0000000022222222" por="0000000022222222" />
+    <sfr address="0x02DA" access="0000000033333333" name="PORTE" mclr="0000000033333333" por="0000000000000000" />
+    <sfr address="0x02DC" access="0000000033333333" name="LATE" mclr="0000000033333333" por="0000000011111111" />
+    <sfr address="0x02DE" access="0033000333333333" name="TRISF" mclr="0022000222222222" por="0022000222222222" />
+    <sfr address="0x02E0" access="0033000333333333" name="PORTF" mclr="0033000333333333" por="0000000000000000" />
+    <sfr address="0x02E2" access="0033000333333333" name="LATF" mclr="0033000333333333" por="0011000111111111" />
+    <sfr address="0x06DE" access="0033000333333333" name="ODCF" mclr="0033000333333333" por="0011000111111111" />
+    <sfr address="0x02E4" access="3333003333003333" name="TRISG" mclr="2222002222002222" por="2222002222002222" />
+    <sfr address="0x02E6" access="3333003333003333" name="PORTG" mclr="3333003333003333" por="0000000000000000" />
+    <sfr address="0x02E8" access="3333003333003333" name="LATG" mclr="3333003333003333" por="1111001111001111" />
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+    <sfr address="0x0302" access="0000111111111111" name="AD1BUF1" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0304" access="0000111111111111" name="AD1BUF2" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0306" access="0000111111111111" name="AD1BUF3" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0308" access="0000111111111111" name="AD1BUF4" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x030A" access="0000111111111111" name="AD1BUF5" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x030C" access="0000111111111111" name="AD1BUF6" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x030E" access="0000111111111111" name="AD1BUF7" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0310" access="0000111111111111" name="AD1BUF8" mclr="0000333333333333" por="0000000000000000" />
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+    <sfr address="0x0314" access="0000111111111111" name="AD1BUFA" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0316" access="0000111111111111" name="AD1BUFB" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0318" access="0000111111111111" name="AD1BUFC" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031A" access="0000111111111111" name="AD1BUFD" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031C" access="0000111111111111" name="AD1BUFE" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031E" access="0000111111111111" name="AD1BUFF" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0320" access="3030003333303335" name="AD1CON1" mclr="1010001111100111" por="1010001111100111" />
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+    <sfr address="0x0326" access="0000033300000333" name="AD1CHS123" mclr="0000011100000111" por="0000011100000111" />
+    <sfr address="0x0328" access="3000333330003333" name="AD1CHS0" mclr="1000111110001111" por="1000111110001111" />
+    <sfr address="0x032C" access="3333333333333333" name="AD1PCFGL" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0330" access="3333333333333333" name="AD1CSSL" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x032A" access="3333333333333333" name="AD1PCFGH" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x032E" access="3333333333333333" name="AD1CSSH" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0380" access="3333300000330033" name="DMA0CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x0382" access="9000000003333333" name="DMA0REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x0384" access="3333333333333333" name="DMA0STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0386" access="3333333333333333" name="DMA0STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0388" access="3333333333333333" name="DMA0PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x038A" access="0000003333333333" name="DMA0CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x038C" access="3333300000330033" name="DMA1CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x038E" access="9000000003333333" name="DMA1REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x0390" access="3333333333333333" name="DMA1STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0392" access="3333333333333333" name="DMA1STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0394" access="3333333333333333" name="DMA1PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0396" access="0000003333333333" name="DMA1CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0398" access="3333300000330033" name="DMA2CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x039A" access="9000000003333333" name="DMA2REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x039C" access="3333333333333333" name="DMA2STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x039E" access="3333333333333333" name="DMA2STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A0" access="3333333333333333" name="DMA2PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A2" access="0000003333333333" name="DMA2CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A4" access="3333300000330033" name="DMA3CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03A6" access="9000000003333333" name="DMA3REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03A8" access="3333333333333333" name="DMA3STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AA" access="3333333333333333" name="DMA3STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AC" access="3333333333333333" name="DMA3PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AE" access="0000003333333333" name="DMA3CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B0" access="3333300000330033" name="DMA4CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03B2" access="9000000003333333" name="DMA4REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03B4" access="3333333333333333" name="DMA4STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B6" access="3333333333333333" name="DMA4STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B8" access="3333333333333333" name="DMA4PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BA" access="0000003333333333" name="DMA4CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BC" access="3333300000330033" name="DMA5CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03BE" access="9000000003333333" name="DMA5REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03C0" access="3333333333333333" name="DMA5STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C2" access="3333333333333333" name="DMA5STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C4" access="3333333333333333" name="DMA5PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C6" access="0000003333333333" name="DMA5CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C8" access="3333300000330033" name="DMA6CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03CA" access="9000000003333333" name="DMA6REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03CC" access="3333333333333333" name="DMA6STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03CE" access="3333333333333333" name="DMA6STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D0" access="3333333333333333" name="DMA6PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D2" access="0000003333333333" name="DMA6CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D4" access="3333300000330033" name="DMA7CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03D6" access="9000000003333333" name="DMA7REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03D8" access="3333333333333333" name="DMA7STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DA" access="3333333333333333" name="DMA7STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DC" access="3333333333333333" name="DMA7PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DE" access="0000003333333333" name="DMA7CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E0" access="1111111111111111" name="DMACS0" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E2" access="0000111111111111" name="DMACS1" mclr="0000111111111111" por="0000111111111111" />
+    <sfr address="0x03E4" access="1111111111111111" name="DSADR" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0600" access="3033333333333333" name="PMPCON" mclr="1011111111111111" por="1011111111111111" />
+    <sfr address="0x0602" access="3333333333333333" name="PMPMODE" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0604" access="3333333333333333" name="PMPADDR" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0606" access="3333333333333333" name="PMPDATA1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0608" access="3333333333333333" name="PMPDATA2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060A" access="3333333333333333" name="PMPPE1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060C" access="3333333333333333" name="PMPPE2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0620" access="3333333333333333" name="ALRMVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0622" access="3333333333333333" name="ALRMCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0624" access="3333333333333333" name="RTCVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0626" access="3333333333333333" name="RTCCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0630" access="3033333333333333" name="CMCON" mclr="3033333333333333" por="1011111111111111" />
+    <sfr address="0x0632" access="0000000033333333" name="CVRCON" mclr="0000000033333333" por="0000000011111111" />
+    <sfr address="0x0740" access="3300000033333333" name="RCON" mclr="3300000033333333" por="1100000011111122" />
+    <sfr address="0x0742" access="0333033330303033" name="OSCCON" mclr="0555055510001111" por="0555055510001111" />
+    <sfr address="0x0744" access="3333333333333333" name="CLKDIV" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0746" access="0000000333333333" name="PLLFBD" mclr="0000000333333333" por="0000000111111111" />
+    <sfr address="0x0748" access="0000000000333333" name="OSCTRIM" mclr="0000000000333333" por="0000000000111111" />
+    <sfr address="0x0760" access="9330000003003333" name="NVMCON" mclr="1110000001001111" por="1110000001001111" />
+    <sfr address="0x0766" access="0000000022222222" name="NVMKEY" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0770" access="3333300333333003" name="PMD1" mclr="1111100111111001" por="1111100111111111" />
+    <sfr address="0x0772" access="3333333333333333" name="PMD2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0774" access="0000033300000030" name="PMD3" mclr="0000011100000010" por="0000011100000010" />
+  </device>
+  <device nb_banks="1" name="24HJ64GP506" >
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+  </device>
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+    <sfr address="0x02DC" access="0000000033333333" name="LATE" mclr="0000000033333333" por="0000000011111111" />
+    <sfr address="0x02DE" access="0033000333333333" name="TRISF" mclr="0022000222222222" por="0022000222222222" />
+    <sfr address="0x02E0" access="0033000333333333" name="PORTF" mclr="0033000333333333" por="0000000000000000" />
+    <sfr address="0x02E2" access="0033000333333333" name="LATF" mclr="0033000333333333" por="0011000111111111" />
+    <sfr address="0x06DE" access="0033000333333333" name="ODCF" mclr="0033000333333333" por="0011000111111111" />
+    <sfr address="0x02E4" access="3333003333003333" name="TRISG" mclr="2222002222002222" por="2222002222002222" />
+    <sfr address="0x02E6" access="3333003333003333" name="PORTG" mclr="3333003333003333" por="0000000000000000" />
+    <sfr address="0x02E8" access="3333003333003333" name="LATG" mclr="3333003333003333" por="1111001111001111" />
+    <sfr address="0x0300" access="0000111111111111" name="AD1BUF0" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0302" access="0000111111111111" name="AD1BUF1" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0304" access="0000111111111111" name="AD1BUF2" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0306" access="0000111111111111" name="AD1BUF3" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0308" access="0000111111111111" name="AD1BUF4" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x030A" access="0000111111111111" name="AD1BUF5" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x030C" access="0000111111111111" name="AD1BUF6" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x030E" access="0000111111111111" name="AD1BUF7" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0310" access="0000111111111111" name="AD1BUF8" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0312" access="0000111111111111" name="AD1BUF9" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0314" access="0000111111111111" name="AD1BUFA" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0316" access="0000111111111111" name="AD1BUFB" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0318" access="0000111111111111" name="AD1BUFC" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031A" access="0000111111111111" name="AD1BUFD" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031C" access="0000111111111111" name="AD1BUFE" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x031E" access="0000111111111111" name="AD1BUFF" mclr="0000333333333333" por="0000000000000000" />
+    <sfr address="0x0320" access="3030003333303335" name="AD1CON1" mclr="1010001111100111" por="1010001111100111" />
+    <sfr address="0x0322" access="3333033310333333" name="AD1CON2" mclr="1111011110111111" por="1111011110111111" />
+    <sfr address="0x0324" access="0003333330333333" name="AD1CON3" mclr="0001111110111111" por="0001111110111111" />
+    <sfr address="0x0332" access="0000000000000333" name="AD1CON4" mclr="0000000000000111" por="0000000000000111" />
+    <sfr address="0x0326" access="0000033300000333" name="AD1CHS123" mclr="0000011100000111" por="0000011100000111" />
+    <sfr address="0x0328" access="3000333330003333" name="AD1CHS0" mclr="1000111110001111" por="1000111110001111" />
+    <sfr address="0x032C" access="3333333333333333" name="AD1PCFGL" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0330" access="3333333333333333" name="AD1CSSL" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x032A" access="3333333333333333" name="AD1PCFGH" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x032E" access="3333333333333333" name="AD1CSSH" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0380" access="3333300000330033" name="DMA0CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x0382" access="9000000003333333" name="DMA0REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x0384" access="3333333333333333" name="DMA0STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0386" access="3333333333333333" name="DMA0STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0388" access="3333333333333333" name="DMA0PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x038A" access="0000003333333333" name="DMA0CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x038C" access="3333300000330033" name="DMA1CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x038E" access="9000000003333333" name="DMA1REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x0390" access="3333333333333333" name="DMA1STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0392" access="3333333333333333" name="DMA1STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0394" access="3333333333333333" name="DMA1PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0396" access="0000003333333333" name="DMA1CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0398" access="3333300000330033" name="DMA2CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x039A" access="9000000003333333" name="DMA2REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x039C" access="3333333333333333" name="DMA2STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x039E" access="3333333333333333" name="DMA2STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A0" access="3333333333333333" name="DMA2PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A2" access="0000003333333333" name="DMA2CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03A4" access="3333300000330033" name="DMA3CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03A6" access="9000000003333333" name="DMA3REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03A8" access="3333333333333333" name="DMA3STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AA" access="3333333333333333" name="DMA3STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AC" access="3333333333333333" name="DMA3PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03AE" access="0000003333333333" name="DMA3CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B0" access="3333300000330033" name="DMA4CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03B2" access="9000000003333333" name="DMA4REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03B4" access="3333333333333333" name="DMA4STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B6" access="3333333333333333" name="DMA4STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03B8" access="3333333333333333" name="DMA4PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BA" access="0000003333333333" name="DMA4CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03BC" access="3333300000330033" name="DMA5CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03BE" access="9000000003333333" name="DMA5REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03C0" access="3333333333333333" name="DMA5STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C2" access="3333333333333333" name="DMA5STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C4" access="3333333333333333" name="DMA5PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C6" access="0000003333333333" name="DMA5CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03C8" access="3333300000330033" name="DMA6CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03CA" access="9000000003333333" name="DMA6REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03CC" access="3333333333333333" name="DMA6STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03CE" access="3333333333333333" name="DMA6STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D0" access="3333333333333333" name="DMA6PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D2" access="0000003333333333" name="DMA6CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03D4" access="3333300000330033" name="DMA7CON" mclr="1111100000110011" por="1111100000110011" />
+    <sfr address="0x03D6" access="9000000003333333" name="DMA7REQ" mclr="1000000002222222" por="1000000002222222" />
+    <sfr address="0x03D8" access="3333333333333333" name="DMA7STA" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DA" access="3333333333333333" name="DMA7STB" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DC" access="3333333333333333" name="DMA7PAD" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03DE" access="0000003333333333" name="DMA7CNT" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E0" access="1111111111111111" name="DMACS0" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x03E2" access="0000111111111111" name="DMACS1" mclr="0000111111111111" por="0000111111111111" />
+    <sfr address="0x03E4" access="1111111111111111" name="DSADR" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0600" access="3033333333333333" name="PMPCON" mclr="1011111111111111" por="1011111111111111" />
+    <sfr address="0x0602" access="3333333333333333" name="PMPMODE" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0604" access="3333333333333333" name="PMPADDR" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0606" access="3333333333333333" name="PMPDATA1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0608" access="3333333333333333" name="PMPDATA2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060A" access="3333333333333333" name="PMPPE1" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x060C" access="3333333333333333" name="PMPPE2" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0620" access="3333333333333333" name="ALRMVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0622" access="3333333333333333" name="ALRMCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0624" access="3333333333333333" name="RTCVAL" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0626" access="3333333333333333" name="RTCCFG" mclr="3333333333333333" por="1111111111111111" />
+    <sfr address="0x0630" access="3033333333333333" name="CMCON" mclr="3033333333333333" por="1011111111111111" />
+    <sfr address="0x0632" access="0000000033333333" name="CVRCON" mclr="0000000033333333" por="0000000011111111" />
+    <sfr address="0x0740" access="3300000033333333" name="RCON" mclr="3300000033333333" por="1100000011111122" />
+    <sfr address="0x0742" access="0333033330303033" name="OSCCON" mclr="0555055510001111" por="0555055510001111" />
+    <sfr address="0x0744" access="3333333333333333" name="CLKDIV" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0746" access="0000000333333333" name="PLLFBD" mclr="0000000333333333" por="0000000111111111" />
+    <sfr address="0x0748" access="0000000000333333" name="OSCTRIM" mclr="0000000000333333" por="0000000000111111" />
+    <sfr address="0x0760" access="9330000003003333" name="NVMCON" mclr="1110000001001111" por="1110000001001111" />
+    <sfr address="0x0766" access="0000000022222222" name="NVMKEY" mclr="0000000011111111" por="0000000011111111" />
+    <sfr address="0x0770" access="3333300333333033" name="PMD1" mclr="1111100111111011" por="1111100111111111" />
+    <sfr address="0x0772" access="3333333333333333" name="PMD2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0774" access="0000033300000000" name="PMD3" mclr="0000011100000000" por="0000011100000000" />
+    <sfr address="0x0400" access="0033333311103003" name="C1CTRL1" mclr="1111121121111111" por="1111121121111111" />
+    <sfr address="0x0402" access="0000000000011111" name="C1CTRL2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0404" access="0001111101111111" name="C1VEC" mclr="1111111112111111" por="1111111112111111" />
+    <sfr address="0x0406" access="3330000000033333" name="C1FCTRL" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0408" access="0011111100111111" name="C1FIFO" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x040A" access="0011111155505555" name="C1INTF" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x040C" access="0000000033333333" name="C1INTE" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0410" access="0000000033333333" name="C1CFG1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0412" access="0300033333333333" name="C1CFG2" mclr="1011100000000000" por="1011100000000000" />
+    <sfr address="0x0414" access="3333333333333333" name="C1FEN1" mclr="1111111111222222" por="1111111111222222" />
+    <sfr address="0x0418" access="3333333333333333" name="C1FMSKSEL1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x041A" access="3333333333333333" name="C1FMSKSEL2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0420" access="5555555555555555" name="C1RXFUL1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0422" access="5555555555555555" name="C1RXFUL2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0424" access="3333333333333333" name="C1BUFPNT3" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0426" access="3333333333333333" name="C1BUFPNT4" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0428" access="5555555555555555" name="C1RXOVF1" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x042A" access="5555555555555555" name="C1RXOVF2" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0430" access="3111333331113333" name="C1TR01CON" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0432" access="3111333331113333" name="C1TR23CON" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0434" access="3111333331113333" name="C1TR45CON" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0436" access="3111333331113333" name="C1TR67CON" mclr="1111111111111111" por="1111111111111111" />
+    <sfr address="0x0438" access="3333333333303033" name="C1RXM2SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x043A" access="3333333333333333" name="C1RXM2EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0440" access="3333333333303033" name="C1RXF0SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0442" access="3333333333333333" name="C1RXF0EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0444" access="3333333333303033" name="C1RXF1SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0446" access="3333333333333333" name="C1RXF1EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0448" access="3333333333303033" name="C1RXF2SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x044A" access="3333333333333333" name="C1RXF2EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x044C" access="3333333333303033" name="C1RXF3SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x044E" access="3333333333333333" name="C1RXF3EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0450" access="3333333333303033" name="C1RXF4SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0452" access="3333333333333333" name="C1RXF4EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0454" access="3333333333303033" name="C1RXF5SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0456" access="3333333333333333" name="C1RXF5EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0458" access="3333333333303033" name="C1RXF6SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x045A" access="3333333333333333" name="C1RXF6EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x045C" access="3333333333303033" name="C1RXF7SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x045E" access="3333333333333333" name="C1RXF7EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0460" access="3333333333303033" name="C1RXF8SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0462" access="3333333333333333" name="C1RXF8EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0464" access="3333333333303033" name="C1RXF9SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0466" access="3333333333333333" name="C1RXF9EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0468" access="3333333333303033" name="C1RXF10SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x046A" access="3333333333333333" name="C1RXF10EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x046C" access="3333333333303033" name="C1RXF11SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x046E" access="3333333333333333" name="C1RXF11EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0470" access="3333333333303033" name="C1RXF12SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0472" access="3333333333333333" name="C1RXF12EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0474" access="3333333333303033" name="C1RXF13SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x0476" access="3333333333333333" name="C1RXF13EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x0478" access="3333333333303033" name="C1RXF14SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x047A" access="3333333333333333" name="C1RXF14EID" mclr="0000000000000000" por="0000000000000000" />
+    <sfr address="0x047C" access="3333333333303033" name="C1RXF15SID" mclr="0000000000010100" por="0000000000010100" />
+    <sfr address="0x047E" access="3333333333333333" name="C1RXF15EID" mclr="0000000000000000" por="0000000000000000" />
+  </device>
+</registers>
diff --git a/src/devices/pic/xml_data/registers/registers_missing.xml b/src/devices/pic/xml_data/registers/registers_missing.xml
new file mode 100644
index 0000000..b6e3173
--- /dev/null
+++ b/src/devices/pic/xml_data/registers/registers_missing.xml
@@ -0,0 +1,59 @@
+<!-- ************************************************************************* -->
+<!-- * Copyright (C) 2006 Nicolas Hadacek <hadacek@kde.org>                  * -->
+<!-- *                                                                       * -->
+<!-- * This program is free software; you can redistribute it and/or modify  * -->
+<!-- * it under the terms of the GNU General Public License as published by  * -->
+<!-- * the Free Software Foundation; either version 2 of the License, or     * -->
+<!-- * (at your option) any later version.                                   * -->
+<!-- *************************************************************************/-->
+<!DOCTYPE piklab>
+<registers>
+  <device name="16C52"   same_as="16C54" />
+  <device name="16C54A"  same_as="16C54" />
+  <device name="16C54B"  same_as="16C54" />
+  <device name="16CR54B" same_as="16C54" />
+  <device name="16CR57B" same_as="16C57" />
+  <device name="16CR58A" same_as="16C58A" />
+  <device nb_banks="2" name="16C61" >
+    <mirror>
+      <range end="0x0000" start="0x0000" />
+      <range end="0x0080" start="0x0080" />
+    </mirror>
+    <mirror>
+      <range end="0x0004" start="0x0002" />
+      <range end="0x0084" start="0x0082" />
+    </mirror>
+    <mirror>
+      <range end="0x000B" start="0x000A" />
+      <range end="0x008B" start="0x008A" />
+    </mirror>
+    <unused end="0x0009" start="0x0007" />
+    <unused end="0x007F" start="0x0030" />
+    <unused end="0x0089" start="0x0087" />
+    <unused end="0x00FF" start="0x00B0" />
+    <sfr address="0x0000" access="00000000" name="INDF" mclr="00000000" por="00000000" />
+    <sfr address="0x0001" access="33333333" name="TMR0" mclr="33333333" por="00000000" />
+    <sfr address="0x0002" access="33333333" name="PCL" mclr="11111111" por="11111111" />
+    <sfr address="0x0003" access="11311333" name="STATUS" mclr="11144333" por="11122000" />
+    <sfr address="0x0004" access="33333333" name="FSR" mclr="33333333" por="00000000" />
+    <sfr address="0x0005" access="00033333" name="PORTA" mclr="00033333" por="00000000" />
+    <sfr address="0x0006" access="33333333" name="PORTB" mclr="33333333" por="00000000" />
+    <sfr address="0x000A" access="00033333" name="PCLATH" mclr="00011111" por="00011111" />
+    <sfr address="0x000B" access="33333333" name="INTCON" mclr="11111113" por="11111110" />
+    <sfr address="0x0081" access="33333333" name="OPTION_REG" mclr="22222222" por="22222222" />
+    <sfr address="0x0085" access="00033333" name="TRISA" mclr="00022222" por="00022222" />
+    <sfr address="0x0086" access="33333333" name="TRISB" mclr="22222222" por="22222222" />
+  </device>
+  <device name="16C62"  same_as="16C62A" />
+  <device name="16C64"  same_as="16C64A" />
+  <device name="16C65"  same_as="16C65A" />
+  <device name="16C73"  same_as="16C73A" />
+  <device name="16CR73" same_as="16F73"  />
+  <device name="16C74"  same_as="16C74A" />
+  <device name="16CR74" same_as="16F74"  />
+  <device name="16CR76" same_as="16F76"  />
+  <device name="16CR77" same_as="16F77"  />
+  <device name="16C84"  same_as="16CR84" />
+  <device name="12HV615"  same_as="12F615" />
+  <device name="16HV615"  same_as="16F615" />
+</registers>
diff --git a/src/devices/pic/xml_data/validate.sh b/src/devices/pic/xml_data/validate.sh
new file mode 100755
index 0000000..20dbe5e
--- /dev/null
+++ b/src/devices/pic/xml_data/validate.sh
@@ -0,0 +1,5 @@
+cd validate
+make
+cd ..
+validate/validate $1
+
diff --git a/src/devices/pic/xml_data/validate/Makefile b/src/devices/pic/xml_data/validate/Makefile
new file mode 100644
index 0000000..d235259
--- /dev/null
+++ b/src/devices/pic/xml_data/validate/Makefile
@@ -0,0 +1,4 @@
+all: validate
+
+validate: validate.cpp
+	g++ -o validate -lxerces-c validate.cpp
diff --git a/src/devices/pic/xml_data/validate/validate.cpp b/src/devices/pic/xml_data/validate/validate.cpp
new file mode 100644
index 0000000..7e733b0
--- /dev/null
+++ b/src/devices/pic/xml_data/validate/validate.cpp
@@ -0,0 +1,72 @@
+// Necessary includes. We refer to these as "common includes" 
+// in the following examples.
+#include <xercesc/sax2/XMLReaderFactory.hpp>
+#include <xercesc/sax2/SAX2XMLReader.hpp>
+#include <xercesc/sax2/DefaultHandler.hpp>
+
+// Handy definitions of constants.
+#include <xercesc/util/XMLUni.hpp>
+
+#include <iostream>
+
+using namespace std;
+XERCES_CPP_NAMESPACE_USE
+
+class Handler : public DefaultHandler
+{
+public:
+  virtual void  error (const SAXParseException &exc) {
+    char* message = XMLString::transcode(exc.getMessage());
+    cout << "Exception: " << message << "\n";
+    XMLString::release(&message);
+  }
+  virtual void fatalError (const SAXParseException &exc) {
+    char* message = XMLString::transcode(exc.getMessage());
+    cout << "Exception: " << message << "\n";
+    XMLString::release(&message);
+  }
+};
+
+int main(int argc, char* argv[])
+{
+XMLPlatformUtils::Initialize();
+
+// Create a SAX2 parser object.
+SAX2XMLReader* parser = XMLReaderFactory::createXMLReader();
+
+// Set the appropriate features on the parser.
+// Enable namespaces, schema validation, and the checking 
+// of all Schema constraints.
+// We refer to these as "common features" in following examples.
+parser->setFeature(XMLUni::fgSAX2CoreNameSpaces, true);
+parser->setFeature(XMLUni::fgSAX2CoreValidation, true);
+parser->setFeature(XMLUni::fgXercesDynamic, false);
+parser->setFeature(XMLUni::fgXercesSchema, true);
+parser->setFeature(XMLUni::fgXercesSchemaFullChecking, true);
+//parser->setProperty(XMLUni::fgXercesSchemaExternalNoNameSpaceSchemaLocation, (void *)"pic.xsd");
+
+// Set appropriate ContentHandler, ErrorHandler, and EntityResolver.
+// These will be referred to as "common handlers" in subsequent examples.
+
+// You will use a default handler provided by Xerces-C++ (no op action).
+// Users should write their own handlers and install them.
+Handler handler;
+parser->setContentHandler(&handler);
+
+// The object parser calls when it detects violations of the schema.
+parser->setErrorHandler(&handler);
+
+// The object parser calls to find the schema and 
+// resolve schema imports/includes.
+parser->setEntityResolver(&handler);
+
+// Parse the XML document.
+// Document content sent to registered ContentHandler instance.
+if ( argc==1 ) { printf("Needs one argument\n"); return -1; }
+parser->parse(argv[1]);
+
+// Delete the parser instance.
+delete parser;
+
+return 0;
+}
diff --git a/src/devices/pic/xml_data/xml_data.pro b/src/devices/pic/xml_data/xml_data.pro
new file mode 100644
index 0000000..086bf53
--- /dev/null
+++ b/src/devices/pic/xml_data/xml_data.pro
@@ -0,0 +1,5 @@
+STOPDIR = ../../../..
+include($${STOPDIR}/lib.pro)
+
+TARGET   = picxml
+SOURCES += pic_data.cpp