summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorTimothy Pearson <kb9vqf@pearsoncomputing.net>2013-10-30 14:36:28 -0500
committerTimothy Pearson <kb9vqf@pearsoncomputing.net>2013-10-30 14:36:28 -0500
commit26c1236cdc377dcdbbe91e565e692316775e5c54 (patch)
tree2cb71bb1f1d3c28aec2a2635b8f3a3da9274fbd1
parent5c2d024b38ebfd6e0bd4c559ba45aa516ab275f2 (diff)
downloadulab-26c1236cdc377dcdbbe91e565e692316775e5c54.tar.gz
ulab-26c1236cdc377dcdbbe91e565e692316775e5c54.zip
Fix prior commit
-rw-r--r--fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v
index 9f37f9d..b852a6d 100644
--- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v
+++ b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v
@@ -296,7 +296,7 @@ module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done);
output reg done;
reg prev_enable;
- reg [(IMAGE_RAM_ADDR_BITS-1):0] counter;
+ reg [IMAGE_RAM_ADDR_BITS:0] counter;
reg toggler;
always @(posedge clk) begin