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authorTimothy Pearson <kb9vqf@pearsoncomputing.net>2014-01-10 02:58:51 -0600
committerTimothy Pearson <kb9vqf@pearsoncomputing.net>2014-01-10 02:58:51 -0600
commit37420cfb78718d7a7ac9bfde754fbd62c6d29f2c (patch)
treebe4c7467e1ed3d1e12c8f5ce7d054758880440ca
parent4436bddc8ceecb5277de73de6c929a3bb6722143 (diff)
downloadulab-37420cfb78718d7a7ac9bfde754fbd62c6d29f2c.tar.gz
ulab-37420cfb78718d7a7ac9bfde754fbd62c6d29f2c.zip
Increase DSP memory size
Fix potential crash in FPGA viewer if hardware debug interface is malfunctioning or offline
-rw-r--r--clients/tde/src/part/fpgaview/part.cpp8
-rw-r--r--fpga/gpmc/xilinx/common/main.v6
-rw-r--r--fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf2
3 files changed, 13 insertions, 3 deletions
diff --git a/clients/tde/src/part/fpgaview/part.cpp b/clients/tde/src/part/fpgaview/part.cpp
index 7ddec7d..36809c2 100644
--- a/clients/tde/src/part/fpgaview/part.cpp
+++ b/clients/tde/src/part/fpgaview/part.cpp
@@ -1203,8 +1203,12 @@ void FPGAViewPart::receiveInputStatesFromRemoteFPGA() {
m_dataMemoryImageHeight = newSize;
m_base->groupInputImage->setTitle(TQString("Input Image (%1x%2):").arg(m_dataMemoryImageWidth).arg(m_dataMemoryImageHeight));
m_base->groupOutputImage->setTitle(TQString("Output Image (%1x%2):").arg(m_dataMemoryImageWidth).arg(m_dataMemoryImageHeight));
- m_inputImageViewer->resize(m_dataMemoryImageWidth, m_dataMemoryImageHeight);
- m_outputImageViewer->resize(m_dataMemoryImageWidth, m_dataMemoryImageHeight);
+ if (m_inputImageViewer) {
+ m_inputImageViewer->resize(m_dataMemoryImageWidth, m_dataMemoryImageHeight);
+ }
+ if (m_outputImageViewer) {
+ m_outputImageViewer->resize(m_dataMemoryImageWidth, m_dataMemoryImageHeight);
+ }
m_dataMemorySizePrev = m_dataMemorySize;
}
diff --git a/fpga/gpmc/xilinx/common/main.v b/fpga/gpmc/xilinx/common/main.v
index 370c3a2..a54de0d 100644
--- a/fpga/gpmc/xilinx/common/main.v
+++ b/fpga/gpmc/xilinx/common/main.v
@@ -53,7 +53,7 @@ module main(
input [3:0] sseg_mux,
input [7:0] sseg_data);
- parameter RAM_ADDR_BITS = 14;
+ parameter RAM_ADDR_BITS = 15;
reg [15:0] sixteen_bit_io_in;
reg [15:0] sixteen_bit_io_out;
@@ -309,6 +309,7 @@ module main(
// 0x0a: User process register
// Bit 0: User processing start
// Bit 1: User processing done (read only)
+ // 0x0b: Number of address bits of DSP RAM (read only)
// 0x20 - 0x3f: LCD data area
if (gpmc_wen_reg == 1'b0) begin
if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f
@@ -380,6 +381,9 @@ module main(
gpmc_data_out[1] = userproc_done;
gpmc_data_out[7:2] = 0;
end
+ 11: begin
+ gpmc_data_out = RAM_ADDR_BITS;
+ end
default: begin
gpmc_data_out = 0;
end
diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf
index d6ccdcc..02c10c4 100644
--- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf
+++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf
@@ -33,6 +33,7 @@ NET "gpmc_address<11>" LOC = "B8" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<12>" LOC = "C7" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<13>" LOC = "D6" |IOSTANDARD = "LVCMOS33";
NET "gpmc_address<14>" LOC = "B4" |IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<15>" LOC = "B2" |IOSTANDARD = "LVCMOS33";
NET "usermem_wen" LOC = "V16" |IOSTANDARD = "LVCMOS33";
NET "usermem_wait" LOC = "T18" |SLEW = FAST |IOSTANDARD = "LVCMOS33";
@@ -63,6 +64,7 @@ NET "usermem_address<11>" LOC = "N16" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<12>" LOC = "L16" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<13>" LOC = "N14" |IOSTANDARD = "LVCMOS33";
NET "usermem_address<14>" LOC = "M13" |IOSTANDARD = "LVCMOS33";
+NET "usermem_address<15>" LOC = "K13" |IOSTANDARD = "LVCMOS33";
NET "four_bit_leds<0>" LOC = "G13" |IOSTANDARD = "LVCMOS33";
NET "four_bit_leds<1>" LOC = "H16" |IOSTANDARD = "LVCMOS33";