Relayout the GUI to be more in line with expected norms

Add user logic reset signal
Stabilize data transfer

1 files changed, 17 insertions, 1 deletions

diff --git a/fpga/gpmc/xilinx/common/main.v b/fpga/gpmc/xilinx/common/main.v
index a54de0d..a06565a 100644
--- a/fpga/gpmc/xilinx/common/main.v
+++ b/fpga/gpmc/xilinx/common/main.v
@@ -39,6 +39,7 @@ module main(
 
 	output reg userproc_start,
 	input userproc_done,
+	output reg userlogic_reset,
 
 	input [3:0] four_bit_leds,
 	input [7:0] eight_bit_leds,
@@ -239,12 +240,18 @@ module main(
 		gpmc_advn_reg = gpmc_advn;
 		gpmc_oen_reg = gpmc_oen;
 		gpmc_wen_reg = gpmc_wen;
-		gpmc_data_reg = gpmc_data;
+		if (gpmc_wen_reg == 1'b0) begin
+			gpmc_data_reg = gpmc_data;
+		end
 		if (gpmc_advn_reg == 1'b0) begin
 			gpmc_address_reg = gpmc_address;
 			data_storage_write_enable = 1'b0;
 			lcd_data_storage_wea = 1'b0;
 		end
+		if (gpmc_wen_reg == 1'b1) begin
+			data_storage_write_enable = 1'b0;
+			lcd_data_storage_wea = 1'b0;
+		end
 
 		if (gpmc_address_reg[RAM_ADDR_BITS] == 1'b1) begin
 			// System memory access
@@ -310,6 +317,8 @@ module main(
 			//       Bit 0: User processing start
 			//       Bit 1: User processing done (read only)
 			// 0x0b: Number of address bits of DSP RAM (read only)
+			// 0x0c: User device control
+			//       Bit 0: User logic reset
 			// 0x20 - 0x3f: LCD data area
 			if (gpmc_wen_reg == 1'b0) begin
 				if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin	// Address range 0x20 - 0x3f
@@ -333,6 +342,9 @@ module main(
 						10: begin
 							userproc_start = gpmc_data_reg[0];
 						end
+						12: begin
+							userlogic_reset = gpmc_data_reg[0];
+						end
 						default: begin
 							// Do nothing
 						end
@@ -384,6 +396,10 @@ module main(
 						11: begin
 							gpmc_data_out = RAM_ADDR_BITS;
 						end
+						12: begin
+							gpmc_data_out[0] = userlogic_reset;
+							gpmc_data_out[7:1] = 0;
+						end
 						default: begin
 							gpmc_data_out = 0;
 						end