Add sample image processing module to Spartan 6 demo project

1 files changed, 72 insertions, 5 deletions

diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v
index a06486e..801a9aa 100644
--- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v
+++ b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v
@@ -105,13 +105,19 @@ module main(
 	//

 	//-------------------------------------------------------------------------------------------------------

 

-	reg sram_wren_in = 0;

+	wire sram_wren_in;

 	wire sram_clock_in;

-	reg [7:0] sram_data_in = 0;

-	reg [13:0] sram_address_in = 0;

-	wire [7:0] sram_data_out = 0;

+	wire [7:0] sram_data_in;

+	wire [13:0] sram_address_in;

+	wire [7:0] sram_data_out;

 	wire sram_available;

-	reg sram_processing_done = 1;

+	wire sram_processing_done;

+

+	// Uncomment this block if no image processing module is provided

+	// assign sram_wren_in = 0;

+	// assign sram_data_in = 0;

+	// assign sram_address_in = 0;

+	// assign sram_processing_done = 1;

 	

 	assign sram_clock_in = main_fifty_clock;

 

@@ -149,6 +155,17 @@ module main(
 		.sixteen_bit_output(sixteen_bit_output), .lcd_data_in_address(lcd_data_in_address),

 		.lcd_data_in_data(lcd_data_in_data), .lcd_data_in_enable(lcd_data_in_enable));

 

+	//-------------------------------------------------------------------------------------------------------

+	//

+	// User Image Processing Module Instantiation

+	//

+	// Instantiate the simple userimage processing module to invert the bits in any images sent to the FPGA

+	//

+	//-------------------------------------------------------------------------------------------------------

+

+	sample_image_processing_demo sample_image_processing_demo(.clk(clk_div_by_two), .wren(sram_wren_in), .dout(sram_data_in), .addr(sram_address_in),

+		.din(sram_data_out), .enable(sram_available), .done(sram_processing_done));

+

 endmodule

 

 //-------------------------------------------------------------------------------------------------------

@@ -202,3 +219,53 @@ module sample_demo(clk, four_bit_input, four_bit_output, eight_bit_input, eight_
 		end

 	end

 endmodule

+

+//-------------------------------------------------------------------------------------------------------

+//

+// Demo User Image Processing Module

+//

+//-------------------------------------------------------------------------------------------------------

+

+module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done);

+	input clk;

+

+	output reg wren;

+	output reg [7:0] dout;

+	output reg [13:0] addr;

+	input [7:0] din;

+	input enable;

+	output reg done;

+

+	reg prev_enable;

+	reg [13:0] counter;

+	reg toggler;

+

+	always @(posedge clk) begin

+		if ((enable == 1) && (prev_enable == 0)) begin

+			counter = 0;

+			toggler = 0;

+		end

+		if ((enable == 1) && (done == 0)) begin

+			if (toggler == 0) begin

+				wren = 0;

+				addr = counter;

+				toggler = 1;

+			end else begin

+				dout = ~din;

+				wren = 1;

+				addr = counter;

+				counter = counter + 1;

+				if (counter >= 16383) begin

+					done = 1;

+				end

+				toggler = 0;

+			end

+		end

+		if (enable == 0) begin

+			done = 0;

+			addr = 0;

+			toggler = 0;

+		end

+		prev_enable = enable;

+	end

+endmodule
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