1 files changed, 50 insertions, 21 deletions

diff --git a/fpga/common/remote_access.v b/fpga/common/remote_access.v
index 049b74f..668a6cc 100644
--- a/fpga/common/remote_access.v
+++ b/fpga/common/remote_access.v
@@ -43,7 +43,13 @@ module remote_access(
 	output sram_available,
 	input sram_processing_done,
 	input [7:0] led_segment_bus,
-	input [3:0] led_digit_select);
+	input [3:0] led_digit_select,
+
+	// For use on Digilent Spartan 3E or compatible board only
+	output [3:0] remote_access_lcd_data_out,
+	output remote_access_lcd_rs_out,
+	output remote_access_lcd_rw_out,
+	output remote_access_lcd_enable_out);
 	
 	reg [7:0] remote_access_4_bit_input_reg;
 	reg [7:0] remote_access_8_bit_input_reg;
@@ -57,7 +63,7 @@ module remote_access(
 	reg sram_available_reg;
 	reg startup_needed = 1;
 	
-	assign remote_access_4_bit_input = remote_access_4_bit_input_reg;
+	assign remote_access_4_bit_input = remote_access_4_bit_input_reg[3:0];
 	assign remote_access_8_bit_input = remote_access_8_bit_input_reg;
 	assign remote_access_16_bit_input = remote_access_16_bit_input_reg;
 	assign remote_access_lcd_data_out = remote_access_lcd_data_out_reg;
@@ -77,6 +83,7 @@ module remote_access(
 	
 	reg four_mhz_clk;
 	reg clk_div_by_two;
+	reg clk_div_by_two_oneeighty;
 	reg clk_div_by_four;
 	reg clk_div_by_eight;
 	reg [3:0] fifty_clock_divider = 0;
@@ -92,8 +99,12 @@ module remote_access(
 	always @(posedge main_fifty_clock) begin
 		clk_div_by_two = !clk_div_by_two;
 	end
+
+	always @(negedge main_fifty_clock) begin
+		clk_div_by_two_oneeighty = !clk_div_by_two_oneeighty;
+	end
 	
-	always @(posedge clk_div_by_two) begin
+	always @(posedge clk_div_by_two_oneeighty) begin
 		clk_div_by_four = !clk_div_by_four;
 	end
 	
@@ -108,45 +119,63 @@ module remote_access(
 	//-----------------------------------------------------------------------------------
 	
 	reg [7:0] led_display_bytes [3:0];
-	reg [4:0] digit_blanker_1 = 0;
-	reg [4:0] digit_blanker_2 = 0;
-	reg [4:0] digit_blanker_3 = 0;
-	reg [4:0] digit_blanker_4 = 0;
+	reg [5:0] digit_blanker_1 = 0;
+	reg [5:0] digit_blanker_2 = 0;
+	reg [5:0] digit_blanker_3 = 0;
+	reg [5:0] digit_blanker_4 = 0;
+
+	reg [7:0] led_segment_bus_latch;
+	reg [3:0] led_digit_select_latch;
 	
 	always @(negedge clk_div_by_eight) begin
-		if (led_digit_select[0] == 0) begin
-			led_display_bytes[0] = led_segment_bus;
+		led_segment_bus_latch = led_segment_bus;
+		led_digit_select_latch = led_digit_select;
+
+		if (led_digit_select_latch[0] == 0) begin
+			led_display_bytes[0] = led_segment_bus_latch;
 			digit_blanker_1 = 0;
+			digit_blanker_2 = digit_blanker_2 + 1;
+			digit_blanker_3 = digit_blanker_3 + 1;
+			digit_blanker_4 = digit_blanker_4 + 1;
 		end
 		
-		if (led_digit_select[1] == 0) begin
-			led_display_bytes[1] = led_segment_bus;
+		if (led_digit_select_latch[1] == 0) begin
+			led_display_bytes[1] = led_segment_bus_latch;
+			digit_blanker_1 = digit_blanker_1 + 1;
 			digit_blanker_2 = 0;
+			digit_blanker_3 = digit_blanker_3 + 1;
+			digit_blanker_4 = digit_blanker_4 + 1;
 		end
 		
-		if (led_digit_select[2] == 0) begin
-			led_display_bytes[2] = led_segment_bus;
+		if (led_digit_select_latch[2] == 0) begin
+			led_display_bytes[2] = led_segment_bus_latch;
+			digit_blanker_1 = digit_blanker_1 + 1;
+			digit_blanker_2 = digit_blanker_2 + 1;
 			digit_blanker_3 = 0;
+			digit_blanker_4 = digit_blanker_4 + 1;
 		end
 		
-		if (led_digit_select[3] == 0) begin
-			led_display_bytes[3] = led_segment_bus;
+		if (led_digit_select_latch[3] == 0) begin
+			led_display_bytes[3] = led_segment_bus_latch;
+			digit_blanker_1 = digit_blanker_1 + 1;
+			digit_blanker_2 = digit_blanker_2 + 1;
+			digit_blanker_3 = digit_blanker_3 + 1;
 			digit_blanker_4 = 0;
 		end
-		
-		if (digit_blanker_1 > 30) begin
+
+		if (digit_blanker_1 > 60) begin
 			led_display_bytes[0] = 255;
 		end
 		
-		if (digit_blanker_2 > 30) begin
+		if (digit_blanker_2 > 60) begin
 			led_display_bytes[1] = 255;
 		end
 		
-		if (digit_blanker_3 > 30) begin
+		if (digit_blanker_3 > 60) begin
 			led_display_bytes[2] = 255;
 		end
 		
-		if (digit_blanker_4 > 30) begin
+		if (digit_blanker_4 > 60) begin
 			led_display_bytes[3] = 255;
 		end
 	end
@@ -245,7 +274,7 @@ module remote_access(
 	reg transmit_dsp_rx_complete = 0;
 	reg transmit_dsp_rx_complete_done = 0;
 	
-	// Transmit!	
+	// Transmit!
 	always @(posedge clk_div_by_two) begin
 		transmitter_4_bit_state = remote_access_4_bit_output;
 		transmitter_8_bit_state = remote_access_8_bit_output;