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-rw-r--r--fpga/gpmc/xilinx/common/main.v10
1 files changed, 9 insertions, 1 deletions
diff --git a/fpga/gpmc/xilinx/common/main.v b/fpga/gpmc/xilinx/common/main.v
index cd811fa..bf6e023 100644
--- a/fpga/gpmc/xilinx/common/main.v
+++ b/fpga/gpmc/xilinx/common/main.v
@@ -58,10 +58,15 @@ module main(
output reg sixteen_bit_io_mode,
input [3:0] sseg_mux,
- input [7:0] sseg_data);
+ input [7:0] sseg_data,
+
+ output userdevice_reset);
parameter RAM_ADDR_BITS = 15;
+ reg userdevice_reset_reg;
+ assign userdevice_reset = ~userdevice_reset_reg;
+
assign host_serial_txd = userlogic_serial_rxd;
assign userlogic_serial_txd = host_serial_rxd;
@@ -394,6 +399,7 @@ module main(
// 0x0b: Number of address bits of DSP RAM (read only)
// 0x0c: User device control
// Bit 0: User logic reset
+ // Bit 1: User device reset
// 0x20 - 0x3f: LCD data area
// 0x4000 - 0x7fff: Logic analyzer data area (read only)
if (gpmc_wen_reg == 1'b0) begin
@@ -420,6 +426,7 @@ module main(
end
12: begin
userlogic_reset = gpmc_data_reg[0];
+ userdevice_reset_reg = gpmc_data_reg[1];
end
default: begin
// Do nothing
@@ -503,6 +510,7 @@ module main(
end
12: begin
gpmc_data_out[0] = userlogic_reset;
+ gpmc_data_out[1] = userdevice_reset_reg;
gpmc_data_out[7:1] = 0;
end
default: begin