diff options
Diffstat (limited to 'fpga/xilinx/digilent')
| -rw-r--r-- | fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v index 85c08be..9f37f9d 100644 --- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v +++ b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v @@ -284,17 +284,19 @@ endmodule //-------------------------------------------------------------------------------------------------------
module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done);
+ parameter IMAGE_RAM_ADDR_BITS = 14;
+
input clk;
output reg wren;
output reg [7:0] dout;
- output reg [(RAM_ADDR_BITS-1):0] addr;
+ output reg [(IMAGE_RAM_ADDR_BITS-1):0] addr;
input [7:0] din;
input enable;
output reg done;
reg prev_enable;
- reg [(RAM_ADDR_BITS-1):0] counter;
+ reg [(IMAGE_RAM_ADDR_BITS-1):0] counter;
reg toggler;
always @(posedge clk) begin
@@ -312,7 +314,7 @@ module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done); wren = 1;
addr = counter;
counter = counter + 1;
- if (counter > (2**RAM_ADDR_BITS)) begin
+ if (counter > (2**IMAGE_RAM_ADDR_BITS)) begin
done = 1;
end
toggler = 0;
@@ -325,4 +327,4 @@ module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done); end
prev_enable = enable;
end
-endmodule
\ No newline at end of file +endmodule
|