diff options
Diffstat (limited to 'fpga')
14 files changed, 846 insertions, 224 deletions
diff --git a/fpga/gpmc/xilinx/common/data_storage.v b/fpga/gpmc/xilinx/common/data_storage.v index b98fb25..f4393a6 100644 --- a/fpga/gpmc/xilinx/common/data_storage.v +++ b/fpga/gpmc/xilinx/common/data_storage.v @@ -8,19 +8,20 @@ module data_storage( input clka, - input [7:0] dina, + input [(RAM_WIDTH-1):0] dina, input [(RAM_ADDR_BITS-1):0] addra, input wea, - output reg [7:0] douta); + output reg [(RAM_WIDTH-1):0] douta); parameter RAM_ADDR_BITS = 14; parameter RAM_WIDTH = 8; - + // Xilinx specific directive (* RAM_STYLE="BLOCK" *) - + reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0]; - + + // Registered always @(posedge clka) begin if (wea) begin data_storage_ram[addra] <= dina; @@ -30,4 +31,12 @@ module data_storage( end end +// // Unregistered +// always @(posedge clka) begin +// if (wea) begin +// data_storage_ram[addra] <= dina; +// end +// end +// assign douta = data_storage_ram[addra]; + endmodule diff --git a/fpga/gpmc/xilinx/common/lcd_data_storage.v b/fpga/gpmc/xilinx/common/lcd_data_storage.v index c1f3559..8f7adac 100644 --- a/fpga/gpmc/xilinx/common/lcd_data_storage.v +++ b/fpga/gpmc/xilinx/common/lcd_data_storage.v @@ -23,22 +23,38 @@ module lcd_data_storage( // Xilinx specific directive (* RAM_STYLE="BLOCK" *) - reg [RAM_WIDTH-1:0] data_storage_ram [(2**5)-1:0]; - + reg [RAM_WIDTH-1:0] lcd_data_storage_ram [(2**5)-1:0]; + + // Registered always @(posedge clka) begin - douta <= data_storage_ram[addra]; + douta <= lcd_data_storage_ram[addra]; if (wea) begin - data_storage_ram[addra] <= dina; + lcd_data_storage_ram[addra] <= dina; douta <= dina; end end always @(posedge clkb) begin - doutb <= data_storage_ram[addrb]; + doutb <= lcd_data_storage_ram[addrb]; if (web) begin - data_storage_ram[addrb] <= dinb; + lcd_data_storage_ram[addrb] <= dinb; doutb <= dinb; end end +// // Unregistered +// always @(posedge clka) begin +// if (wea) begin +// lcd_data_storage_ram[addra] <= dina; +// end +// end +// assign douta = lcd_data_storage_ram[addra]; +// +// always @(posedge clkb) begin +// if (web) begin +// lcd_data_storage_ram[addrb] <= dinb; +// end +// end +// assign doutb = lcd_data_storage_ram[addrb]; + endmodule diff --git a/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v b/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v index 1dd957e..a68d800 100644 --- a/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v +++ b/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v @@ -7,38 +7,63 @@ ////////////////////////////////////////////////////////////////////////////////// module logic_analyzer_data_storage( - input clka, - input clkb, - input [63:0] dina, - input [63:0] dinb, - input [10:0] addra, - input [10:0] addrb, + input clk, + input [(RAM_WIDTH-1):0] dina, + input [(RAM_WIDTH-1):0] dinb, + input [(RAM_ADDR_BITS-1):0] addra, + input [(RAM_ADDR_BITS-1):0] addrb, input wea, input web, - output reg [63:0] douta, - output reg [63:0] doutb); + output reg [(RAM_WIDTH-1):0] douta, + output reg [(RAM_WIDTH-1):0] doutb); + parameter RAM_ADDR_BITS = 11; parameter RAM_WIDTH = 64; // Xilinx specific directive (* RAM_STYLE="BLOCK" *) - reg [RAM_WIDTH-1:0] data_storage_ram [(2**11)-1:0]; - + reg [RAM_WIDTH-1:0] logic_analyzer_data_storage_ram [(2**RAM_ADDR_BITS)-1:0]; + + // Initial RAM values for debugging + integer index; + initial begin + for (index = 0; index < ((2**RAM_ADDR_BITS)-1); index = index + 2) begin + logic_analyzer_data_storage_ram[index+0] = {(RAM_WIDTH/4){4'ha}}; + logic_analyzer_data_storage_ram[index+1] = {(RAM_WIDTH/4){4'h5}}; + end + end + + // Registered always @(posedge clka) begin - douta <= data_storage_ram[addra]; + douta <= logic_analyzer_data_storage_ram[addra]; if (wea) begin - data_storage_ram[addra] <= dina; + logic_analyzer_data_storage_ram[addra] <= dina; douta <= dina; end end always @(posedge clkb) begin - doutb <= data_storage_ram[addrb]; + doutb <= logic_analyzer_data_storage_ram[addrb]; if (web) begin - data_storage_ram[addrb] <= dinb; + logic_analyzer_data_storage_ram[addrb] <= dinb; doutb <= dinb; end end +// // Unregistered +// always @(posedge clka) begin +// if (wea) begin +// logic_analyzer_data_storage_ram[addra] <= dina; +// end +// end +// assign douta = logic_analyzer_data_storage_ram[addra]; +// +// always @(posedge clkb) begin +// if (web) begin +// logic_analyzer_data_storage_ram[addrb] <= dinb; +// end +// end +// assign doutb = logic_analyzer_data_storage_ram[addrb]; + endmodule diff --git a/fpga/gpmc/xilinx/common/main.v b/fpga/gpmc/xilinx/common/main.v index bf6e023..ef0df6b 100644 --- a/fpga/gpmc/xilinx/common/main.v +++ b/fpga/gpmc/xilinx/common/main.v @@ -63,6 +63,10 @@ module main( output userdevice_reset); parameter RAM_ADDR_BITS = 15; + parameter CLKIN_PERIOD_NS = 10; + parameter LOGIC_ANALYZER_CLOCK_DIV = 2; + parameter LOGIC_ANALYZER_CLOCK_MULT = 2; + parameter LOGIC_ANALYZER_STEP = (CLKIN_PERIOD_NS*(LOGIC_ANALYZER_CLOCK_MULT/LOGIC_ANALYZER_CLOCK_DIV)); reg userdevice_reset_reg; assign userdevice_reset = ~userdevice_reset_reg; @@ -70,6 +74,10 @@ module main( assign host_serial_txd = userlogic_serial_rxd; assign userlogic_serial_txd = host_serial_rxd; + wire main_clk; + wire main_clk_online; + main_clock_generator main_clock_generator(.clkin(clk), .clkout(main_clk), .online(main_clk_online)); + reg [15:0] sixteen_bit_io_in; reg [15:0] sixteen_bit_io_out; reg [15:0] sixteen_bit_io_reg; @@ -77,7 +85,7 @@ module main( assign sixteen_bit_io = (sixteen_bit_io_wen) ? sixteen_bit_io_out : 16'bz; - always @(posedge clk) begin + always @(posedge main_clk) begin sixteen_bit_io_reg = sixteen_bit_io; sixteen_bit_io_wen_reg = sixteen_bit_io_wen; if (sixteen_bit_io_wen_reg == 1'b0) begin @@ -100,10 +108,10 @@ module main( wire data_storage_clka; reg [7:0] data_storage_dina; reg [(RAM_ADDR_BITS-1):0] data_storage_addra; - reg data_storage_write_enable; + reg data_storage_write_enable = 1'b0; wire [7:0] data_storage_data_out; - assign data_storage_clka = clk; + assign data_storage_clka = main_clk; data_storage #(RAM_ADDR_BITS) data_storage(.clka(data_storage_clka), .dina(data_storage_dina), .addra(data_storage_addra), .wea(data_storage_write_enable), .douta(data_storage_data_out)); @@ -114,13 +122,13 @@ module main( reg [7:0] lcd_data_storage_dinb; reg [4:0] lcd_data_storage_addra; reg [4:0] lcd_data_storage_addrb; - reg lcd_data_storage_wea; - reg lcd_data_storage_web; + reg lcd_data_storage_wea = 1'b0; + reg lcd_data_storage_web = 1'b0; wire [7:0] lcd_data_storage_douta; wire [7:0] lcd_data_storage_doutb; - assign lcd_data_storage_clka = clk; - assign lcd_data_storage_clkb = clk; + assign lcd_data_storage_clka = main_clk; + assign lcd_data_storage_clkb = main_clk; lcd_data_storage lcd_data_storage(.clka(lcd_data_storage_clka), .clkb(lcd_data_storage_clkb), .dina(lcd_data_storage_dina), .dinb(lcd_data_storage_dinb), @@ -129,7 +137,12 @@ module main( .douta(lcd_data_storage_douta), .doutb(lcd_data_storage_doutb)); wire logic_analyzer_clk; - logic_analyzer_clock_generator logic_analyzer_clock_generator(.clkin(clk), .clkout(logic_analyzer_clk)); + wire logic_analyzer_online; + //logic_analyzer_clock_generator #(LOGIC_ANALYZER_CLOCK_MULT, LOGIC_ANALYZER_CLOCK_DIV) logic_analyzer_clock_generator(.clkin(clk), .clkout(logic_analyzer_clk), .online(logic_analyzer_online)); + // FIXME + // Work around block RAM problems + assign logic_analyzer_clk = main_clk; + assign logic_analyzer_online = 1'b1; wire logic_analyzer_data_storage_clka; wire logic_analyzer_data_storage_clkb; @@ -137,13 +150,13 @@ module main( reg [63:0] logic_analyzer_data_storage_dinb; reg [10:0] logic_analyzer_data_storage_addra; reg [10:0] logic_analyzer_data_storage_addrb; - reg logic_analyzer_data_storage_wea; - reg logic_analyzer_data_storage_web; + reg logic_analyzer_data_storage_wea = 1'b0; + reg logic_analyzer_data_storage_web = 1'b0; wire [63:0] logic_analyzer_data_storage_douta; wire [63:0] logic_analyzer_data_storage_doutb; - assign logic_analyzer_data_storage_clka = clk; - assign logic_analyzer_data_storage_clkb = logic_analyzer_clk; + assign logic_analyzer_data_storage_clka = logic_analyzer_clk; + assign logic_analyzer_data_storage_clkb = main_clk; logic_analyzer_data_storage logic_analyzer_data_storage(.clka(logic_analyzer_data_storage_clka), .clkb(logic_analyzer_data_storage_clkb), .dina(logic_analyzer_data_storage_dina), .dinb(logic_analyzer_data_storage_dinb), @@ -163,7 +176,7 @@ module main( reg clk_div_by_eight; reg clk_div_by_sixteen; - always @(posedge clk) begin + always @(posedge main_clk) begin clk_div_by_two = !clk_div_by_two; end @@ -206,32 +219,32 @@ module main( if (sseg_mux_latch[0] == 0) begin led_display_bytes[0] = sseg_data_latch; digit_blanker_1 = 0; - digit_blanker_2 = digit_blanker_2 + 1; - digit_blanker_3 = digit_blanker_3 + 1; - digit_blanker_4 = digit_blanker_4 + 1; + digit_blanker_2 = digit_blanker_2 + 1'b1; + digit_blanker_3 = digit_blanker_3 + 1'b1; + digit_blanker_4 = digit_blanker_4 + 1'b1; end if (sseg_mux_latch[1] == 0) begin led_display_bytes[1] = sseg_data_latch; - digit_blanker_1 = digit_blanker_1 + 1; + digit_blanker_1 = digit_blanker_1 + 1'b1; digit_blanker_2 = 0; - digit_blanker_3 = digit_blanker_3 + 1; - digit_blanker_4 = digit_blanker_4 + 1; + digit_blanker_3 = digit_blanker_3 + 1'b1; + digit_blanker_4 = digit_blanker_4 + 1'b1; end if (sseg_mux_latch[2] == 0) begin led_display_bytes[2] = sseg_data_latch; - digit_blanker_1 = digit_blanker_1 + 1; - digit_blanker_2 = digit_blanker_2 + 1; + digit_blanker_1 = digit_blanker_1 + 1'b1; + digit_blanker_2 = digit_blanker_2 + 1'b1; digit_blanker_3 = 0; - digit_blanker_4 = digit_blanker_4 + 1; + digit_blanker_4 = digit_blanker_4 + 1'b1; end if (sseg_mux_latch[3] == 0) begin led_display_bytes[3] = sseg_data_latch; - digit_blanker_1 = digit_blanker_1 + 1; - digit_blanker_2 = digit_blanker_2 + 1; - digit_blanker_3 = digit_blanker_3 + 1; + digit_blanker_1 = digit_blanker_1 + 1'b1; + digit_blanker_2 = digit_blanker_2 + 1'b1; + digit_blanker_3 = digit_blanker_3 + 1'b1; digit_blanker_4 = 0; end @@ -258,39 +271,113 @@ module main( // //----------------------------------------------------------------------------------- - reg logic_analyzer_trigger; - reg logic_analyzer_trigger_prev; - reg [11:0] logic_analyzer_address_counter; + reg [32*8:0] logic_analyzer_signal_names [63:0]; + + initial begin + logic_analyzer_signal_names[0] <= "Four bit LEDs <0>\0"; + logic_analyzer_signal_names[1] <= "Four bit LEDs <1>\0"; + logic_analyzer_signal_names[2] <= "Four bit LEDs <2>\0"; + logic_analyzer_signal_names[3] <= "Four bit LEDs <3>\0"; + logic_analyzer_signal_names[4] <= "Four bit switches <0>\0"; + logic_analyzer_signal_names[5] <= "Four bit switches <1>\0"; + logic_analyzer_signal_names[6] <= "Four bit switches <2>\0"; + logic_analyzer_signal_names[7] <= "Four bit switches <3>\0"; + logic_analyzer_signal_names[8] <= "Eight bit LEDs <0>\0"; + logic_analyzer_signal_names[9] <= "Eight bit LEDs <1>\0"; + logic_analyzer_signal_names[10] <= "Eight bit LEDs <2>\0"; + logic_analyzer_signal_names[11] <= "Eight bit LEDs <3>\0"; + logic_analyzer_signal_names[12] <= "Eight bit LEDs <4>\0"; + logic_analyzer_signal_names[13] <= "Eight bit LEDs <5>\0"; + logic_analyzer_signal_names[14] <= "Eight bit LEDs <6>\0"; + logic_analyzer_signal_names[15] <= "Eight bit LEDs <7>\0"; + logic_analyzer_signal_names[16] <= "Eight bit switches <0>\0"; + logic_analyzer_signal_names[17] <= "Eight bit switches <1>\0"; + logic_analyzer_signal_names[18] <= "Eight bit switches <2>\0"; + logic_analyzer_signal_names[19] <= "Eight bit switches <3>\0"; + logic_analyzer_signal_names[20] <= "Eight bit switches <4>\0"; + logic_analyzer_signal_names[21] <= "Eight bit switches <5>\0"; + logic_analyzer_signal_names[22] <= "Eight bit switches <6>\0"; + logic_analyzer_signal_names[23] <= "Eight bit switches <7>\0"; + logic_analyzer_signal_names[24] <= "Seven-segment MUX <0>\0"; + logic_analyzer_signal_names[25] <= "Seven-segment MUX <1>\0"; + logic_analyzer_signal_names[26] <= "Seven-segment MUX <2>\0"; + logic_analyzer_signal_names[27] <= "Seven-segment MUX <3>\0"; + logic_analyzer_signal_names[28] <= "Seven-segment DATA <0>\0"; + logic_analyzer_signal_names[29] <= "Seven-segment DATA <1>\0"; + logic_analyzer_signal_names[30] <= "Seven-segment DATA <2>\0"; + logic_analyzer_signal_names[31] <= "Seven-segment DATA <3>\0"; + logic_analyzer_signal_names[32] <= "Seven-segment DATA <4>\0"; + logic_analyzer_signal_names[33] <= "Seven-segment DATA <5>\0"; + logic_analyzer_signal_names[34] <= "Seven-segment DATA <6>\0"; + logic_analyzer_signal_names[35] <= "Seven-segment DATA <7>\0"; + logic_analyzer_signal_names[36] <= "User memory DATA <0>\0"; + logic_analyzer_signal_names[37] <= "User memory DATA <1>\0"; + logic_analyzer_signal_names[38] <= "User memory DATA <2>\0"; + logic_analyzer_signal_names[39] <= "User memory DATA <3>\0"; + logic_analyzer_signal_names[40] <= "User memory DATA <4>\0"; + logic_analyzer_signal_names[41] <= "User memory DATA <5>\0"; + logic_analyzer_signal_names[42] <= "User memory DATA <6>\0"; + logic_analyzer_signal_names[43] <= "User memory DATA <7>\0"; + logic_analyzer_signal_names[44] <= "User memory ADDR <0>\0"; + logic_analyzer_signal_names[45] <= "User memory ADDR <1>\0"; + logic_analyzer_signal_names[46] <= "User memory ADDR <2>\0"; + logic_analyzer_signal_names[47] <= "User memory ADDR <3>\0"; + logic_analyzer_signal_names[48] <= "User memory ADDR <4>\0"; + logic_analyzer_signal_names[49] <= "User memory ADDR <5>\0"; + logic_analyzer_signal_names[50] <= "User memory ADDR <6>\0"; + logic_analyzer_signal_names[51] <= "User memory ADDR <7>\0"; + logic_analyzer_signal_names[52] <= "User memory ADDR <8>\0"; + logic_analyzer_signal_names[53] <= "User memory ADDR <9>\0"; + logic_analyzer_signal_names[54] <= "User memory ADDR <10>\0"; + logic_analyzer_signal_names[55] <= "User memory ADDR <11>\0"; + logic_analyzer_signal_names[56] <= "User memory ADDR <12>\0"; + logic_analyzer_signal_names[57] <= "User memory ADDR <13>\0"; + logic_analyzer_signal_names[58] <= "User memory ADDR <14>\0"; + logic_analyzer_signal_names[59] <= "User memory ADDR <15>\0"; + logic_analyzer_signal_names[60] <= "User memory WEN\0"; + logic_analyzer_signal_names[61] <= "User memory WAIT\0"; + logic_analyzer_signal_names[62] <= "GND REF\0"; + logic_analyzer_signal_names[63] <= "User logic clock\0"; + end + + reg logic_analyzer_running = 1; + reg [15:0] logic_analyzer_timestep = LOGIC_ANALYZER_STEP; + reg [1:0] logic_analyzer_trigger = 2'b11; + reg [11:0] logic_analyzer_address_counter = 12'b100000000000; always @(posedge logic_analyzer_clk) begin // Trigger - logic_analyzer_trigger = ~userlogic_reset; // Trigger on userlogic_reset falling edge - if ((logic_analyzer_trigger == 1) && (logic_analyzer_trigger_prev == 0)) begin + logic_analyzer_trigger[1] = logic_analyzer_trigger[0]; + logic_analyzer_trigger[0] = ~userlogic_reset; // Trigger on userlogic_reset falling edge + if ((logic_analyzer_running == 1) && (logic_analyzer_trigger[0] == 1) && (logic_analyzer_trigger[1] == 0)) begin logic_analyzer_address_counter = 0; end // Data load if (logic_analyzer_address_counter[11] == 1'b0) begin - logic_analyzer_data_storage_addrb = logic_analyzer_address_counter; + // Set up write address + logic_analyzer_data_storage_addra <= logic_analyzer_address_counter[10:0]; // Connect signals to logic analyzer - logic_analyzer_data_storage_dinb[3:0] = four_bit_leds; - logic_analyzer_data_storage_dinb[7:4] = four_bit_switches; - logic_analyzer_data_storage_dinb[15:8] = eight_bit_leds; - logic_analyzer_data_storage_dinb[23:16] = eight_bit_switches; - logic_analyzer_data_storage_dinb[27:24] = sseg_mux; - logic_analyzer_data_storage_dinb[35:28] = sseg_data; - logic_analyzer_data_storage_dinb[43:36] = usermem_data; - logic_analyzer_data_storage_dinb[59:44] = usermem_address; - logic_analyzer_data_storage_dinb[60] = usermem_wen; - logic_analyzer_data_storage_dinb[61] = usermem_wait; - logic_analyzer_data_storage_dinb[62] = 1'b0; // UNUSED - logic_analyzer_data_storage_dinb[63] = userlogic_clock; - - logic_analyzer_data_storage_web = 1'b1; - logic_analyzer_address_counter = logic_analyzer_address_counter + 1; + logic_analyzer_data_storage_dina[3:0] <= four_bit_leds; + logic_analyzer_data_storage_dina[7:4] <= four_bit_switches; + logic_analyzer_data_storage_dina[15:8] <= eight_bit_leds; + logic_analyzer_data_storage_dina[23:16] <= eight_bit_switches; + logic_analyzer_data_storage_dina[27:24] <= sseg_mux; + logic_analyzer_data_storage_dina[35:28] <= sseg_data; + logic_analyzer_data_storage_dina[43:36] <= usermem_data; + logic_analyzer_data_storage_dina[59:44] <= usermem_address; + logic_analyzer_data_storage_dina[60] <= usermem_wen; + logic_analyzer_data_storage_dina[61] <= usermem_wait; + logic_analyzer_data_storage_dina[62] <= 1'b0; // UNUSED + logic_analyzer_data_storage_dina[63] <= userlogic_clock; + + logic_analyzer_data_storage_wea <= 1'b1; + logic_analyzer_address_counter = logic_analyzer_address_counter + 1'b1; + end else begin + logic_analyzer_data_storage_addra <= 0; + logic_analyzer_data_storage_dina <= 0; + logic_analyzer_data_storage_wea <= 1'b0; end - - logic_analyzer_trigger_prev = logic_analyzer_trigger; end @@ -310,40 +397,39 @@ module main( reg [7:0] usermem_data_reg; reg [RAM_ADDR_BITS:0] usermem_address_reg; - always @(posedge clk) begin - usermem_wen_reg = usermem_wen; - usermem_data_reg = usermem_data; - usermem_address_reg = usermem_address; - - gpmc_advn_reg = gpmc_advn; - gpmc_oen_reg = gpmc_oen; - gpmc_wen_reg = gpmc_wen; - if (gpmc_wen_reg == 1'b0) begin - gpmc_data_reg = gpmc_data; + always @(posedge main_clk) begin + usermem_wen_reg <= usermem_wen; + usermem_data_reg <= usermem_data; + usermem_address_reg <= usermem_address; + + gpmc_advn_reg <= gpmc_advn; + gpmc_oen_reg <= gpmc_oen; + gpmc_wen_reg <= gpmc_wen; + // wen and advn are both verified before executing any write operations to avoid momentary wen glitches corrupting memory contents + if ((gpmc_wen_reg == 1'b0) && (gpmc_advn_reg == 1'b0)) begin + gpmc_data_reg <= gpmc_data; end if (gpmc_advn_reg == 1'b0) begin - gpmc_address_reg = gpmc_address; - data_storage_write_enable = 1'b0; - lcd_data_storage_wea = 1'b0; - logic_analyzer_data_storage_wea = 1'b0; + gpmc_address_reg <= gpmc_address; end if (gpmc_wen_reg == 1'b1) begin - data_storage_write_enable = 1'b0; - lcd_data_storage_wea = 1'b0; - logic_analyzer_data_storage_wea = 1'b0; + data_storage_write_enable <= 1'b0; + lcd_data_storage_wea <= 1'b0; + logic_analyzer_data_storage_web <= 1'b0; end + gpmc_data_driven <= ((~gpmc_oen_reg) && gpmc_wen_reg); if (gpmc_address_reg[RAM_ADDR_BITS] == 1'b1) begin // System memory access usermem_wait = 1'b1; - if (gpmc_wen_reg == 1'b0) begin - data_storage_addra = gpmc_address_reg[(RAM_ADDR_BITS-1):0]; - data_storage_dina = gpmc_data_reg; - data_storage_write_enable = 1'b1; + if ((gpmc_wen_reg == 1'b0) && (gpmc_advn_reg == 1'b0)) begin + data_storage_addra <= gpmc_address_reg[(RAM_ADDR_BITS-1):0]; + data_storage_dina <= gpmc_data_reg; + data_storage_write_enable <= 1'b1; end else begin - data_storage_addra = gpmc_address_reg[(RAM_ADDR_BITS-1):0]; - data_storage_write_enable = 1'b0; - gpmc_data_out = data_storage_data_out; + data_storage_addra <= gpmc_address_reg[(RAM_ADDR_BITS-1):0]; + data_storage_write_enable <= 1'b0; + gpmc_data_out <= data_storage_data_out; end end else begin // User memory access @@ -354,30 +440,30 @@ module main( // 0x20 - 0x3f: LCD data area if (usermem_wen_reg == 1'b0) begin if (usermem_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f - lcd_data_storage_addrb = usermem_address_reg[4:0]; - lcd_data_storage_dinb = usermem_data_reg; - lcd_data_storage_web = 1'b1; + lcd_data_storage_addrb <= usermem_address_reg[4:0]; + lcd_data_storage_dinb <= usermem_data_reg; + lcd_data_storage_web <= 1'b1; end end else begin if (usermem_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f - lcd_data_storage_addrb = usermem_address_reg[4:0]; - lcd_data_storage_web = 1'b0; - usermem_data_out = lcd_data_storage_doutb; + lcd_data_storage_addrb <= usermem_address_reg[4:0]; + lcd_data_storage_web <= 1'b0; + usermem_data_out <= lcd_data_storage_doutb; end else begin // Default - usermem_data_out = 8'b00000000; + usermem_data_out <= 8'b00000000; end end end else begin // Client scratchpad memory area if (usermem_wen_reg == 1'b0) begin - data_storage_addra = usermem_address_reg[(RAM_ADDR_BITS-1):0]; - data_storage_dina = usermem_data_reg; - data_storage_write_enable = 1'b1; + data_storage_addra <= usermem_address_reg[(RAM_ADDR_BITS-1):0]; + data_storage_dina <= usermem_data_reg; + data_storage_write_enable <= 1'b1; end else begin - data_storage_addra = usermem_address_reg[(RAM_ADDR_BITS-1):0]; - data_storage_write_enable = 1'b0; - usermem_data_out = data_storage_data_out; + data_storage_addra <= usermem_address_reg[(RAM_ADDR_BITS-1):0]; + data_storage_write_enable <= 1'b0; + usermem_data_out <= data_storage_data_out; end end @@ -400,33 +486,55 @@ module main( // 0x0c: User device control // Bit 0: User logic reset // Bit 1: User device reset + // 0x0d: Logic analyzer control + // Bit 0: Logic analyzer capture active + // Bit 7: Logic analyzer online (DCM locked) (read only) + // 0x0e: Logic analyzer timestep (ns) (upper 8 bits) (read only) + // 0x0f: Logic analyzer timestep (ns) (lower 8 bits) (read only) // 0x20 - 0x3f: LCD data area + // 0x800 - 0xfff: Logic analyzer signal names area (read only) // 0x4000 - 0x7fff: Logic analyzer data area (read only) - if (gpmc_wen_reg == 1'b0) begin + if ((gpmc_wen_reg == 1'b0) && (gpmc_advn_reg == 1'b0)) begin if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f - lcd_data_storage_addra = gpmc_address_reg[4:0]; - lcd_data_storage_dina = gpmc_data_reg; - lcd_data_storage_wea = 1'b1; + lcd_data_storage_addra <= gpmc_address_reg[4:0]; + lcd_data_storage_dina <= gpmc_data_reg; + lcd_data_storage_wea <= 1'b1; + end else if (gpmc_address_reg[(RAM_ADDR_BITS-1):14] == 1) begin // Address range 0x4000 - 0x7fff + // FIXME + // Prevent incorrect operation of the block RAM by allowing the Port B write signal to be set under certain conditions + logic_analyzer_data_storage_addrb <= gpmc_address_reg[13:3]; + logic_analyzer_data_storage_dinb[7:0] <= gpmc_data_reg; + logic_analyzer_data_storage_dinb[15:8] <= gpmc_data_reg; + logic_analyzer_data_storage_dinb[23:16] <= gpmc_data_reg; + logic_analyzer_data_storage_dinb[31:24] <= gpmc_data_reg; + logic_analyzer_data_storage_dinb[39:32] <= gpmc_data_reg; + logic_analyzer_data_storage_dinb[47:40] <= gpmc_data_reg; + logic_analyzer_data_storage_dinb[55:48] <= gpmc_data_reg; + logic_analyzer_data_storage_dinb[63:56] <= gpmc_data_reg; + logic_analyzer_data_storage_web <= 1'b1; end else begin case (gpmc_address_reg[(RAM_ADDR_BITS-1):0]) 2: begin - four_bit_switches = gpmc_data_reg[3:0]; + four_bit_switches <= gpmc_data_reg[3:0]; end 3: begin - eight_bit_switches = gpmc_data_reg; + eight_bit_switches <= gpmc_data_reg; end 4: begin - sixteen_bit_io_out[15:8] = gpmc_data_reg; + sixteen_bit_io_out[15:8] <= gpmc_data_reg; end 5: begin - sixteen_bit_io_out[7:0] = gpmc_data_reg; + sixteen_bit_io_out[7:0] <= gpmc_data_reg; end 10: begin - userproc_start = gpmc_data_reg[0]; + userproc_start <= gpmc_data_reg[0]; end 12: begin - userlogic_reset = gpmc_data_reg[0]; - userdevice_reset_reg = gpmc_data_reg[1]; + userlogic_reset <= gpmc_data_reg[0]; + userdevice_reset_reg <= gpmc_data_reg[1]; + end + 13: begin + logic_analyzer_running <= gpmc_data_reg[0]; end default: begin // Do nothing @@ -435,92 +543,103 @@ module main( end end else begin if (gpmc_address_reg[(RAM_ADDR_BITS-1):5] == 1) begin // Address range 0x20 - 0x3f - lcd_data_storage_addra = gpmc_address_reg[4:0]; - lcd_data_storage_wea = 1'b0; - gpmc_data_out = lcd_data_storage_douta; + lcd_data_storage_addra <= gpmc_address_reg[4:0]; + lcd_data_storage_wea <= 1'b0; + gpmc_data_out <= lcd_data_storage_douta; + end else if (gpmc_address_reg[(RAM_ADDR_BITS-1):11] == 1) begin // Address range 0x800 - 0xfff + gpmc_data_out <= logic_analyzer_signal_names[gpmc_address_reg[10:5]][(((32*8)-(gpmc_address_reg[4:0]*8))-1)-:8]; end else if (gpmc_address_reg[(RAM_ADDR_BITS-1):14] == 1) begin // Address range 0x4000 - 0x7fff - logic_analyzer_data_storage_addra = gpmc_address_reg[13:3]; - logic_analyzer_data_storage_wea = 1'b0; + logic_analyzer_data_storage_addrb <= gpmc_address_reg[13:3]; + logic_analyzer_data_storage_web <= 1'b0; case (gpmc_address_reg[2:0]) 0: begin - gpmc_data_out = logic_analyzer_data_storage_douta[7:0]; + gpmc_data_out <= logic_analyzer_data_storage_doutb[63:56]; end 1: begin - gpmc_data_out = logic_analyzer_data_storage_douta[15:8]; + gpmc_data_out <= logic_analyzer_data_storage_doutb[55:48]; end 2: begin - gpmc_data_out = logic_analyzer_data_storage_douta[23:16]; + gpmc_data_out <= logic_analyzer_data_storage_doutb[47:40]; end 3: begin - gpmc_data_out = logic_analyzer_data_storage_douta[31:24]; + gpmc_data_out <= logic_analyzer_data_storage_doutb[39:32]; end 4: begin - gpmc_data_out = logic_analyzer_data_storage_douta[39:32]; + gpmc_data_out <= logic_analyzer_data_storage_doutb[31:24]; end 5: begin - gpmc_data_out = logic_analyzer_data_storage_douta[47:40]; + gpmc_data_out <= logic_analyzer_data_storage_doutb[23:16]; end 6: begin - gpmc_data_out = logic_analyzer_data_storage_douta[55:48]; + gpmc_data_out <= logic_analyzer_data_storage_doutb[15:8]; end 7: begin - gpmc_data_out = logic_analyzer_data_storage_douta[63:56]; + gpmc_data_out <= logic_analyzer_data_storage_doutb[7:0]; end endcase end else begin case (gpmc_address_reg[(RAM_ADDR_BITS-1):0]) 0: begin - gpmc_data_out = 8'b01000010; + gpmc_data_out <= 8'b01000010; end 1: begin - gpmc_data_out = 8'b00000001; + gpmc_data_out <= 8'b00000001; end 2: begin - gpmc_data_out[7:4] = 0; - gpmc_data_out[3:0] = four_bit_leds; + gpmc_data_out[7:4] <= 0; + gpmc_data_out[3:0] <= four_bit_leds; end 3: begin - gpmc_data_out = eight_bit_leds; + gpmc_data_out <= eight_bit_leds; end 4: begin - gpmc_data_out = sixteen_bit_io_in[15:8]; + gpmc_data_out <= sixteen_bit_io_in[15:8]; end 5: begin - gpmc_data_out = sixteen_bit_io_in[7:0]; + gpmc_data_out <= sixteen_bit_io_in[7:0]; end 6: begin - gpmc_data_out = led_display_bytes[0]; + gpmc_data_out <= led_display_bytes[0]; end 7: begin - gpmc_data_out = led_display_bytes[1]; + gpmc_data_out <= led_display_bytes[1]; end 8: begin - gpmc_data_out = led_display_bytes[2]; + gpmc_data_out <= led_display_bytes[2]; end 9: begin - gpmc_data_out = led_display_bytes[3]; + gpmc_data_out <= led_display_bytes[3]; end 10: begin - gpmc_data_out[0] = userproc_start; - gpmc_data_out[1] = userproc_done; - gpmc_data_out[7:2] = 0; + gpmc_data_out[0] <= userproc_start; + gpmc_data_out[1] <= userproc_done; + gpmc_data_out[7:2] <= 0; end 11: begin - gpmc_data_out = RAM_ADDR_BITS; + gpmc_data_out <= RAM_ADDR_BITS; end 12: begin - gpmc_data_out[0] = userlogic_reset; - gpmc_data_out[1] = userdevice_reset_reg; - gpmc_data_out[7:1] = 0; + gpmc_data_out[0] <= userlogic_reset; + gpmc_data_out[1] <= userdevice_reset_reg; + gpmc_data_out[7:2] <= 0; + end + 13: begin + gpmc_data_out[0] <= logic_analyzer_running; + gpmc_data_out[6:1] <= 0; + gpmc_data_out[7] <= logic_analyzer_online; + end + 14: begin + gpmc_data_out <= logic_analyzer_timestep[15:8]; + end + 15: begin + gpmc_data_out <= logic_analyzer_timestep[7:0]; end default: begin - gpmc_data_out = 0; + gpmc_data_out <= 0; end endcase end end end - - gpmc_data_driven = ((~gpmc_oen) && gpmc_wen); end endmodule diff --git a/fpga/gpmc/xilinx/common/verification.v b/fpga/gpmc/xilinx/common/verification.v new file mode 100644 index 0000000..c871b26 --- /dev/null +++ b/fpga/gpmc/xilinx/common/verification.v @@ -0,0 +1,151 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// uLab GPMC interface verification test bench +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +// (c) 2014 Timothy Pearson +// Raptor Engineering +// http://www.raptorengineeringinc.com +// +////////////////////////////////////////////////////////////////////////////////// + +module verification; + + // Inputs + reg clk; + reg gpmc_advn; + reg gpmc_oen; + reg gpmc_wen; + reg [15:0] gpmc_address; + reg usermem_wen; + reg userproc_done; + reg userlogic_clock; + reg userlogic_serial_rxd; + reg host_serial_rxd; + reg [3:0] four_bit_leds; + reg [7:0] eight_bit_leds; + reg sixteen_bit_io_wen; + reg [3:0] sseg_mux; + reg [7:0] sseg_data; + + // Outputs + wire usermem_wait; + wire userproc_start; + wire userlogic_reset; + wire userlogic_serial_txd; + wire host_serial_txd; + wire [3:0] four_bit_switches; + wire [7:0] eight_bit_switches; + wire sixteen_bit_io_mode; + wire userdevice_reset; + + // Bidirs + wire [7:0] gpmc_data; + wire [7:0] usermem_data; + wire [15:0] usermem_address; + wire [15:0] sixteen_bit_io; + + // Instantiate the Unit Under Test (UUT) + main uut ( + .clk(clk), + .gpmc_advn(gpmc_advn), + .gpmc_oen(gpmc_oen), + .gpmc_wen(gpmc_wen), + .gpmc_data(gpmc_data), + .gpmc_address(gpmc_address), + .usermem_wen(usermem_wen), + .usermem_wait(usermem_wait), + .usermem_data(usermem_data), + .usermem_address(usermem_address), + .userproc_start(userproc_start), + .userproc_done(userproc_done), + .userlogic_reset(userlogic_reset), + .userlogic_clock(userlogic_clock), + .userlogic_serial_txd(userlogic_serial_txd), + .userlogic_serial_rxd(userlogic_serial_rxd), + .host_serial_txd(host_serial_txd), + .host_serial_rxd(host_serial_rxd), + .four_bit_leds(four_bit_leds), + .eight_bit_leds(eight_bit_leds), + .four_bit_switches(four_bit_switches), + .eight_bit_switches(eight_bit_switches), + .sixteen_bit_io(sixteen_bit_io), + .sixteen_bit_io_wen(sixteen_bit_io_wen), + .sixteen_bit_io_mode(sixteen_bit_io_mode), + .sseg_mux(sseg_mux), + .sseg_data(sseg_data), + .userdevice_reset(userdevice_reset) + ); + + reg gpmc_data_driven = 0; + reg [7:0] gpmc_data_out; + assign gpmc_data = (gpmc_data_driven) ? gpmc_data_out : 8'bz; + + // Generate 100MHz clock + always begin + #5; + clk = !clk; + end + + // Terminate test bench after specified time has elapsed + initial begin + #10000; + $finish; + end + + // Test logic analyzer triggering and data acquisition + initial begin + // Initialize Inputs + clk = 0; + gpmc_advn = 0; + gpmc_oen = 0; + gpmc_wen = 0; + gpmc_address = 0; + usermem_wen = 0; + userproc_done = 0; + userlogic_clock = 0; + userlogic_serial_rxd = 0; + host_serial_rxd = 0; + four_bit_leds = 0; + eight_bit_leds = 0; + sixteen_bit_io_wen = 0; + sseg_mux = 0; + sseg_data = 0; + + // Wait 100 ns for global reset to finish + #100; + + // Send user logic reset signal to GPMC interface + gpmc_address = 16'h000c; + gpmc_data_out = 8'h01; + gpmc_data_driven = 1'b1; + gpmc_advn = 1'b0; + gpmc_wen = 1'b0; + #1000 + gpmc_address = 16'h000c; + gpmc_data_out = 8'h00; + gpmc_data_driven = 1'b1; + gpmc_advn = 1'b0; + gpmc_wen = 1'b0; + #100 + gpmc_data_driven = 1'b0; + gpmc_advn = 1'b1; + gpmc_wen = 1'b1; + end + +endmodule + diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ipcore_dir/lcd_data_storage.xco b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ipcore_dir/lcd_data_storage.xco new file mode 100644 index 0000000..4f77059 --- /dev/null +++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ipcore_dir/lcd_data_storage.xco @@ -0,0 +1,108 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Wed Feb 26 21:06:18 2014 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:7.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=lcd_data_storage +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_32bit_address=false +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET mem_file=no_Mem_file_loaded +CSET memory_type=True_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=50 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_bram_block=Stand_Alone +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=32 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T16:22:25Z +# END Extra information +GENERATE +# CRC: 6d3195aa diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ipcore_dir/logic_analyzer_data_storage.xco b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ipcore_dir/logic_analyzer_data_storage.xco new file mode 100644 index 0000000..c47a6a7 --- /dev/null +++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ipcore_dir/logic_analyzer_data_storage.xco @@ -0,0 +1,108 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Wed Feb 26 10:22:39 2014 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:7.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=logic_analyzer_data_storage +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_32bit_address=false +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=true +CSET interface_type=Native +CSET load_init_file=false +CSET mem_file=no_Mem_file_loaded +CSET memory_type=True_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=50 +CSET primitive=8kx2 +CSET read_width_a=64 +CSET read_width_b=64 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=AAAAAAAAAAAAAAAA +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_bram_block=Stand_Alone +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=2048 +CSET write_width_a=64 +CSET write_width_b=64 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T16:22:25Z +# END Extra information +GENERATE +# CRC: 7f171f5 diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/lcd_data_storage.v b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/lcd_data_storage.v deleted file mode 120000 index 1c1aa6b..0000000 --- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/lcd_data_storage.v +++ /dev/null @@ -1 +0,0 @@ -../../../common/lcd_data_storage.v
\ No newline at end of file diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_clock_generator.v b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_clock_generator.v index f13b1e3..05e78dc 100644 --- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_clock_generator.v +++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_clock_generator.v @@ -8,14 +8,23 @@ module logic_analyzer_clock_generator( input clkin, - output clkout); + output clkout, + output online); + + parameter LOGIC_ANALYZER_CLOCK_MULT = 2; + parameter LOGIC_ANALYZER_CLOCK_DIV = 2; wire clk0; wire clk2x; - reg reset; + wire clkfx; + reg reset = 1'b0; + wire locked; + wire [7:0] status; + + assign clkout = clkfx; - assign clkout = clk0; -// assign clkout = clk2x; + // Only signal online if the DCM is locked and clkfx is toggling + assign online = locked & (~status[2]); // DCM_SP: Digital Clock Manager // Spartan-6 @@ -24,8 +33,8 @@ module logic_analyzer_clock_generator( DCM_SP #( .CLKDV_DIVIDE(2.0), // CLKDV divide value // (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16). - .CLKFX_DIVIDE(1), // Divide value on CLKFX outputs - D - (1-32) - .CLKFX_MULTIPLY(4), // Multiply value on CLKFX outputs - M - (2-32) + .CLKFX_DIVIDE(LOGIC_ANALYZER_CLOCK_DIV), // Divide value on CLKFX outputs - D - (1-32) + .CLKFX_MULTIPLY(LOGIC_ANALYZER_CLOCK_MULT), // Multiply value on CLKFX outputs - M - (2-32) .CLKIN_DIVIDE_BY_2("FALSE"), // CLKIN divide by two (TRUE/FALSE) .CLKIN_PERIOD(10.0), // Input clock period specified in nS .CLKOUT_PHASE_SHIFT("NONE"), // Output phase shift (NONE, FIXED, VARIABLE) @@ -47,11 +56,11 @@ module logic_analyzer_clock_generator( .CLK2X180(), // 1-bit output: 2X clock frequency, 180 degree clock output .CLK90(), // 1-bit output: 90 degree clock output .CLKDV(), // 1-bit output: Divided clock output - .CLKFX(), // 1-bit output: Digital Frequency Synthesizer output (DFS) + .CLKFX(clkfx), // 1-bit output: Digital Frequency Synthesizer output (DFS) .CLKFX180(), // 1-bit output: 180 degree CLKFX output - .LOCKED(), // 1-bit output: DCM_SP Lock Output + .LOCKED(locked), // 1-bit output: DCM_SP Lock Output .PSDONE(), // 1-bit output: Phase shift done output - .STATUS(), // 8-bit output: DCM_SP status output + .STATUS(status), // 8-bit output: DCM_SP status output .CLKFB(clk0), // 1-bit input: Clock feedback input .CLKIN(clkin), // 1-bit input: Clock input .DSSEN(1'b0), // 1-bit input: Unsupported, specify to GND. @@ -65,12 +74,11 @@ module logic_analyzer_clock_generator( reg [7:0] reset_counter = 8'b00000001; always @(posedge clkin) begin - if (reset_counter[7] != 1'b1) begin + if (reset_counter[7] == 1'b0) begin reset_counter = reset_counter << 1; reset = 1'b1; end else begin reset = 1'b0; end end - endmodule diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_data_storage.v b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_data_storage.v deleted file mode 120000 index 1e8f72d..0000000 --- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_data_storage.v +++ /dev/null @@ -1 +0,0 @@ -../../../common/logic_analyzer_data_storage.v
\ No newline at end of file diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf index 8d5384f..1bfce49 100644 --- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf +++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf @@ -1,42 +1,84 @@ -# (c) 2013 Timothy Pearson, Raptor Engineering +# (c) 2013-2014 Timothy Pearson, Raptor Engineering # Released into the Public Domain NET "clk" LOC = "V10" | IOSTANDARD = "LVCMOS33"; NET "clk" TNM_NET = clk; TIMESPEC TS_clk = PERIOD "clk" 100000 KHz HIGH 50%; +NET "main_clk" TNM_NET = main_clk; +TIMESPEC TS_main_clk = PERIOD "main_clk" 100000 KHz HIGH 50%; + +NET "gpmc_data<0>" OFFSET = OUT 8 ns AFTER "clk"; +NET "gpmc_data<1>" OFFSET = OUT 8 ns AFTER "clk"; +NET "gpmc_data<2>" OFFSET = OUT 8 ns AFTER "clk"; +NET "gpmc_data<3>" OFFSET = OUT 8 ns AFTER "clk"; +NET "gpmc_data<4>" OFFSET = OUT 8 ns AFTER "clk"; +NET "gpmc_data<5>" OFFSET = OUT 8 ns AFTER "clk"; +NET "gpmc_data<6>" OFFSET = OUT 8 ns AFTER "clk"; +NET "gpmc_data<7>" OFFSET = OUT 8 ns AFTER "clk"; + +NET "gpmc_data<0>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_data<1>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_data<2>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_data<3>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_data<4>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_data<5>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_data<6>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_data<7>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; + +NET "gpmc_address<0>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<1>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<2>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<3>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<4>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<5>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<6>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<7>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<8>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<9>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<10>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<11>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<12>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<13>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<14>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_address<15>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; + +NET "gpmc_advn" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_oen" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; +NET "gpmc_wen" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk"; + #NET "serial_input" LOC = "T12" | IOSTANDARD = "LVCMOS33"; #NET "serial_output" LOC = "M10" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; -NET "gpmc_advn" LOC = "C5" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_oen" LOC = "A3" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_wen" LOC = "A5" | IOSTANDARD = "LVCMOS33"; - -NET "gpmc_data<0>" LOC = "A6" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; -NET "gpmc_data<1>" LOC = "C8" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; -NET "gpmc_data<2>" LOC = "C9" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; -NET "gpmc_data<3>" LOC = "A10" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; -NET "gpmc_data<4>" LOC = "C10" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; -NET "gpmc_data<5>" LOC = "D9" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; -NET "gpmc_data<6>" LOC = "D8" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; -NET "gpmc_data<7>" LOC = "B6" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; - -NET "gpmc_address<0>" LOC = "A11" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<1>" LOC = "F9" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<2>" LOC = "A9" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<3>" LOC = "A8" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<4>" LOC = "A7" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<5>" LOC = "C6" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<6>" LOC = "A4" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<7>" LOC = "A2" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<8>" LOC = "B11" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<9>" LOC = "G9" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<10>" LOC = "B9" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<11>" LOC = "B8" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<12>" LOC = "C7" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<13>" LOC = "D6" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<14>" LOC = "B4" | IOSTANDARD = "LVCMOS33"; -NET "gpmc_address<15>" LOC = "B2" | IOSTANDARD = "LVCMOS33"; - -NET "usermem_wen" LOC = "V16" | IOSTANDARD = "LVCMOS33"; +NET "gpmc_advn" LOC = "C5" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_oen" LOC = "A3" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_wen" LOC = "A5" | FLOAT | IOSTANDARD = "LVCMOS33"; + +NET "gpmc_data<0>" LOC = "A6" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_data<1>" LOC = "C8" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_data<2>" LOC = "C9" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_data<3>" LOC = "A10" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_data<4>" LOC = "C10" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_data<5>" LOC = "D9" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_data<6>" LOC = "D8" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_data<7>" LOC = "B6" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33"; + +NET "gpmc_address<0>" LOC = "A11" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<1>" LOC = "F9" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<2>" LOC = "A9" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<3>" LOC = "A8" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<4>" LOC = "A7" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<5>" LOC = "C6" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<6>" LOC = "A4" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<7>" LOC = "A2" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<8>" LOC = "B11" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<9>" LOC = "G9" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<10>" LOC = "B9" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<11>" LOC = "B8" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<12>" LOC = "C7" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<13>" LOC = "D6" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<14>" LOC = "B4" | FLOAT | IOSTANDARD = "LVCMOS33"; +NET "gpmc_address<15>" LOC = "B2" | FLOAT | IOSTANDARD = "LVCMOS33"; + +NET "usermem_wen" LOC = "V16" | PULLUP | IOSTANDARD = "LVCMOS33"; NET "usermem_wait" LOC = "T18" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; NET "userproc_start" LOC = "K16" | SLEW = FAST | IOSTANDARD = "LVCMOS33"; NET "userproc_done" LOC = "L13" | IOSTANDARD = "LVCMOS33"; diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main_clock_generator.v b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main_clock_generator.v new file mode 100644 index 0000000..b867c02 --- /dev/null +++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main_clock_generator.v @@ -0,0 +1,20 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// (c) 2014 Timothy Pearson, Raptor Engineering +// Released into the Public Domain +// +////////////////////////////////////////////////////////////////////////////////// + +module main_clock_generator( + input clkin, + output clkout, + output online); + + assign online = 1'b1; + + BUFG BUFG_inst ( + .O(clkout), // 1-bit output: Clock buffer output + .I(clkin) // 1-bit input: Clock buffer input + ); +endmodule
\ No newline at end of file diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise index 774cabd..dfb47cf 100644 --- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise +++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise @@ -16,28 +16,44 @@ <files> <file xil_pn:name="data_storage.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/> </file> - <file xil_pn:name="lcd_data_storage.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> - <association xil_pn:name="Implementation" xil_pn:seqID="3"/> - </file> <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/> </file> - <file xil_pn:name="logic_analyzer_data_storage.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/> + <file xil_pn:name="logic_analyzer_clock_generator.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + </file> + <file xil_pn:name="main_clock_generator.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/> </file> - <file xil_pn:name="logic_analyzer_clock_generator.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/> + <file xil_pn:name="verification.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="58"/> + </file> + <file xil_pn:name="ipcore_dir/logic_analyzer_data_storage.xco" xil_pn:type="FILE_COREGEN"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/> </file> + <file xil_pn:name="ipcore_dir/lcd_data_storage.xco" xil_pn:type="FILE_COREGEN"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + </file> + <file xil_pn:name="ipcore_dir/logic_analyzer_data_storage.xise" xil_pn:type="FILE_COREGENISE"> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + </file> + <file xil_pn:name="ipcore_dir/lcd_data_storage.xise" xil_pn:type="FILE_COREGENISE"> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + </file> </files> <properties> @@ -151,7 +167,7 @@ <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> - <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Implementation Top" xil_pn:value="Module|main" xil_pn:valueState="non-default"/> @@ -227,7 +243,7 @@ <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> + <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="Standard" xil_pn:valueState="non-default"/> <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> @@ -269,7 +285,7 @@ <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> - <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Resource Sharing" xil_pn:value="false" xil_pn:valueState="non-default"/> <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/> @@ -281,27 +297,28 @@ <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> - <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/verification" xil_pn:valueState="non-default"/> + <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.verification" xil_pn:valueState="non-default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.verification" xil_pn:valueState="non-default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.verification" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut" xil_pn:valueState="non-default"/> <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> - <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="10000 ns" xil_pn:valueState="non-default"/> <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> - <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> - <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.verification" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.verification" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.verification" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> @@ -349,12 +366,12 @@ <!-- --> <!-- The following properties are for internal use only. These should not be modified.--> <!-- --> - <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|verification" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="ulab_debug_interface" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> - <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="Module|verification" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|verification" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/verification.v b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/verification.v new file mode 120000 index 0000000..2a3bfa8 --- /dev/null +++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/verification.v @@ -0,0 +1 @@ +../../../common/verification.v
\ No newline at end of file |