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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2014 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////
module data_storage(
input clka,
input [(RAM_WIDTH-1):0] dina,
input [(RAM_ADDR_BITS-1):0] addra,
input wea,
output reg [(RAM_WIDTH-1):0] douta);
parameter RAM_ADDR_BITS = 14;
parameter RAM_WIDTH = 8;
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0];
// Registered
always @(posedge clka) begin
if (wea) begin
data_storage_ram[addra] <= dina;
douta <= dina;
end else begin
douta <= data_storage_ram[addra];
end
end
// // Unregistered
// always @(posedge clka) begin
// if (wea) begin
// data_storage_ram[addra] <= dina;
// end
// end
// assign douta = data_storage_ram[addra];
endmodule
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