fpga/serial/xilinx/digilent/spartan_6/s6_remotefpga_test/main.ucf


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# (c) 2013 Timothy Pearson, Raptor Engineering
# Released into the Public Domain

NET "clk"  LOC = "V10" | IOSTANDARD = "LVCMOS33";
TIMESPEC TS_clk = PERIOD clk 100000 kHz;

NET "serial_input"  LOC = "T12" | IOSTANDARD = "LVCMOS33";
NET "serial_output"  LOC = "M10" | IOSTANDARD = "LVCMOS33";