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| author | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2013-04-21 23:45:00 -0500 |
|---|---|---|
| committer | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2013-04-21 23:45:00 -0500 |
| commit | 976f4c5dfeb6a42f3728d24293e61010f4a8ba7e (patch) | |
| tree | a4c4b56230e3dcd9eb8ed91a80d960f917e7af6c /fpga | |
| parent | 3f00d517b806d31105b962ab191c149fa12290b6 (diff) | |
| download | ulab-976f4c5dfeb6a42f3728d24293e61010f4a8ba7e.tar.gz ulab-976f4c5dfeb6a42f3728d24293e61010f4a8ba7e.zip | |
Use 10-pin headers for ulab debug interface serial port on Spartan 6
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.ucf | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.ucf b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.ucf index 1504c2e..ab433e5 100644 --- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.ucf +++ b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.ucf @@ -4,5 +4,5 @@ NET "clk" LOC = "V10"; TIMESPEC TS_clk = PERIOD clk 100000 kHz; -NET "serial_input" LOC = "N17"; -NET "serial_output" LOC = "N18"; +NET "serial_input" LOC = "T12"; +NET "serial_output" LOC = "M10"; |