1 files changed, 12 insertions, 12 deletions
diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v
index f1d10be..60c1dff 100644
--- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v
+++ b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v
@@ -13,20 +13,20 @@ module data_storage(
 	input wea,
 	output reg [7:0] douta);
 
-   parameter RAM_WIDTH = 8;
-   parameter RAM_ADDR_BITS = 14;
- 
-   // Xilinx specific directive
-   (* RAM_STYLE="BLOCK" *)
-
-   reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0];
-
-   always @(posedge clka) begin
-      if (wea) begin
+	parameter RAM_ADDR_BITS = 14;
+	parameter RAM_WIDTH = 8;
+	
+	// Xilinx specific directive
+	(* RAM_STYLE="BLOCK" *)
+	
+	reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0];
+	
+	always @(posedge clka) begin
+	if (wea) begin
 			data_storage_ram[addra] <= dina;
 			douta <= dina;
-      end else begin
-			douta <= data_storage_ram[addra];					
+	end else begin
+			douta <= data_storage_ram[addra];
 		end
 	end