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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2013 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////
module data_storage(
input clka,
input [7:0] dina,
input [13:0] addra,
input wea,
output reg [7:0] douta);
parameter RAM_ADDR_BITS = 14;
parameter RAM_WIDTH = 8;
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0];
always @(posedge clka) begin
if (wea) begin
data_storage_ram[addra] <= dina;
douta <= dina;
end else begin
douta <= data_storage_ram[addra];
end
end
endmodule
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