| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | First pass of logic analyzer functionality (client and FPGA core) | Timothy Pearson | 2014-02-27 | 5 | -155/+475 |
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| * | Add ability to hard reset user device | Timothy Pearson | 2014-01-13 | 1 | -1/+9 |
| | | | | | Fix initial size of serial and terminal windows | ||||
| * | Add serial I/O to host FPGA | Timothy Pearson | 2014-01-12 | 1 | -0/+8 |
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| * | Max out logic analyzer memory | Timothy Pearson | 2014-01-12 | 2 | -14/+18 |
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| * | Add logic analyzer block to control FPGA | Timothy Pearson | 2014-01-11 | 2 | -2/+139 |
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| * | Relayout the GUI to be more in line with expected norms | Timothy Pearson | 2014-01-10 | 1 | -1/+17 |
| | | | | | | Add user logic reset signal Stabilize data transfer | ||||
| * | Increase DSP memory size | Timothy Pearson | 2014-01-10 | 1 | -1/+5 |
| | | | | | Fix potential crash in FPGA viewer if hardware debug interface is malfunctioning or offline | ||||
| * | Move hardware design files to their correct locations | Timothy Pearson | 2014-01-09 | 3 | -0/+470 |
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index : ulab | |
| Donated space for related uLab project | TDE Gitea Workspace |
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